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Tue, 17 Oct 2023 05:38:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Cc: Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 1/2] target/loongarch: Use i128 for 128-bit load/store in VST[X]/XVST Date: Tue, 17 Oct 2023 14:38:48 +0200 Message-ID: <20231017123849.40834-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231017123849.40834-1-philmd@linaro.org> References: <20231017123849.40834-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/translate.c | 6 +++++ target/loongarch/insn_trans/trans_vec.c.inc | 30 +++++++-------------- 2 files changed, 15 insertions(+), 21 deletions(-) diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 21f4db6fbd..c6edfc800f 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -61,6 +61,12 @@ static inline void set_vreg64(TCGv_i64 src, int regno, int index) offsetof(CPULoongArchState, fpr[regno].vreg.D(index))); } +static inline void get_vreg128(TCGv_i128 dest, int regno, int index) +{ + tcg_gen_ld_i128(dest, tcg_env, + offsetof(CPULoongArchState, fpr[regno].vreg.Q(index))); +} + static inline int plus_1(DisasContext *ctx, int x) { return x + 1; diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/trans_vec.c.inc index 98f856bb29..dd41f5e48e 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -5285,7 +5285,6 @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a) { TCGv addr; TCGv_i128 val; - TCGv_i64 ah, al; if (!avail_LSX(ctx)) { return false; @@ -5297,14 +5296,10 @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a) addr = gpr_src(ctx, a->rj, EXT_NONE); val = tcg_temp_new_i128(); - ah = tcg_temp_new_i64(); - al = tcg_temp_new_i64(); addr = make_address_i(ctx, addr, a->imm); - get_vreg64(ah, a->vd, 1); - get_vreg64(al, a->vd, 0); - tcg_gen_concat_i64_i128(val, al, ah); + get_vreg128(val, a->vd, 0); tcg_gen_qemu_st_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); return true; @@ -5342,7 +5337,6 @@ static bool trans_vldx(DisasContext *ctx, arg_vrr *a) static bool trans_vstx(DisasContext *ctx, arg_vrr *a) { TCGv addr, src1, src2; - TCGv_i64 ah, al; TCGv_i128 val; if (!avail_LSX(ctx)) { @@ -5356,13 +5350,9 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a) src1 = gpr_src(ctx, a->rj, EXT_NONE); src2 = gpr_src(ctx, a->rk, EXT_NONE); val = tcg_temp_new_i128(); - ah = tcg_temp_new_i64(); - al = tcg_temp_new_i64(); addr = make_address_x(ctx, src1, src2); - get_vreg64(ah, a->vd, 1); - get_vreg64(al, a->vd, 0); - tcg_gen_concat_i64_i128(val, al, ah); + get_vreg128(val, a->vd, 0); tcg_gen_qemu_st_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); return true; @@ -5484,18 +5474,16 @@ static void gen_xvld(DisasContext *ctx, int vreg, TCGv addr) static void gen_xvst(DisasContext * ctx, int vreg, TCGv addr) { - int i; + MemOp mop = MO_128 | MO_TE; TCGv temp = tcg_temp_new(); - TCGv dest = tcg_temp_new(); + TCGv_i128 dest = tcg_temp_new_i128(); - get_vreg64(dest, vreg, 0); - tcg_gen_qemu_st_i64(dest, addr, ctx->mem_idx, MO_TEUQ); + get_vreg128(dest, vreg, 0); + tcg_gen_qemu_st_i128(dest, addr, ctx->mem_idx, mop); - for (i = 1; i < 4; i++) { - tcg_gen_addi_tl(temp, addr, 8 * i); - get_vreg64(dest, vreg, i); - tcg_gen_qemu_st_i64(dest, temp, ctx->mem_idx, MO_TEUQ); - } + tcg_gen_addi_tl(temp, addr, 16); + get_vreg128(dest, vreg, 1); + tcg_gen_qemu_st_i128(dest, temp, ctx->mem_idx, mop); } TRANS(xvld, LASX, gen_lasx_memory, gen_xvld) From patchwork Tue Oct 17 12:38:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 734378 Delivered-To: patch@linaro.org Received: by 2002:adf:f0cd:0:b0:32d:baff:b0ca with SMTP id x13csp455364wro; Tue, 17 Oct 2023 05:39:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE4XrfYUVs2W9W+8R5KoheAPsozxVtxgJYqaEzqZUmOIwcKmzsvN8O91H/9U0fg1AsNMLST X-Received: by 2002:adf:f48a:0:b0:32d:b732:8d49 with SMTP id l10-20020adff48a000000b0032db7328d49mr1874385wro.28.1697546375637; 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Tue, 17 Oct 2023 05:39:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Cc: Song Gao , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [RFC PATCH 2/2] target/loongarch: Use i128 for 128-bit load/store in XVLD Date: Tue, 17 Oct 2023 14:38:49 +0200 Message-ID: <20231017123849.40834-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231017123849.40834-1-philmd@linaro.org> References: <20231017123849.40834-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/loongarch/translate.c | 6 ++++++ target/loongarch/insn_trans/trans_vec.c.inc | 16 +++++++--------- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index c6edfc800f..89e35770b7 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -67,6 +67,12 @@ static inline void get_vreg128(TCGv_i128 dest, int regno, int index) offsetof(CPULoongArchState, fpr[regno].vreg.Q(index))); } +static inline void set_vreg128(TCGv_i128 src, int regno, int index) +{ + tcg_gen_st_i128(src, tcg_env, + offsetof(CPULoongArchState, fpr[regno].vreg.Q(index))); +} + static inline int plus_1(DisasContext *ctx, int x) { return x + 1; diff --git a/target/loongarch/insn_trans/trans_vec.c.inc b/target/loongarch/insn_trans/trans_vec.c.inc index dd41f5e48e..c8b7bfa67f 100644 --- a/target/loongarch/insn_trans/trans_vec.c.inc +++ b/target/loongarch/insn_trans/trans_vec.c.inc @@ -5458,18 +5458,16 @@ static bool gen_lasx_memory(DisasContext *ctx, arg_vr_i *a, static void gen_xvld(DisasContext *ctx, int vreg, TCGv addr) { - int i; + MemOp mop = MO_128 | MO_TE; TCGv temp = tcg_temp_new(); - TCGv dest = tcg_temp_new(); + TCGv_i128 dest = tcg_temp_new_i128(); - tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUQ); - set_vreg64(dest, vreg, 0); + tcg_gen_qemu_ld_i128(dest, addr, ctx->mem_idx, mop); + set_vreg128(dest, vreg, 0); - for (i = 1; i < 4; i++) { - tcg_gen_addi_tl(temp, addr, 8 * i); - tcg_gen_qemu_ld_i64(dest, temp, ctx->mem_idx, MO_TEUQ); - set_vreg64(dest, vreg, i); - } + tcg_gen_addi_tl(temp, addr, 16); + tcg_gen_qemu_ld_i128(dest, temp, ctx->mem_idx, mop); + set_vreg128(dest, vreg, 1); } static void gen_xvst(DisasContext * ctx, int vreg, TCGv addr)