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Tue, 17 Oct 2023 05:27:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Richard Henderson Cc: Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [RFC PATCH] target/m68k: Use i128 for 128-bit load/store in m68k_copy_line() Date: Tue, 17 Oct 2023 14:27:02 +0200 Message-ID: <20231017122702.39311-1-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- Based-on: <20231013175109.124308-1-richard.henderson@linaro.org> tcg: Add tcg_gen_{ld,st}_i128 RFC because unsure and untested... --- target/m68k/translate.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4d0110de95..1e3d155bd9 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -4293,23 +4293,17 @@ DISAS_INSN(chk2) static void m68k_copy_line(TCGv dst, TCGv src, int index) { + MemOp mop = MO_128 | MO_TE; + TCGv_i128 t = tcg_temp_new_i128(); TCGv addr; - TCGv_i64 t0, t1; addr = tcg_temp_new(); - t0 = tcg_temp_new_i64(); - t1 = tcg_temp_new_i64(); - tcg_gen_andi_i32(addr, src, ~15); - tcg_gen_qemu_ld_i64(t0, addr, index, MO_TEUQ); - tcg_gen_addi_i32(addr, addr, 8); - tcg_gen_qemu_ld_i64(t1, addr, index, MO_TEUQ); + tcg_gen_qemu_ld_i128(t, addr, index, mop); tcg_gen_andi_i32(addr, dst, ~15); - tcg_gen_qemu_st_i64(t0, addr, index, MO_TEUQ); - tcg_gen_addi_i32(addr, addr, 8); - tcg_gen_qemu_st_i64(t1, addr, index, MO_TEUQ); + tcg_gen_st_i128(t, addr, index); } DISAS_INSN(move16_reg)