From patchwork Mon Oct 16 16:49:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 737363 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B7AE286AF for ; Mon, 16 Oct 2023 16:50:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="TQEbZR5I" Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79E2D30DB for ; Mon, 16 Oct 2023 09:50:11 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-6b3c2607d9bso2337534b3a.1 for ; Mon, 16 Oct 2023 09:50:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697475011; x=1698079811; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fGpfWXp12h96iIrhrZ9w/4qboCYb79h5kFDLjoFea9A=; b=TQEbZR5I3mwF8aFca89GAt1KoFSJF53udj3ReynViMjvp2q8ufWOGy0GN7Cic0tmkN FkqN1ONwbQuJLdOG0eTtttNh7I1WCiLRDHqUm31nqK12LOxH0mMwkOJIJUJulouAmgRE 9xDhUu0y5t5fkL9Ig6wqMVRktaPZUgu0F30UFAbgEHCRByEg/1Oc0oro+Vc7h5RkEuqi UD44Hp4YOyYgjbnHxB3CcH2ZkgiI2PzcGXitKOhBhfpuefPB2Rd/TakKdbXl9YV/qw41 Du5xujCVEwQROZfyOy0x5UOo0uY8JuUAbwonigxsONkPeBWiCbpEHseJcP4qUpFyvU4J TRcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697475011; x=1698079811; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fGpfWXp12h96iIrhrZ9w/4qboCYb79h5kFDLjoFea9A=; b=fFkTSOl2uCAIwO+hsC27IRMbha7XHsN62ght0veC7fAPdKt67L69lps9/BrOlLG2WI PMlPLD27K7MJUEnR0TQ/VPsalRkeJLBhsxrbHx/94mlfPhxMX6K30Ke5clq5z/YkmCI5 YT2wmq6xaUNyaqx7mcePK+i8qkyEE14gO2mWAYbTKpqeJPIMuy6bnYdDzQMLw4fvwdj8 VDaG5uiS7zUmSmyTAZBmjIKvlKUSguB7T0rNkEI+Y+2kMGDMHj6kZiAk0ND1OyqOc8jY +YTRPZ1P/5eXp6G1NDTyypb/sIFdJuQwElQpD4XPXWrSHsI0m8HUEyJ2VoxeomQRWhze WSjg== X-Gm-Message-State: AOJu0YzVTy5L9DFfIerRtXsLCl6pWzeeNOxmeeUd2Tz0USMyB893oveg QxCJUYZ5tFlUKQACdm6oENsjog== X-Google-Smtp-Source: AGHT+IGjQ2ofm9vq+rM9KYxzcQbOI6U0lRLO3PtlSK9ezYbqJA021qj0LVOx7aeW/7sHzfS/fqtlUw== X-Received: by 2002:a05:6a00:1389:b0:6b2:6835:2a82 with SMTP id t9-20020a056a00138900b006b268352a82mr9317417pfg.13.1697475010850; Mon, 16 Oct 2023 09:50:10 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id t21-20020a056a0021d500b006b1e8f17b85sm111252pfj.201.2023.10.16.09.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 09:50:10 -0700 (PDT) From: Sunil V L To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Andrew Jones , Conor Dooley , Anup Patel , Ard Biesheuvel , Atish Kumar Patra , Sunil V L , Alexandre Ghiti Subject: [PATCH v3 -next 1/3] RISC-V: ACPI: Enhance acpi_os_ioremap with MMIO remapping Date: Mon, 16 Oct 2023 22:19:56 +0530 Message-Id: <20231016164958.1191529-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231016164958.1191529-1-sunilvl@ventanamicro.com> References: <20231016164958.1191529-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Enhance the acpi_os_ioremap() to support opregions in MMIO space. Also, have strict checks using EFI memory map to allow remapping the RAM similar to arm64. Signed-off-by: Sunil V L Reviewed-by: Andrew Jones Reviewed-by: Alexandre Ghiti Acked-by: Conor Dooley --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/acpi.c | 87 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 86 insertions(+), 2 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d607ab0f7c6d..805c8ab7f23b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -39,6 +39,7 @@ config RISCV select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST select ARCH_HAS_UBSAN_SANITIZE_ALL select ARCH_HAS_VDSO_DATA + select ARCH_KEEP_MEMBLOCK if ACPI select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT select ARCH_STACKWALK diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 56cb2c986c48..e619edc8b0cc 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -14,9 +14,10 @@ */ #include +#include #include +#include #include -#include int acpi_noirq = 1; /* skip ACPI IRQ initialization */ int acpi_disabled = 1; @@ -217,7 +218,89 @@ void __init __acpi_unmap_table(void __iomem *map, unsigned long size) void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) { - return (void __iomem *)memremap(phys, size, MEMREMAP_WB); + efi_memory_desc_t *md, *region = NULL; + pgprot_t prot; + + if (WARN_ON_ONCE(!efi_enabled(EFI_MEMMAP))) + return NULL; + + for_each_efi_memory_desc(md) { + u64 end = md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT); + + if (phys < md->phys_addr || phys >= end) + continue; + + if (phys + size > end) { + pr_warn(FW_BUG "requested region covers multiple EFI memory regions\n"); + return NULL; + } + region = md; + break; + } + + /* + * It is fine for AML to remap regions that are not represented in the + * EFI memory map at all, as it only describes normal memory, and MMIO + * regions that require a virtual mapping to make them accessible to + * the EFI runtime services. + */ + prot = PAGE_KERNEL_IO; + if (region) { + switch (region->type) { + case EFI_LOADER_CODE: + case EFI_LOADER_DATA: + case EFI_BOOT_SERVICES_CODE: + case EFI_BOOT_SERVICES_DATA: + case EFI_CONVENTIONAL_MEMORY: + case EFI_PERSISTENT_MEMORY: + if (memblock_is_map_memory(phys) || + !memblock_is_region_memory(phys, size)) { + pr_warn(FW_BUG "requested region covers kernel memory\n"); + return NULL; + } + + /* + * Mapping kernel memory is permitted if the region in + * question is covered by a single memblock with the + * NOMAP attribute set: this enables the use of ACPI + * table overrides passed via initramfs. + * This particular use case only requires read access. + */ + fallthrough; + + case EFI_RUNTIME_SERVICES_CODE: + /* + * This would be unusual, but not problematic per se, + * as long as we take care not to create a writable + * mapping for executable code. + */ + prot = PAGE_KERNEL_RO; + break; + + case EFI_ACPI_RECLAIM_MEMORY: + /* + * ACPI reclaim memory is used to pass firmware tables + * and other data that is intended for consumption by + * the OS only, which may decide it wants to reclaim + * that memory and use it for something else. We never + * do that, but we usually add it to the linear map + * anyway, in which case we should use the existing + * mapping. + */ + if (memblock_is_map_memory(phys)) + return (void __iomem *)__va(phys); + fallthrough; + + default: + if (region->attribute & EFI_MEMORY_WB) + prot = PAGE_KERNEL; + else if ((region->attribute & EFI_MEMORY_WC) || + (region->attribute & EFI_MEMORY_WT)) + prot = pgprot_writecombine(PAGE_KERNEL); + } + } + + return ioremap_prot(phys, size, pgprot_val(prot)); } #ifdef CONFIG_PCI From patchwork Mon Oct 16 16:49:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 734041 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1B91286AF for ; Mon, 16 Oct 2023 16:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="ejddTP9L" Received: from mail-oo1-xc30.google.com (mail-oo1-xc30.google.com [IPv6:2607:f8b0:4864:20::c30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03BEAE1CE for ; Mon, 16 Oct 2023 09:50:15 -0700 (PDT) Received: by mail-oo1-xc30.google.com with SMTP id 006d021491bc7-57bca5b9b0aso2503026eaf.3 for ; Mon, 16 Oct 2023 09:50:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697475015; x=1698079815; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=771urCD3ivMrGFxRwO6FF0bHhNMWlumN7WHUnj5mC2E=; b=ejddTP9LVNNwFngQrJ2MDm+S6rqEhAZBTy5rwQ2m0W9rGjH2ZCCFikWZ5j57O7cvkQ C6HibdcLOD2rMH6vyIEWjT6kEfexxPxBwFhVFTqt8QRmJK5N+d2XBgI4QDeCc+W2D179 HPuPXbg6rspGID9EXgbjFYuWH1C/mlCHMbGGTEW/n7sej0YASa91E7TjkbFQEKFhJzVb 6OH9GnHg/zmNLWglO/0HheXV+lmWfVmOsYfFjQZAvZkJK9p5WariVEYDQXAIuakIuGdl 1/pYUrfMH531wx85NJEq+sARZpNhMaBa3uUpq7qY4pq5TIXnIdXnRxHE5iizYQgy02H7 Sy6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697475015; x=1698079815; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=771urCD3ivMrGFxRwO6FF0bHhNMWlumN7WHUnj5mC2E=; b=qBz9hl8ypGUonyoJ7ChPrB4XM/AgUVVKVx/7mIbMAysg/IphWT9n7u5ik8j+dufw3V mEjVlQkxYcWVKBBo/SzpaTaGdlKJy3T/zd25S8pWUyAunpQYKrcF7kcNgWgH+Nw75MkX pBek6Vf3WUSCYACeKomCtVYaLj/W+9IQOKl93QldoooY8s2XTCtoVMsDlagsfIwLe1hp JqNBJAZmOIgdmFfpSBQwRBcbd2g1aIVbtvq8RqFcszpv9nBkNZLyfsIy6MmgJNglPYOe JpGEEOhmtYsw1T61FIizZ/+frf+tV/lFtn/B0J3J+sfHlDNjN90FfUwwlkY78cc5+EMW DXtg== X-Gm-Message-State: AOJu0YxCWvqRQqxIBOe0tZXViMDEoQToE3fD7kKY0vjyBQB6vaOQR6qp 8QmSQIy15JIvbi60EpFwFVu6Lg== X-Google-Smtp-Source: AGHT+IHj6pvcAY/EU6tBAGFPTeSDrRqJvly9AhUO9Z+1tZDpjcbVdOpa7xjrqxaz1DWdPrnVU3y4vw== X-Received: by 2002:a05:6358:18:b0:164:a5c0:46ac with SMTP id 24-20020a056358001800b00164a5c046acmr18820773rww.21.1697475015175; Mon, 16 Oct 2023 09:50:15 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id t21-20020a056a0021d500b006b1e8f17b85sm111252pfj.201.2023.10.16.09.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 09:50:14 -0700 (PDT) From: Sunil V L To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Andrew Jones , Conor Dooley , Anup Patel , Ard Biesheuvel , Atish Kumar Patra , Sunil V L Subject: [PATCH v3 -next 2/3] RISC-V: ACPI: RHCT: Add function to get CBO block sizes Date: Mon, 16 Oct 2023 22:19:57 +0530 Message-Id: <20231016164958.1191529-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231016164958.1191529-1-sunilvl@ventanamicro.com> References: <20231016164958.1191529-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Cache Block Operation (CBO) related block size in ACPI is provided by RHCT. Add support to read the CMO node in RHCT to get this information. Signed-off-by: Sunil V L Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 6 +++ drivers/acpi/riscv/rhct.c | 93 +++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index d5604d2073bc..7dad0cf9d701 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -66,6 +66,8 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa); static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; } +void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_size, + u32 *cboz_size, u32 *cbop_size); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -79,6 +81,10 @@ static inline int acpi_get_riscv_isa(struct acpi_table_header *table, return -EINVAL; } +static inline void acpi_get_cbo_block_size(struct acpi_table_header *table, + u32 *cbom_size, u32 *cboz_size, + u32 *cbop_size) { } + #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c index b280b3e9c7d9..105f1aaa3fac 100644 --- a/drivers/acpi/riscv/rhct.c +++ b/drivers/acpi/riscv/rhct.c @@ -8,6 +8,7 @@ #define pr_fmt(fmt) "ACPI: RHCT: " fmt #include +#include static struct acpi_table_header *acpi_get_rhct(void) { @@ -81,3 +82,95 @@ int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const return -1; } + +static void acpi_parse_hart_info_cmo_node(struct acpi_table_rhct *rhct, + struct acpi_rhct_hart_info *hart_info, + u32 *cbom_size, u32 *cboz_size, u32 *cbop_size) +{ + u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info); + u32 size_hdr = sizeof(struct acpi_rhct_node_header); + struct acpi_rhct_node_header *ref_node; + struct acpi_rhct_cmo_node *cmo_node; + u32 *hart_info_node_offset; + + hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo); + for (int i = 0; i < hart_info->num_offsets; i++) { + ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header, + rhct, hart_info_node_offset[i]); + if (ref_node->type == ACPI_RHCT_NODE_TYPE_CMO) { + cmo_node = ACPI_ADD_PTR(struct acpi_rhct_cmo_node, + ref_node, size_hdr); + if (cbom_size && cmo_node->cbom_size <= 30) { + if (!*cbom_size) { + *cbom_size = BIT(cmo_node->cbom_size); + } else if (*cbom_size != + BIT(cmo_node->cbom_size)) { + pr_warn("CBOM size is not the same across harts\n"); + } + } + + if (cboz_size && cmo_node->cboz_size <= 30) { + if (!*cboz_size) { + *cboz_size = BIT(cmo_node->cboz_size); + } else if (*cboz_size != + BIT(cmo_node->cboz_size)) { + pr_warn("CBOZ size is not the same across harts\n"); + } + } + + if (cbop_size && cmo_node->cbop_size <= 30) { + if (!*cbop_size) { + *cbop_size = BIT(cmo_node->cbop_size); + } else if (*cbop_size != + BIT(cmo_node->cbop_size)) { + pr_warn("CBOP size is not the same across harts\n"); + } + } + } + } +} + +/* + * During early boot, the caller should call acpi_get_table() and pass its pointer to + * these functions(and free up later). At run time, since this table can be used + * multiple times, pass NULL so that the table remains in memory + */ +void acpi_get_cbo_block_size(struct acpi_table_header *table, u32 *cbom_size, + u32 *cboz_size, u32 *cbop_size) +{ + u32 size_hdr = sizeof(struct acpi_rhct_node_header); + struct acpi_rhct_node_header *node, *end; + struct acpi_rhct_hart_info *hart_info; + struct acpi_table_rhct *rhct; + + if (acpi_disabled) + return; + + if (table) { + rhct = (struct acpi_table_rhct *)table; + } else { + rhct = (struct acpi_table_rhct *)acpi_get_rhct(); + if (!rhct) + return; + } + + if (cbom_size) + *cbom_size = 0; + + if (cboz_size) + *cboz_size = 0; + + if (cbop_size) + *cbop_size = 0; + + end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length); + for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset); + node < end; + node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) { + if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) { + hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr); + acpi_parse_hart_info_cmo_node(rhct, hart_info, cbom_size, + cboz_size, cbop_size); + } + } +} From patchwork Mon Oct 16 16:49:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 737362 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C18D2286AF for ; Mon, 16 Oct 2023 16:50:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="gQArJ88m" Received: from mail-ot1-x336.google.com (mail-ot1-x336.google.com [IPv6:2607:f8b0:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79ADA35AE for ; Mon, 16 Oct 2023 09:50:20 -0700 (PDT) Received: by mail-ot1-x336.google.com with SMTP id 46e09a7af769-6c644a1845cso3244536a34.2 for ; Mon, 16 Oct 2023 09:50:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697475019; x=1698079819; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZZ0vGD2+BKy40gDZpkmDGFYSfDE+/JpanTOV3I4/UO0=; b=gQArJ88mZHl4FZCcgOndCz7jWFnjzhzDkmv73hirutORkdAvF/uryfkl4E7orGhVAq vFZVFGowdwMfpS4bbJu+2TDe/YtN+1O31HgopAffcByIEX1EKA0gJQlPQVTquhalTXJh 8Q0cPjouu+tU6EhjLWB+9F5VzXNW9DgPqN3o6LOV+L0qj+lcoF3M7X79KHEruRIDTtTr qGYMPbJgcRn7/B7roaTjuThQEz0590Cx82ZgRcivNXKc9ftOMF/PU2mEdLBEfQvq+Ocw Y8Dt+8f8yURcAuTAPPH8DdLCVlTPOYkA5Le5TTibEcTP9p6OJVt99sgSgu4cLBdJe4pv iuxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697475019; x=1698079819; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZZ0vGD2+BKy40gDZpkmDGFYSfDE+/JpanTOV3I4/UO0=; b=efRSIv6e2+wjnS/MzzXNqHxY5f8zbUudt5mXY8fLG7trtmfZhbL4I8u+zA/6PdPqZo OzuYOHhFfsU1Wtr6ss/2hD3OmYCmLHKemg+M2gmj5dzW8cE16Uzwrz2ZrpHffQSD8IT0 F9v+hnwg9Jn4XO97duL89uahUY3oX8LawSORnmIdzfcy/hsGyLx/4q0f4Vc1VFlYeszS BglN7ykgnrqvIWMFYFRdcGOfj7taqIxYSr2T9Nm7mvcii0jcR0EwbtLe+NHrOWHPGWlY SJROHkAAAqyb1M+4uUl1PyzIjp89bRzMDKdkAr7IV38+VFBjyZ3En6d9Hx83SJk4NkU7 saKg== X-Gm-Message-State: AOJu0YxilHU1T8xQbQWdz0BId/yP/OXjrg9vWjNPwKmD1Y1q7Hc6AZto c1h1b0yeygcD9oQI0y4e7FluiA== X-Google-Smtp-Source: AGHT+IHqliXUJFOJEhcrG6Kun9snmsLpe7mNtDv2ZFSs1vqugxC/0ZpQcV+6xbYVXPNJauOh7+BCtw== X-Received: by 2002:a05:6830:4ae:b0:6c4:9ca1:f13a with SMTP id l14-20020a05683004ae00b006c49ca1f13amr35003337otd.35.1697475019591; Mon, 16 Oct 2023 09:50:19 -0700 (PDT) Received: from sunil-pc.Dlink ([106.51.188.78]) by smtp.gmail.com with ESMTPSA id t21-20020a056a0021d500b006b1e8f17b85sm111252pfj.201.2023.10.16.09.50.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 09:50:18 -0700 (PDT) From: Sunil V L To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Andrew Jones , Conor Dooley , Anup Patel , Ard Biesheuvel , Atish Kumar Patra , Sunil V L Subject: [PATCH v3 -next 3/3] RISC-V: cacheflush: Initialize CBO variables on ACPI systems Date: Mon, 16 Oct 2023 22:19:58 +0530 Message-Id: <20231016164958.1191529-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231016164958.1191529-1-sunilvl@ventanamicro.com> References: <20231016164958.1191529-1-sunilvl@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Initialize the CBO variables on ACPI based systems using information in RHCT. Signed-off-by: Sunil V L --- arch/riscv/mm/cacheflush.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index f1387272a551..55a34f2020a8 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -3,7 +3,9 @@ * Copyright (C) 2017 SiFive */ +#include #include +#include #include #ifdef CONFIG_SMP @@ -124,13 +126,24 @@ void __init riscv_init_cbo_blocksizes(void) unsigned long cbom_hartid, cboz_hartid; u32 cbom_block_size = 0, cboz_block_size = 0; struct device_node *node; + struct acpi_table_header *rhct; + acpi_status status; + + if (acpi_disabled) { + for_each_of_cpu_node(node) { + /* set block-size for cbom and/or cboz extension if available */ + cbo_get_block_size(node, "riscv,cbom-block-size", + &cbom_block_size, &cbom_hartid); + cbo_get_block_size(node, "riscv,cboz-block-size", + &cboz_block_size, &cboz_hartid); + } + } else { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) + return; - for_each_of_cpu_node(node) { - /* set block-size for cbom and/or cboz extension if available */ - cbo_get_block_size(node, "riscv,cbom-block-size", - &cbom_block_size, &cbom_hartid); - cbo_get_block_size(node, "riscv,cboz-block-size", - &cboz_block_size, &cboz_hartid); + acpi_get_cbo_block_size(rhct, &cbom_block_size, &cboz_block_size, NULL); + acpi_put_table((struct acpi_table_header *)rhct); } if (cbom_block_size)