From patchwork Wed Aug 7 09:44:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 170742 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp6888629ile; Wed, 7 Aug 2019 02:44:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqzqbFb5+A5MqGJJApFiypQuApUc473CHhiFtdIpMpMQyMK1q+jaKestCUHsAriKEB4lRLmP X-Received: by 2002:aa7:8752:: with SMTP id g18mr8061879pfo.201.1565171096885; Wed, 07 Aug 2019 02:44:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565171096; cv=none; d=google.com; s=arc-20160816; b=AQY1cSilJjss8bwQfixpSRbnLG0KcYzPK/HVFmNP93kDcJis73q1uTwlhD32Xjz0rq MaBcpzlYB8OAu8rOuPag/MsIwKn7KnlcB3ALBum4rf27VAbIZSz0RHIWgddN+Ia0Pa3B amyhxPim6sbSSpCemN44b6es9K+wiuPSFk8hQERLe19YaqKT88N8O+wVSCKgutfVHkfW TpNTnMkGdyNLksJH3EAmYtVgtxOOPQ/4fFW0nVDHLzqufvCY1vf2mAIDOPlm2Q00dSHE 6Xv+pvn+OikwUd+/dTA+h8X2FN+tuIod6bSQgqa5L3+fPSBMlnRNRtvwR2UjnbMAUB32 BjKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=WYojn9LceY76Mlk7Y/OrkqTjskWrmEg3mDRct7IOXUk=; b=a9MsSWBkSPORn01UO1rVfzJP0wqJ8hOuRQgKR6DUqfoXw81r1kj4GQQRrO6oB77mMd wr9d1+3EVWicbzTqqBH3ToKK0jME5ivZ3Co9bTn8tppkI4SvqU7Wu18z2H0Q23JfTtLq kal2EJXkLKFlNO+XPyoIxqHtyezchCl7Fv8l/Cf3v8bYOof7nzUk4FprERGkRAODnPed sQofXWEOPZEIRHJaZ7/U84LqhEvUXMqYZX2vTJ1hhwoyfAzVCgHFgD/wQ81Md/VzfvC+ Dyk/X7R7zxAfxmbQQD/2N8/bKcZX/rPQUk8WwMAv29ZW2RsaSkodOiJ8JGB4CbB5Ory8 6ULw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="BBrlzK/4"; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bj10si1912984plb.23.2019.08.07.02.44.56; Wed, 07 Aug 2019 02:44:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="BBrlzK/4"; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727464AbfHGJo4 (ORCPT + 5 others); Wed, 7 Aug 2019 05:44:56 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:51096 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726612AbfHGJo4 (ORCPT ); Wed, 7 Aug 2019 05:44:56 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x779ioO7102937; Wed, 7 Aug 2019 04:44:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1565171090; bh=WYojn9LceY76Mlk7Y/OrkqTjskWrmEg3mDRct7IOXUk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BBrlzK/4ZjX/bMNgogTjSTtX1euRW11CG3ZBYen8IAbGG9eHMkgOEmQZltrcHa5gC 1hY1s5zdLjyE7mGAzZixVUD6VRJNP8MwTDX9fxRLqPzZUnM/haFhqITRrdSzYRv84l 0hhtOh+U/fcOEiUw8I4c0nsrHAKPCwnqCYs9h2i0= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x779iovK067638 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 Aug 2019 04:44:50 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 7 Aug 2019 04:44:50 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 7 Aug 2019 04:44:50 -0500 Received: from gomoku.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x779imdS037583; Wed, 7 Aug 2019 04:44:49 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 1/3] ARM: OMAP4+: remove pdata quirks for omap4+ iommus Date: Wed, 7 Aug 2019 12:44:39 +0300 Message-ID: <1565171081-7899-2-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1565171081-7899-1-git-send-email-t-kristo@ti.com> References: <1565171081-7899-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org IOMMU driver will be using ti-sysc bus driver for power management control going forward, and the pdata quirks are not needed for anything anymore. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/pdata-quirks.c | 12 ------------ 1 file changed, 12 deletions(-) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 6c6f8fc..58fb0de 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -419,14 +419,6 @@ static void __init omap3_pandora_legacy_init(void) } #endif /* CONFIG_ARCH_OMAP3 */ -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) -static struct iommu_platform_data omap4_iommu_pdata = { - .reset_name = "mmu_cache", - .assert_reset = omap_device_assert_hardreset, - .deassert_reset = omap_device_deassert_hardreset, -}; -#endif - #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX) static struct wkup_m3_platform_data wkup_m3_data = { .reset_name = "wkup_m3", @@ -642,10 +634,6 @@ static void __init omap3_mcbsp_init(void) {} &wkup_m3_data), #endif #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) - OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu", - &omap4_iommu_pdata), - OF_DEV_AUXDATA("ti,omap4-iommu", 0x55082000, "55082000.mmu", - &omap4_iommu_pdata), OF_DEV_AUXDATA("ti,omap4-smartreflex-iva", 0x4a0db000, "4a0db000.smartreflex", &omap_sr_pdata[OMAP_SR_IVA]), OF_DEV_AUXDATA("ti,omap4-smartreflex-core", 0x4a0dd000, From patchwork Wed Aug 7 09:44:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 170741 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp6888637ile; Wed, 7 Aug 2019 02:44:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqzBMVJ0kmuJuSRP7GsDYzCzTJ+EbGnKJuUFAB0/kZLkOYAG8NPKK2KViF+gTvJXAbywKNMP X-Received: by 2002:a17:902:f301:: with SMTP id gb1mr7243548plb.292.1565171097139; Wed, 07 Aug 2019 02:44:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565171097; cv=none; d=google.com; s=arc-20160816; b=cUfDHn6529PTrduzFvlrsZoipZYQQ50tQyi9XeZs5fgUoS/SqPbEgSURmQl5zME0W2 7+g7zIwgcDy8r2PWGxAfoNxNkEK9qiH8/vwIobatQVWrMplJLyVUe5qrLEzCPpmpVN2X xN0owdn0QR/IsucAXhqmReGcC7fuTX7oWSR4x2gb1vbegj4lMGE0GGuDNyGDwarLC2FU N2dBWFlvhREm5oiZivRxp+DAFvU+HdMww6rl9I0J0y//J0WA6zgyAHQS4OPwet1MedU2 wCmoOyHpSTimyTSSAm4wtHn4F7kEcE5T1pyJ3a8n42jDD3lN6tMBAnr02/FlgF+S4qMP HHHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=DET4bLd9R6fJVFl04ZsNlYyjILosap4hxhkL44UmIlI=; b=rDQlrvD2cnDigfRPKAN8faJjWt67RslI7hkqze+L1UGetseYbhxB73NUlgSEw7CC1o zWyZKn6Eu593+XajSfEH8oOrv7lgiPc46BQjRFVRyUr7Zd/H0+gMdEjZbJi+ewE9DDKB ZBxJoFfQH5oj2s6fuq4jebk/j/rHhSaDLnpB274Skgy7u+woZG8TmACd+pqLscCeKzwA UZR3WgIKendBScKvwvfDM+ncnY/TIrvUY7oeNDmtwBvmW2lRCwxErCmGHG0UtQ7GP/UV iPvy9yYI1jyuiFOCTBzqrSABkUzxo/oAToqltmK5LSPVl2WFr2hm2ZjPQtlhR6BpvCi8 7LRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KJh+qigm; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bj10si1912984plb.23.2019.08.07.02.44.56; Wed, 07 Aug 2019 02:44:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KJh+qigm; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726612AbfHGJo4 (ORCPT + 5 others); Wed, 7 Aug 2019 05:44:56 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:51098 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727275AbfHGJo4 (ORCPT ); Wed, 7 Aug 2019 05:44:56 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x779iq4W102943; Wed, 7 Aug 2019 04:44:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1565171092; bh=DET4bLd9R6fJVFl04ZsNlYyjILosap4hxhkL44UmIlI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KJh+qigmaKoGPWysJ3NGk5QazzoRwLetG1Q0ypFMcdyJVsHcyDbsC/dnKeFyLRdIQ chvb9vqDB7VkR5YfaFHfweK1n4o7uaQswm06nW4OLvVB2vgMKwB7/yx2fDIXXpsc/b 97XpoMFEkwA/DUPOgfK2m/6L42olrC2HIf8Qt/Kc= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x779iqFh067651 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 7 Aug 2019 04:44:52 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 7 Aug 2019 04:44:51 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 7 Aug 2019 04:44:51 -0500 Received: from gomoku.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x779imdT037583; Wed, 7 Aug 2019 04:44:50 -0500 From: Tero Kristo To: , CC: , Subject: [PATCH 2/3] ARM: OMAP2+: Add workaround for DRA7 DSP MStandby errata i879 Date: Wed, 7 Aug 2019 12:44:40 +0300 Message-ID: <1565171081-7899-3-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1565171081-7899-1-git-send-email-t-kristo@ti.com> References: <1565171081-7899-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: Suman Anna Errata Title: i879: DSP MStandby requires CD_EMU in SW_WKUP Description: The DSP requires the internal emulation clock to be actively toggling in order to successfully enter a low power mode via execution of the IDLE instruction and PRCM MStandby/Idle handshake. This assumes that other prerequisites and software sequence are followed. Workaround: The emulation clock to the DSP is free-running anytime CCS is connected via JTAG debugger to the DSP subsystem or when the CD_EMU clock domain is set in SW_WKUP mode. The CD_EMU domain can be set in SW_WKUP mode via the CM_EMU_CLKSTCTRL [1:0]CLKTRCTRL field. Implementation: This patch implements this workaround by denying the HW_AUTO mode for the EMU clockdomain during the power-up of any DSP processor and re-enabling the HW_AUTO mode during the shutdown of the last DSP processor (actually done during the enabling and disabling of the respective DSP MDMA MMUs). Reference counting has to be used to manage the independent sequencing between the multiple DSP processors. This switching is done at runtime rather than a static clockdomain flags value to meet the target power domain state for the EMU power domain during suspend. Note that the DSP MStandby behavior is not consistent across all boards prior to this fix. Please see commit 45f871eec6c0 ("ARM: OMAP2+: Extend DRA7 IPU1 MMU pdata quirks to DSP MDMA MMUs") for details. Signed-off-by: Suman Anna --- arch/arm/mach-omap2/omap-iommu.c | 43 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 40 insertions(+), 3 deletions(-) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index 1392a5b..8f6b6b8 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -19,14 +19,43 @@ #include "omap_hwmod.h" #include "omap_device.h" +#include "clockdomain.h" #include "powerdomain.h" +static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev, + bool enable) +{ + static struct clockdomain *emu_clkdm; + static DEFINE_SPINLOCK(emu_lock); + static atomic_t count; + struct device_node *np = pdev->dev.of_node; + + if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) + return; + + if (!emu_clkdm) { + emu_clkdm = clkdm_lookup("emu_clkdm"); + if (WARN_ON_ONCE(!emu_clkdm)) + return; + } + + spin_lock(&emu_lock); + + if (enable && (atomic_inc_return(&count) == 1)) + clkdm_deny_idle(emu_clkdm); + else if (!enable && (atomic_dec_return(&count) == 0)) + clkdm_allow_idle(emu_clkdm); + + spin_unlock(&emu_lock); +} + int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, u8 *pwrst) { struct powerdomain *pwrdm; struct omap_device *od; u8 next_pwrst; + int ret = 0; od = to_omap_device(pdev); if (!od) @@ -39,13 +68,21 @@ int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, if (!pwrdm) return -EINVAL; - if (request) + if (request) { *pwrst = pwrdm_read_next_pwrst(pwrdm); + omap_iommu_dra7_emu_swsup_config(pdev, true); + } if (*pwrst > PWRDM_POWER_RET) - return 0; + goto out; next_pwrst = request ? PWRDM_POWER_ON : *pwrst; - return pwrdm_set_next_pwrst(pwrdm, next_pwrst); + ret = pwrdm_set_next_pwrst(pwrdm, next_pwrst); + +out: + if (!request) + omap_iommu_dra7_emu_swsup_config(pdev, false); + + return ret; } From patchwork Wed Aug 7 09:44:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 170743 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp6888690ile; Wed, 7 Aug 2019 02:45:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqyjDITtCLpuOHZrA2Gp0FTpiDq+X4hTPWxF03VHNq3kRiXXsynIyxMfU6cLvAWpyePZ6Q/o X-Received: by 2002:a62:cdc8:: with SMTP id o191mr8462989pfg.74.1565171100675; Wed, 07 Aug 2019 02:45:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565171100; cv=none; d=google.com; s=arc-20160816; b=FcLBBp7osAic63zeAp9LPX/TLNg5RQO5qwph5a8dWXgSd2hA87nEwYsISpCf4msAm9 jVZ5hICt9mwETUK6b/BIo4P5qeKa2S4RpXj0hyATh/Bz1XaOYiM0msYa4KuIRC0sHLUI aobefFvg/QS+OTwSSidCW+aG4vxjiiqWq/YWaqSejWVRhYG0EGqaGYNJK+3uBa/A2/ef brS+uhVZ5zAmnMjhjbZBRPHDSsSmhfIwOp3UDhvEAxEQvad1alOnlpVcdMcORjkpsV1D R9st41vXllmeMIS40tpGAHTQ5dwUtEShGFAAwdALlg20lgrVwowU5tTXqSFglZVPVAZG +0Xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=D1ABe6UuCy+19McIAI+7AapSCDTHrhabTxuSk376CL4=; b=cU7UwouFMlOg/c2oT9aIO8IYN68iY7uncOfVw70UPO5uIhf+ml6lFJf9VifgwfxZUm SIwOJgo5LisnZ7aQbCYTrb+DQq/b2joAwALN3i4Ajy/IoGeye46+EATqp0Q0fxz5bVLI npGjeCjYqwZzCHXw6pVfFckN0DvDJBmTcd0zZiJCNfobPWrQt1crMrQpSSJysX8lCxt7 oJZp4bVNen2yG9zdeN0l7weknitjmgAxIVQehrx+WoQqL0PnbwQLtdLxqVDpS2h4B11s f0TLCLHNi7ieo2//hUXJ/s2gTzNgT0yE7WpJtniHnUtgkyKgEuT15HU/4ucYqUpUnbPl brpQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=GWKMwM7l; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/omap-iommu.c | 99 ++++++++++++++++++++++++++++++++-------- 1 file changed, 80 insertions(+), 19 deletions(-) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c index 8f6b6b8..f8cbf6b 100644 --- a/arch/arm/mach-omap2/omap-iommu.c +++ b/arch/arm/mach-omap2/omap-iommu.c @@ -16,19 +16,27 @@ #include #include +#include +#include -#include "omap_hwmod.h" -#include "omap_device.h" #include "clockdomain.h" #include "powerdomain.h" +struct pwrdm_link { + struct device *dev; + struct powerdomain *pwrdm; + struct list_head node; +}; + +static DEFINE_SPINLOCK(iommu_lock); +static struct clockdomain *emu_clkdm; +static atomic_t emu_count; + static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev, bool enable) { - static struct clockdomain *emu_clkdm; - static DEFINE_SPINLOCK(emu_lock); - static atomic_t count; struct device_node *np = pdev->dev.of_node; + unsigned long flags; if (!of_device_is_compatible(np, "ti,dra7-dsp-iommu")) return; @@ -39,34 +47,87 @@ static void omap_iommu_dra7_emu_swsup_config(struct platform_device *pdev, return; } - spin_lock(&emu_lock); + spin_lock_irqsave(&iommu_lock, flags); - if (enable && (atomic_inc_return(&count) == 1)) + if (enable && (atomic_inc_return(&emu_count) == 1)) clkdm_deny_idle(emu_clkdm); - else if (!enable && (atomic_dec_return(&count) == 0)) + else if (!enable && (atomic_dec_return(&emu_count) == 0)) clkdm_allow_idle(emu_clkdm); - spin_unlock(&emu_lock); + spin_unlock_irqrestore(&iommu_lock, flags); +} + +static struct powerdomain *_get_pwrdm(struct device *dev) +{ + struct clk *clk; + struct clk_hw_omap *hwclk; + struct clockdomain *clkdm; + struct powerdomain *pwrdm = NULL; + struct pwrdm_link *entry; + unsigned long flags; + static LIST_HEAD(cache); + + spin_lock_irqsave(&iommu_lock, flags); + + list_for_each_entry(entry, &cache, node) { + if (entry->dev == dev) { + pwrdm = entry->pwrdm; + break; + } + } + + spin_unlock_irqrestore(&iommu_lock, flags); + + if (pwrdm) + return pwrdm; + + clk = of_clk_get(dev->of_node->parent, 0); + if (!clk) { + dev_err(dev, "no fck found\n"); + return NULL; + } + + hwclk = to_clk_hw_omap(__clk_get_hw(clk)); + clk_put(clk); + if (!hwclk || !hwclk->clkdm_name) { + dev_err(dev, "no hwclk data\n"); + return NULL; + } + + clkdm = clkdm_lookup(hwclk->clkdm_name); + if (!clkdm) { + dev_err(dev, "clkdm not found: %s\n", hwclk->clkdm_name); + return NULL; + } + + pwrdm = clkdm_get_pwrdm(clkdm); + if (!pwrdm) { + dev_err(dev, "pwrdm not found: %s\n", clkdm->name); + return NULL; + } + + entry = kmalloc(sizeof(*entry), GFP_KERNEL); + if (entry) { + entry->dev = dev; + entry->pwrdm = pwrdm; + spin_lock_irqsave(&iommu_lock, flags); + list_add(&entry->node, &cache); + spin_unlock_irqrestore(&iommu_lock, flags); + } + + return pwrdm; } int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request, u8 *pwrst) { struct powerdomain *pwrdm; - struct omap_device *od; u8 next_pwrst; int ret = 0; - od = to_omap_device(pdev); - if (!od) - return -ENODEV; - - if (od->hwmods_cnt != 1) - return -EINVAL; - - pwrdm = omap_hwmod_get_pwrdm(od->hwmods[0]); + pwrdm = _get_pwrdm(&pdev->dev); if (!pwrdm) - return -EINVAL; + return -ENODEV; if (request) { *pwrst = pwrdm_read_next_pwrst(pwrdm);