From patchwork Fri Oct 13 10:14:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Teja Kundanala X-Patchwork-Id: 733464 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A58E11C96 for ; Fri, 13 Oct 2023 10:15:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="RYIIwgd8" Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2075.outbound.protection.outlook.com [40.107.244.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94D47BB; Fri, 13 Oct 2023 03:15:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=DViq1alVTxNkvoWNLBD+OEYBIDwGTo8T/TP9XVENZ+wXLRhnWtjeL1q7PwoDZ2kszVAUqcwj0KzlbbOtGaWkiPSOOF1s9/gMYn5aBskbzhOXD4wzR6i9mtZBqh5ZYy8UuSgw2kbC/PRVCU2XKuAtFMoYGXphmmmYULISt9Wfo46w6FTIhd+UoKJlvF2Rma7pSnr3FcJFl+Ja4UC8rt7J00e8yXxMgAlMp8qJBewohETGnVW/a5exvHaZCfjMP89XMyhQ337lSuR75o1UpHkXnahk7UGC5HcnvfpYlI2Aexgc2Vh5xF9Zsw/3m1Lfvann/Jh5JGqE5nsBQmJ28rL3JQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sboTPLMsvuXH+DRirYYy6pBrX+DY9o8mpm7Qul25hFY=; b=EpTtOKNP+LFrGoO5uHLZX91YTzRi2BDitq9WiuvAC9xDfbMggKo8+cT1SLfyCUa4WZei5z6uhmySho1gXxzYLTB7cDvOOpPF5YfjDvqmP8COvvlhLJ/TSvdWoEmE68I7vld1JUmnacnlxSA/FuUIOTwpYpGffFjGs8+tefrwptT8O9z0myxhDX3MB+pVF8Nh4sQ1MCliefKet6dVMB6N4dYzYbCfPY/wBUaQ9h3ECXDkOwvcOVXHDEWsbaq8R7CVZxINls4WzCDUHZPwEqDAhk07xmonCKGqNisRqsvXr5mbf3AkzUu649K3CeTrremi1z9tVdNZo2yJ8zRs875tNA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=linaro.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sboTPLMsvuXH+DRirYYy6pBrX+DY9o8mpm7Qul25hFY=; b=RYIIwgd8IHFPqQXFaopHCZTInMAbREvFST5uU/0TBOCePsAUaEko7WnJgKZKWa+ffUfpA++GsHosk6VdHneWCIlYV2fdVxWM/d4xRP5CqmzbQhm3J4KQ4RLmfz1F3o2Bj+rM7Gp8+M/djTxm44shKHhtFcH0XqqtewDMDCaXe6c= Received: from BL1P223CA0029.NAMP223.PROD.OUTLOOK.COM (2603:10b6:208:2c4::34) by DS0PR12MB7898.namprd12.prod.outlook.com (2603:10b6:8:14c::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.43; Fri, 13 Oct 2023 10:15:18 +0000 Received: from BL6PEPF0001AB53.namprd02.prod.outlook.com (2603:10b6:208:2c4:cafe::60) by BL1P223CA0029.outlook.office365.com (2603:10b6:208:2c4::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.29 via Frontend Transport; Fri, 13 Oct 2023 10:15:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by BL6PEPF0001AB53.mail.protection.outlook.com (10.167.241.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Fri, 13 Oct 2023 10:15:18 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 13 Oct 2023 05:15:15 -0500 Received: from xhdharshah40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 13 Oct 2023 05:15:13 -0500 From: Praveen Teja Kundanala To: , , , , , , CC: Subject: [PATCH 1/5] firmware: xilinx: Add ZynqMP efuse access API Date: Fri, 13 Oct 2023 15:44:46 +0530 Message-ID: <20231013101450.573-2-praveen.teja.kundanala@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20231013101450.573-1-praveen.teja.kundanala@amd.com> References: <20231013101450.573-1-praveen.teja.kundanala@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB53:EE_|DS0PR12MB7898:EE_ X-MS-Office365-Filtering-Correlation-Id: 65a0d7cd-a37f-443e-6603-08dbcbd54cd7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: P4Pd2evyjJaCZp1FHojbRclJnQQvyiWeFpM/Y3aTIoccgb7PDrIFEnmUKlq9tjuzJ6abg920zN5wYbve4jypdP3alv3VIEeJVsayhyWn4QkzGpA6F7qS4I1incVzdwdivY8xeDWkrHwDBN+brmxfax2Uz2C0vLiPJxQESPkN5dgc5//ibQEc6GaBkkybvq1LAq2w9TmnMNGM+rD1RI6HjUVZSFExmjKMNZpPb3Xio6OfDMqFy9vRo8E7O0J/5UJLvPMvGsiBX9nBNSU1Q4l3HcU1ERjXm7mweZ9eY3T/uQy2LcadFCUH7juDEOUba63zSVGSe3XMLJkeVv6Z0HSGryZ1RuzfPFdAEtiW9QXeRjsXpkTSUqHxRXbtpYUghuT203ogRCKdYHyqcwPG0wDfFh2LkMIznQpU0Thk9SJm5FBUi2suluefybIre7VX9cOgtwikPlNIRacKQrQrQUx1GIG7h/1EoSRnqvmWLeQPDnlYe+nGFQ0ilyleTdZC1A/jm4XjJJJkELyvpuiisSz0tL+6TSuidROpDPX5TzyQNFzNWc52FxOiP4W8iSfvsSCkvL5fdaucXTF2DgTWGirp2YgOUqQM058Neqfdla7mJP40qY3HbKdOnWfaDtO9N7EB1uhEkagd5abvrM22hYIiIMCI3bVIpG19HBYr5wiw1VozndwHzUZiJXGC2ONYhsm5IOUQUrtBARXiN+6JUpdr6iVkIZd5vyM6HJcioaAm7KJ+KXS5mXLDvfr2nNHmvoJgtMlOqb/7ctA/3MbS5pJlJg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(136003)(376002)(346002)(396003)(230922051799003)(1800799009)(64100799003)(451199024)(186009)(82310400011)(46966006)(40470700004)(36840700001)(110136005)(8936002)(70586007)(4326008)(5660300002)(8676002)(70206006)(316002)(41300700001)(40460700003)(2906002)(336012)(26005)(83380400001)(356005)(81166007)(82740400003)(47076005)(36860700001)(2616005)(40480700001)(86362001)(1076003)(103116003)(426003)(36756003)(6666004)(478600001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2023 10:15:18.0401 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 65a0d7cd-a37f-443e-6603-08dbcbd54cd7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB53.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7898 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add zynqmp_pm_efuse_access API in the ZynqMP firmware for read/write access of efuse memory. Signed-off-by: Praveen Teja Kundanala --- drivers/firmware/xilinx/zynqmp.c | 25 +++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index f8c4eb2b43f8..b0f6272e0844 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -3,6 +3,7 @@ * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. + * Copyright (C), 2022 - 2023 Advanced Micro Devices, Inc. * * Michal Simek * Davorin Mista @@ -1390,6 +1391,30 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out) } EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine); +/** + * zynqmp_pm_efuse_access - Provides access to efuse memory. + * @address: Address of the efuse params structure + * @out: Returned output value + * + * Return: Returns status, either success or error code. + */ +int zynqmp_pm_efuse_access(const u64 address, u32 *out) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!out) + return -EINVAL; + + ret = zynqmp_pm_invoke_fn(PM_EFUSE_ACCESS, upper_32_bits(address), + lower_32_bits(address), 0, 0, + ret_payload); + *out = ret_payload[1]; + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_pm_efuse_access); + /** * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash * @address: Address of the data/ Address of output buffer where diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 9dda7d9898ff..721cebae3f14 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -3,6 +3,7 @@ * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2021 Xilinx + * Copyright (C), 2022 - 2023 Advanced Micro Devices, Inc. * * Michal Simek * Davorin Mista @@ -130,6 +131,7 @@ enum pm_api_id { PM_CLOCK_GETPARENT = 44, PM_FPGA_READ = 46, PM_SECURE_AES = 47, + PM_EFUSE_ACCESS = 53, PM_FEATURE_CHECK = 63, }; @@ -521,6 +523,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_aes_engine(const u64 address, u32 *out); +int zynqmp_pm_efuse_access(const u64 address, u32 *out); int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_get_status(u32 *value); @@ -714,6 +717,11 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) return -ENODEV; } +static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out) +{ + return -ENODEV; +} + static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags) { From patchwork Fri Oct 13 10:14:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Teja Kundanala X-Patchwork-Id: 733463 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9019711CA0 for ; Fri, 13 Oct 2023 10:15:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="DmwfaumX" Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2062.outbound.protection.outlook.com [40.107.243.62]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10AD4E7; Fri, 13 Oct 2023 03:15:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=am/NYtrscdYUL8uUO3uKRuUxmITOwoVYPT0pR4LCZgNDqmbs1US+nmphC3+xZ3SaViGxUqQC1mVsB3dVT12CE7jnkFdz9bThW6/fN6rsiJo27XIzOzQ6gQHDR5UlS/L0LIxFep1BBuD/nPeiAr6XZiEJqWdii5C3MJn2u8DeUwZml+otAtpLmB8TML9ZyP7Xp7TXlQPSEto3zBvQGpXl1dsLl21NtAmhrkZLEguav19OXyW9USNRR9UJmfiNfAF1g2tksrasi4idLI/dT23ukhv4jnzwlz9ACM17bfaOC/u6YtbpJYongCOwd5bRTLAdho/hpwVzq2JE/5MYNwSbLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=C3aiIK1J/uxTumQDI4aYsDbzu79nt0ZPEBe//iwH6XA=; b=ALC2ard9kgtKChIUZvEROUQT6vfwv+5g0Z8Gp2Am7I1cw81jRJ3rFo9wMeVahD9lTNWdf6XQT1JHQTHaTrw0m9tBYxZPkSKldJ9jScZpOuaqOjMmqcg0sfQy9AkJz1jPTvI24/6EmAiTb7UVnQMsFZ2fLi4lJN1vTeUE+vyTua0gG2qzTcO/gIzs7L+5NvR/Y7iRKyjFzHPqoO1PgKeSQsJNPWIueFYIFSruU63qMgMX9wOWLgtp/6Zi826/Cg7VH0w+9q+prFxbdc+6UVzKTDes710H42Js7ABlnaIjr0Gp0SNAsL2qEM6YJjiZTKU2JWWq3gYgjH+LxlT0LnbrSw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=linaro.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=C3aiIK1J/uxTumQDI4aYsDbzu79nt0ZPEBe//iwH6XA=; b=DmwfaumXRukRadSbF5ZZYXPy+WSy2NEBkRYxu+n9UcXUUqKVzgvRFrnmQDlgHiUZghl9NtbneBcZA4x40Ef59DGAvxNONJJFZ7XCRA5FD7vLJQT4pad6xm8TjJjPj6lgB6KTn1iePFSKgeY0db99yYc7Fkb4F8EIANcF1HYakBA= Received: from BL1PR13CA0271.namprd13.prod.outlook.com (2603:10b6:208:2bc::6) by DM4PR12MB8558.namprd12.prod.outlook.com (2603:10b6:8:187::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.44; Fri, 13 Oct 2023 10:15:22 +0000 Received: from BL02EPF0001A108.namprd05.prod.outlook.com (2603:10b6:208:2bc:cafe::99) by BL1PR13CA0271.outlook.office365.com (2603:10b6:208:2bc::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.27 via Frontend Transport; Fri, 13 Oct 2023 10:15:22 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF0001A108.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Fri, 13 Oct 2023 10:15:21 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 13 Oct 2023 05:15:21 -0500 Received: from xhdharshah40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 13 Oct 2023 05:15:19 -0500 From: Praveen Teja Kundanala To: , , , , , , CC: Subject: [PATCH 3/5] dt-bindings: nvmem: Add nodes for ZynqMP efuses Date: Fri, 13 Oct 2023 15:44:48 +0530 Message-ID: <20231013101450.573-4-praveen.teja.kundanala@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20231013101450.573-1-praveen.teja.kundanala@amd.com> References: <20231013101450.573-1-praveen.teja.kundanala@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A108:EE_|DM4PR12MB8558:EE_ X-MS-Office365-Filtering-Correlation-Id: b86d1ae2-23ee-43bf-ea18-08dbcbd54f32 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gXQjNCpoJUckor14poBIcmaQ+mRBtel2bh8kZMUYX2bzxBxZg3mJUCHL3fWsxkEu5g9AceN2PMjfXQ5s8Myp9IEBN99CcnEFMCOEPnvyibH4wdMj2itX0RD8KXRVK+bzsQ3ZEgwZcqJiFcTVIV1mJkO7K34MI/ZDIK5+GSV9wpc7aWsFyvDu7a5A4XRjESnvlcwjWtDg3KL6Lyhd1BxT0f1rgKqyX3jU/4xnSEZlP/07YQaMNjK+wbxufhvT9m+RVrMZzzuokJ7WjjHyGzUcJ4F9e2Hp5k5BAC+pimZ0EbxWrStqFyhvvZwXj2w1U/POnx1C0hCZemIzU8OAGgQv/+t1E7E48tKq5F30dXvnqEPsdwOesj6SdN/XuwMNfG4QgQpYibzKs+gi9OgDyracEGTAX6M3txvvjTjWodeHJmyf7Tx8WqkthJ1js1UNBrTIeqttCmJ5gN0p08eneatdOcFO1oWI+PpRaacZJn2KbAk5jhSxfU0umr0tbaD8FR6XPLd79pPlPzBUtNimI2c8LjMr9o8895T6T3dZy/mvO3rg7ugxj19qILj6z93CNgX0ddFuk8tBjqMLw1GbYe0qFxqDkDyATsbOG/8O3LC/4z8wlIVHf4nlhZlRiAVb2OhiE2yBOpaHYr3RseClKyPTd4BbFUbjTi53GvjE87VUHC2iFL2IT3bpcXX6bNJMbiK7Td2YrrvQqNbgi8d0dzN9iWJpoGjXZ/rPrnEIpqTyaXWfDEVvswi5giCZU8j+ojY1Z+BR9Ud+LVTvcElyz8ep6w== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(376002)(136003)(346002)(39860400002)(396003)(230922051799003)(186009)(1800799009)(451199024)(82310400011)(64100799003)(40470700004)(46966006)(36840700001)(70206006)(316002)(70586007)(110136005)(4326008)(8936002)(8676002)(41300700001)(36756003)(336012)(426003)(36860700001)(5660300002)(356005)(82740400003)(81166007)(2906002)(103116003)(26005)(47076005)(2616005)(478600001)(40460700003)(6666004)(1076003)(86362001)(40480700001)(83380400001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2023 10:15:21.9954 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b86d1ae2-23ee-43bf-ea18-08dbcbd54f32 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A108.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8558 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Added nodes for ZynqMP specific purpose and PUF user efuses Signed-off-by: Praveen Teja Kundanala --- .../bindings/nvmem/xlnx,zynqmp-nvmem.yaml | 213 +++++++++++++++++- 1 file changed, 212 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml index e03ed8c32537..d2a036a80cda 100644 --- a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml +++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml @@ -8,7 +8,7 @@ title: Zynq UltraScale+ MPSoC Non Volatile Memory interface description: | The ZynqMP MPSoC provides access to the hardware related data - like SOC revision, IDCODE. + like SOC revision, IDCODE and specific purpose efuses. maintainers: - Kalyani Akula @@ -43,6 +43,140 @@ patternProperties: required: - reg + "^efuse_dna@c$": + type: object + description: + This node is used to read DNA of ZynqMP SOC. Read-only. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_usr(0@20|1@24|2@28|3@2c|4@30|5@34|6@38|7@3c)$": + type: object + description: + Eight 32-bit user efuses. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_miscusr@40$": + type: object + description: + 32-bit MISC user efuse space. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_chash@50$": + type: object + description: + 32-bit PUF chash space. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_pufmisc@54$": + type: object + description: + 32-bit PUF MISC control space. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_sec@58$": + type: object + description: + 32-bit secure control space. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_spkid@5c$": + type: object + description: + 32-bit SPK ID. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_aeskey@60$": + type: object + description: + 256-bit aes key. Only Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_ppk0hash@a0$": + type: object + description: + 384-bit PPK0 hash. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_ppk1hash@d0$": + type: object + description: + 384-bit PPK1 hash. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_pufuser@100$": + type: object + description: + This node represents the 127(0x7F) 32-bit PUF(Physical Unclonable Function) + helper data efuses which are repurposed as user fuses. + Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + additionalProperties: false examples: @@ -56,4 +190,81 @@ examples: soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; + /* + * efuse memory access: + * all the efuse fields need to be read + * with the exact size specified in the node + */ + /* DNA */ + efuse_dna: efuse_dna@c { + reg = <0xc 0xc>; + }; + /* User 0 */ + efuse_usr0: efuse_usr0@20 { + reg = <0x20 0x4>; + }; + /* User 1 */ + efuse_usr1: efuse_usr1@24 { + reg = <0x24 0x4>; + }; + /* User 2 */ + efuse_usr2: efuse_usr2@28 { + reg = <0x28 0x4>; + }; + /* User 3 */ + efuse_usr3: efuse_usr3@2c { + reg = <0x2c 0x4>; + }; + /* User 4 */ + efuse_usr4: efuse_usr4@30 { + reg = <0x30 0x4>; + }; + /* User 5 */ + efuse_usr5: efuse_usr5@34 { + reg = <0x34 0x4>; + }; + /* User 6 */ + efuse_usr6: efuse_usr6@38 { + reg = <0x38 0x4>; + }; + /* User 7 */ + efuse_usr7: efuse_usr7@3c { + reg = <0x3c 0x4>; + }; + /* Misc user control bits */ + efuse_miscusr: efuse_miscusr@40 { + reg = <0x40 0x4>; + }; + /* PUF chash */ + efuse_chash: efuse_chash@50 { + reg = <0x50 0x4>; + }; + /* PUF misc */ + efuse_pufmisc: efuse_pufmisc@54 { + reg = <0x54 0x4>; + }; + /* SEC_CTRL */ + efuse_sec: efuse_sec@58 { + reg = <0x58 0x4>; + }; + /* SPK ID */ + efuse_spkid: efuse_spkid@5c { + reg = <0x5c 0x4>; + }; + /* AES Key */ + efuse_aeskey: efuse_aeskey@60 { + reg = <0x60 0x20>; + }; + /* PPK0 hash */ + efuse_ppk0hash: efuse_ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + /* PPK1 hash */ + efuse_ppk1hash: efuse_ppk1hash@d0 { + reg = <0xd0 0x30>; + }; + /* PUF user fuses */ + efuse_pufuser: efuse_pufuser@100 { + reg = <0x100 0x7F>; + }; }; From patchwork Fri Oct 13 10:14:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Teja Kundanala X-Patchwork-Id: 733462 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE69F11CA0 for ; Fri, 13 Oct 2023 10:15:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="amFS8TWi" Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2052.outbound.protection.outlook.com [40.107.220.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A82F3C2; Fri, 13 Oct 2023 03:15:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=bpZlH2hzfExyBEZYMPClob4L0sibfmXjmC43Q2VVhmz4kJKc9OFM20TPWVz13xuFFh0pEqgN41dyrEc68XTNdAASWtJUO5ThksnRIguS/cqcHOC6aRu8a/p1joOsjWkDPsz/pAOoiZ0gzZbfO9At855Eoedo1FToFQ21udFkNxYtQHIA0moDoZx5RU+yZhKRuTZTsryO7r4bc4caoQ8K+jW6AdxuEXTzhZ35fffDHg26w505CI2SIZJCVsu6WXI8DPVHSjsGR3Ep9j93GS9uKE81kun6uyGLphukzHAHhVxMm4dvE0cyXqWuxcdqHFSBr4MygYaSoB7SBtNo9CdCrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Cs3xTZXNQ9ThDGQ9UX4jqxxKmQCRuE/oJnMwNPqvfeo=; b=NNBDKXiy2AaTCcOOyAibwvBiwxWbWq+gmGNholI/eauxp9tYkCobAHtVbXpPn7Ox8uH72ahiDiCq4681iPcXRwa2YP3Qq5qdbGKaLSKby3Z5TRvqwJasSsnlbUqkeIVHhjV0xJ+NOqIchinlOiu6dfiOaPdx0Kfblmwy5UiTqGPmJYPYlHeBw5Ea/C6ko4P1VKnil9+cLxR30kPz5vTt361aP2ME1QvQSMQZpPj8AdX0cpflelh5HoMcsfGnt7WTDdL7yQHirzO4+PD9WUimnQZhYzPUAdAH7hatVbU0PbHsFAYSynPH6UBxn2k72YU3aa5GkOd4mK8SeGmLxlZz/Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=linaro.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Cs3xTZXNQ9ThDGQ9UX4jqxxKmQCRuE/oJnMwNPqvfeo=; b=amFS8TWiuPR+UKU3R6TD1tTjmqa/prrqwuPlGzsok+9eUm0PnS0q5X1+sd5AK9+iXuRnpNnJNKo89fNrQNhVNHTSOyUEaBUSlLA8ntODA/eiPQ3rMaeHqhoCC+luQqgXbauinJRUoLh+wrQKKWkaq2q8xbzUhLNNnGHjCEMui3o= Received: from BL1PR13CA0115.namprd13.prod.outlook.com (2603:10b6:208:2b9::30) by MW6PR12MB8708.namprd12.prod.outlook.com (2603:10b6:303:242::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.45; Fri, 13 Oct 2023 10:15:27 +0000 Received: from BL02EPF0001A101.namprd05.prod.outlook.com (2603:10b6:208:2b9:cafe::b0) by BL1PR13CA0115.outlook.office365.com (2603:10b6:208:2b9::30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.30 via Frontend Transport; Fri, 13 Oct 2023 10:15:27 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF0001A101.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.22 via Frontend Transport; Fri, 13 Oct 2023 10:15:27 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Fri, 13 Oct 2023 05:15:26 -0500 Received: from xhdharshah40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Fri, 13 Oct 2023 05:15:24 -0500 From: Praveen Teja Kundanala To: , , , , , , CC: Subject: [PATCH 5/5] nvmem: zynqmp_nvmem: Add support to access efuse Date: Fri, 13 Oct 2023 15:44:50 +0530 Message-ID: <20231013101450.573-6-praveen.teja.kundanala@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20231013101450.573-1-praveen.teja.kundanala@amd.com> References: <20231013101450.573-1-praveen.teja.kundanala@amd.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A101:EE_|MW6PR12MB8708:EE_ X-MS-Office365-Filtering-Correlation-Id: 95af8458-a558-4393-e6ae-08dbcbd55283 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9ye6Jh0PEaYddlE8RLprNQbkBw67gUtr7S0m3oqGAyVa9RCV3lJCiQK3o9qesByNe5h7K9PL3u5uWcq95DRWWQ0tfVN9LMPRGIB0IuF4mlXNTQ0xO+fDUQnMS31NrSHdeuq1NBMh2dmP4y3UbmV0cx8EHufnjHphxppl508++Ww5VhJh8FO2WVTxlN3J71VzXIAGp2zFg2uxfKThj/Ih9S9BwLuEtfIKI9+xRTXGVWH8bHo/T+NR6SejMCXGReifWx/Y7S9vKX5owAgaktQqmxVgaWRHjNybd06GlNlCwiJV2H9bKX+TXYgubGpjgi0rH3YLpJNafeFD3Pg5TrZ1QBdRXIWxewszWgCqai2lmuhRyJs0HN7oSowbQKB+whfBWgbr1Q1zRcAsgWW8yujWLSa4tSBnMjXaP4Fq9LYJvQXTG3243lFhHF78L2rVIWwCmrfH9NgaDlvaMvQiyJs2CUfjCzRJzr6niuLCniztREG05VbILpMSft6zPTh3zI+EwvOdodaJaVA2//FPEi4IAX3KTP0mryYHResHoiFBV2mX1NSbysH/oPO5fjgNLbBZqS6WWCZGtPuMnf4hG/T/HQusx6L83g5ef4lz+Zhvq/YWyMLGpruSvncCerv+UMXtWlCqPx0outMdebZvB9s9vKl9fzf515folcC53OqhxWBayZcVuP/uqjOLwgjBgUAust3Pp3U+WyIb3oP/wJAdIygcHWrmP74/YtwsT0M4hu4jY8K/ZekgkqDANbj5bmDINwm7Sliu4WicN0HaGFj7zw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(346002)(136003)(376002)(39860400002)(396003)(230922051799003)(1800799009)(64100799003)(82310400011)(451199024)(186009)(46966006)(40470700004)(36840700001)(478600001)(316002)(82740400003)(6666004)(70586007)(110136005)(70206006)(4326008)(41300700001)(8676002)(8936002)(103116003)(426003)(356005)(81166007)(1076003)(26005)(40480700001)(2616005)(336012)(36860700001)(2906002)(5660300002)(83380400001)(40460700003)(36756003)(47076005)(86362001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2023 10:15:27.5436 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95af8458-a558-4393-e6ae-08dbcbd55283 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A101.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8708 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Add support to read/write efuse memory map of ZynqMP Below are the offsets of ZynqMP efuse memory map 0 - SOC version(read only) 0xC - 0xFC -ZynqMP specific purpose efuses 0x100 - 0x17F - Physical Unclonable Function(PUF) efuses repurposed as user efuses Signed-off-by: Praveen Teja Kundanala --- drivers/nvmem/zynqmp_nvmem.c | 216 ++++++++++++++++++++++++++++++----- 1 file changed, 185 insertions(+), 31 deletions(-) diff --git a/drivers/nvmem/zynqmp_nvmem.c b/drivers/nvmem/zynqmp_nvmem.c index f49bb9a26d05..e6123a32268a 100644 --- a/drivers/nvmem/zynqmp_nvmem.c +++ b/drivers/nvmem/zynqmp_nvmem.c @@ -1,8 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Xilinx, Inc. + * Copyright (C), 2022 - 2023 Advanced Micro Devices, Inc. */ +#include #include #include #include @@ -10,36 +12,190 @@ #include #define SILICON_REVISION_MASK 0xF +#define P_USER_0_64_UPPER_MASK GENMASK(31, 16) +#define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0) +#define WORD_INBYTES 4 +#define SOC_VER_SIZE 0x4 +#define EFUSE_MEMORY_SIZE 0x177 +#define UNUSED_SPACE 0x8 +#define ZYNQMP_NVMEM_SIZE (SOC_VER_SIZE + UNUSED_SPACE + \ + EFUSE_MEMORY_SIZE) +#define SOC_VERSION_OFFSET 0x0 +#define EFUSE_START_OFFSET 0xC +#define EFUSE_END_OFFSET 0xFC +#define EFUSE_PUF_START_OFFSET 0x100 +#define EFUSE_PUF_MID_OFFSET 0x140 +#define EFUSE_PUF_END_OFFSET 0x17F +#define EFUSE_NOT_ENABLED 29 -struct zynqmp_nvmem_data { - struct device *dev; - struct nvmem_device *nvmem; +/* + * efuse access type + */ +enum efuse_access { + EFUSE_READ = 0, + EFUSE_WRITE +}; + +/** + * struct xilinx_efuse - the basic structure + * @src: address of the buffer to store the data to be write/read + * @size: read/write word count + * @offset: read/write offset + * @flag: 0 - represents efuse read and 1- represents efuse write + * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write + * 1 - represents puf user fuse row number. + * + * this structure stores all the required details to + * read/write efuse memory. + */ +struct xilinx_efuse { + u64 src; + u32 size; + u32 offset; + enum efuse_access flag; + u32 pufuserfuse; }; -static int zynqmp_nvmem_read(void *context, unsigned int offset, - void *val, size_t bytes) +static int zynqmp_efuse_access(void *context, unsigned int offset, + void *val, size_t bytes, enum efuse_access flag, + unsigned int pufflag) { + struct device *dev = context; + struct xilinx_efuse *efuse; + dma_addr_t dma_addr; + dma_addr_t dma_buf; + size_t words = bytes / WORD_INBYTES; int ret; - int idcode, version; - struct zynqmp_nvmem_data *priv = context; - - ret = zynqmp_pm_get_chipid(&idcode, &version); - if (ret < 0) - return ret; + int value; + char *data; + + if (bytes % WORD_INBYTES != 0) { + dev_err(dev, "Bytes requested should be word aligned\n"); + return -EOPNOTSUPP; + } + + if (pufflag == 0 && offset % WORD_INBYTES) { + dev_err(dev, "Offset requested should be word aligned\n"); + return -EOPNOTSUPP; + } + + if (pufflag == 1 && flag == EFUSE_WRITE) { + memcpy(&value, val, bytes); + if ((offset == EFUSE_PUF_START_OFFSET || + offset == EFUSE_PUF_MID_OFFSET) && + value & P_USER_0_64_UPPER_MASK) { + dev_err(dev, "Only lower 4 bytes are allowed to be programmed in P_USER_0 & P_USER_64\n"); + return -EOPNOTSUPP; + } + + if (offset == EFUSE_PUF_END_OFFSET && + (value & P_USER_127_LOWER_4_BIT_MASK)) { + dev_err(dev, "Only MSB 28 bits are allowed to be programmed for P_USER_127\n"); + return -EOPNOTSUPP; + } + } + + efuse = dma_alloc_coherent(dev, sizeof(struct xilinx_efuse), + &dma_addr, GFP_KERNEL); + if (!efuse) + return -ENOMEM; - dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version); - *(int *)val = version & SILICON_REVISION_MASK; + data = dma_alloc_coherent(dev, sizeof(bytes), + &dma_buf, GFP_KERNEL); + if (!data) { + ret = -ENOMEM; + goto efuse_data_fail; + } + + if (flag == EFUSE_WRITE) { + memcpy(data, val, bytes); + efuse->flag = EFUSE_WRITE; + } else { + efuse->flag = EFUSE_READ; + } + + efuse->src = dma_buf; + efuse->size = words; + efuse->offset = offset; + efuse->pufuserfuse = pufflag; + + zynqmp_pm_efuse_access(dma_addr, (u32 *)&ret); + if (ret != 0) { + if (ret == EFUSE_NOT_ENABLED) { + dev_err(dev, "efuse access is not enabled\n"); + ret = -EOPNOTSUPP; + } else { + dev_err(dev, "Error in efuse read %x\n", ret); + ret = -EPERM; + } + goto efuse_access_err; + } + + if (flag == EFUSE_READ) + memcpy(val, data, bytes); +efuse_access_err: + dma_free_coherent(dev, sizeof(bytes), + data, dma_buf); +efuse_data_fail: + dma_free_coherent(dev, sizeof(struct xilinx_efuse), + efuse, dma_addr); + + return ret; +} - return 0; +static int zynqmp_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes) +{ + struct device *dev = context; + int ret; + int pufflag = 0; + int idcode; + int version; + + if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET) + pufflag = 1; + + switch (offset) { + /* Soc version offset is zero */ + case SOC_VERSION_OFFSET: + if (bytes != SOC_VER_SIZE) + return -EOPNOTSUPP; + + ret = zynqmp_pm_get_chipid((u32 *)&idcode, (u32 *)&version); + if (ret < 0) + return ret; + + dev_dbg(dev, "Read chipid val %x %x\n", idcode, version); + *(int *)val = version & SILICON_REVISION_MASK; + break; + /* Efuse offset starts from 0xc */ + case EFUSE_START_OFFSET ... EFUSE_END_OFFSET: + case EFUSE_PUF_START_OFFSET ... EFUSE_PUF_END_OFFSET: + ret = zynqmp_efuse_access(context, offset, val, + bytes, EFUSE_READ, pufflag); + break; + default: + *(u32 *)val = 0xDEADBEEF; + ret = 0; + break; + } + + return ret; } -static struct nvmem_config econfig = { - .name = "zynqmp-nvmem", - .owner = THIS_MODULE, - .word_size = 1, - .size = 1, - .read_only = true, -}; +static int zynqmp_nvmem_write(void *context, + unsigned int offset, void *val, size_t bytes) +{ + int pufflag = 0; + + if (offset < EFUSE_START_OFFSET || offset > EFUSE_PUF_END_OFFSET) + return -EOPNOTSUPP; + + if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET) + pufflag = 1; + + return zynqmp_efuse_access(context, offset, + val, bytes, EFUSE_WRITE, pufflag); +} static const struct of_device_id zynqmp_nvmem_match[] = { { .compatible = "xlnx,zynqmp-nvmem-fw", }, @@ -50,20 +206,18 @@ MODULE_DEVICE_TABLE(of, zynqmp_nvmem_match); static int zynqmp_nvmem_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct zynqmp_nvmem_data *priv; - - priv = devm_kzalloc(dev, sizeof(struct zynqmp_nvmem_data), GFP_KERNEL); - if (!priv) - return -ENOMEM; + struct nvmem_config econfig = {}; - priv->dev = dev; + econfig.name = "zynqmp-nvmem"; + econfig.owner = THIS_MODULE; + econfig.word_size = 1; + econfig.size = ZYNQMP_NVMEM_SIZE; econfig.dev = dev; + econfig.priv = dev; econfig.reg_read = zynqmp_nvmem_read; - econfig.priv = priv; - - priv->nvmem = devm_nvmem_register(dev, &econfig); + econfig.reg_write = zynqmp_nvmem_write; - return PTR_ERR_OR_ZERO(priv->nvmem); + return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig)); } static struct platform_driver zynqmp_nvmem_driver = {