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[93.65.126.31]) by smtp.googlemail.com with ESMTPSA id a6-20020a170906190600b009ad89697c86sm12341169eje.144.2023.10.13.04.02.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 04:02:06 -0700 (PDT) From: M0Rf30 To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: morf3089@gmail.com Subject: [PATCH] arm64: dts: qcom: msm8953: add SPI interfaces Date: Fri, 13 Oct 2023 13:01:36 +0200 Message-ID: <20231013110137.82439-1-morf3089@gmail.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Gianluca Boiano This change add spi_3, spi_5 and spi_6 interfaces to MSM8953 devices. Signed-off-by: Gianluca Boiano --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 102 ++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index e7de7632669a..cdfc38e562b6 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -726,6 +726,48 @@ i2c_8_sleep: i2c-8-sleep-state { bias-disable; }; + spi_3_default: spi-3-default-state { + pins = "gpio10", "gpio11"; + function = "blsp_spi3"; + drive-strength = <2>; + bias-disable; + }; + + spi_3_sleep: spi-3-sleep-state { + pins = "gpio10", "gpio11"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi_5_default: spi-5-default-state { + pins = "gpio18", "gpio19"; + function = "blsp_spi5"; + drive-strength = <2>; + bias-disable; + }; + + spi_5_sleep: spi-5-sleep-state { + pins = "gpio18", "gpio19"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + spi_6_default: spi-6-default-state { + pins = "gpio22", "gpio23"; + function = "blsp_spi6"; + drive-strength = <2>; + bias-disable; + }; + + spi_6_sleep: spi-6-sleep-state { + pins = "gpio22", "gpio23"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wcnss_pin_a: wcnss-active-state { wcss-wlan2-pins { @@ -1360,6 +1402,26 @@ i2c_3: i2c@78b7000 { status = "disabled"; }; + spi_3: spi@78b7000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x078b7000 0x600>; + interrupts = ; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; + dma-names = "tx", "rx"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi_3_default>; + pinctrl-1 = <&spi_3_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + i2c_4: i2c@78b8000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b8000 0x600>; @@ -1413,6 +1475,26 @@ i2c_5: i2c@7af5000 { status = "disabled"; }; + spi_5: spi@7af5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af5000 0x600>; + interrupts = ; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; + dma-names = "tx", "rx"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi_5_default>; + pinctrl-1 = <&spi_5_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + i2c_6: i2c@7af6000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af6000 0x600>; @@ -1433,6 +1515,26 @@ i2c_6: i2c@7af6000 { status = "disabled"; }; + spi_6: spi@7af6000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x07af6000 0x600>; + interrupts = ; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; + dma-names = "tx", "rx"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi_6_default>; + pinctrl-1 = <&spi_6_sleep>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + i2c_7: i2c@7af7000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af7000 0x600>;