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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 01/85] target/sparc: Set TCG_GUEST_DEFAULT_MO Date: Fri, 13 Oct 2023 14:27:22 -0700 Message-Id: <20231013212846.165724-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Always use TSO, per the Oracle 2015 manual. This is slightly less restrictive than the TCG_MO_ALL default, and happens to match the i386 model, which will eliminate a few extra barriers on that host. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/sparc/cpu.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index b3a98f1d74..9fc5c401d2 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -6,6 +6,29 @@ #include "exec/cpu-defs.h" #include "qemu/cpu-float.h" +/* + * From Oracle SPARC Architecture 2015: + * + * Compatibility notes: The PSO memory model described in SPARC V8 and + * SPARC V9 compatibility architecture specifications was never implemented + * in a SPARC V9 implementation and is not included in the Oracle SPARC + * Architecture specification. + * + * The RMO memory model described in the SPARC V9 specification was + * implemented in some non-Sun SPARC V9 implementations, but is not + * directly supported in Oracle SPARC Architecture 2015 implementations. + * + * Therefore always use TSO in QEMU. + * + * D.5 Specification of Partial Store Order (PSO) + * ... [loads] are followed by an implied MEMBAR #LoadLoad | #LoadStore. + * + * D.6 Specification of Total Store Order (TSO) + * ... PSO with the additional requirement that all [stores] are followed + * by an implied MEMBAR #StoreStore. + */ +#define TCG_GUEST_DEFAULT_MO (TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST) + #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 #else From patchwork Fri Oct 13 21:27:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733283 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678811wrv; Fri, 13 Oct 2023 14:33:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH7pp4w+F3AK/BzfSM27xJer3YPVACJ0F77jtbJSZKwwjocFFi6ZG2jEBMC1FfzDqZ31kuZ X-Received: by 2002:ad4:5be2:0:b0:66d:23e4:2ce8 with SMTP id k2-20020ad45be2000000b0066d23e42ce8mr4266986qvc.7.1697232792871; Fri, 13 Oct 2023 14:33:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232792; cv=none; d=google.com; s=arc-20160816; b=h84nI6WjEa1L2hLCQ+Ay2xQUrdXT6jpRn1waNiExdg1oSWWcAKmAsP9WGsJsIrXu7m 2Vb2XmSi3AAulklJ8RzGYXgsZxxUPl87IoMziPrLmkfs3sFDEMUwSrdCznlRo5OrHqZF QslvHCJwDUGQPONgTNNxtz1fU6i+MwfJrl+lgA/RmJI8ynBjZvXJVj/5moLr/gv4tvTi xZPHdO5xLspR8lldRI0D4qTJlYVNwdPBoOZL6+tvn5i8BBpXcZuGmUwOXy5URA1RX+4J 5DDpCRDjzvCd0FJ1hb4sttY3pHMditikxRNN3UO7YdteC5CKfNzWof9NMVfyc3EwvC1v vrPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jct63rFb48sV+5hvOO6V2h6GbxQHLHhpSIfreHhtJXo=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=C3/cbY8rw0+ijyXAOY471gYEo+doumqZHkvGjELEy7dcjyIp3xj5sXl9XM2PkFM6BA B7puPCNjNYv0iDHFpCt5wmFySaFTHoioM2ffXDMPyWvjw5yIR4vkKNRgfPD4FZn1lPoT sM+BM9GEHz4FK8ESgRQUEZKMHZUhBwiS9FwOm0CWbzyaWtQqyFajc3sTlngIju998uyf ARMtJkBPCkGFaZs4PPj3dGwoZCxBUV1VoKXvNLdfkuWE7ZWq/D7mpqGFTHfEyGn2L2sH sXj8QEqlkkplSwCnenA4pkFADZyTNz+6rRvPvCcsBFjMtslM8EPqBS4ZQuGEjHycmiz1 KHoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P6GG0pbW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 02/85] configs: Enable MTTCG for sparc, sparc64 Date: Fri, 13 Oct 2023 14:27:23 -0700 Message-Id: <20231013212846.165724-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This will be of small comfort to sparc64, because both sun4u and sun4v board models force max_cpus = 1. But it does enable actual smp for sparc32 sun4m. Signed-off-by: Richard Henderson --- configs/targets/sparc-softmmu.mak | 1 + configs/targets/sparc64-softmmu.mak | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak index 454eb35499..a5d9200382 100644 --- a/configs/targets/sparc-softmmu.mak +++ b/configs/targets/sparc-softmmu.mak @@ -1,2 +1,3 @@ TARGET_ARCH=sparc TARGET_BIG_ENDIAN=y +TARGET_SUPPORTS_MTTCG=y diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak index d3f8a3b710..36ca64ec41 100644 --- a/configs/targets/sparc64-softmmu.mak +++ b/configs/targets/sparc64-softmmu.mak @@ -1,3 +1,4 @@ TARGET_ARCH=sparc64 TARGET_BASE_ARCH=sparc TARGET_BIG_ENDIAN=y +TARGET_SUPPORTS_MTTCG=y From patchwork Fri Oct 13 21:27:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733296 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679261wrv; Fri, 13 Oct 2023 14:34:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG4iM7LWuaQ/gTJi4qSm57iqYS5gK5wbax/48FmA/RwxpsAplBMrXJOQ5wPPtx5H6NMFPnp X-Received: by 2002:a05:622a:249:b0:411:fc77:5863 with SMTP id c9-20020a05622a024900b00411fc775863mr37409893qtx.34.1697232878899; Fri, 13 Oct 2023 14:34:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232878; cv=none; d=google.com; s=arc-20160816; b=chJI47P2jm33eg98SEtRQfG2ZCrIYMEV69PLPF1WyB3yojlBhZg0xZR/ym2QdXADWy 7tecKn6AYqrg+7bJN1wz3NxfhMxdmrya3Dfk6RlxBVBcve8kwkcC+WanXf1tJp5RIQNu jbqKPvmLBcjfZAmhlIg70iB5/khVXnBa6f0ri9k9xNvVApZAkibhz0QSzVjrxiFgrSWL gIHpLJyQTGJoZAZ4A+Ki7zTXe6CC1+/8JY2LeCp3HwNFrbUIINqKtWF34LgCuSCVTPjV Y5ZLXbuoKuZVdw8XOinymkvz3M3dAOtyPymwzl/1xVvfIKNcS7upXLRaibHp4JXPiaIi V7Ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/NSD1a8m2pJ6AL+7QLFHG+z8njvoCbrnsh9v22o4fA4=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=fJfHm4fCSsHzGwYO9aVQxBGqlkW2pzo5ozYYusHa+prrt4fE/LmJgqFxGf2wdsXmH9 OmnKMIrixDXUmRXXwP3LykRauUSHvf3c8n0Iq96d5QPuJr9IcY2o+Dkvp+y7dd/eNH36 9CLIDaZCPGwrbEFt7W0FUdXQxKK989icNWHW+xaiRjpvAlyYNnoCikbo1aNPTjDWEIwM 8ZarEWbfXJ/QkmJJPX6zRAKlHPqozXSlMWJVPRJsAuHANGVBC1x/9lCOdE4br2AfVvFK Bc81TNdAABLRWNP6PfO2MRZNr3/knZ2lvw12mR6qrD24VJgClQZ6gWRwM3i2FehAiAOE zn7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vLbCXBWV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 03/85] target/sparc: Remove always-set cpu features Date: Fri, 13 Oct 2023 14:27:24 -0700 Message-Id: <20231013212846.165724-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The oldest supported cpu is the microsparc 1; all other cpus use CPU_DEFAULT_FEATURES. Remove all bits that are always set: FLOAT, SWAP, MUL, DIV, FLUSH, FSQRT, FMUL. Signed-off-by: Richard Henderson --- linux-user/sparc/target_syscall.h | 6 +--- target/sparc/cpu.h | 50 +++++++++++-------------------- target/sparc/cpu.c | 8 ++--- target/sparc/translate.c | 16 ---------- 4 files changed, 20 insertions(+), 60 deletions(-) diff --git a/linux-user/sparc/target_syscall.h b/linux-user/sparc/target_syscall.h index be77e44eb8..e421165357 100644 --- a/linux-user/sparc/target_syscall.h +++ b/linux-user/sparc/target_syscall.h @@ -50,11 +50,7 @@ static inline abi_ulong target_shmlba(CPUSPARCState *env) #ifdef TARGET_SPARC64 return MAX(TARGET_PAGE_SIZE, 16 * 1024); #else - if (!(env->def.features & CPU_FEATURE_FLUSH)) { - return 64 * 1024; - } else { - return 256 * 1024; - } + return 256 * 1024; #endif } diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 9fc5c401d2..bb8b65e47e 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -291,38 +291,24 @@ struct sparc_def_t { uint32_t maxtl; }; -#define CPU_FEATURE_FLOAT (1 << 0) -#define CPU_FEATURE_FLOAT128 (1 << 1) -#define CPU_FEATURE_SWAP (1 << 2) -#define CPU_FEATURE_MUL (1 << 3) -#define CPU_FEATURE_DIV (1 << 4) -#define CPU_FEATURE_FLUSH (1 << 5) -#define CPU_FEATURE_FSQRT (1 << 6) -#define CPU_FEATURE_FMUL (1 << 7) -#define CPU_FEATURE_VIS1 (1 << 8) -#define CPU_FEATURE_VIS2 (1 << 9) -#define CPU_FEATURE_FSMULD (1 << 10) -#define CPU_FEATURE_HYPV (1 << 11) -#define CPU_FEATURE_CMT (1 << 12) -#define CPU_FEATURE_GL (1 << 13) -#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */ -#define CPU_FEATURE_ASR17 (1 << 15) -#define CPU_FEATURE_CACHE_CTRL (1 << 16) -#define CPU_FEATURE_POWERDOWN (1 << 17) -#define CPU_FEATURE_CASA (1 << 18) +#define CPU_FEATURE_FLOAT128 (1 << 0) +#define CPU_FEATURE_VIS1 (1 << 1) +#define CPU_FEATURE_VIS2 (1 << 2) +#define CPU_FEATURE_FSMULD (1 << 3) +#define CPU_FEATURE_HYPV (1 << 4) +#define CPU_FEATURE_CMT (1 << 5) +#define CPU_FEATURE_GL (1 << 6) +#define CPU_FEATURE_TA0_SHUTDOWN (1 << 7) /* Shutdown on "ta 0x0" */ +#define CPU_FEATURE_ASR17 (1 << 8) +#define CPU_FEATURE_CACHE_CTRL (1 << 9) +#define CPU_FEATURE_POWERDOWN (1 << 10) +#define CPU_FEATURE_CASA (1 << 11) #ifndef TARGET_SPARC64 -#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ - CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ - CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ - CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD) +#define CPU_DEFAULT_FEATURES CPU_FEATURE_FSMULD #else -#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \ - CPU_FEATURE_MUL | CPU_FEATURE_DIV | \ - CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \ - CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 | \ - CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \ - CPU_FEATURE_CASA) +#define CPU_DEFAULT_FEATURES (CPU_FEATURE_VIS1 | CPU_FEATURE_VIS2 | \ + CPU_FEATURE_FSMULD | CPU_FEATURE_CASA) enum { mmu_us_12, // Ultrasparc < III (64 entry TLB) mmu_us_3, // Ultrasparc III (512 entry TLB) @@ -805,14 +791,12 @@ static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, if (env->pstate & PS_AM) { flags |= TB_FLAG_AM_ENABLED; } - if ((env->def.features & CPU_FEATURE_FLOAT) - && (env->pstate & PS_PEF) - && (env->fprs & FPRS_FEF)) { + if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { flags |= TB_FLAG_FPU_ENABLED; } flags |= env->asi << TB_FLAG_ASI_SHIFT; #else - if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) { + if (env->psref) { flags |= TB_FLAG_FPU_ENABLED; } #endif diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 8ba96ae225..117800d670 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -403,9 +403,7 @@ static const sparc_def_t sparc_defs[] = { .mmu_sfsr_mask = 0x00016fff, .mmu_trcr_mask = 0x0000003f, .nwindows = 7, - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | - CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | - CPU_FEATURE_FMUL, + .features = 0, }, { .name = "TI MicroSparc II", @@ -757,9 +755,7 @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) CPUSPARCState *env = &cpu->env; #if defined(CONFIG_USER_ONLY) - if ((env->def.features & CPU_FEATURE_FLOAT)) { - env->def.features |= CPU_FEATURE_FLOAT128; - } + env->def.features |= CPU_FEATURE_FLOAT128; #endif env->version = env->def.iu_version; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f92ff80ac8..7405173dea 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3488,11 +3488,9 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss); break; case 0x29: /* fsqrts */ - CHECK_FPU_FEATURE(dc, FSQRT); gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); break; case 0x2a: /* fsqrtd */ - CHECK_FPU_FEATURE(dc, FSQRT); gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); break; case 0x2b: /* fsqrtq */ @@ -3520,16 +3518,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); break; case 0x49: /* fmuls */ - CHECK_FPU_FEATURE(dc, FMUL); gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls); break; case 0x4a: /* fmuld */ - CHECK_FPU_FEATURE(dc, FMUL); gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); break; case 0x4b: /* fmulq */ CHECK_FPU_FEATURE(dc, FLOAT128); - CHECK_FPU_FEATURE(dc, FMUL); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); break; case 0x4d: /* fdivs */ @@ -3979,7 +3974,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; #endif case 0xa: /* umul */ - CHECK_IU_FEATURE(dc, MUL); gen_op_umul(cpu_dst, cpu_src1, cpu_src2); if (xop & 0x10) { tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); @@ -3988,7 +3982,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) } break; case 0xb: /* smul */ - CHECK_IU_FEATURE(dc, MUL); gen_op_smul(cpu_dst, cpu_src1, cpu_src2); if (xop & 0x10) { tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); @@ -4006,7 +3999,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; #endif case 0xe: /* udiv */ - CHECK_IU_FEATURE(dc, DIV); if (xop & 0x10) { gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1, cpu_src2); @@ -4017,7 +4009,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) } break; case 0xf: /* sdiv */ - CHECK_IU_FEATURE(dc, DIV); if (xop & 0x10) { gen_helper_sdiv_cc(cpu_dst, tcg_env, cpu_src1, cpu_src2); @@ -5069,8 +5060,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) goto jmp_insn; #endif case 0x3b: /* flush */ - if (!((dc)->def->features & CPU_FEATURE_FLUSH)) - goto unimp_flush; /* nop */ break; case 0x3c: /* save */ @@ -5188,7 +5177,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x0f: /* swap, swap register with memory. Also atomically */ - CHECK_IU_FEATURE(dc, SWAP); cpu_src1 = gen_load_gpr(dc, rd); gen_swap(dc, cpu_val, cpu_src1, cpu_addr, dc->mem_idx, MO_TEUL); @@ -5220,7 +5208,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 0x1f: /* swapa, swap reg with alt. memory. Also atomically */ - CHECK_IU_FEATURE(dc, SWAP); cpu_src1 = gen_load_gpr(dc, rd); gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn); break; @@ -5542,9 +5529,6 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) illegal_insn: gen_exception(dc, TT_ILL_INSN); return; - unimp_flush: - gen_exception(dc, TT_UNIMP_FLUSH); - return; #if !defined(CONFIG_USER_ONLY) priv_insn: gen_exception(dc, TT_PRIV_INSN); From patchwork Fri Oct 13 21:27:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733287 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679040wrv; Fri, 13 Oct 2023 14:33:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEismpWMSdF6kP2PxmQ4OvI8c1wrnhYSy0nkyB9FVFjy+v7iDd02EnZNbaWKVokTKg25ax1 X-Received: by 2002:a81:72c5:0:b0:59f:4bc3:3e9 with SMTP id n188-20020a8172c5000000b0059f4bc303e9mr27984388ywc.46.1697232834447; Fri, 13 Oct 2023 14:33:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232834; cv=none; d=google.com; s=arc-20160816; b=0iCLnNneeP4ixJXDFxC1Ue25s36I8tc08q7JcewBbMNEVFVDH94LnNwWuFfpE/gEmS QJY4ujQc6kr5bKX76bISyNLSJkIksDhRI/pOa2AlxtasOa3pOX5xp/IJg2kwp2xw+AUV YH/pAfyVZEXBh2+5UbSmx8IHxHSIZNBptAhBtbNaumqqV7avLdgwn28vI/QRTziCA/Hf raZKRVf2RNJT4jCMfRTq/+Z4w8yyJZ+TJCJZ5wje/8q1J/Rnveiv98fLNRYRSka9oGr4 AARcau+lVdhJnad0dQMhdZdnakK8+mwofP20RNbDaiJ5A2pQzf73yizp1Q949/xVDJIW 9s3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9VMW1A6SYv+Q5MYpjx2tuCSklX9h/fdNRcIcNEOnWHE=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=cBXx1PXd005XXCTGlULHO19Ahbr4e4VaZ8+ZsPJRl4oXxFNuk6lNyU4jltXePKGyOv gHL/BO3VzTQlanjjU4dRH64DihBKYebGcKbr0WZLRVf7IUlDDgnum1+hkdpC4ftVP4oz 5uM727leG6/uYq7GdCGXdF6YMmq1bouIiA6ypltKC3KoqxmbMcPeXRbRuBov3sXqZIbC /tM0iT81U8PJYAZoJ7c+ERzRZfiBLZhkFQ2jtlAQSuCasEYG7T0a0fGxvhKIUP0ttzVa 751uzzAQNwcvN84MEQaNlUbf+LITgelV5EhXwJ/myoI8M8ZoZCb4VVtufRB81+abMF4M QxQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HXSgGVj2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 04/85] target/sparc: Add decodetree infrastructure Date: Fri, 13 Oct 2023 14:27:25 -0700 Message-Id: <20231013212846.165724-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++ target/sparc/translate.c | 69 ++++++++++++++++++++++++++------------- target/sparc/meson.build | 3 ++ 3 files changed, 55 insertions(+), 22 deletions(-) create mode 100644 target/sparc/insns.decode diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode new file mode 100644 index 0000000000..5811a679db --- /dev/null +++ b/target/sparc/insns.decode @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: LGPL-2.0+ +# +# Sparc instruction decode definitions. +# Copyright (c) 2023 Richard Henderson + diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7405173dea..59e5289693 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2964,6 +2964,47 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) } #endif +/* Include the auto-generated decoder. */ +#include "decode-insns.c.inc" + +#define TRANS(NAME, AVAIL, FUNC, ...) \ + static bool trans_##NAME(DisasContext *dc, arg_##NAME *a) \ + { return avail_##AVAIL(dc) && FUNC(dc, __VA_ARGS__); } + +#define avail_ALL(C) true +#ifdef TARGET_SPARC64 +# define avail_32(C) false +# define avail_64(C) true +#else +# define avail_32(C) true +# define avail_64(C) false +#endif + +/* Default case for non jump instructions. */ +static bool advance_pc(DisasContext *dc) +{ + if (dc->npc & 3) { + switch (dc->npc) { + case DYNAMIC_PC: + case DYNAMIC_PC_LOOKUP: + dc->pc = dc->npc; + gen_op_next_insn(); + break; + case JUMP_PC: + /* we can do a static jump */ + gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); + dc->base.is_jmp = DISAS_NORETURN; + break; + default: + g_assert_not_reached(); + } + } else { + dc->pc = dc->npc; + dc->npc = dc->npc + 4; + } + return true; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -2972,7 +3013,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) goto nfpu_insn; /* before an instruction, dc->pc must be static */ -static void disas_sparc_insn(DisasContext * dc, unsigned int insn) +static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) { unsigned int opc, rs1, rs2, rd; TCGv cpu_src1, cpu_src2; @@ -5504,26 +5545,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) } break; } - /* default case for non jump instructions */ - if (dc->npc & 3) { - switch (dc->npc) { - case DYNAMIC_PC: - case DYNAMIC_PC_LOOKUP: - dc->pc = dc->npc; - gen_op_next_insn(); - break; - case JUMP_PC: - /* we can do a static jump */ - gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond); - dc->base.is_jmp = DISAS_NORETURN; - break; - default: - g_assert_not_reached(); - } - } else { - dc->pc = dc->npc; - dc->npc = dc->npc + 4; - } + advance_pc(dc); jmp_insn: return; illegal_insn: @@ -5614,7 +5636,10 @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) insn = translator_ldl(env, &dc->base, dc->pc); dc->base.pc_next += 4; - disas_sparc_insn(dc, insn); + + if (!decode(dc, insn)) { + disas_sparc_legacy(dc, insn); + } if (dc->base.is_jmp == DISAS_NORETURN) { return; diff --git a/target/sparc/meson.build b/target/sparc/meson.build index 48025cce76..c316773db6 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -1,4 +1,7 @@ +gen = decodetree.process('insns.decode') + sparc_ss = ss.source_set() +sparc_ss.add(gen) sparc_ss.add(files( 'cc_helper.c', 'cpu.c', From patchwork Fri Oct 13 21:27:26 2023 Content-Type: text/plain; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 05/85] target/sparc: Define AM_CHECK for sparc32 Date: Fri, 13 Oct 2023 14:27:26 -0700 Message-Id: <20231013212846.165724-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Define as false, which allows some ifdef removal. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 59e5289693..da6503e101 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -258,20 +258,21 @@ static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) #endif #endif -#ifdef TARGET_SPARC64 -#ifndef TARGET_ABI32 -#define AM_CHECK(dc) ((dc)->address_mask_32bit) +#if !defined(TARGET_SPARC64) +# define AM_CHECK(dc) false +#elif defined(TARGET_ABI32) +# define AM_CHECK(dc) true +#elif defined(CONFIG_USER_ONLY) +# define AM_CHECK(dc) false #else -#define AM_CHECK(dc) (1) -#endif +# define AM_CHECK(dc) ((dc)->address_mask_32bit) #endif static void gen_address_mask(DisasContext *dc, TCGv addr) { -#ifdef TARGET_SPARC64 - if (AM_CHECK(dc)) + if (AM_CHECK(dc)) { tcg_gen_andi_tl(addr, addr, 0xffffffffULL); -#endif + } } static TCGv gen_load_gpr(DisasContext *dc, int reg) @@ -1327,11 +1328,9 @@ static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); target_ulong target = dc->pc + offset; -#ifdef TARGET_SPARC64 if (unlikely(AM_CHECK(dc))) { target &= 0xffffffffULL; } -#endif if (cond == 0x0) { /* unconditional not taken */ if (a) { @@ -1367,11 +1366,9 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); target_ulong target = dc->pc + offset; -#ifdef TARGET_SPARC64 if (unlikely(AM_CHECK(dc))) { target &= 0xffffffffULL; } -#endif if (cond == 0x0) { /* unconditional not taken */ if (a) { From patchwork Fri Oct 13 21:27:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733258 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1677635wrv; Fri, 13 Oct 2023 14:29:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF0E6wuU2p/nqNX17izQMZmAPHdORDLUQo6TUAeOhklFj/LBq1u+M73dnZ7f+AhcwjhdFdH X-Received: by 2002:ad4:5310:0:b0:653:5960:8959 with SMTP id y16-20020ad45310000000b0065359608959mr27780269qvr.41.1697232579255; Fri, 13 Oct 2023 14:29:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232579; cv=none; d=google.com; s=arc-20160816; b=JGiS38Zqnm5orSN3OmWiePLRxCkEzhDTiYXCZOx1y/7MdRNB7YFDViKMwauQma1Ew8 zNgrOnwXVn43VaDeu2l/VvUN8EPEw4JB4D/QH4vCgE+mvjzhZ9RWsdLuG5jpr4YELZSW 6z80IwcXj/5FL9+CzfmzPLFrhCKUNwuOdLQytdS0+K6QS/f+Zo3s13xSl6LqktJ/wX9+ Seket2LyprD+myFRxCQzOyu3GtP84uotx+9Ar0Ax34zb/ZabMmSPh0AY+ZKhrpwHiQIB i7yJ2rYZvZJSG6PrQM6NblLvJcTO017JLgBcAN3Q3fdK8Ry7wJkGH4uyPCl4ZSD/WEvy 30qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PNIL4pN5JeJ3Z5YvYXuXP0cO4Np1EpKLwd4Cf3DmRtw=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=Vl+ITOy6EKLwG89yrbSByJ8qkmqj5y4Qb/YWla3nXn9izGGtwQrlTeTfSgxEJPpJ1F RFT20MQT+DvYI5ecUCOv08u4+7PgbeJQTOKhanUtCM0qGRfTAr69XA9p9lAcqa6rDK/n BNTG0+NamIRlh/J64YUyvsz2xo88kwreejtEAcOgHhrV9ytY1eP+LXP3mYZw5ImPZHgf vHWuGYbH6pDohAxFA1WHdx4xpk/kPbDROhkmK7FRgGUiOPkroNw4rNnXnaNztt/V1bpZ Hg8846QHOl4sc2GbI2km8PkNFD6zsZPOmLw3VKciX7N/Wr3UInrk5rhcsvNJAYnXS+Fn EA4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HrEO8QD4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 06/85] target/sparc: Move CALL to decodetree Date: Fri, 13 Oct 2023 14:27:27 -0700 Message-Id: <20231013212846.165724-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 33 ++++++++++++++++----------------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5811a679db..a5f5d2681e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -3,3 +3,4 @@ # Sparc instruction decode definitions. # Copyright (c) 2023 Richard Henderson +CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index da6503e101..bc1033231f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3002,6 +3002,20 @@ static bool advance_pc(DisasContext *dc) return true; } +static bool trans_CALL(DisasContext *dc, arg_CALL *a) +{ + target_long target = dc->pc + a->i * 4; + + gen_store_gpr(dc, 15, tcg_constant_tl(dc->pc)); + gen_mov_pc_npc(dc); + + if (unlikely(AM_CHECK(dc))) { + target &= 0xffffffffULL; + } + dc->npc = target; + return true; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3107,23 +3121,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) break; } break; - case 1: /*CALL*/ - { - target_long target = GET_FIELDs(insn, 2, 31) << 2; - TCGv o7 = gen_dest_gpr(dc, 15); - - tcg_gen_movi_tl(o7, dc->pc); - gen_store_gpr(dc, 15, o7); - target += dc->pc; - gen_mov_pc_npc(dc); -#ifdef TARGET_SPARC64 - if (unlikely(AM_CHECK(dc))) { - target &= 0xffffffffULL; - } -#endif - dc->npc = target; - } - goto jmp_insn; + case 1: + g_assert_not_reached(); /* in decodetree */ case 2: /* FPU & Logical Operations */ { unsigned int xop = GET_FIELD(insn, 7, 12); From patchwork Fri Oct 13 21:27:28 2023 Content-Type: text/plain; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 07/85] target/sparc: Move BPcc and Bicc to decodetree Date: Fri, 13 Oct 2023 14:27:28 -0700 Message-Id: <20231013212846.165724-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 120 +++++++++++++++++++------------------- 2 files changed, 64 insertions(+), 60 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a5f5d2681e..15cd975f4e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -3,4 +3,8 @@ # Sparc instruction decode definitions. # Copyright (c) 2023 Richard Henderson +&bcc i a cond cc +BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc +Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0 + CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bc1033231f..125015fe1e 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1323,44 +1323,6 @@ static void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) } #endif -static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) -{ - unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); - target_ulong target = dc->pc + offset; - - if (unlikely(AM_CHECK(dc))) { - target &= 0xffffffffULL; - } - if (cond == 0x0) { - /* unconditional not taken */ - if (a) { - dc->pc = dc->npc + 4; - dc->npc = dc->pc + 4; - } else { - dc->pc = dc->npc; - dc->npc = dc->pc + 4; - } - } else if (cond == 0x8) { - /* unconditional taken */ - if (a) { - dc->pc = target; - dc->npc = dc->pc + 4; - } else { - dc->pc = dc->npc; - dc->npc = target; - tcg_gen_mov_tl(cpu_pc, cpu_npc); - } - } else { - flush_cond(dc); - gen_cond(cpu_cond, cc, cond, dc); - if (a) { - gen_branch_a(dc, target); - } else { - gen_branch_n(dc, target); - } - } -} - static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) { unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); @@ -3002,6 +2964,64 @@ static bool advance_pc(DisasContext *dc) return true; } +static bool advance_jump_uncond_never(DisasContext *dc, bool annul) +{ + if (annul) { + dc->pc = dc->npc + 4; + dc->npc = dc->pc + 4; + } else { + dc->pc = dc->npc; + dc->npc = dc->pc + 4; + } + return true; +} + +static bool advance_jump_uncond_always(DisasContext *dc, bool annul, + target_ulong dest) +{ + if (annul) { + dc->pc = dest; + dc->npc = dest + 4; + } else { + dc->pc = dc->npc; + dc->npc = dest; + tcg_gen_mov_tl(cpu_pc, cpu_npc); + } + return true; +} + +static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong dest) +{ + if (annul) { + gen_branch_a(dc, dest); + } else { + gen_branch_n(dc, dest); + } + return true; +} + +static bool do_bpcc(DisasContext *dc, arg_bcc *a) +{ + target_long target = dc->pc + a->i * 4; + + if (unlikely(AM_CHECK(dc))) { + target &= 0xffffffffULL; + } + switch (a->cond) { + case 0x0: + return advance_jump_uncond_never(dc, a->a); + case 0x8: + return advance_jump_uncond_always(dc, a->a, target); + default: + flush_cond(dc); + gen_cond(cpu_cond, a->cc, a->cond, dc); + return advance_jump_cond(dc, a->a, target); + } +} + +TRANS(BPcc, 64, do_bpcc, a) +TRANS(Bicc, ALL, do_bpcc, a) + static bool trans_CALL(DisasContext *dc, arg_CALL *a) { target_long target = dc->pc + a->i * 4; @@ -3043,21 +3063,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) switch (xop) { #ifdef TARGET_SPARC64 case 0x1: /* V9 BPcc */ - { - int cc; - - target = GET_FIELD_SP(insn, 0, 18); - target = sign_extend(target, 19); - target <<= 2; - cc = GET_FIELD_SP(insn, 20, 21); - if (cc == 0) - do_branch(dc, target, insn, 0); - else if (cc == 2) - do_branch(dc, target, insn, 1); - else - goto illegal_insn; - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ case 0x3: /* V9 BPr */ { target = GET_FIELD_SP(insn, 0, 13) | @@ -3087,13 +3093,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } #endif case 0x2: /* BN+x */ - { - target = GET_FIELD(insn, 10, 31); - target = sign_extend(target, 22); - target <<= 2; - do_branch(dc, target, insn, 0); - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ case 0x6: /* FBN+x */ { if (gen_trap_ifnofpu(dc)) { From patchwork Fri Oct 13 21:27:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733262 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1677702wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 08/85] target/sparc: Move BPr to decodetree Date: Fri, 13 Oct 2023 14:27:29 -0700 Message-Id: <20231013212846.165724-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d35; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 70 ++++++++++++++++----------------------- 2 files changed, 32 insertions(+), 41 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 15cd975f4e..838f4cdb1d 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -7,4 +7,7 @@ BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0 +%d16 20:s2 0:14 +BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 + CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 125015fe1e..f72e6eb756 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1292,14 +1292,13 @@ static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) } } -#ifdef TARGET_SPARC64 // Inverted logic -static const int gen_tcg_cond_reg[8] = { - -1, +static const TCGCond gen_tcg_cond_reg[8] = { + TCG_COND_NEVER, /* reserved */ TCG_COND_NE, TCG_COND_GT, TCG_COND_GE, - -1, + TCG_COND_NEVER, /* reserved */ TCG_COND_EQ, TCG_COND_LE, TCG_COND_LT, @@ -1313,16 +1312,6 @@ static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) cmp->c2 = tcg_constant_tl(0); } -static void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src) -{ - DisasCompare cmp; - gen_compare_reg(&cmp, cond, r_src); - - /* The interface is to return a boolean in r_dst. */ - tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); -} -#endif - static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) { unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); @@ -1362,24 +1351,6 @@ static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) } #ifdef TARGET_SPARC64 -static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, - TCGv r_reg) -{ - unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); - target_ulong target = dc->pc + offset; - - if (unlikely(AM_CHECK(dc))) { - target &= 0xffffffffULL; - } - flush_cond(dc); - gen_cond_reg(cpu_cond, cond, r_reg); - if (a) { - gen_branch_a(dc, target); - } else { - gen_branch_n(dc, target); - } -} - static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { switch (fccno) { @@ -3022,6 +2993,31 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) TRANS(BPcc, 64, do_bpcc, a) TRANS(Bicc, ALL, do_bpcc, a) +static bool trans_BPr(DisasContext *dc, arg_BPr *a) +{ + target_long target; + DisasCompare cmp; + + if (!avail_64(dc)) { + return false; + } + if (gen_tcg_cond_reg[a->cond] == TCG_COND_NEVER) { + return false; + } + + target = dc->pc + a->i * 4; + if (unlikely(AM_CHECK(dc))) { + target &= 0xffffffffULL; + } + + flush_cond(dc); + + gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); + tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); + + return advance_jump_cond(dc, a->a, target); +} + static bool trans_CALL(DisasContext *dc, arg_CALL *a) { target_long target = dc->pc + a->i * 4; @@ -3065,15 +3061,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x1: /* V9 BPcc */ g_assert_not_reached(); /* in decodetree */ case 0x3: /* V9 BPr */ - { - target = GET_FIELD_SP(insn, 0, 13) | - (GET_FIELD_SP(insn, 20, 21) << 14); - target = sign_extend(target, 16); - target <<= 2; - cpu_src1 = get_src1(dc, insn); - do_branch_reg(dc, target, insn, cpu_src1); - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ case 0x5: /* V9 FBPcc */ { int cc = GET_FIELD_SP(insn, 20, 21); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 09/85] target/sparc: Move FBPfcc and FBfcc to decodetree Date: Fri, 13 Oct 2023 14:27:30 -0700 Message-Id: <20231013212846.165724-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22b; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 105 +++++++++++++++----------------------- 2 files changed, 46 insertions(+), 63 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 838f4cdb1d..9ab3f2eb82 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -6,8 +6,12 @@ &bcc i a cond cc BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0 +FBPfcc 00 a:1 cond:4 101 cc:2 - i:s19 &bcc +FBfcc 00 a:1 cond:4 110 i:s22 &bcc cc=0 %d16 20:s2 0:14 BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 +NCP 00 - ---- 111 ---------------------- # CBcc + CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f72e6eb756..8c15ca08c4 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1312,44 +1312,6 @@ static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src) cmp->c2 = tcg_constant_tl(0); } -static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc) -{ - unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); - target_ulong target = dc->pc + offset; - - if (unlikely(AM_CHECK(dc))) { - target &= 0xffffffffULL; - } - if (cond == 0x0) { - /* unconditional not taken */ - if (a) { - dc->pc = dc->npc + 4; - dc->npc = dc->pc + 4; - } else { - dc->pc = dc->npc; - dc->npc = dc->pc + 4; - } - } else if (cond == 0x8) { - /* unconditional taken */ - if (a) { - dc->pc = target; - dc->npc = dc->pc + 4; - } else { - dc->pc = dc->npc; - dc->npc = target; - tcg_gen_mov_tl(cpu_pc, cpu_npc); - } - } else { - flush_cond(dc); - gen_fcond(cpu_cond, cc, cond); - if (a) { - gen_branch_a(dc, target); - } else { - gen_branch_n(dc, target); - } - } -} - #ifdef TARGET_SPARC64 static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { @@ -2993,6 +2955,31 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) TRANS(BPcc, 64, do_bpcc, a) TRANS(Bicc, ALL, do_bpcc, a) +static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) +{ + target_long target = dc->pc + a->i * 4; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (unlikely(AM_CHECK(dc))) { + target &= 0xffffffffULL; + } + switch (a->cond) { + case 0x0: + return advance_jump_uncond_never(dc, a->a); + case 0x8: + return advance_jump_uncond_always(dc, a->a, target); + default: + flush_cond(dc); + gen_fcond(cpu_cond, a->cc, a->cond); + return advance_jump_cond(dc, a->a, target); + } +} + +TRANS(FBPfcc, 64, do_fbpfcc, a) +TRANS(FBfcc, ALL, do_fbpfcc, a) + static bool trans_BPr(DisasContext *dc, arg_BPr *a) { target_long target; @@ -3032,6 +3019,20 @@ static bool trans_CALL(DisasContext *dc, arg_CALL *a) return true; } +static bool trans_NCP(DisasContext *dc, arg_NCP *a) +{ + /* + * For sparc32, always generate the no-coprocessor exception. + * For sparc64, always generate illegal instruction. + */ +#ifdef TARGET_SPARC64 + return false; +#else + gen_exception(dc, TT_NCP_INSN); + return true; +#endif +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3055,7 +3056,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0: /* branches/sethi */ { unsigned int xop = GET_FIELD(insn, 7, 9); - int32_t target; switch (xop) { #ifdef TARGET_SPARC64 case 0x1: /* V9 BPcc */ @@ -3063,36 +3063,15 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x3: /* V9 BPr */ g_assert_not_reached(); /* in decodetree */ case 0x5: /* V9 FBPcc */ - { - int cc = GET_FIELD_SP(insn, 20, 21); - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - target = GET_FIELD_SP(insn, 0, 18); - target = sign_extend(target, 19); - target <<= 2; - do_fbranch(dc, target, insn, cc); - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ #else case 0x7: /* CBN+x */ - { - goto ncp_insn; - } + g_assert_not_reached(); /* in decodetree */ #endif case 0x2: /* BN+x */ g_assert_not_reached(); /* in decodetree */ case 0x6: /* FBN+x */ - { - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - target = GET_FIELD(insn, 10, 31); - target = sign_extend(target, 22); - target <<= 2; - do_fbranch(dc, target, insn, 0); - goto jmp_insn; - } + g_assert_not_reached(); /* in decodetree */ case 0x4: /* SETHI */ /* Special-case %g0 because that's the canonical nop. */ if (rd) { From patchwork Fri Oct 13 21:27:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733260 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1677662wrv; Fri, 13 Oct 2023 14:29:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGyUTGWLqTx+O3o37VBbI3HmwelQh2uDLCb23Hwjm4/MDN2s/tsZR3RxQZhfH9nahM1lzK/ X-Received: by 2002:a9d:6b0c:0:b0:6c6:4843:2abe with SMTP id g12-20020a9d6b0c000000b006c648432abemr30261202otp.14.1697232586621; Fri, 13 Oct 2023 14:29:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232586; cv=none; d=google.com; s=arc-20160816; b=xmI8yK95Be78hBL7hgmG7C8n6zsfOeYk+amhgPO85eLU/VdsEB5Y1MjVlY1xgu0rK+ FePIJ9suQfZzjXuedF3MwU2vVTimnJArbe07p7H4gWIVWFx0Dgf57gEB1nWu8eRteIfE 6vI7ngeNflZPS8C2BQJpIlHEPHmvQ+SZAc2wjnXKsHpc/BzvocsX3OT+krrABlprzbU1 Ffd1BHF6mIUTmBIaXLh06uEexWtiYwy1QAah+SylKbfnXzYsuRHBtAdjZ97NUL9MRYj9 NbNbjL5WqupqIOZhxP6ftRZ6YX0ddVVTHwbZ3EWgU42Yvw/RI3NN2jve3BWJ8jCrevZN iV1A== ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 10/85] target/sparc: Merge gen_cond with only caller Date: Fri, 13 Oct 2023 14:27:31 -0700 Message-Id: <20231013212846.165724-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/sparc/translate.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 8c15ca08c4..1ac3bdd03f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1265,20 +1265,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond) } } -static void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond, - DisasContext *dc) -{ - DisasCompare cmp; - gen_compare(&cmp, cc, cond, dc); - - /* The interface is to return a boolean in r_dst. */ - if (cmp.is_bool) { - tcg_gen_mov_tl(r_dst, cmp.c1); - } else { - tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); - } -} - static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) { DisasCompare cmp; @@ -2936,6 +2922,7 @@ static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong dest) static bool do_bpcc(DisasContext *dc, arg_bcc *a) { target_long target = dc->pc + a->i * 4; + DisasCompare cmp; if (unlikely(AM_CHECK(dc))) { target &= 0xffffffffULL; @@ -2947,7 +2934,13 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) return advance_jump_uncond_always(dc, a->a, target); default: flush_cond(dc); - gen_cond(cpu_cond, a->cc, a->cond, dc); + + gen_compare(&cmp, a->cc, a->cond, dc); + if (cmp.is_bool) { + tcg_gen_mov_tl(cpu_cond, cmp.c1); + } else { + tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); + } return advance_jump_cond(dc, a->a, target); } } From patchwork Fri Oct 13 21:27:32 2023 Content-Type: text/plain; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 11/85] target/sparc: Merge gen_fcond with only caller Date: Fri, 13 Oct 2023 14:27:32 -0700 Message-Id: <20231013212846.165724-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/sparc/translate.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1ac3bdd03f..ecb485c305 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1265,19 +1265,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int cc, unsigned int cond) } } -static void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond) -{ - DisasCompare cmp; - gen_fcompare(&cmp, cc, cond); - - /* The interface is to return a boolean in r_dst. */ - if (cmp.is_bool) { - tcg_gen_mov_tl(r_dst, cmp.c1); - } else { - tcg_gen_setcond_tl(cmp.cond, r_dst, cmp.c1, cmp.c2); - } -} - // Inverted logic static const TCGCond gen_tcg_cond_reg[8] = { TCG_COND_NEVER, /* reserved */ @@ -2951,6 +2938,7 @@ TRANS(Bicc, ALL, do_bpcc, a) static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) { target_long target = dc->pc + a->i * 4; + DisasCompare cmp; if (gen_trap_ifnofpu(dc)) { return true; @@ -2965,7 +2953,13 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) return advance_jump_uncond_always(dc, a->a, target); default: flush_cond(dc); - gen_fcond(cpu_cond, a->cc, a->cond); + + gen_fcompare(&cmp, a->cc, a->cond); + if (cmp.is_bool) { + tcg_gen_mov_tl(cpu_cond, cmp.c1); + } else { + tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); + } return advance_jump_cond(dc, a->a, target); } } From patchwork Fri Oct 13 21:27:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733259 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1677636wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 12/85] target/sparc: Merge gen_branch_[an] with only caller Date: Fri, 13 Oct 2023 14:27:33 -0700 Message-Id: <20231013212846.165724-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/translate.c | 73 +++++++++++++++++----------------------- 1 file changed, 30 insertions(+), 43 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ecb485c305..ee8c0450aa 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -885,47 +885,6 @@ static void gen_branch2(DisasContext *dc, target_ulong pc1, gen_goto_tb(dc, 1, pc2, pc2 + 4); } -static void gen_branch_a(DisasContext *dc, target_ulong pc1) -{ - TCGLabel *l1 = gen_new_label(); - target_ulong npc = dc->npc; - - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1); - - gen_goto_tb(dc, 0, npc, pc1); - - gen_set_label(l1); - gen_goto_tb(dc, 1, npc + 4, npc + 8); - - dc->base.is_jmp = DISAS_NORETURN; -} - -static void gen_branch_n(DisasContext *dc, target_ulong pc1) -{ - target_ulong npc = dc->npc; - - if (npc & 3) { - switch (npc) { - case DYNAMIC_PC: - case DYNAMIC_PC_LOOKUP: - tcg_gen_mov_tl(cpu_pc, cpu_npc); - tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, - cpu_cond, tcg_constant_tl(0), - tcg_constant_tl(pc1), cpu_npc); - dc->pc = npc; - break; - default: - g_assert_not_reached(); - } - } else { - dc->pc = npc; - dc->jump_pc[0] = pc1; - dc->jump_pc[1] = npc + 4; - dc->npc = JUMP_PC; - } -} - static void gen_generic_branch(DisasContext *dc) { TCGv npc0 = tcg_constant_tl(dc->jump_pc[0]); @@ -2898,10 +2857,38 @@ static bool advance_jump_uncond_always(DisasContext *dc, bool annul, static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong dest) { + target_ulong npc = dc->npc; + if (annul) { - gen_branch_a(dc, dest); + TCGLabel *l1 = gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1); + gen_goto_tb(dc, 0, npc, dest); + gen_set_label(l1); + gen_goto_tb(dc, 1, npc + 4, npc + 8); + + dc->base.is_jmp = DISAS_NORETURN; } else { - gen_branch_n(dc, dest); + if (npc & 3) { + switch (npc) { + case DYNAMIC_PC: + case DYNAMIC_PC_LOOKUP: + tcg_gen_mov_tl(cpu_pc, cpu_npc); + tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); + tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, + cpu_cond, tcg_constant_tl(0), + tcg_constant_tl(dest), cpu_npc); + dc->pc = npc; + break; + default: + g_assert_not_reached(); + } + } else { + dc->pc = npc; + dc->jump_pc[0] = dest; + dc->jump_pc[1] = npc + 4; + dc->npc = JUMP_PC; + } } return true; } From patchwork Fri Oct 13 21:27:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733291 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679106wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:28:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 13/85] target/sparc: Pass DisasCompare to advance_jump_cond Date: Fri, 13 Oct 2023 14:27:34 -0700 Message-Id: <20231013212846.165724-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fold the condition into the branch or movcond when possible. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 32 +++++++++++++------------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ee8c0450aa..5cea835b28 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2855,14 +2855,15 @@ static bool advance_jump_uncond_always(DisasContext *dc, bool annul, return true; } -static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong dest) +static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp, + bool annul, target_ulong dest) { target_ulong npc = dc->npc; if (annul) { TCGLabel *l1 = gen_new_label(); - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cond, 0, l1); + tcg_gen_brcond_tl(tcg_invert_cond(cmp->cond), cmp->c1, cmp->c2, l1); gen_goto_tb(dc, 0, npc, dest); gen_set_label(l1); gen_goto_tb(dc, 1, npc + 4, npc + 8); @@ -2875,8 +2876,8 @@ static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong dest) case DYNAMIC_PC_LOOKUP: tcg_gen_mov_tl(cpu_pc, cpu_npc); tcg_gen_addi_tl(cpu_npc, cpu_npc, 4); - tcg_gen_movcond_tl(TCG_COND_NE, cpu_npc, - cpu_cond, tcg_constant_tl(0), + tcg_gen_movcond_tl(cmp->cond, cpu_npc, + cmp->c1, cmp->c2, tcg_constant_tl(dest), cpu_npc); dc->pc = npc; break; @@ -2888,6 +2889,11 @@ static bool advance_jump_cond(DisasContext *dc, bool annul, target_ulong dest) dc->jump_pc[0] = dest; dc->jump_pc[1] = npc + 4; dc->npc = JUMP_PC; + if (cmp->is_bool) { + tcg_gen_mov_tl(cpu_cond, cmp->c1); + } else { + tcg_gen_setcond_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2); + } } } return true; @@ -2910,12 +2916,7 @@ static bool do_bpcc(DisasContext *dc, arg_bcc *a) flush_cond(dc); gen_compare(&cmp, a->cc, a->cond, dc); - if (cmp.is_bool) { - tcg_gen_mov_tl(cpu_cond, cmp.c1); - } else { - tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); - } - return advance_jump_cond(dc, a->a, target); + return advance_jump_cond(dc, &cmp, a->a, target); } } @@ -2942,12 +2943,7 @@ static bool do_fbpfcc(DisasContext *dc, arg_bcc *a) flush_cond(dc); gen_fcompare(&cmp, a->cc, a->cond); - if (cmp.is_bool) { - tcg_gen_mov_tl(cpu_cond, cmp.c1); - } else { - tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); - } - return advance_jump_cond(dc, a->a, target); + return advance_jump_cond(dc, &cmp, a->a, target); } } @@ -2974,9 +2970,7 @@ static bool trans_BPr(DisasContext *dc, arg_BPr *a) flush_cond(dc); gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); - tcg_gen_setcond_tl(cmp.cond, cpu_cond, cmp.c1, cmp.c2); - - return advance_jump_cond(dc, a->a, target); + return advance_jump_cond(dc, &cmp, a->a, target); } static bool trans_CALL(DisasContext *dc, arg_CALL *a) From patchwork Fri Oct 13 21:27:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733275 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678525wrv; Fri, 13 Oct 2023 14:32:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFXlS3sxU4OcSgpx6eSnYctg3DO/RKCn8N6yTLH3b1haQ7JWuOjSyM2xmKvpQJYZUacdpiY X-Received: by 2002:a05:620a:25cd:b0:775:6650:bc54 with SMTP id y13-20020a05620a25cd00b007756650bc54mr31232336qko.28.1697232740055; Fri, 13 Oct 2023 14:32:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232740; cv=none; d=google.com; s=arc-20160816; b=IWTgVYpItF7MZAioJ5SS0uMLMxBNxBzVumCUQOCoV5FtFEGf7TCjW9bvcbWdWU95lL XCARmcGGFQzVPlfMLnMf5Ryqtf8LJRVKKkmWzeuieFZjV2SaH3jutnHTd+EdYsUsOhmT HQXs7pDrYFrlthV716fFQx7fJMPyMibY7OynF3zUDXp1hF8KdoCrBztpuqQpDgqBQr8a brM9FZCWJMjRH3bK4utkmSbSyrxv8arA2omunsNY4t+v5vYEQlRuRfZuBrIGq2e4RNCU NekOKVlwfXRSoYyU1N1Qcfzp1AEVHIiscMzb8vKiNAEcJoeZP8vwengIlEhZE6clbrEu Azag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=c7TwK33eQMZo3s9feaizPS6nBLLo3Koe/HwD3VuT/NI=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=Vw84z01Jed6V5O+hgLVMGGJj73uyxah/SSY5iRM0FStfhJmR/OW+yUknzsHFOKrX2v 3Oz6wl2Cw5m+XRTxeMCl+0dkGRlJP0WOqAhILDGLLpfkmdu8NWIIaHXSy46tsyZd2reY zBJTnWYv0oXtB8I7t88J7td+FuTH4BPSbf0GKnxBRpGVma4La3xcY9aaDiZG4X9VVNBS gnwj/YpzdbDUb3u7VQCe53LcuMtGOrq8UajuT558yFVvoZIYeIWaBalvIlD/0aO7vGKq hwLdQ/jfNN4RZNuighg0Zd/gKDhGAaD9SrW54S2OnEiKF1aBxD9QVKMtC9NpK96kup4a aV7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m1cWOv+S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 14/85] target/sparc: Move SETHI to decodetree Date: Fri, 13 Oct 2023 14:27:35 -0700 Message-Id: <20231013212846.165724-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 6 +++++ target/sparc/translate.c | 50 ++++++++++++--------------------------- 2 files changed, 21 insertions(+), 35 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 9ab3f2eb82..f6f5401b10 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -3,6 +3,10 @@ # Sparc instruction decode definitions. # Copyright (c) 2023 Richard Henderson +## +## Major Opcodes 00 and 01 -- branches, call, and sethi. +## + &bcc i a cond cc BPcc 00 a:1 cond:4 001 cc:1 0 - i:s19 &bcc Bicc 00 a:1 cond:4 010 i:s22 &bcc cc=0 @@ -14,4 +18,6 @@ BPr 00 a:1 0 cond:3 011 .. - rs1:5 .............. i=%d16 NCP 00 - ---- 111 ---------------------- # CBcc +SETHI 00 rd:5 100 i:22 + CALL 01 i:s30 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5cea835b28..cc39a25275 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2829,6 +2829,10 @@ static bool advance_pc(DisasContext *dc) return true; } +/* + * Major opcodes 00 and 01 -- branches, call, and sethi + */ + static bool advance_jump_uncond_never(DisasContext *dc, bool annul) { if (annul) { @@ -3001,6 +3005,15 @@ static bool trans_NCP(DisasContext *dc, arg_NCP *a) #endif } +static bool trans_SETHI(DisasContext *dc, arg_SETHI *a) +{ + /* Special-case %g0 because that's the canonical nop. */ + if (a->rd) { + gen_store_gpr(dc, a->rd, tcg_constant_tl((uint32_t)a->i << 10)); + } + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3021,41 +3034,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) rd = GET_FIELD(insn, 2, 6); switch (opc) { - case 0: /* branches/sethi */ - { - unsigned int xop = GET_FIELD(insn, 7, 9); - switch (xop) { -#ifdef TARGET_SPARC64 - case 0x1: /* V9 BPcc */ - g_assert_not_reached(); /* in decodetree */ - case 0x3: /* V9 BPr */ - g_assert_not_reached(); /* in decodetree */ - case 0x5: /* V9 FBPcc */ - g_assert_not_reached(); /* in decodetree */ -#else - case 0x7: /* CBN+x */ - g_assert_not_reached(); /* in decodetree */ -#endif - case 0x2: /* BN+x */ - g_assert_not_reached(); /* in decodetree */ - case 0x6: /* FBN+x */ - g_assert_not_reached(); /* in decodetree */ - case 0x4: /* SETHI */ - /* Special-case %g0 because that's the canonical nop. */ - if (rd) { - uint32_t value = GET_FIELD(insn, 10, 31); - TCGv t = gen_dest_gpr(dc, rd); - tcg_gen_movi_tl(t, value << 10); - gen_store_gpr(dc, rd, t); - } - break; - case 0x0: /* UNIMPL */ - default: - goto illegal_insn; - } - break; - } - break; + case 0: + goto illegal_insn; /* in decodetree */ case 1: g_assert_not_reached(); /* in decodetree */ case 2: /* FPU & Logical Operations */ From patchwork Fri Oct 13 21:27:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733261 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1677667wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 15/85] target/sparc: Move Tcc to decodetree Date: Fri, 13 Oct 2023 14:27:36 -0700 Message-Id: <20231013212846.165724-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 + target/sparc/translate.c | 148 ++++++++++++++++++-------------------- 2 files changed, 72 insertions(+), 79 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f6f5401b10..2945575268 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -21,3 +21,6 @@ NCP 00 - ---- 111 ---------------------- # CBcc SETHI 00 rd:5 100 i:22 CALL 01 i:s30 + +Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 +Tcc_i 10 0 cond:4 111010 rs1:5 1 cc:1 0000 i:8 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index cc39a25275..a1c2796782 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3014,6 +3014,74 @@ static bool trans_SETHI(DisasContext *dc, arg_SETHI *a) return advance_pc(dc); } +static bool do_tcc(DisasContext *dc, int cc, int cond, + bool imm, int rs1, int rs2_or_imm) +{ + TCGLabel *l1 = NULL; + TCGv_i32 trap; + int mask; + + /* Reject %xcc for sparc32. */ + if (avail_32(dc) && cc) { + return false; + } + + /* Trap never. */ + if (cond == 0) { + return advance_pc(dc); + } + + save_state(dc); + + /* Conditional trap. */ + if (cond != 8) { + DisasCompare cmp; + + gen_compare(&cmp, cc, cond, dc); + l1 = gen_new_label(); + tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond), cmp.c1, cmp.c2, l1); + } + + mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc) + ? UA2005_HTRAP_MASK : V8_TRAP_MASK); + + if (rs2_or_imm == 0) { + imm = true; + } + if (rs1 == 0 && imm) { + trap = tcg_constant_i32((rs2_or_imm & mask) + TT_TRAP); + } else { + TCGv tmp = tcg_temp_new(); + TCGv src1 = gen_load_gpr(dc, rs1); + + if (imm) { + tcg_gen_addi_tl(tmp, src1, rs2_or_imm); + } else { + tcg_gen_add_tl(tmp, src1, gen_load_gpr(dc, rs2_or_imm)); + } + + trap = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(trap, tmp); + tcg_gen_andi_i32(trap, trap, mask); + tcg_gen_addi_i32(trap, trap, TT_TRAP); + } + + gen_helper_raise_exception(tcg_env, trap); + + if (l1 == NULL) { + /* An unconditional trap ends the TB. */ + dc->base.is_jmp = DISAS_NORETURN; + return true; + } + + /* A conditional trap falls through to the next insn. */ + gen_set_label(l1); + return advance_pc(dc); +} + +TRANS(Tcc_r, ALL, do_tcc, a->cc, a->cond, false, a->rs1, a->rs2) +TRANS(Tcc_i, ALL, do_tcc, a->cc, a->cond, true, a->rs1, a->i) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3044,85 +3112,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv cpu_dst = tcg_temp_new(); TCGv cpu_tmp0; - if (xop == 0x3a) { /* generate trap */ - int cond = GET_FIELD(insn, 3, 6); - TCGv_i32 trap; - TCGLabel *l1 = NULL; - int mask; - - if (cond == 0) { - /* Trap never. */ - break; - } - - save_state(dc); - - if (cond != 8) { - /* Conditional trap. */ - DisasCompare cmp; -#ifdef TARGET_SPARC64 - /* V9 icc/xcc */ - int cc = GET_FIELD_SP(insn, 11, 12); - if (cc == 0) { - gen_compare(&cmp, 0, cond, dc); - } else if (cc == 2) { - gen_compare(&cmp, 1, cond, dc); - } else { - goto illegal_insn; - } -#else - gen_compare(&cmp, 0, cond, dc); -#endif - l1 = gen_new_label(); - tcg_gen_brcond_tl(tcg_invert_cond(cmp.cond), - cmp.c1, cmp.c2, l1); - } - - mask = ((dc->def->features & CPU_FEATURE_HYPV) && supervisor(dc) - ? UA2005_HTRAP_MASK : V8_TRAP_MASK); - - /* Don't use the normal temporaries, as they may well have - gone out of scope with the branch above. While we're - doing that we might as well pre-truncate to 32-bit. */ - trap = tcg_temp_new_i32(); - - rs1 = GET_FIELD_SP(insn, 14, 18); - if (IS_IMM) { - rs2 = GET_FIELD_SP(insn, 0, 7); - if (rs1 == 0) { - tcg_gen_movi_i32(trap, (rs2 & mask) + TT_TRAP); - /* Signal that the trap value is fully constant. */ - mask = 0; - } else { - TCGv t1 = gen_load_gpr(dc, rs1); - tcg_gen_trunc_tl_i32(trap, t1); - tcg_gen_addi_i32(trap, trap, rs2); - } - } else { - TCGv t1, t2; - rs2 = GET_FIELD_SP(insn, 0, 4); - t1 = gen_load_gpr(dc, rs1); - t2 = gen_load_gpr(dc, rs2); - tcg_gen_add_tl(t1, t1, t2); - tcg_gen_trunc_tl_i32(trap, t1); - } - if (mask != 0) { - tcg_gen_andi_i32(trap, trap, mask); - tcg_gen_addi_i32(trap, trap, TT_TRAP); - } - - gen_helper_raise_exception(tcg_env, trap); - - if (cond == 8) { - /* An unconditional trap ends the TB. */ - dc->base.is_jmp = DISAS_NORETURN; - goto jmp_insn; - } else { - /* A conditional trap falls through to the next insn. */ - gen_set_label(l1); - break; - } - } else if (xop == 0x28) { + if (xop == 0x28) { rs1 = GET_FIELD(insn, 13, 17); switch(rs1) { case 0: /* rdy */ From patchwork Fri Oct 13 21:27:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733281 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678798wrv; Fri, 13 Oct 2023 14:33:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHh/ZaU38N149819rwjHKLotG/ec//uhTy6DKZ8j7GCzAaYaO8IIrnugp/+Hz48dD+wBki2 X-Received: by 2002:a05:620a:25ce:b0:76e:f3a3:4ac6 with SMTP id y14-20020a05620a25ce00b0076ef3a34ac6mr29434036qko.35.1697232789187; Fri, 13 Oct 2023 14:33:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232789; cv=none; d=google.com; s=arc-20160816; b=qOWYgDIrRdCZz0/QMaS5IfAYfxBIWWUXJRFpfcki2yOxrR1ulhehw7oghHwmLAzNgX nGRMdLt4lFJvhlGwS3r0YYRpgZgveDW2JVvEXZFMLk+G3P9rjtFdi1hM8xOXgMQ3OwK5 BoVLj6O9wus5SgM+CTemPzyO9+PL9Fu7bSFKwsCOcsl0qlZTWheXC2thDGYfiwmkGiaL 7hrTiUIRSoQRF596470bSOTG5fK8ABvCx82MzJ5ajr3KKqRrBbnhf1ExDGsJUti6ibM1 igg7FBsMFfUxKN3pjZF/IEl+R6yHStfOuon3HB0odYClOGiOAee0+bTi0mkbNXWhrWn0 41iw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gbR0keYcjz5jMnEd2GZBRdS0VP6EA5r4Z+3eb9rgrA0=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=SLXIIPHzZBt5ajGdadVcZiLt/ocalMM1DvNJYg7xz9UTHKjat7Pe5XooDuX/rbxzAd mfRpJiwdHs2umweZ4gUdCw8iCYkhxBIPtC5KQePQwmqsq0W0BbpzQVWHbVhPGMWgRJAx c//n/gsY3xumhlXen1oZK/W+3l4eFFp3CLHG/UWTs3bcEgZ55u5feRvxW+MHZN2fqT1F XTdgg+H8HaBn44VeZjP80Gstmn4tTu9+vjNTnKq+H4qC+lxcBhZApkZ70HxBLpHV2gZD frTn5P3j6N+Q68/PBIsentm9AunZxHtt7u14Nz6f5l6SjMJWlN4lVtn3cpzANRsC83Kh 1rJA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="O92yMy/A"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 16/85] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree Date: Fri, 13 Oct 2023 14:27:37 -0700 Message-Id: <20231013212846.165724-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++ target/sparc/translate.c | 360 ++++++++++++++++++++++++-------------- 2 files changed, 253 insertions(+), 129 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 2945575268..8dc45f5abc 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -24,3 +24,25 @@ CALL 01 i:s30 Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 Tcc_i 10 0 cond:4 111010 rs1:5 1 cc:1 0000 i:8 + +{ + [ + STBAR 10 00000 101000 01111 0 0000000000000 + MEMBAR 10 00000 101000 01111 1 000000 cmask:3 mmask:4 + + RDCCR 10 rd:5 101000 00010 0 0000000000000 + RDASI 10 rd:5 101000 00011 0 0000000000000 + RDTICK 10 rd:5 101000 00100 0 0000000000000 + RDPC 10 rd:5 101000 00101 0 0000000000000 + RDFPRS 10 rd:5 101000 00110 0 0000000000000 + RDASR17 10 rd:5 101000 10001 0 0000000000000 + RDGSR 10 rd:5 101000 10011 0 0000000000000 + RDSOFTINT 10 rd:5 101000 10110 0 0000000000000 + RDTICK_CMPR 10 rd:5 101000 10111 0 0000000000000 + RDSTICK 10 rd:5 101000 11000 0 0000000000000 + RDSTICK_CMPR 10 rd:5 101000 11001 0 0000000000000 + RDSTRAND_STATUS 10 rd:5 101000 11010 0 0000000000000 + ] + # Before v8, all rs1 accepted; otherwise rs1==0. + RDY 10 rd:5 101000 rs1:5 0 0000000000000 +} diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a1c2796782..55ddd7b051 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -36,6 +36,10 @@ #include "exec/helper-info.c.inc" #undef HELPER_H +#ifndef TARGET_SPARC64 +#define gen_helper_rdccr(D, E) qemu_build_not_reached() +#endif + /* Dynamic PC, must exit to main loop. */ #define DYNAMIC_PC 1 /* Dynamic PC, one of two values according to jump_pc[T2]. */ @@ -2803,6 +2807,8 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) # define avail_32(C) true # define avail_64(C) false #endif +#define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) +#define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) /* Default case for non jump instructions. */ static bool advance_pc(DisasContext *dc) @@ -2903,6 +2909,12 @@ static bool advance_jump_cond(DisasContext *dc, DisasCompare *cmp, return true; } +static bool raise_priv(DisasContext *dc) +{ + gen_exception(dc, TT_PRIV_INSN); + return true; +} + static bool do_bpcc(DisasContext *dc, arg_bcc *a) { target_long target = dc->pc + a->i * 4; @@ -3082,6 +3094,215 @@ static bool do_tcc(DisasContext *dc, int cc, int cond, TRANS(Tcc_r, ALL, do_tcc, a->cc, a->cond, false, a->rs1, a->rs2) TRANS(Tcc_i, ALL, do_tcc, a->cc, a->cond, true, a->rs1, a->i) +static bool trans_STBAR(DisasContext *dc, arg_STBAR *a) +{ + tcg_gen_mb(TCG_MO_ST_ST | TCG_BAR_SC); + return advance_pc(dc); +} + +static bool trans_MEMBAR(DisasContext *dc, arg_MEMBAR *a) +{ + if (avail_32(dc)) { + return false; + } + if (a->mmask) { + /* Note TCG_MO_* was modeled on sparc64, so mmask matches. */ + tcg_gen_mb(a->mmask | TCG_BAR_SC); + } + if (a->cmask) { + /* For #Sync, etc, end the TB to recognize interrupts. */ + dc->base.is_jmp = DISAS_EXIT; + } + return advance_pc(dc); +} + +static bool do_rd_special(DisasContext *dc, bool priv, int rd, + TCGv (*func)(DisasContext *, TCGv)) +{ + if (!priv) { + return raise_priv(dc); + } + gen_store_gpr(dc, rd, func(dc, gen_dest_gpr(dc, rd))); + return advance_pc(dc); +} + +static TCGv do_rdy(DisasContext *dc, TCGv dst) +{ + return cpu_y; +} + +static bool trans_RDY(DisasContext *dc, arg_RDY *a) +{ + /* + * TODO: Need a feature bit for sparcv8. In the meantime, treat all + * 32-bit cpus like sparcv7, which ignores the rs1 field. + * This matches after all other ASR, so Leon3 Asr17 is handled first. + */ + if (avail_64(dc) && a->rs1 != 0) { + return false; + } + return do_rd_special(dc, true, a->rd, do_rdy); +} + +static TCGv do_rd_leon3_config(DisasContext *dc, TCGv dst) +{ + uint32_t val; + + /* + * TODO: There are many more fields to be filled, + * some of which are writable. + */ + val = dc->def->nwindows - 1; /* [4:0] NWIN */ + val |= 1 << 8; /* [8] V8 */ + + return tcg_constant_tl(val); +} + +TRANS(RDASR17, ASR17, do_rd_special, true, a->rd, do_rd_leon3_config) + +static TCGv do_rdccr(DisasContext *dc, TCGv dst) +{ + update_psr(dc); + gen_helper_rdccr(dst, tcg_env); + return dst; +} + +TRANS(RDCCR, 64, do_rd_special, true, a->rd, do_rdccr) + +static TCGv do_rdasi(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + return tcg_constant_tl(dc->asi); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDASI, 64, do_rd_special, true, a->rd, do_rdasi) + +static TCGv do_rdtick(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tickptr = tcg_temp_new_ptr(); + TCGv_i32 r_const = tcg_constant_i32(dc->mem_idx); + + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, tick)); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp = DISAS_EXIT; + } + gen_helper_tick_get_count(dst, tcg_env, r_tickptr, r_const); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +/* TODO: non-priv access only allowed when enabled. */ +TRANS(RDTICK, 64, do_rd_special, true, a->rd, do_rdtick) + +static TCGv do_rdpc(DisasContext *dc, TCGv dst) +{ + target_ulong val = dc->pc; + if (AM_CHECK(dc)) { + val &= 0xffffffffULL; + } + return tcg_constant_tl(val); +} + +TRANS(RDPC, 64, do_rd_special, true, a->rd, do_rdpc) + +static TCGv do_rdfprs(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ext_i32_tl(dst, cpu_fprs); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDFPRS, 64, do_rd_special, true, a->rd, do_rdfprs) + +static TCGv do_rdgsr(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + gen_trap_ifnofpu(dc); + return cpu_gsr; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDGSR, 64, do_rd_special, true, a->rd, do_rdgsr) + +static TCGv do_rdsoftint(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ld32s_tl(dst, tcg_env, offsetof(CPUSPARCState, softint)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDSOFTINT, 64, do_rd_special, supervisor(dc), a->rd, do_rdsoftint) + +static TCGv do_rdtick_cmpr(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + return cpu_tick_cmpr; +#else + qemu_build_not_reached(); +#endif +} + +/* TODO: non-priv access only allowed when enabled. */ +TRANS(RDTICK_CMPR, 64, do_rd_special, true, a->rd, do_rdtick_cmpr) + +static TCGv do_rdstick(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tickptr = tcg_temp_new_ptr(); + TCGv_i32 r_const = tcg_constant_i32(dc->mem_idx); + + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick)); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp = DISAS_EXIT; + } + gen_helper_tick_get_count(dst, tcg_env, r_tickptr, r_const); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +/* TODO: non-priv access only allowed when enabled. */ +TRANS(RDSTICK, 64, do_rd_special, true, a->rd, do_rdstick) + +static TCGv do_rdstick_cmpr(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + return cpu_stick_cmpr; +#else + qemu_build_not_reached(); +#endif +} + +/* TODO: supervisor access only allowed when enabled by hypervisor. */ +TRANS(RDSTICK_CMPR, 64, do_rd_special, supervisor(dc), a->rd, do_rdstick_cmpr) + +/* + * UltraSPARC-T1 Strand status. + * HYPV check maybe not enough, UA2005 & UA2007 describe + * this ASR as impl. dep + */ +static TCGv do_rdstrand_status(DisasContext *dc, TCGv dst) +{ + return tcg_constant_tl(1); +} + +TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_status) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3108,134 +3329,12 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) g_assert_not_reached(); /* in decodetree */ case 2: /* FPU & Logical Operations */ { - unsigned int xop = GET_FIELD(insn, 7, 12); - TCGv cpu_dst = tcg_temp_new(); - TCGv cpu_tmp0; + unsigned int xop __attribute__((unused)) = GET_FIELD(insn, 7, 12); + TCGv cpu_dst __attribute__((unused)) = tcg_temp_new(); + TCGv cpu_tmp0 __attribute__((unused)); - if (xop == 0x28) { - rs1 = GET_FIELD(insn, 13, 17); - switch(rs1) { - case 0: /* rdy */ -#ifndef TARGET_SPARC64 - case 0x01 ... 0x0e: /* undefined in the SPARCv8 - manual, rdy on the microSPARC - II */ - case 0x0f: /* stbar in the SPARCv8 manual, - rdy on the microSPARC II */ - case 0x10 ... 0x1f: /* implementation-dependent in the - SPARCv8 manual, rdy on the - microSPARC II */ - /* Read Asr17 */ - if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) { - TCGv t = gen_dest_gpr(dc, rd); - /* Read Asr17 for a Leon3 monoprocessor */ - tcg_gen_movi_tl(t, (1 << 8) | (dc->def->nwindows - 1)); - gen_store_gpr(dc, rd, t); - break; - } -#endif - gen_store_gpr(dc, rd, cpu_y); - break; -#ifdef TARGET_SPARC64 - case 0x2: /* V9 rdccr */ - update_psr(dc); - gen_helper_rdccr(cpu_dst, tcg_env); - gen_store_gpr(dc, rd, cpu_dst); - break; - case 0x3: /* V9 rdasi */ - tcg_gen_movi_tl(cpu_dst, dc->asi); - gen_store_gpr(dc, rd, cpu_dst); - break; - case 0x4: /* V9 rdtick */ - { - TCGv_ptr r_tickptr; - TCGv_i32 r_const; - - r_tickptr = tcg_temp_new_ptr(); - r_const = tcg_constant_i32(dc->mem_idx); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, tick)); - if (translator_io_start(&dc->base)) { - dc->base.is_jmp = DISAS_EXIT; - } - gen_helper_tick_get_count(cpu_dst, tcg_env, r_tickptr, - r_const); - gen_store_gpr(dc, rd, cpu_dst); - } - break; - case 0x5: /* V9 rdpc */ - { - TCGv t = gen_dest_gpr(dc, rd); - if (unlikely(AM_CHECK(dc))) { - tcg_gen_movi_tl(t, dc->pc & 0xffffffffULL); - } else { - tcg_gen_movi_tl(t, dc->pc); - } - gen_store_gpr(dc, rd, t); - } - break; - case 0x6: /* V9 rdfprs */ - tcg_gen_ext_i32_tl(cpu_dst, cpu_fprs); - gen_store_gpr(dc, rd, cpu_dst); - break; - case 0xf: /* V9 membar */ - break; /* no effect */ - case 0x13: /* Graphics Status */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_store_gpr(dc, rd, cpu_gsr); - break; - case 0x16: /* Softint */ - tcg_gen_ld32s_tl(cpu_dst, tcg_env, - offsetof(CPUSPARCState, softint)); - gen_store_gpr(dc, rd, cpu_dst); - break; - case 0x17: /* Tick compare */ - gen_store_gpr(dc, rd, cpu_tick_cmpr); - break; - case 0x18: /* System tick */ - { - TCGv_ptr r_tickptr; - TCGv_i32 r_const; - - r_tickptr = tcg_temp_new_ptr(); - r_const = tcg_constant_i32(dc->mem_idx); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, stick)); - if (translator_io_start(&dc->base)) { - dc->base.is_jmp = DISAS_EXIT; - } - gen_helper_tick_get_count(cpu_dst, tcg_env, r_tickptr, - r_const); - gen_store_gpr(dc, rd, cpu_dst); - } - break; - case 0x19: /* System tick compare */ - gen_store_gpr(dc, rd, cpu_stick_cmpr); - break; - case 0x1a: /* UltraSPARC-T1 Strand status */ - /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe - * this ASR as impl. dep - */ - CHECK_IU_FEATURE(dc, HYPV); - { - TCGv t = gen_dest_gpr(dc, rd); - tcg_gen_movi_tl(t, 1UL); - gen_store_gpr(dc, rd, t); - } - break; - case 0x10: /* Performance Control */ - case 0x11: /* Performance Instrumentation Counter */ - case 0x12: /* Dispatch Control */ - case 0x14: /* Softint set, WO */ - case 0x15: /* Softint clear, WO */ -#endif - default: - goto illegal_insn; - } #if !defined(CONFIG_USER_ONLY) - } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ + if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ #ifndef TARGET_SPARC64 if (!supervisor(dc)) { goto priv_insn; @@ -3273,7 +3372,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) #endif gen_store_gpr(dc, rd, cpu_dst); break; - } else if (xop == 0x2a) { /* rdwim / V9 rdpr */ + } + if (xop == 0x2a) { /* rdwim / V9 rdpr */ if (!supervisor(dc)) { goto priv_insn; } @@ -3397,9 +3497,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) #endif gen_store_gpr(dc, rd, cpu_tmp0); break; + } #endif #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) - } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ + if (xop == 0x2b) { /* rdtbr / V9 flushw */ #ifdef TARGET_SPARC64 gen_helper_flushw(tcg_env); #else @@ -3408,8 +3509,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_store_gpr(dc, rd, cpu_tbr); #endif break; + } #endif - } else if (xop == 0x34) { /* FPU Operations */ + if (xop == 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) { goto jmp_insn; } From patchwork Fri Oct 13 21:27:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733279 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678744wrv; Fri, 13 Oct 2023 14:32:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFS2GEXUo+HckGJQzJKPxln3JxPYqqApNN1bd+fUO8mwJaKDe8x3k99iOuj5xLDCsY6R7Gu X-Received: by 2002:a1f:6682:0:b0:4a0:6fd4:4334 with SMTP id a124-20020a1f6682000000b004a06fd44334mr15641942vkc.12.1697232778993; Fri, 13 Oct 2023 14:32:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232778; cv=none; d=google.com; s=arc-20160816; b=gwBESIWAe0t6k30cowqF4MUIKR0IH1MJCBHyHo9sU3MfmlMf1AdZH9OB/ibSBs/nnm qJGi/U82kw7VMih3m4wzlT0de3B8yxC4rpNDUaWuxDPUFxC7uQLNESBhuJEJCt0TbdZh mKToAR7rgFKIQ1BVJAm85i8dcYhjtV7GcxJ/JeCaxY3OV+9rOwV8CrLcqiGHOPijRkQU 0AfXnCNbTj+2b1gvr/Xydv7klKg0Cb/CKMa5ErDmkldIBBiq29htjvjf3PwYtp9ekNNe +KO/X0gSM1NbNeloEunOqwp6PnACW144pEZ6Iy5/4Er7L7q9XTWaUUf8Hdsu8VxQFSVw byag== ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 17/85] target/sparc: Move RDPSR, RDHPR to decodetree Date: Fri, 13 Oct 2023 14:27:38 -0700 Message-Id: <20231013212846.165724-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::135; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x135.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 10 ++++ target/sparc/translate.c | 112 ++++++++++++++++++++++++-------------- 2 files changed, 80 insertions(+), 42 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 8dc45f5abc..d3ca9061ce 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -46,3 +46,13 @@ Tcc_i 10 0 cond:4 111010 rs1:5 1 cc:1 0000 i:8 # Before v8, all rs1 accepted; otherwise rs1==0. RDY 10 rd:5 101000 rs1:5 0 0000000000000 } + +{ + RDPSR 10 rd:5 101001 00000 0 0000000000000 + RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000 +} +# RDHPR_tstate +RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000 +RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 +RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 +RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 55ddd7b051..a88f514399 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -36,7 +36,9 @@ #include "exec/helper-info.c.inc" #undef HELPER_H -#ifndef TARGET_SPARC64 +#ifdef TARGET_SPARC64 +#define gen_helper_rdpsr(D, E) qemu_build_not_reached() +#else #define gen_helper_rdccr(D, E) qemu_build_not_reached() #endif @@ -250,15 +252,14 @@ static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) /* moves */ #ifdef CONFIG_USER_ONLY #define supervisor(dc) 0 -#ifdef TARGET_SPARC64 #define hypervisor(dc) 0 -#endif #else #ifdef TARGET_SPARC64 #define hypervisor(dc) (dc->hypervisor) #define supervisor(dc) (dc->supervisor | dc->hypervisor) #else #define supervisor(dc) (dc->supervisor) +#define hypervisor(dc) 0 #endif #endif @@ -3303,6 +3304,72 @@ static TCGv do_rdstrand_status(DisasContext *dc, TCGv dst) TRANS(RDSTRAND_STATUS, HYPV, do_rd_special, true, a->rd, do_rdstrand_status) +static TCGv do_rdpsr(DisasContext *dc, TCGv dst) +{ + update_psr(dc); + gen_helper_rdpsr(dst, tcg_env); + return dst; +} + +TRANS(RDPSR, 32, do_rd_special, supervisor(dc), a->rd, do_rdpsr) + +static TCGv do_rdhpstate(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ld_i64(dst, tcg_env, offsetof(CPUSPARCState, hpstate)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDHPR_hpstate, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhpstate) + +static TCGv do_rdhintp(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + return cpu_hintp; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDHPR_hintp, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhintp) + +static TCGv do_rdhtba(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + return cpu_htba; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDHPR_htba, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhtba) + +static TCGv do_rdhver(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + return cpu_hver; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDHPR_hver, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhver) + +static TCGv do_rdhstick_cmpr(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + return cpu_hstick_cmpr; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd, + do_rdhstick_cmpr) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3334,45 +3401,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv cpu_tmp0 __attribute__((unused)); #if !defined(CONFIG_USER_ONLY) - if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */ -#ifndef TARGET_SPARC64 - if (!supervisor(dc)) { - goto priv_insn; - } - update_psr(dc); - gen_helper_rdpsr(cpu_dst, tcg_env); -#else - CHECK_IU_FEATURE(dc, HYPV); - if (!hypervisor(dc)) - goto priv_insn; - rs1 = GET_FIELD(insn, 13, 17); - switch (rs1) { - case 0: // hpstate - tcg_gen_ld_i64(cpu_dst, tcg_env, - offsetof(CPUSPARCState, hpstate)); - break; - case 1: // htstate - // gen_op_rdhtstate(); - break; - case 3: // hintp - tcg_gen_mov_tl(cpu_dst, cpu_hintp); - break; - case 5: // htba - tcg_gen_mov_tl(cpu_dst, cpu_htba); - break; - case 6: // hver - tcg_gen_mov_tl(cpu_dst, cpu_hver); - break; - case 31: // hstick_cmpr - tcg_gen_mov_tl(cpu_dst, cpu_hstick_cmpr); - break; - default: - goto illegal_insn; - } -#endif - gen_store_gpr(dc, rd, cpu_dst); - break; - } if (xop == 0x2a) { /* rdwim / V9 rdpr */ if (!supervisor(dc)) { goto priv_insn; From patchwork Fri Oct 13 21:27:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733277 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678665wrv; Fri, 13 Oct 2023 14:32:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGdvKGgaQVYGvfLjBcUATE+GfrfUjE2K2bZHCz424oQcECbqNPkskgASskwEsBnyjAzZLh2 X-Received: by 2002:a54:4388:0:b0:3af:8672:36f8 with SMTP id u8-20020a544388000000b003af867236f8mr29539163oiv.7.1697232761697; Fri, 13 Oct 2023 14:32:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232761; cv=none; d=google.com; s=arc-20160816; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 18/85] target/sparc: Move RDWIM, RDPR to decodetree Date: Fri, 13 Oct 2023 14:27:39 -0700 Message-Id: <20231013212846.165724-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++ target/sparc/translate.c | 360 +++++++++++++++++++++++--------------- 2 files changed, 244 insertions(+), 138 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d3ca9061ce..05329803f4 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -56,3 +56,25 @@ RDHPR_hintp 10 rd:5 101001 00011 0 0000000000000 RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 + +{ + RDWIM 10 rd:5 101010 00000 0 0000000000000 + RDPR_tpc 10 rd:5 101010 00000 0 0000000000000 +} +RDPR_tnpc 10 rd:5 101010 00001 0 0000000000000 +RDPR_tstate 10 rd:5 101010 00010 0 0000000000000 +RDPR_tt 10 rd:5 101010 00011 0 0000000000000 +RDPR_tick 10 rd:5 101010 00100 0 0000000000000 +RDPR_tba 10 rd:5 101010 00101 0 0000000000000 +RDPR_pstate 10 rd:5 101010 00110 0 0000000000000 +RDPR_tl 10 rd:5 101010 00111 0 0000000000000 +RDPR_pil 10 rd:5 101010 01000 0 0000000000000 +RDPR_cwp 10 rd:5 101010 01001 0 0000000000000 +RDPR_cansave 10 rd:5 101010 01010 0 0000000000000 +RDPR_canrestore 10 rd:5 101010 01011 0 0000000000000 +RDPR_cleanwin 10 rd:5 101010 01100 0 0000000000000 +RDPR_otherwin 10 rd:5 101010 01101 0 0000000000000 +RDPR_wstate 10 rd:5 101010 01110 0 0000000000000 +RDPR_gl 10 rd:5 101010 10000 0 0000000000000 +RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 +RDPR_ver 10 rd:5 101010 11111 0 0000000000000 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a88f514399..00264326da 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -40,6 +40,7 @@ #define gen_helper_rdpsr(D, E) qemu_build_not_reached() #else #define gen_helper_rdccr(D, E) qemu_build_not_reached() +#define gen_helper_rdcwp(D, E) qemu_build_not_reached() #endif /* Dynamic PC, must exit to main loop. */ @@ -59,9 +60,7 @@ static TCGv_i32 cpu_psr; static TCGv cpu_fsr, cpu_pc, cpu_npc; static TCGv cpu_regs[32]; static TCGv cpu_y; -#ifndef CONFIG_USER_ONLY static TCGv cpu_tbr; -#endif static TCGv cpu_cond; #ifdef TARGET_SPARC64 static TCGv_i32 cpu_xcc, cpu_fprs; @@ -2648,8 +2647,7 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) gen_update_fprs_dirty(dc, qd); } -#ifndef CONFIG_USER_ONLY -static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env tcg_env) +static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr) { TCGv_i32 r_tl = tcg_temp_new_i32(); @@ -2670,7 +2668,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_env tcg_env) tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); } } -#endif static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, int width, bool cc, bool left) @@ -2809,6 +2806,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) # define avail_64(C) false #endif #define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) +#define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) #define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) /* Default case for non jump instructions. */ @@ -3370,6 +3368,221 @@ static TCGv do_rdhstick_cmpr(DisasContext *dc, TCGv dst) TRANS(RDHPR_hstick_cmpr, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdhstick_cmpr) +static TCGv do_rdwim(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + qemu_build_not_reached(); +#else + return cpu_wim; +#endif +} + +TRANS(RDWIM, 32, do_rd_special, supervisor(dc), a->rd, do_rdwim) + +static TCGv do_rdtpc(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr = tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tpc)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_tpc, 64, do_rd_special, supervisor(dc), a->rd, do_rdtpc) + +static TCGv do_rdtnpc(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr = tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tnpc)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_tnpc, 64, do_rd_special, supervisor(dc), a->rd, do_rdtnpc) + +static TCGv do_rdtstate(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr = tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_ld_tl(dst, r_tsptr, offsetof(trap_state, tstate)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_tstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdtstate) + +static TCGv do_rdtt(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr = tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_ld32s_tl(dst, r_tsptr, offsetof(trap_state, tt)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_tt, 64, do_rd_special, supervisor(dc), a->rd, do_rdtt) +TRANS(RDPR_tick, 64, do_rd_special, supervisor(dc), a->rd, do_rdtick) + +static TCGv do_rdtba(DisasContext *dc, TCGv dst) +{ + return cpu_tbr; +} + +TRANS(RDPR_tba, 64, do_rd_special, supervisor(dc), a->rd, do_rdtba) + +static TCGv do_rdpstate(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ld32s_tl(dst, tcg_env, offsetof(CPUSPARCState, pstate)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_pstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdpstate) + +static TCGv do_rdtl(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ld32s_tl(dst, tcg_env, offsetof(CPUSPARCState, tl)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_tl, 64, do_rd_special, supervisor(dc), a->rd, do_rdtl) + +static TCGv do_rdpil(DisasContext *dc, TCGv dst) +{ + tcg_gen_ld32s_tl(dst, tcg_env, offsetof(CPUSPARCState, psrpil)); + return dst; +} + +TRANS(RDPR_pil, 64, do_rd_special, supervisor(dc), a->rd, do_rdpil) + +static TCGv do_rdcwp(DisasContext *dc, TCGv dst) +{ + gen_helper_rdcwp(dst, tcg_env); + return dst; +} + +TRANS(RDPR_cwp, 64, do_rd_special, supervisor(dc), a->rd, do_rdcwp) + +static TCGv do_rdcansave(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ld32s_tl(dst, tcg_env, offsetof(CPUSPARCState, cansave)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_cansave, 64, do_rd_special, supervisor(dc), a->rd, do_rdcansave) + +static TCGv do_rdcanrestore(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ld32s_tl(dst, tcg_env, offsetof(CPUSPARCState, canrestore)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_canrestore, 64, do_rd_special, supervisor(dc), a->rd, + do_rdcanrestore) + +static TCGv do_rdcleanwin(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ld32s_tl(dst, tcg_env, offsetof(CPUSPARCState, cleanwin)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_cleanwin, 64, do_rd_special, supervisor(dc), a->rd, do_rdcleanwin) + +static TCGv do_rdotherwin(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ld32s_tl(dst, tcg_env, offsetof(CPUSPARCState, otherwin)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_otherwin, 64, do_rd_special, supervisor(dc), a->rd, do_rdotherwin) + +static TCGv do_rdwstate(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ld32s_tl(dst, tcg_env, offsetof(CPUSPARCState, wstate)); + return dst; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_wstate, 64, do_rd_special, supervisor(dc), a->rd, do_rdwstate) + +static TCGv do_rdgl(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + tcg_gen_ld32s_tl(dst, tcg_env, offsetof(CPUSPARCState, gl)); + return dst; +#else + g_assert_not_reached(); +#endif +} + +TRANS(RDPR_gl, GL, do_rd_special, supervisor(dc), a->rd, do_rdgl) + +/* UA2005 strand status */ +static TCGv do_rdssr(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + return cpu_ssr; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_strand_status, HYPV, do_rd_special, hypervisor(dc), a->rd, do_rdssr) + +static TCGv do_rdver(DisasContext *dc, TCGv dst) +{ +#ifdef TARGET_SPARC64 + return cpu_ver; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3400,133 +3613,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv cpu_dst __attribute__((unused)) = tcg_temp_new(); TCGv cpu_tmp0 __attribute__((unused)); -#if !defined(CONFIG_USER_ONLY) - if (xop == 0x2a) { /* rdwim / V9 rdpr */ - if (!supervisor(dc)) { - goto priv_insn; - } - cpu_tmp0 = tcg_temp_new(); -#ifdef TARGET_SPARC64 - rs1 = GET_FIELD(insn, 13, 17); - switch (rs1) { - case 0: // tpc - { - TCGv_ptr r_tsptr; - - r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg_env); - tcg_gen_ld_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tpc)); - } - break; - case 1: // tnpc - { - TCGv_ptr r_tsptr; - - r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg_env); - tcg_gen_ld_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tnpc)); - } - break; - case 2: // tstate - { - TCGv_ptr r_tsptr; - - r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg_env); - tcg_gen_ld_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tstate)); - } - break; - case 3: // tt - { - TCGv_ptr r_tsptr = tcg_temp_new_ptr(); - - gen_load_trap_state_at_tl(r_tsptr, tcg_env); - tcg_gen_ld32s_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tt)); - } - break; - case 4: // tick - { - TCGv_ptr r_tickptr; - TCGv_i32 r_const; - - r_tickptr = tcg_temp_new_ptr(); - r_const = tcg_constant_i32(dc->mem_idx); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, tick)); - if (translator_io_start(&dc->base)) { - dc->base.is_jmp = DISAS_EXIT; - } - gen_helper_tick_get_count(cpu_tmp0, tcg_env, - r_tickptr, r_const); - } - break; - case 5: // tba - tcg_gen_mov_tl(cpu_tmp0, cpu_tbr); - break; - case 6: // pstate - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, pstate)); - break; - case 7: // tl - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, tl)); - break; - case 8: // pil - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, psrpil)); - break; - case 9: // cwp - gen_helper_rdcwp(cpu_tmp0, tcg_env); - break; - case 10: // cansave - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, cansave)); - break; - case 11: // canrestore - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, canrestore)); - break; - case 12: // cleanwin - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, cleanwin)); - break; - case 13: // otherwin - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, otherwin)); - break; - case 14: // wstate - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, wstate)); - break; - case 16: // UA2005 gl - CHECK_IU_FEATURE(dc, GL); - tcg_gen_ld32s_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, gl)); - break; - case 26: // UA2005 strand status - CHECK_IU_FEATURE(dc, HYPV); - if (!hypervisor(dc)) - goto priv_insn; - tcg_gen_mov_tl(cpu_tmp0, cpu_ssr); - break; - case 31: // ver - tcg_gen_mov_tl(cpu_tmp0, cpu_ver); - break; - case 15: // fq - default: - goto illegal_insn; - } -#else - tcg_gen_ext_i32_tl(cpu_tmp0, cpu_wim); -#endif - gen_store_gpr(dc, rd, cpu_tmp0); - break; - } -#endif #if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) if (xop == 0x2b) { /* rdtbr / V9 flushw */ #ifdef TARGET_SPARC64 @@ -4368,7 +4454,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv_ptr r_tsptr; r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg_env); + gen_load_trap_state_at_tl(r_tsptr); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tpc)); } @@ -4378,7 +4464,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv_ptr r_tsptr; r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg_env); + gen_load_trap_state_at_tl(r_tsptr); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tnpc)); } @@ -4388,7 +4474,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv_ptr r_tsptr; r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg_env); + gen_load_trap_state_at_tl(r_tsptr); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tstate)); @@ -4399,7 +4485,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv_ptr r_tsptr; r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr, tcg_env); + gen_load_trap_state_at_tl(r_tsptr); tcg_gen_st32_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tt)); } @@ -5803,9 +5889,7 @@ void sparc_tcg_init(void) { &cpu_pc, offsetof(CPUSPARCState, pc), "pc" }, { &cpu_npc, offsetof(CPUSPARCState, npc), "npc" }, { &cpu_y, offsetof(CPUSPARCState, y), "y" }, -#ifndef CONFIG_USER_ONLY { &cpu_tbr, offsetof(CPUSPARCState, tbr), "tbr" }, -#endif }; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 19/85] target/sparc: Move RDTBR, FLUSHW to decodetree Date: Fri, 13 Oct 2023 14:27:40 -0700 Message-Id: <20231013212846.165724-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++++ target/sparc/translate.c | 23 +++++++++++------------ 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 05329803f4..9142e0e2f0 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -78,3 +78,8 @@ RDPR_wstate 10 rd:5 101010 01110 0 0000000000000 RDPR_gl 10 rd:5 101010 10000 0 0000000000000 RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 RDPR_ver 10 rd:5 101010 11111 0 0000000000000 + +{ + FLUSHW 10 00000 101011 00000 0 0000000000000 + RDTBR 10 rd:5 101011 00000 0 0000000000000 +} diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 00264326da..26601e508f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3445,6 +3445,7 @@ static TCGv do_rdtba(DisasContext *dc, TCGv dst) return cpu_tbr; } +TRANS(RDTBR, 32, do_rd_special, supervisor(dc), a->rd, do_rdtba) TRANS(RDPR_tba, 64, do_rd_special, supervisor(dc), a->rd, do_rdtba) static TCGv do_rdpstate(DisasContext *dc, TCGv dst) @@ -3583,6 +3584,16 @@ static TCGv do_rdver(DisasContext *dc, TCGv dst) TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver) +static bool trans_FLUSHW(DisasContext *dc, arg_FLUSHW *a) +{ +#ifdef TARGET_SPARC64 + gen_helper_flushw(tcg_env); + return advance_pc(dc); +#else + return false; +#endif +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3613,18 +3624,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv cpu_dst __attribute__((unused)) = tcg_temp_new(); TCGv cpu_tmp0 __attribute__((unused)); -#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) - if (xop == 0x2b) { /* rdtbr / V9 flushw */ -#ifdef TARGET_SPARC64 - gen_helper_flushw(tcg_env); -#else - if (!supervisor(dc)) - goto priv_insn; - gen_store_gpr(dc, rd, cpu_tbr); -#endif - break; - } -#endif if (xop == 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) { goto jmp_insn; From patchwork Fri Oct 13 21:27:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733276 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678622wrv; Fri, 13 Oct 2023 14:32:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGceQOq/t7q3jMrSVDzI09c2gBkbvxz0IacERe8yBQVcDg2R8lMaA4lv8AfTCvqxYIkTpy9 X-Received: by 2002:a05:620a:2903:b0:775:9071:fbc9 with SMTP id m3-20020a05620a290300b007759071fbc9mr33544893qkp.20.1697232755021; Fri, 13 Oct 2023 14:32:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232755; cv=none; d=google.com; s=arc-20160816; b=eIatvBOY9Bbq/0CN5HLJm7FZm+KHfQiZAml20Wgx0QQf7SBDF1K3cuatKcgOehO2iw SPdXkbdxsuGX159wmt06lUZKPNhUSDj/p8umN31Jcqp4BYKIA2oVyME892CrxyAhqN8G dmT7NOaiusDveZK7IwICQRHnlf8woX8TlDyMljOiFdQzVqH11f7JaLP6Z/yO+Gurzvxd ZHoGcVzxYxzfNljYqkDQWzSHtshis/rVEY38PoMBxNX4MWL5xcpEpjGaQXMHXdXfR3tj mdny/FB9ZCzVrbv+vzhI1dhPLjq5pVEkcBevL50r3FiDFhLden7iXDLdOxsOzIrTvhyj 8dkA== ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 20/85] target/sparc: Move WRASR to decodetree Date: Fri, 13 Oct 2023 14:27:41 -0700 Message-Id: <20231013212846.165724-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 31 ++++ target/sparc/translate.c | 353 +++++++++++++++++++++----------------- 2 files changed, 225 insertions(+), 159 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 9142e0e2f0..c253c6b1c1 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -22,6 +22,13 @@ SETHI 00 rd:5 100 i:22 CALL 01 i:s30 +## +## Major Opcode 10 -- integer, floating-point, vis, and system insns. +## + +&r_r_ri rd rs1 rs2_or_imm imm:bool +@n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0 + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 Tcc_i 10 0 cond:4 111010 rs1:5 1 cc:1 0000 i:8 @@ -47,6 +54,30 @@ Tcc_i 10 0 cond:4 111010 rs1:5 1 cc:1 0000 i:8 RDY 10 rd:5 101000 rs1:5 0 0000000000000 } +{ + [ + WRY 10 00000 110000 ..... . ............. @n_r_ri + WRCCR 10 00010 110000 ..... . ............. @n_r_ri + WRASI 10 00011 110000 ..... . ............. @n_r_ri + WRFPRS 10 00110 110000 ..... . ............. @n_r_ri + { + WRGSR 10 10011 110000 ..... . ............. @n_r_ri + WRPOWERDOWN 10 10011 110000 ..... . ............. @n_r_ri + } + WRSOFTINT_SET 10 10100 110000 ..... . ............. @n_r_ri + WRSOFTINT_CLR 10 10101 110000 ..... . ............. @n_r_ri + WRSOFTINT 10 10110 110000 ..... . ............. @n_r_ri + WRTICK_CMPR 10 10111 110000 ..... . ............. @n_r_ri + WRSTICK 10 11000 110000 ..... . ............. @n_r_ri + WRSTICK_CMPR 10 11001 110000 ..... . ............. @n_r_ri + ] + # Before v8, rs1==0 was WRY, and the rest executed as nop. + [ + NOP_v7 10 ----- 110000 ----- 0 00000000 ----- + NOP_v7 10 ----- 110000 ----- 1 -------- ----- + ] +} + { RDPSR 10 rd:5 101001 00000 0 0000000000000 RDHPR_hpstate 10 rd:5 101001 00000 0 0000000000000 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 26601e508f..917a4299ff 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -37,10 +37,15 @@ #undef HELPER_H #ifdef TARGET_SPARC64 -#define gen_helper_rdpsr(D, E) qemu_build_not_reached() +#define gen_helper_rdpsr(D, E) qemu_build_not_reached() +#define gen_helper_power_down(E) g_assert_not_reached() #else -#define gen_helper_rdccr(D, E) qemu_build_not_reached() -#define gen_helper_rdcwp(D, E) qemu_build_not_reached() +#define gen_helper_rdccr(D, E) qemu_build_not_reached() +#define gen_helper_rdcwp(D, E) qemu_build_not_reached() +#define gen_helper_wrccr(E, S) qemu_build_not_reached() +#define gen_helper_set_softint(E, S) qemu_build_not_reached() +#define gen_helper_clear_softint(E, S) qemu_build_not_reached() +#define gen_helper_write_softint(E, S) qemu_build_not_reached() #endif /* Dynamic PC, must exit to main loop. */ @@ -2808,6 +2813,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) #define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) #define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) #define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) +#define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN) /* Default case for non jump instructions. */ static bool advance_pc(DisasContext *dc) @@ -3025,6 +3031,10 @@ static bool trans_SETHI(DisasContext *dc, arg_SETHI *a) return advance_pc(dc); } +/* + * Major Opcode 10 -- integer, floating-point, vis, and system insns. + */ + static bool do_tcc(DisasContext *dc, int cc, int cond, bool imm, int rs1, int rs2_or_imm) { @@ -3594,6 +3604,186 @@ static bool trans_FLUSHW(DisasContext *dc, arg_FLUSHW *a) #endif } +static bool do_wr_special(DisasContext *dc, arg_r_r_ri *a, bool priv, + void (*func)(DisasContext *, TCGv)) +{ + TCGv src; + + /* For simplicity, we under-decoded the rs2 form. */ + if (!a->imm && (a->rs2_or_imm & ~0x1f)) { + return false; + } + if (!priv) { + return raise_priv(dc); + } + + if (a->rs1 == 0 && (a->imm || a->rs2_or_imm == 0)) { + src = tcg_constant_tl(a->rs2_or_imm); + } else { + TCGv src1 = gen_load_gpr(dc, a->rs1); + if (a->rs2_or_imm == 0) { + src = src1; + } else { + src = tcg_temp_new(); + if (a->imm) { + tcg_gen_xori_tl(src, src1, a->rs2_or_imm); + } else { + tcg_gen_xor_tl(src, src1, gen_load_gpr(dc, a->rs2_or_imm)); + } + } + } + func(dc, src); + return advance_pc(dc); +} + +static void do_wry(DisasContext *dc, TCGv src) +{ + tcg_gen_ext32u_tl(cpu_y, src); +} + +TRANS(WRY, ALL, do_wr_special, a, true, do_wry) + +static void do_wrccr(DisasContext *dc, TCGv src) +{ + gen_helper_wrccr(tcg_env, src); +} + +TRANS(WRCCR, 64, do_wr_special, a, true, do_wrccr) + +static void do_wrasi(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv tmp = tcg_temp_new(); + tcg_gen_andi_tl(tmp, src, 0xff); + tcg_gen_st32_tl(tmp, tcg_env, offsetof(CPUSPARCState, asi)); + /* End TB to notice changed ASI. */ + dc->base.is_jmp = DISAS_EXIT; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRASI, 64, do_wr_special, a, true, do_wrasi) + +static void do_wrfprs(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_trunc_tl_i32(cpu_fprs, src); + dc->fprs_dirty = 0; + dc->base.is_jmp = DISAS_EXIT; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRFPRS, 64, do_wr_special, a, true, do_wrfprs) + +static void do_wrgsr(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + gen_trap_ifnofpu(dc); + tcg_gen_mov_tl(cpu_gsr, src); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRGSR, 64, do_wr_special, a, true, do_wrgsr) + +static void do_wrsoftint_set(DisasContext *dc, TCGv src) +{ + gen_helper_set_softint(tcg_env, src); +} + +TRANS(WRSOFTINT_SET, 64, do_wr_special, a, supervisor(dc), do_wrsoftint_set) + +static void do_wrsoftint_clr(DisasContext *dc, TCGv src) +{ + gen_helper_clear_softint(tcg_env, src); +} + +TRANS(WRSOFTINT_CLR, 64, do_wr_special, a, supervisor(dc), do_wrsoftint_clr) + +static void do_wrsoftint(DisasContext *dc, TCGv src) +{ + gen_helper_write_softint(tcg_env, src); +} + +TRANS(WRSOFTINT, 64, do_wr_special, a, supervisor(dc), do_wrsoftint) + +static void do_wrtick_cmpr(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tickptr = tcg_temp_new_ptr(); + + tcg_gen_mov_tl(cpu_tick_cmpr, src); + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, tick)); + translator_io_start(&dc->base); + gen_helper_tick_set_limit(r_tickptr, cpu_tick_cmpr); + /* End TB to handle timer interrupt */ + dc->base.is_jmp = DISAS_EXIT; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrtick_cmpr) + +static void do_wrstick(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tickptr = tcg_temp_new_ptr(); + + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick)); + translator_io_start(&dc->base); + gen_helper_tick_set_count(r_tickptr, src); + /* End TB to handle timer interrupt */ + dc->base.is_jmp = DISAS_EXIT; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRSTICK, 64, do_wr_special, a, supervisor(dc), do_wrstick) + +static void do_wrstick_cmpr(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tickptr = tcg_temp_new_ptr(); + + tcg_gen_mov_tl(cpu_stick_cmpr, src); + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, stick)); + translator_io_start(&dc->base); + gen_helper_tick_set_limit(r_tickptr, cpu_stick_cmpr); + /* End TB to handle timer interrupt */ + dc->base.is_jmp = DISAS_EXIT; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRSTICK_CMPR, 64, do_wr_special, a, supervisor(dc), do_wrstick_cmpr) + +static void do_wrpowerdown(DisasContext *dc, TCGv src) +{ + save_state(dc); + gen_helper_power_down(tcg_env); +} + +TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpowerdown) + +static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a) +{ + /* + * TODO: Need a feature bit for sparcv8. + * In the meantime, treat all 32-bit cpus like sparcv7. + */ + if (avail_32(dc)) { + return advance_pc(dc); + } + return false; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4250,162 +4440,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) break; #endif case 0x30: - { - cpu_tmp0 = tcg_temp_new(); - switch(rd) { - case 0: /* wry */ - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); - break; -#ifndef TARGET_SPARC64 - case 0x01 ... 0x0f: /* undefined in the - SPARCv8 manual, nop - on the microSPARC - II */ - case 0x10 ... 0x1f: /* implementation-dependent - in the SPARCv8 - manual, nop on the - microSPARC II */ - if ((rd == 0x13) && (dc->def->features & - CPU_FEATURE_POWERDOWN)) { - /* LEON3 power-down */ - save_state(dc); - gen_helper_power_down(tcg_env); - } - break; -#else - case 0x2: /* V9 wrccr */ - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - gen_helper_wrccr(tcg_env, cpu_tmp0); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); - dc->cc_op = CC_OP_FLAGS; - break; - case 0x3: /* V9 wrasi */ - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xff); - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, asi)); - /* - * End TB to notice changed ASI. - * TODO: Could notice src1 = %g0 and IS_IMM, - * update DisasContext and not exit the TB. - */ - save_state(dc); - gen_op_next_insn(); - tcg_gen_lookup_and_goto_ptr(); - dc->base.is_jmp = DISAS_NORETURN; - break; - case 0x6: /* V9 wrfprs */ - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - tcg_gen_trunc_tl_i32(cpu_fprs, cpu_tmp0); - dc->fprs_dirty = 0; - save_state(dc); - gen_op_next_insn(); - tcg_gen_exit_tb(NULL, 0); - dc->base.is_jmp = DISAS_NORETURN; - break; - case 0xf: /* V9 sir, nop if user */ -#if !defined(CONFIG_USER_ONLY) - if (supervisor(dc)) { - ; // XXX - } -#endif - break; - case 0x13: /* Graphics Status */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2); - break; - case 0x14: /* Softint set */ - if (!supervisor(dc)) - goto illegal_insn; - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - gen_helper_set_softint(tcg_env, cpu_tmp0); - break; - case 0x15: /* Softint clear */ - if (!supervisor(dc)) - goto illegal_insn; - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - gen_helper_clear_softint(tcg_env, cpu_tmp0); - break; - case 0x16: /* Softint write */ - if (!supervisor(dc)) - goto illegal_insn; - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - gen_helper_write_softint(tcg_env, cpu_tmp0); - break; - case 0x17: /* Tick compare */ -#if !defined(CONFIG_USER_ONLY) - if (!supervisor(dc)) - goto illegal_insn; -#endif - { - TCGv_ptr r_tickptr; - - tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, - cpu_src2); - r_tickptr = tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, tick)); - translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, - cpu_tick_cmpr); - /* End TB to handle timer interrupt */ - dc->base.is_jmp = DISAS_EXIT; - } - break; - case 0x18: /* System tick */ -#if !defined(CONFIG_USER_ONLY) - if (!supervisor(dc)) - goto illegal_insn; -#endif - { - TCGv_ptr r_tickptr; - - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, - cpu_src2); - r_tickptr = tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, stick)); - translator_io_start(&dc->base); - gen_helper_tick_set_count(r_tickptr, - cpu_tmp0); - /* End TB to handle timer interrupt */ - dc->base.is_jmp = DISAS_EXIT; - } - break; - case 0x19: /* System tick compare */ -#if !defined(CONFIG_USER_ONLY) - if (!supervisor(dc)) - goto illegal_insn; -#endif - { - TCGv_ptr r_tickptr; - - tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, - cpu_src2); - r_tickptr = tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, stick)); - translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, - cpu_stick_cmpr); - /* End TB to handle timer interrupt */ - dc->base.is_jmp = DISAS_EXIT; - } - break; - - case 0x10: /* Performance Control */ - case 0x11: /* Performance Instrumentation - Counter */ - case 0x12: /* Dispatch Control */ -#endif - default: - goto illegal_insn; - } - } - break; + goto illegal_insn; /* WRASR in decodetree */ #if !defined(CONFIG_USER_ONLY) case 0x31: /* wrpsr, V9 saved, restored */ { From patchwork Fri Oct 13 21:27:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733289 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679069wrv; Fri, 13 Oct 2023 14:34:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG6eYi8YWerjhbm+lq3P7+V3Eelq0vIsJzeDn3OVcfgAysbwc2k/1MPSuGPrX92sgPDdnyE X-Received: by 2002:ac8:5dc7:0:b0:418:152d:bf4 with SMTP id e7-20020ac85dc7000000b00418152d0bf4mr31137396qtx.51.1697232840176; Fri, 13 Oct 2023 14:34:00 -0700 (PDT) ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 21/85] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree Date: Fri, 13 Oct 2023 14:27:42 -0700 Message-Id: <20231013212846.165724-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 10 +++++++ target/sparc/translate.c | 61 ++++++++++++++++++--------------------- 2 files changed, 38 insertions(+), 33 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index c253c6b1c1..db5a899bdf 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -88,6 +88,16 @@ RDHPR_htba 10 rd:5 101001 00101 0 0000000000000 RDHPR_hver 10 rd:5 101001 00110 0 0000000000000 RDHPR_hstick_cmpr 10 rd:5 101001 11111 0 0000000000000 +{ + WRPSR 10 00000 110001 ..... . ............. @n_r_ri + SAVED 10 00000 110001 00000 0 0000000000000 +} +RESTORED 10 00001 110001 00000 0 0000000000000 +# UA2005 ALLCLEAN +# UA2005 OTHERW +# UA2005 NORMALW +# UA2005 INVALW + { RDWIM 10 rd:5 101010 00000 0 0000000000000 RDPR_tpc 10 rd:5 101010 00000 0 0000000000000 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 917a4299ff..5f2e5d5a82 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -38,6 +38,7 @@ #ifdef TARGET_SPARC64 #define gen_helper_rdpsr(D, E) qemu_build_not_reached() +#define gen_helper_wrpsr(E, S) qemu_build_not_reached() #define gen_helper_power_down(E) g_assert_not_reached() #else #define gen_helper_rdccr(D, E) qemu_build_not_reached() @@ -46,6 +47,8 @@ #define gen_helper_set_softint(E, S) qemu_build_not_reached() #define gen_helper_clear_softint(E, S) qemu_build_not_reached() #define gen_helper_write_softint(E, S) qemu_build_not_reached() +#define gen_helper_saved ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_restored ({ qemu_build_not_reached(); NULL; }) #endif /* Dynamic PC, must exit to main loop. */ @@ -3772,6 +3775,31 @@ static void do_wrpowerdown(DisasContext *dc, TCGv src) TRANS(WRPOWERDOWN, POWERDOWN, do_wr_special, a, supervisor(dc), do_wrpowerdown) +static void do_wrpsr(DisasContext *dc, TCGv src) +{ + gen_helper_wrpsr(tcg_env, src); + tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); + dc->cc_op = CC_OP_FLAGS; + save_state(dc); + gen_op_next_insn(); + tcg_gen_exit_tb(NULL, 0); + dc->base.is_jmp = DISAS_NORETURN; +} + +TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr) + +static bool do_saved_restored(DisasContext *dc, void (*func)(TCGv_env)) +{ + if (!supervisor(dc)) { + return raise_priv(dc); + } + func(tcg_env); + return advance_pc(dc); +} + +TRANS(SAVED, 64, do_saved_restored, gen_helper_saved) +TRANS(RESTORED, 64, do_saved_restored, gen_helper_restored) + static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a) { /* @@ -4442,39 +4470,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x30: goto illegal_insn; /* WRASR in decodetree */ #if !defined(CONFIG_USER_ONLY) - case 0x31: /* wrpsr, V9 saved, restored */ - { - if (!supervisor(dc)) - goto priv_insn; -#ifdef TARGET_SPARC64 - switch (rd) { - case 0: - gen_helper_saved(tcg_env); - break; - case 1: - gen_helper_restored(tcg_env); - break; - case 2: /* UA2005 allclean */ - case 3: /* UA2005 otherw */ - case 4: /* UA2005 normalw */ - case 5: /* UA2005 invalw */ - // XXX - default: - goto illegal_insn; - } -#else - cpu_tmp0 = tcg_temp_new(); - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - gen_helper_wrpsr(tcg_env, cpu_tmp0); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS); - dc->cc_op = CC_OP_FLAGS; - save_state(dc); - gen_op_next_insn(); - tcg_gen_exit_tb(NULL, 0); - dc->base.is_jmp = DISAS_NORETURN; -#endif - } - break; case 0x32: /* wrwim, V9 wrpr */ { if (!supervisor(dc)) From patchwork Fri Oct 13 21:27:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733266 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678044wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 22/85] target/sparc: Move WRWIM, WRPR to decodetree Date: Fri, 13 Oct 2023 14:27:43 -0700 Message-Id: <20231013212846.165724-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 21 +++ target/sparc/translate.c | 350 +++++++++++++++++++++++--------------- 2 files changed, 235 insertions(+), 136 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index db5a899bdf..b61926d278 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -120,6 +120,27 @@ RDPR_gl 10 rd:5 101010 10000 0 0000000000000 RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 RDPR_ver 10 rd:5 101010 11111 0 0000000000000 +{ + WRWIM 10 00000 110010 ..... . ............. @n_r_ri + WRPR_tpc 10 00000 110010 ..... . ............. @n_r_ri +} +WRPR_tnpc 10 00001 110010 ..... . ............. @n_r_ri +WRPR_tstate 10 00010 110010 ..... . ............. @n_r_ri +WRPR_tt 10 00011 110010 ..... . ............. @n_r_ri +WRPR_tick 10 00100 110010 ..... . ............. @n_r_ri +WRPR_tba 10 00101 110010 ..... . ............. @n_r_ri +WRPR_pstate 10 00110 110010 ..... . ............. @n_r_ri +WRPR_tl 10 00111 110010 ..... . ............. @n_r_ri +WRPR_pil 10 01000 110010 ..... . ............. @n_r_ri +WRPR_cwp 10 01001 110010 ..... . ............. @n_r_ri +WRPR_cansave 10 01010 110010 ..... . ............. @n_r_ri +WRPR_canrestore 10 01011 110010 ..... . ............. @n_r_ri +WRPR_cleanwin 10 01100 110010 ..... . ............. @n_r_ri +WRPR_otherwin 10 01101 110010 ..... . ............. @n_r_ri +WRPR_wstate 10 01110 110010 ..... . ............. @n_r_ri +WRPR_gl 10 10000 110010 ..... . ............. @n_r_ri +WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri + { FLUSHW 10 00000 101011 00000 0 0000000000000 RDTBR 10 rd:5 101011 00000 0 0000000000000 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5f2e5d5a82..4b4ca04d62 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -44,6 +44,10 @@ #define gen_helper_rdccr(D, E) qemu_build_not_reached() #define gen_helper_rdcwp(D, E) qemu_build_not_reached() #define gen_helper_wrccr(E, S) qemu_build_not_reached() +#define gen_helper_wrcwp(E, S) qemu_build_not_reached() +#define gen_helper_wrgl(E, S) g_assert_not_reached() +#define gen_helper_wrpil(E, S) qemu_build_not_reached() +#define gen_helper_wrpstate(E, S) qemu_build_not_reached() #define gen_helper_set_softint(E, S) qemu_build_not_reached() #define gen_helper_clear_softint(E, S) qemu_build_not_reached() #define gen_helper_write_softint(E, S) qemu_build_not_reached() @@ -3788,6 +3792,214 @@ static void do_wrpsr(DisasContext *dc, TCGv src) TRANS(WRPSR, 32, do_wr_special, a, supervisor(dc), do_wrpsr) +static void do_wrwim(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + qemu_build_not_reached(); +#else + target_ulong mask = MAKE_64BIT_MASK(0, dc->def->nwindows); + tcg_gen_andi_tl(cpu_wim, src, mask); +#endif +} + +TRANS(WRWIM, 32, do_wr_special, a, supervisor(dc), do_wrwim) + +static void do_wrtpc(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr = tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tpc)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_tpc, 64, do_wr_special, a, supervisor(dc), do_wrtpc) + +static void do_wrtnpc(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr = tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tnpc)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_tnpc, 64, do_wr_special, a, supervisor(dc), do_wrtnpc) + +static void do_wrtstate(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr = tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_st_tl(src, r_tsptr, offsetof(trap_state, tstate)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_tstate, 64, do_wr_special, a, supervisor(dc), do_wrtstate) + +static void do_wrtt(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tsptr = tcg_temp_new_ptr(); + + gen_load_trap_state_at_tl(r_tsptr); + tcg_gen_st32_tl(src, r_tsptr, offsetof(trap_state, tt)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_tt, 64, do_wr_special, a, supervisor(dc), do_wrtt) + +static void do_wrtick(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tickptr = tcg_temp_new_ptr(); + + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, tick)); + translator_io_start(&dc->base); + gen_helper_tick_set_count(r_tickptr, src); + /* End TB to handle timer interrupt */ + dc->base.is_jmp = DISAS_EXIT; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_tick, 64, do_wr_special, a, supervisor(dc), do_wrtick) + +static void do_wrtba(DisasContext *dc, TCGv src) +{ + tcg_gen_mov_tl(cpu_tbr, src); +} + +TRANS(WRPR_tba, 64, do_wr_special, a, supervisor(dc), do_wrtba) + +static void do_wrpstate(DisasContext *dc, TCGv src) +{ + save_state(dc); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp = DISAS_EXIT; + } + gen_helper_wrpstate(tcg_env, src); + dc->npc = DYNAMIC_PC; +} + +TRANS(WRPR_pstate, 64, do_wr_special, a, supervisor(dc), do_wrpstate) + +static void do_wrtl(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + save_state(dc); + tcg_gen_st32_tl(src, tcg_env, offsetof(CPUSPARCState, tl)); + dc->npc = DYNAMIC_PC; +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_tl, 64, do_wr_special, a, supervisor(dc), do_wrtl) + +static void do_wrpil(DisasContext *dc, TCGv src) +{ + if (translator_io_start(&dc->base)) { + dc->base.is_jmp = DISAS_EXIT; + } + gen_helper_wrpil(tcg_env, src); +} + +TRANS(WRPR_pil, 64, do_wr_special, a, supervisor(dc), do_wrpil) + +static void do_wrcwp(DisasContext *dc, TCGv src) +{ + gen_helper_wrcwp(tcg_env, src); +} + +TRANS(WRPR_cwp, 64, do_wr_special, a, supervisor(dc), do_wrcwp) + +static void do_wrcansave(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_st32_tl(src, tcg_env, offsetof(CPUSPARCState, cansave)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_cansave, 64, do_wr_special, a, supervisor(dc), do_wrcansave) + +static void do_wrcanrestore(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_st32_tl(src, tcg_env, offsetof(CPUSPARCState, canrestore)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_canrestore, 64, do_wr_special, a, supervisor(dc), do_wrcanrestore) + +static void do_wrcleanwin(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_st32_tl(src, tcg_env, offsetof(CPUSPARCState, cleanwin)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_cleanwin, 64, do_wr_special, a, supervisor(dc), do_wrcleanwin) + +static void do_wrotherwin(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_st32_tl(src, tcg_env, offsetof(CPUSPARCState, otherwin)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_otherwin, 64, do_wr_special, a, supervisor(dc), do_wrotherwin) + +static void do_wrwstate(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_st32_tl(src, tcg_env, offsetof(CPUSPARCState, wstate)); +#else + qemu_build_not_reached(); +#endif +} + +TRANS(WRPR_wstate, 64, do_wr_special, a, supervisor(dc), do_wrwstate) + +static void do_wrgl(DisasContext *dc, TCGv src) +{ + gen_helper_wrgl(tcg_env, src); +} + +TRANS(WRPR_gl, GL, do_wr_special, a, supervisor(dc), do_wrgl) + +/* UA2005 strand status */ +static void do_wrssr(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_mov_tl(cpu_ssr, src); +#else + g_assert_not_reached(); +#endif +} + +TRANS(WRPR_strand_status, HYPV, do_wr_special, a, hypervisor(dc), do_wrssr) + static bool do_saved_restored(DisasContext *dc, void (*func)(TCGv_env)) { if (!supervisor(dc)) { @@ -4470,142 +4682,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x30: goto illegal_insn; /* WRASR in decodetree */ #if !defined(CONFIG_USER_ONLY) - case 0x32: /* wrwim, V9 wrpr */ - { - if (!supervisor(dc)) - goto priv_insn; - cpu_tmp0 = tcg_temp_new(); - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); -#ifdef TARGET_SPARC64 - switch (rd) { - case 0: // tpc - { - TCGv_ptr r_tsptr; - - r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr); - tcg_gen_st_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tpc)); - } - break; - case 1: // tnpc - { - TCGv_ptr r_tsptr; - - r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr); - tcg_gen_st_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tnpc)); - } - break; - case 2: // tstate - { - TCGv_ptr r_tsptr; - - r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr); - tcg_gen_st_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, - tstate)); - } - break; - case 3: // tt - { - TCGv_ptr r_tsptr; - - r_tsptr = tcg_temp_new_ptr(); - gen_load_trap_state_at_tl(r_tsptr); - tcg_gen_st32_tl(cpu_tmp0, r_tsptr, - offsetof(trap_state, tt)); - } - break; - case 4: // tick - { - TCGv_ptr r_tickptr; - - r_tickptr = tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, tick)); - translator_io_start(&dc->base); - gen_helper_tick_set_count(r_tickptr, - cpu_tmp0); - /* End TB to handle timer interrupt */ - dc->base.is_jmp = DISAS_EXIT; - } - break; - case 5: // tba - tcg_gen_mov_tl(cpu_tbr, cpu_tmp0); - break; - case 6: // pstate - save_state(dc); - if (translator_io_start(&dc->base)) { - dc->base.is_jmp = DISAS_EXIT; - } - gen_helper_wrpstate(tcg_env, cpu_tmp0); - dc->npc = DYNAMIC_PC; - break; - case 7: // tl - save_state(dc); - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, tl)); - dc->npc = DYNAMIC_PC; - break; - case 8: // pil - if (translator_io_start(&dc->base)) { - dc->base.is_jmp = DISAS_EXIT; - } - gen_helper_wrpil(tcg_env, cpu_tmp0); - break; - case 9: // cwp - gen_helper_wrcwp(tcg_env, cpu_tmp0); - break; - case 10: // cansave - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - cansave)); - break; - case 11: // canrestore - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - canrestore)); - break; - case 12: // cleanwin - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - cleanwin)); - break; - case 13: // otherwin - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - otherwin)); - break; - case 14: // wstate - tcg_gen_st32_tl(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - wstate)); - break; - case 16: // UA2005 gl - CHECK_IU_FEATURE(dc, GL); - gen_helper_wrgl(tcg_env, cpu_tmp0); - break; - case 26: // UA2005 strand status - CHECK_IU_FEATURE(dc, HYPV); - if (!hypervisor(dc)) - goto priv_insn; - tcg_gen_mov_tl(cpu_ssr, cpu_tmp0); - break; - default: - goto illegal_insn; - } -#else - tcg_gen_trunc_tl_i32(cpu_wim, cpu_tmp0); - if (dc->def->nwindows != 32) { - tcg_gen_andi_tl(cpu_wim, cpu_wim, - (1 << dc->def->nwindows) - 1); - } -#endif - } - break; + case 0x32: + goto illegal_insn; /* WRPR in decodetree */ case 0x33: /* wrtbr, UA2005 wrhpr */ { #ifndef TARGET_SPARC64 From patchwork Fri Oct 13 21:27:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733274 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678524wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 23/85] target/sparc: Move WRTBR, WRHPR to decodetree Date: Fri, 13 Oct 2023 14:27:44 -0700 Message-Id: <20231013212846.165724-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 9 ++++ target/sparc/translate.c | 110 +++++++++++++++++++------------------- 2 files changed, 65 insertions(+), 54 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index b61926d278..0425764973 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -145,3 +145,12 @@ WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri FLUSHW 10 00000 101011 00000 0 0000000000000 RDTBR 10 rd:5 101011 00000 0 0000000000000 } + +{ + WRTBR 10 00000 110011 ..... . ............. @n_r_ri + WRHPR_hpstate 10 00000 110011 ..... . ............. @n_r_ri +} +# WRHPR_htstate +WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri +WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri +WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 4b4ca04d62..efb3c7c570 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4000,6 +4000,61 @@ static void do_wrssr(DisasContext *dc, TCGv src) TRANS(WRPR_strand_status, HYPV, do_wr_special, a, hypervisor(dc), do_wrssr) +TRANS(WRTBR, 32, do_wr_special, a, supervisor(dc), do_wrtba) + +static void do_wrhpstate(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_st_i64(src, tcg_env, offsetof(CPUSPARCState, hpstate)); + dc->base.is_jmp = DISAS_EXIT; +#else + g_assert_not_reached(); +#endif +} + +TRANS(WRHPR_hpstate, HYPV, do_wr_special, a, hypervisor(dc), do_wrhpstate) + +static void do_wrhintp(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_mov_tl(cpu_hintp, src); +#else + g_assert_not_reached(); +#endif +} + +TRANS(WRHPR_hintp, HYPV, do_wr_special, a, hypervisor(dc), do_wrhintp) + +static void do_wrhtba(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + tcg_gen_mov_tl(cpu_htba, src); +#else + g_assert_not_reached(); +#endif +} + +TRANS(WRHPR_htba, HYPV, do_wr_special, a, hypervisor(dc), do_wrhtba) + +static void do_wrhstick_cmpr(DisasContext *dc, TCGv src) +{ +#ifdef TARGET_SPARC64 + TCGv_ptr r_tickptr = tcg_temp_new_ptr(); + + tcg_gen_mov_tl(cpu_hstick_cmpr, src); + tcg_gen_ld_ptr(r_tickptr, tcg_env, offsetof(CPUSPARCState, hstick)); + translator_io_start(&dc->base); + gen_helper_tick_set_limit(r_tickptr, cpu_hstick_cmpr); + /* End TB to handle timer interrupt */ + dc->base.is_jmp = DISAS_EXIT; +#else + g_assert_not_reached(); +#endif +} + +TRANS(WRHPR_hstick_cmpr, HYPV, do_wr_special, a, hypervisor(dc), + do_wrhstick_cmpr) + static bool do_saved_restored(DisasContext *dc, void (*func)(TCGv_env)) { if (!supervisor(dc)) { @@ -4681,63 +4736,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) #endif case 0x30: goto illegal_insn; /* WRASR in decodetree */ -#if !defined(CONFIG_USER_ONLY) case 0x32: goto illegal_insn; /* WRPR in decodetree */ case 0x33: /* wrtbr, UA2005 wrhpr */ - { -#ifndef TARGET_SPARC64 - if (!supervisor(dc)) - goto priv_insn; - tcg_gen_xor_tl(cpu_tbr, cpu_src1, cpu_src2); -#else - CHECK_IU_FEATURE(dc, HYPV); - if (!hypervisor(dc)) - goto priv_insn; - cpu_tmp0 = tcg_temp_new(); - tcg_gen_xor_tl(cpu_tmp0, cpu_src1, cpu_src2); - switch (rd) { - case 0: // hpstate - tcg_gen_st_i64(cpu_tmp0, tcg_env, - offsetof(CPUSPARCState, - hpstate)); - save_state(dc); - gen_op_next_insn(); - tcg_gen_exit_tb(NULL, 0); - dc->base.is_jmp = DISAS_NORETURN; - break; - case 1: // htstate - // XXX gen_op_wrhtstate(); - break; - case 3: // hintp - tcg_gen_mov_tl(cpu_hintp, cpu_tmp0); - break; - case 5: // htba - tcg_gen_mov_tl(cpu_htba, cpu_tmp0); - break; - case 31: // hstick_cmpr - { - TCGv_ptr r_tickptr; - - tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); - r_tickptr = tcg_temp_new_ptr(); - tcg_gen_ld_ptr(r_tickptr, tcg_env, - offsetof(CPUSPARCState, hstick)); - translator_io_start(&dc->base); - gen_helper_tick_set_limit(r_tickptr, - cpu_hstick_cmpr); - /* End TB to handle timer interrupt */ - dc->base.is_jmp = DISAS_EXIT; - } - break; - case 6: // hver readonly - default: - goto illegal_insn; - } -#endif - } - break; -#endif + goto illegal_insn; /* WRTBR, WRHPR in decodetree */ #ifdef TARGET_SPARC64 case 0x2c: /* V9 movcc */ { From patchwork Fri Oct 13 21:27:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733311 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679824wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 24/85] target/sparc: Move basic arithmetic to decodetree Date: Fri, 13 Oct 2023 14:27:45 -0700 Message-Id: <20231013212846.165724-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move ADD, AND, OR, XOR, SUB, ANDN, ORN, XORN. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 18 ++++ target/sparc/translate.c | 183 +++++++++++++++++--------------------- 2 files changed, 98 insertions(+), 103 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0425764973..a95f682fa7 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -28,6 +28,7 @@ CALL 01 i:s30 &r_r_ri rd rs1 rs2_or_imm imm:bool @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0 +@r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 Tcc_i 10 0 cond:4 111010 rs1:5 1 cc:1 0000 i:8 @@ -154,3 +155,20 @@ WRPR_strand_status 10 11010 110010 ..... . ............. @n_r_ri WRHPR_hintp 10 00011 110011 ..... . ............. @n_r_ri WRHPR_htba 10 00101 110011 ..... . ............. @n_r_ri WRHPR_hstick_cmpr 10 11111 110011 ..... . ............. @n_r_ri + +ADD 10 ..... 000000 ..... . ............. @r_r_ri +ADDcc 10 ..... 010000 ..... . ............. @r_r_ri +AND 10 ..... 000001 ..... . ............. @r_r_ri +ANDcc 10 ..... 010001 ..... . ............. @r_r_ri +OR 10 ..... 000010 ..... . ............. @r_r_ri +ORcc 10 ..... 010010 ..... . ............. @r_r_ri +XOR 10 ..... 000011 ..... . ............. @r_r_ri +XORcc 10 ..... 010011 ..... . ............. @r_r_ri +SUB 10 ..... 000100 ..... . ............. @r_r_ri +SUBcc 10 ..... 010100 ..... . ............. @r_r_ri +ANDN 10 ..... 000101 ..... . ............. @r_r_ri +ANDNcc 10 ..... 010101 ..... . ............. @r_r_ri +ORN 10 ..... 000110 ..... . ............. @r_r_ri +ORNcc 10 ..... 010110 ..... . ............. @r_r_ri +XORN 10 ..... 000111 ..... . ............. @r_r_ri +XORNcc 10 ..... 010111 ..... . ............. @r_r_ri diff --git a/target/sparc/translate.c b/target/sparc/translate.c index efb3c7c570..a21c5ec329 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4079,6 +4079,86 @@ static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a) return false; } +static bool do_cc_arith(DisasContext *dc, arg_r_r_ri *a, int cc_op, + void (*func)(TCGv, TCGv, TCGv), + void (*funci)(TCGv, TCGv, target_long)) +{ + TCGv dst, src1; + + /* For simplicity, we under-decoded the rs2 form. */ + if (!a->imm && a->rs2_or_imm & ~0x1f) { + return false; + } + + if (cc_op < 0) { + dst = gen_dest_gpr(dc, a->rd); + } else { + dst = cpu_cc_dst; + tcg_gen_movi_i32(cpu_cc_op, cc_op); + dc->cc_op = cc_op; + } + src1 = gen_load_gpr(dc, a->rs1); + + if (a->imm || a->rs2_or_imm == 0) { + if (funci) { + funci(dst, src1, a->rs2_or_imm); + } else { + func(dst, src1, tcg_constant_tl(a->rs2_or_imm)); + } + } else { + func(dst, src1, cpu_regs[a->rs2_or_imm]); + } + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +static bool do_arith(DisasContext *dc, arg_r_r_ri *a, + void (*func)(TCGv, TCGv, TCGv), + void (*funci)(TCGv, TCGv, target_long)) +{ + return do_cc_arith(dc, a, -1, func, funci); +} + +static bool trans_OR(DisasContext *dc, arg_r_r_ri *a) +{ + /* For simplicity, we under-decoded the rs2 form. */ + if (!a->imm && a->rs2_or_imm & ~0x1f) { + return false; + } + + /* OR with %g0 is the canonical alias for MOV. */ + if (a->rs1 == 0) { + TCGv src2; + + if (a->imm || a->rs2_or_imm == 0) { + src2 = tcg_constant_tl(a->rs2_or_imm); + } else { + src2 = cpu_regs[a->rs2_or_imm]; + } + gen_store_gpr(dc, a->rd, src2); + return advance_pc(dc); + } + + return do_arith(dc, a, tcg_gen_or_tl, tcg_gen_ori_tl); +} + +TRANS(ADD, ALL, do_arith, a, tcg_gen_add_tl, tcg_gen_addi_tl) +TRANS(AND, ALL, do_arith, a, tcg_gen_and_tl, tcg_gen_andi_tl) +TRANS(XOR, ALL, do_arith, a, tcg_gen_xor_tl, tcg_gen_xori_tl) +TRANS(SUB, ALL, do_arith, a, tcg_gen_sub_tl, tcg_gen_subi_tl) +TRANS(ANDN, ALL, do_arith, a, tcg_gen_andc_tl, NULL) +TRANS(ORN, ALL, do_arith, a, tcg_gen_orc_tl, NULL) +TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL) + +TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL) +TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl) +TRANS(ORcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_or_tl, tcg_gen_ori_tl) +TRANS(XORcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_xor_tl, tcg_gen_xori_tl) +TRANS(SUBcc, ALL, do_cc_arith, a, CC_OP_SUB, gen_op_sub_cc, NULL) +TRANS(ANDNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_andc_tl, NULL) +TRANS(ORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL) +TRANS(XORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4427,43 +4507,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) default: goto illegal_insn; } - } else if (xop == 0x2) { - TCGv dst = gen_dest_gpr(dc, rd); - rs1 = GET_FIELD(insn, 13, 17); - if (rs1 == 0) { - /* clr/mov shortcut : or %g0, x, y -> mov x, y */ - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 19, 31); - tcg_gen_movi_tl(dst, simm); - gen_store_gpr(dc, rd, dst); - } else { /* register */ - rs2 = GET_FIELD(insn, 27, 31); - if (rs2 == 0) { - tcg_gen_movi_tl(dst, 0); - gen_store_gpr(dc, rd, dst); - } else { - cpu_src2 = gen_load_gpr(dc, rs2); - gen_store_gpr(dc, rd, cpu_src2); - } - } - } else { - cpu_src1 = get_src1(dc, insn); - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 19, 31); - tcg_gen_ori_tl(dst, cpu_src1, simm); - gen_store_gpr(dc, rd, dst); - } else { /* register */ - rs2 = GET_FIELD(insn, 27, 31); - if (rs2 == 0) { - /* mov shortcut: or x, %g0, y -> mov x, y */ - gen_store_gpr(dc, rd, cpu_src1); - } else { - cpu_src2 = gen_load_gpr(dc, rs2); - tcg_gen_or_tl(dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, dst); - } - } - } #ifdef TARGET_SPARC64 } else if (xop == 0x25) { /* sll, V9 sllx */ cpu_src1 = get_src1(dc, insn); @@ -4540,72 +4583,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { - case 0x0: /* add */ - if (xop & 0x10) { - gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); - dc->cc_op = CC_OP_ADD; - } else { - tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); - } - break; - case 0x1: /* and */ - tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op = CC_OP_LOGIC; - } - break; - case 0x2: /* or */ - tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op = CC_OP_LOGIC; - } - break; - case 0x3: /* xor */ - tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op = CC_OP_LOGIC; - } - break; - case 0x4: /* sub */ - if (xop & 0x10) { - gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); - dc->cc_op = CC_OP_SUB; - } else { - tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2); - } - break; - case 0x5: /* andn */ - tcg_gen_andc_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op = CC_OP_LOGIC; - } - break; - case 0x6: /* orn */ - tcg_gen_orc_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op = CC_OP_LOGIC; - } - break; - case 0x7: /* xorn */ - tcg_gen_eqv_tl(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 25/85] target/sparc: Move ADDC to decodetree Date: Fri, 13 Oct 2023 14:27:46 -0700 Message-Id: <20231013212846.165724-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 41 +++++++++++++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 4 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a95f682fa7..87108da5da 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -172,3 +172,5 @@ ORN 10 ..... 000110 ..... . ............. @r_r_ri ORNcc 10 ..... 010110 ..... . ............. @r_r_ri XORN 10 ..... 000111 ..... . ............. @r_r_ri XORNcc 10 ..... 010111 ..... . ............. @r_r_ri +ADDC 10 ..... 001000 ..... . ............. @r_r_ri +ADDCcc 10 ..... 011000 ..... . ............. @r_r_ri diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a21c5ec329..37917ad397 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4159,6 +4159,43 @@ TRANS(ANDNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_andc_tl, NULL) TRANS(ORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL) TRANS(XORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL) +static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm) +{ + /* For simplicity, we under-decoded the rs2 form. */ + if (!imm && rs2_or_imm & ~0x1f) { + return NULL; + } + if (imm || rs2_or_imm == 0) { + return tcg_constant_tl(rs2_or_imm); + } else { + return cpu_regs[rs2_or_imm]; + } +} + +static bool trans_ADDC(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + + if (src2 == NULL) { + return false; + } + gen_op_addx_int(dc, gen_dest_gpr(dc, a->rd), + gen_load_gpr(dc, a->rs1), src2, false); + return advance_pc(dc); +} + +static bool trans_ADDCcc(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + + if (src2 == NULL) { + return false; + } + gen_op_addx_int(dc, gen_dest_gpr(dc, a->rd), + gen_load_gpr(dc, a->rs1), src2, true); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4583,10 +4620,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { - case 0x8: /* addx, V9 addc */ - gen_op_addx_int(dc, cpu_dst, cpu_src1, cpu_src2, - (xop & 0x10)); - break; #ifdef TARGET_SPARC64 case 0x9: /* V9 mulx */ tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); From patchwork Fri Oct 13 21:27:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733268 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678159wrv; Fri, 13 Oct 2023 14:31:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGHrYnR2yv/yjflD8tRZSAZDvgo/Mw5xxi+o8bbps0jk5D7rA+TtPH7aKPGtdlMQuMKM9YC X-Received: by 2002:a0c:fc49:0:b0:651:800d:ffc9 with SMTP id w9-20020a0cfc49000000b00651800dffc9mr2309168qvp.22.1697232669615; Fri, 13 Oct 2023 14:31:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232669; cv=none; d=google.com; s=arc-20160816; b=TundvDdajH0yv49rYJF3OSRGVt3qfIqFRslN4MW4y7ltulsC+jh0OPSvU5jvd71RVx L/URQx58X3OtrrKZDaaPzsNwEE3tVecVEVvFV12/Ty7lK/AHqV8JkPbYeuDdGg8Wnrfy kipILuBAxCF6ZSndBKzkM4SOE7fyCPJn3L6ZS4kFXGL5MKlI8lhNWDNXEhe1AvZ1EqiW OOg+GvAKTwJxo3VD0DW5zfcZ/BpZSkN3dvmYcSnoVd2fTK+izL7StlMqXQuquER8m4Bh PKBZdZeEN6k9cA1xUao6EDPjmvazDBalP/a9lHUkcPbaIMjKvSdUY9uDGyIqrorODaxU 4o7A== ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 26/85] target/sparc: Move MULX to decodetree Date: Fri, 13 Oct 2023 14:27:47 -0700 Message-Id: <20231013212846.165724-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 6 +----- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 87108da5da..d907a4a69f 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -174,3 +174,4 @@ XORN 10 ..... 000111 ..... . ............. @r_r_ri XORNcc 10 ..... 010111 ..... . ............. @r_r_ri ADDC 10 ..... 001000 ..... . ............. @r_r_ri ADDCcc 10 ..... 011000 ..... . ............. @r_r_ri +MULX 10 ..... 001001 ..... . ............. @r_r_ri diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 37917ad397..7a7d517fac 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4149,6 +4149,7 @@ TRANS(SUB, ALL, do_arith, a, tcg_gen_sub_tl, tcg_gen_subi_tl) TRANS(ANDN, ALL, do_arith, a, tcg_gen_andc_tl, NULL) TRANS(ORN, ALL, do_arith, a, tcg_gen_orc_tl, NULL) TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL) +TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl) TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL) TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl) @@ -4620,11 +4621,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { -#ifdef TARGET_SPARC64 - case 0x9: /* V9 mulx */ - tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); - break; -#endif case 0xa: /* umul */ gen_op_umul(cpu_dst, cpu_src1, cpu_src2); if (xop & 0x10) { From patchwork Fri Oct 13 21:27:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733280 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678773wrv; Fri, 13 Oct 2023 14:33:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IET37DXY+ABGSmmOPhUQggAPmbxvvz4bz/wFX0hdEa3//1ZKEODExTzERxn9kJsAmTRMEV1 X-Received: by 2002:ac8:5c15:0:b0:418:1da6:eb8f with SMTP id i21-20020ac85c15000000b004181da6eb8fmr37426827qti.27.1697232783071; Fri, 13 Oct 2023 14:33:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232783; cv=none; d=google.com; s=arc-20160816; b=NsDQJKDWLLbbPlX3RJeuiS5oHYVAQYE8483RSDjEgCD8JwbfcosiMN7vsXYp2zFjZH E5waKNAskrCFcZi9NPpNZ63yoKnfYouZSE4Dqda57tvsEwmxJ1OIQn0E7TzF+WUqfl4L mRGpD5BJrq0W98ulagDRKj1yM9ndysrtVNO40NhfP3MhwTvMzjvEoVfhpLolJ3NVA1ou yApoyG0rywZgbItxhZAB52a4Fd2NEYqEbHILgv9nIP/I1LkXcAAAQP+bqMfeQ6utNFMG +RJyuH2dyyEbUpBIDJv2cEXb56rURH+a6PkqXhGANN4I0u93ZOGPsesGMfwbXp13l60A wfwg== ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 27/85] target/sparc: Move UMUL, SMUL to decodetree Date: Fri, 13 Oct 2023 14:27:48 -0700 Message-Id: <20231013212846.165724-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++++ target/sparc/translate.c | 20 ++++---------------- 2 files changed, 8 insertions(+), 16 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d907a4a69f..9cd89cf03b 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -175,3 +175,7 @@ XORNcc 10 ..... 010111 ..... . ............. @r_r_ri ADDC 10 ..... 001000 ..... . ............. @r_r_ri ADDCcc 10 ..... 011000 ..... . ............. @r_r_ri MULX 10 ..... 001001 ..... . ............. @r_r_ri +UMUL 10 ..... 001010 ..... . ............. @r_r_ri +UMULcc 10 ..... 011010 ..... . ............. @r_r_ri +SMUL 10 ..... 001011 ..... . ............. @r_r_ri +SMULcc 10 ..... 011011 ..... . ............. @r_r_ri diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7a7d517fac..38c1f2f79a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4150,6 +4150,8 @@ TRANS(ANDN, ALL, do_arith, a, tcg_gen_andc_tl, NULL) TRANS(ORN, ALL, do_arith, a, tcg_gen_orc_tl, NULL) TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL) TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl) +TRANS(UMUL, ALL, do_arith, a, gen_op_umul, NULL) +TRANS(SMUL, ALL, do_arith, a, gen_op_smul, NULL) TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL) TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl) @@ -4159,6 +4161,8 @@ TRANS(SUBcc, ALL, do_cc_arith, a, CC_OP_SUB, gen_op_sub_cc, NULL) TRANS(ANDNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_andc_tl, NULL) TRANS(ORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL) TRANS(XORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL) +TRANS(UMULcc, ALL, do_cc_arith, a, CC_OP_LOGIC, gen_op_umul, NULL) +TRANS(SMULcc, ALL, do_cc_arith, a, CC_OP_LOGIC, gen_op_smul, NULL) static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm) { @@ -4621,22 +4625,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { - case 0xa: /* umul */ - gen_op_umul(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op = CC_OP_LOGIC; - } - break; - case 0xb: /* smul */ - gen_op_smul(cpu_dst, cpu_src1, cpu_src2); - if (xop & 0x10) { - tcg_gen_mov_tl(cpu_cc_dst, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC); - dc->cc_op = CC_OP_LOGIC; - } - break; case 0xc: /* subx, V9 subc */ gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, (xop & 0x10)); From patchwork Fri Oct 13 21:27:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733269 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678157wrv; Fri, 13 Oct 2023 14:31:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFG78UOtq3KTxejC23PK8q1sthdt7oh9gEiLT8ll+4dJJoteBuhqjGMbVxQ72dE7Jbp+7QK X-Received: by 2002:a9d:7dd1:0:b0:6b9:350e:4051 with SMTP id k17-20020a9d7dd1000000b006b9350e4051mr29904090otn.4.1697232669738; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 28/85] target/sparc: Move SUBC to decodetree Date: Fri, 13 Oct 2023 14:27:49 -0700 Message-Id: <20231013212846.165724-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 28 ++++++++++++++++++++++++---- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 9cd89cf03b..69b3e82ae9 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -179,3 +179,5 @@ UMUL 10 ..... 001010 ..... . ............. @r_r_ri UMULcc 10 ..... 011010 ..... . ............. @r_r_ri SMUL 10 ..... 001011 ..... . ............. @r_r_ri SMULcc 10 ..... 011011 ..... . ............. @r_r_ri +SUBC 10 ..... 001100 ..... . ............. @r_r_ri +SUBCcc 10 ..... 011100 ..... . ............. @r_r_ri diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 38c1f2f79a..1ddf5f3f60 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4201,6 +4201,30 @@ static bool trans_ADDCcc(DisasContext *dc, arg_r_r_ri *a) return advance_pc(dc); } +static bool trans_SUBC(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + + if (src2 == NULL) { + return false; + } + gen_op_subx_int(dc, gen_dest_gpr(dc, a->rd), + gen_load_gpr(dc, a->rs1), src2, false); + return advance_pc(dc); +} + +static bool trans_SUBCcc(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + + if (src2 == NULL) { + return false; + } + gen_op_subx_int(dc, gen_dest_gpr(dc, a->rd), + gen_load_gpr(dc, a->rs1), src2, true); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4625,10 +4649,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { - case 0xc: /* subx, V9 subc */ - gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, - (xop & 0x10)); - break; #ifdef TARGET_SPARC64 case 0xd: /* V9 udivx */ gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_src2); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 29/85] target/sparc: Move UDIVX, SDIVX to decodetree Date: Fri, 13 Oct 2023 14:27:50 -0700 Message-Id: <20231013212846.165724-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 24 ++++++++++++++---------- 2 files changed, 16 insertions(+), 10 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 69b3e82ae9..d5f5dfff14 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -181,3 +181,5 @@ SMUL 10 ..... 001011 ..... . ............. @r_r_ri SMULcc 10 ..... 011011 ..... . ............. @r_r_ri SUBC 10 ..... 001100 ..... . ............. @r_r_ri SUBCcc 10 ..... 011100 ..... . ............. @r_r_ri +UDIVX 10 ..... 001101 ..... . ............. @r_r_ri +SDIVX 10 ..... 101101 ..... . ............. @r_r_ri diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1ddf5f3f60..ec5ae92e07 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -53,6 +53,8 @@ #define gen_helper_write_softint(E, S) qemu_build_not_reached() #define gen_helper_saved ({ qemu_build_not_reached(); NULL; }) #define gen_helper_restored ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() +#define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() #endif /* Dynamic PC, must exit to main loop. */ @@ -633,6 +635,16 @@ static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) gen_op_multiply(dst, src1, src2, 1); } +static void gen_op_udivx(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_udivx(dst, tcg_env, src1, src2); +} + +static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_sdivx(dst, tcg_env, src1, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -4152,6 +4164,8 @@ TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL) TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl) TRANS(UMUL, ALL, do_arith, a, gen_op_umul, NULL) TRANS(SMUL, ALL, do_arith, a, gen_op_smul, NULL) +TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL) +TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL) TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL) TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl) @@ -4224,7 +4238,6 @@ static bool trans_SUBCcc(DisasContext *dc, arg_r_r_ri *a) gen_load_gpr(dc, a->rs1), src2, true); return advance_pc(dc); } - #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4649,11 +4662,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { -#ifdef TARGET_SPARC64 - case 0xd: /* V9 udivx */ - gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_src2); - break; -#endif case 0xe: /* udiv */ if (xop & 0x10) { gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1, @@ -4789,10 +4797,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_store_gpr(dc, rd, dst); break; } - case 0x2d: /* V9 sdivx */ - gen_helper_sdivx(cpu_dst, tcg_env, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x2e: /* V9 popc */ tcg_gen_ctpop_tl(cpu_dst, cpu_src2); gen_store_gpr(dc, rd, cpu_dst); From patchwork Fri Oct 13 21:27:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733270 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678327wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 30/85] target/sparc: Move UDIV, SDIV to decodetree Date: Fri, 13 Oct 2023 14:27:51 -0700 Message-Id: <20231013212846.165724-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++++ target/sparc/translate.c | 43 +++++++++++++++------------------------ 2 files changed, 20 insertions(+), 27 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d5f5dfff14..35e7905bfe 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -183,3 +183,7 @@ SUBC 10 ..... 001100 ..... . ............. @r_r_ri SUBCcc 10 ..... 011100 ..... . ............. @r_r_ri UDIVX 10 ..... 001101 ..... . ............. @r_r_ri SDIVX 10 ..... 101101 ..... . ............. @r_r_ri +UDIV 10 ..... 001110 ..... . ............. @r_r_ri +UDIVcc 10 ..... 011110 ..... . ............. @r_r_ri +SDIV 10 ..... 001111 ..... . ............. @r_r_ri +SDIVcc 10 ..... 011111 ..... . ............. @r_r_ri diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ec5ae92e07..1c335fb826 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -645,6 +645,16 @@ static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) gen_helper_sdivx(dst, tcg_env, src1, src2); } +static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_udiv(dst, tcg_env, src1, src2); +} + +static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_sdiv(dst, tcg_env, src1, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -4166,6 +4176,8 @@ TRANS(UMUL, ALL, do_arith, a, gen_op_umul, NULL) TRANS(SMUL, ALL, do_arith, a, gen_op_smul, NULL) TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL) TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL) +TRANS(UDIV, ALL, do_arith, a, gen_op_udiv, NULL) +TRANS(SDIV, ALL, do_arith, a, gen_op_sdiv, NULL) TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL) TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl) @@ -4177,6 +4189,8 @@ TRANS(ORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL) TRANS(XORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL) TRANS(UMULcc, ALL, do_cc_arith, a, CC_OP_LOGIC, gen_op_umul, NULL) TRANS(SMULcc, ALL, do_cc_arith, a, CC_OP_LOGIC, gen_op_smul, NULL) +TRANS(UDIVcc, ALL, do_cc_arith, a, CC_OP_DIV, gen_op_udiv, NULL) +TRANS(SDIVcc, ALL, do_cc_arith, a, CC_OP_DIV, gen_op_sdiv, NULL) static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm) { @@ -4238,6 +4252,7 @@ static bool trans_SUBCcc(DisasContext *dc, arg_r_r_ri *a) gen_load_gpr(dc, a->rs1), src2, true); return advance_pc(dc); } + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4659,33 +4674,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) #endif } else if (xop < 0x36) { if (xop < 0x20) { - cpu_src1 = get_src1(dc, insn); - cpu_src2 = get_src2(dc, insn); - switch (xop & ~0x10) { - case 0xe: /* udiv */ - if (xop & 0x10) { - gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - dc->cc_op = CC_OP_DIV; - } else { - gen_helper_udiv(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - } - break; - case 0xf: /* sdiv */ - if (xop & 0x10) { - gen_helper_sdiv_cc(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - dc->cc_op = CC_OP_DIV; - } else { - gen_helper_sdiv(cpu_dst, tcg_env, cpu_src1, - cpu_src2); - } - break; - default: - goto illegal_insn; - } - gen_store_gpr(dc, rd, cpu_dst); + goto illegal_insn; } else { cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); From patchwork Fri Oct 13 21:27:52 2023 Content-Type: text/plain; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 31/85] target/sparc: Move TADD, TSUB, MULS to decodetree Date: Fri, 13 Oct 2023 14:27:52 -0700 Message-Id: <20231013212846.165724-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++++ target/sparc/translate.c | 47 +++++++++++++++++---------------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 35e7905bfe..2aae7d9514 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -187,3 +187,8 @@ UDIV 10 ..... 001110 ..... . ............. @r_r_ri UDIVcc 10 ..... 011110 ..... . ............. @r_r_ri SDIV 10 ..... 001111 ..... . ............. @r_r_ri SDIVcc 10 ..... 011111 ..... . ............. @r_r_ri +TADDcc 10 ..... 100000 ..... . ............. @r_r_ri +TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri +TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri +TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri +MULScc 10 ..... 100100 ..... . ............. @r_r_ri diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1c335fb826..5f5c24b112 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -655,6 +655,16 @@ static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2) gen_helper_sdiv(dst, tcg_env, src1, src2); } +static void gen_op_taddcctv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_taddcctv(dst, tcg_env, src1, src2); +} + +static void gen_op_tsubcctv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_tsubcctv(dst, tcg_env, src1, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -4191,6 +4201,10 @@ TRANS(UMULcc, ALL, do_cc_arith, a, CC_OP_LOGIC, gen_op_umul, NULL) TRANS(SMULcc, ALL, do_cc_arith, a, CC_OP_LOGIC, gen_op_smul, NULL) TRANS(UDIVcc, ALL, do_cc_arith, a, CC_OP_DIV, gen_op_udiv, NULL) TRANS(SDIVcc, ALL, do_cc_arith, a, CC_OP_DIV, gen_op_sdiv, NULL) +TRANS(TADDcc, ALL, do_cc_arith, a, CC_OP_TADD, gen_op_add_cc, NULL) +TRANS(TSUBcc, ALL, do_cc_arith, a, CC_OP_TSUB, gen_op_sub_cc, NULL) +TRANS(TADDccTV, ALL, do_cc_arith, a, CC_OP_TADDTV, gen_op_taddcctv, NULL) +TRANS(TSUBccTV, ALL, do_cc_arith, a, CC_OP_TSUBTV, gen_op_tsubcctv, NULL) static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm) { @@ -4253,6 +4267,12 @@ static bool trans_SUBCcc(DisasContext *dc, arg_r_r_ri *a) return advance_pc(dc); } +static bool trans_MULScc(DisasContext *dc, arg_r_r_ri *a) +{ + update_psr(dc); + return do_cc_arith(dc, a, CC_OP_ADD, gen_op_mulscc, NULL); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4680,36 +4700,11 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src2 = get_src2(dc, insn); switch (xop) { case 0x20: /* taddcc */ - gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD); - dc->cc_op = CC_OP_TADD; - break; case 0x21: /* tsubcc */ - gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB); - dc->cc_op = CC_OP_TSUB; - break; case 0x22: /* taddcctv */ - gen_helper_taddcctv(cpu_dst, tcg_env, - cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - dc->cc_op = CC_OP_TADDTV; - break; case 0x23: /* tsubcctv */ - gen_helper_tsubcctv(cpu_dst, tcg_env, - cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - dc->cc_op = CC_OP_TSUBTV; - break; case 0x24: /* mulscc */ - update_psr(dc); - gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); - dc->cc_op = CC_OP_ADD; - break; + goto illegal_insn; /* in decodetree */ #ifndef TARGET_SPARC64 case 0x25: /* sll */ if (IS_IMM) { /* immediate */ From patchwork Fri Oct 13 21:27:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733295 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679237wrv; Fri, 13 Oct 2023 14:34:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHcrO9nAgmHrZiICzeIVB+lgyK1PIQdS/Bl1OSGGbhdtyKBY0zdIZj6ldlNcg2FWDk6jaja X-Received: by 2002:a0c:b3cf:0:b0:659:71ac:84df with SMTP id b15-20020a0cb3cf000000b0065971ac84dfmr25146343qvf.26.1697232874671; Fri, 13 Oct 2023 14:34:34 -0700 (PDT) ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 32/85] target/sparc: Move SLL, SRL, SRA to decodetree Date: Fri, 13 Oct 2023 14:27:53 -0700 Message-Id: <20231013212846.165724-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 14 +++ target/sparc/translate.c | 182 ++++++++++++++++---------------------- 2 files changed, 92 insertions(+), 104 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 2aae7d9514..597519b99b 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -192,3 +192,17 @@ TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri MULScc 10 ..... 100100 ..... . ............. @r_r_ri + +&shiftr rd rs1 rs2 x:bool +@shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr + +SLL_r 10 ..... 100101 ..... 0 . 0000000 ..... @shiftr +SRL_r 10 ..... 100110 ..... 0 . 0000000 ..... @shiftr +SRA_r 10 ..... 100111 ..... 0 . 0000000 ..... @shiftr + +&shifti rd rs1 i x:bool +@shifti .. rd:5 ...... rs1:5 . x:1 ...... i:6 &shifti + +SLL_i 10 ..... 100101 ..... 1 . 000000 ...... @shifti +SRL_i 10 ..... 100110 ..... 1 . 000000 ...... @shifti +SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5f5c24b112..3672a8105b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4273,6 +4273,83 @@ static bool trans_MULScc(DisasContext *dc, arg_r_r_ri *a) return do_cc_arith(dc, a, CC_OP_ADD, gen_op_mulscc, NULL); } +static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) +{ + TCGv dst, src1, src2; + + /* Reject 64-bit shifts for sparc32. */ + if (avail_32(dc) && a->x) { + return false; + } + + src2 = tcg_temp_new(); + tcg_gen_andi_tl(src2, gen_load_gpr(dc, a->rs2), a->x ? 63 : 31); + src1 = gen_load_gpr(dc, a->rs1); + dst = gen_dest_gpr(dc, a->rd); + + if (l) { + tcg_gen_shl_tl(dst, src1, src2); + if (!a->x) { + tcg_gen_ext32u_tl(dst, dst); + } + } else if (u) { + if (!a->x) { + tcg_gen_ext32u_tl(dst, src1); + src1 = dst; + } + tcg_gen_shr_tl(dst, src1, src2); + } else { + if (!a->x) { + tcg_gen_ext32s_tl(dst, src1); + src1 = dst; + } + tcg_gen_sar_tl(dst, src1, src2); + } + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(SLL_r, ALL, do_shift_r, a, true, true) +TRANS(SRL_r, ALL, do_shift_r, a, false, true) +TRANS(SRA_r, ALL, do_shift_r, a, false, false) + +static bool do_shift_i(DisasContext *dc, arg_shifti *a, bool l, bool u) +{ + TCGv dst, src1; + + /* Reject 64-bit shifts for sparc32. */ + if (avail_32(dc) && (a->x || a->i >= 32)) { + return false; + } + + src1 = gen_load_gpr(dc, a->rs1); + dst = gen_dest_gpr(dc, a->rd); + + if (avail_32(dc) || a->x) { + if (l) { + tcg_gen_shli_tl(dst, src1, a->i); + } else if (u) { + tcg_gen_shri_tl(dst, src1, a->i); + } else { + tcg_gen_sari_tl(dst, src1, a->i); + } + } else { + if (l) { + tcg_gen_deposit_z_tl(dst, src1, a->i, 32 - a->i); + } else if (u) { + tcg_gen_extract_tl(dst, src1, a->i, 32 - a->i); + } else { + tcg_gen_sextract_tl(dst, src1, a->i, 32 - a->i); + } + } + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(SLL_i, ALL, do_shift_i, a, true, true) +TRANS(SRL_i, ALL, do_shift_i, a, false, true) +TRANS(SRA_i, ALL, do_shift_i, a, false, false) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4621,77 +4698,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) default: goto illegal_insn; } -#ifdef TARGET_SPARC64 - } else if (xop == 0x25) { /* sll, V9 sllx */ - cpu_src1 = get_src1(dc, insn); - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 20, 31); - if (insn & (1 << 12)) { - tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x3f); - } else { - tcg_gen_shli_i64(cpu_dst, cpu_src1, simm & 0x1f); - } - } else { /* register */ - rs2 = GET_FIELD(insn, 27, 31); - cpu_src2 = gen_load_gpr(dc, rs2); - cpu_tmp0 = tcg_temp_new(); - if (insn & (1 << 12)) { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); - } else { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); - } - tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0); - } - gen_store_gpr(dc, rd, cpu_dst); - } else if (xop == 0x26) { /* srl, V9 srlx */ - cpu_src1 = get_src1(dc, insn); - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 20, 31); - if (insn & (1 << 12)) { - tcg_gen_shri_i64(cpu_dst, cpu_src1, simm & 0x3f); - } else { - tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); - tcg_gen_shri_i64(cpu_dst, cpu_dst, simm & 0x1f); - } - } else { /* register */ - rs2 = GET_FIELD(insn, 27, 31); - cpu_src2 = gen_load_gpr(dc, rs2); - cpu_tmp0 = tcg_temp_new(); - if (insn & (1 << 12)) { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); - tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0); - } else { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL); - tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0); - } - } - gen_store_gpr(dc, rd, cpu_dst); - } else if (xop == 0x27) { /* sra, V9 srax */ - cpu_src1 = get_src1(dc, insn); - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 20, 31); - if (insn & (1 << 12)) { - tcg_gen_sari_i64(cpu_dst, cpu_src1, simm & 0x3f); - } else { - tcg_gen_ext32s_i64(cpu_dst, cpu_src1); - tcg_gen_sari_i64(cpu_dst, cpu_dst, simm & 0x1f); - } - } else { /* register */ - rs2 = GET_FIELD(insn, 27, 31); - cpu_src2 = gen_load_gpr(dc, rs2); - cpu_tmp0 = tcg_temp_new(); - if (insn & (1 << 12)) { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f); - tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0); - } else { - tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_ext32s_i64(cpu_dst, cpu_src1); - tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0); - } - } - gen_store_gpr(dc, rd, cpu_dst); -#endif } else if (xop < 0x36) { if (xop < 0x20) { goto illegal_insn; @@ -4704,42 +4710,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x22: /* taddcctv */ case 0x23: /* tsubcctv */ case 0x24: /* mulscc */ - goto illegal_insn; /* in decodetree */ -#ifndef TARGET_SPARC64 case 0x25: /* sll */ - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 20, 31); - tcg_gen_shli_tl(cpu_dst, cpu_src1, simm & 0x1f); - } else { /* register */ - cpu_tmp0 = tcg_temp_new(); - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0); - } - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x26: /* srl */ - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 20, 31); - tcg_gen_shri_tl(cpu_dst, cpu_src1, simm & 0x1f); - } else { /* register */ - cpu_tmp0 = tcg_temp_new(); - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0); - } - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x27: /* sra */ - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 20, 31); - tcg_gen_sari_tl(cpu_dst, cpu_src1, simm & 0x1f); - } else { /* register */ - cpu_tmp0 = tcg_temp_new(); - tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f); - tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0); - } - gen_store_gpr(dc, rd, cpu_dst); - break; -#endif + goto illegal_insn; /* in decodetree */ case 0x30: goto illegal_insn; /* WRASR in decodetree */ case 0x32: From patchwork Fri Oct 13 21:27:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733278 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678690wrv; Fri, 13 Oct 2023 14:32:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFFjFHVN91lGXiFq+cco7yqMruXKjCUwYSL1HiEizXesImKsXfEtycGB4C/t1wtdMFcZ9C5 X-Received: by 2002:a05:620a:1a86:b0:773:ae67:4b96 with SMTP id bl6-20020a05620a1a8600b00773ae674b96mr32692048qkb.53.1697232766103; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 33/85] target/sparc: Move MOVcc, MOVR to decodetree Date: Fri, 13 Oct 2023 14:27:54 -0700 Message-Id: <20231013212846.165724-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++ target/sparc/translate.c | 103 +++++++++++++++++--------------------- 2 files changed, 51 insertions(+), 56 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 597519b99b..1f6dfa210f 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -206,3 +206,7 @@ SRA_r 10 ..... 100111 ..... 0 . 0000000 ..... @shiftr SLL_i 10 ..... 100101 ..... 1 . 000000 ...... @shifti SRL_i 10 ..... 100110 ..... 1 . 000000 ...... @shifti SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti + +MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11 +MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11 +MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3672a8105b..81a2518498 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4350,6 +4350,51 @@ TRANS(SLL_i, ALL, do_shift_i, a, true, true) TRANS(SRL_i, ALL, do_shift_i, a, false, true) TRANS(SRA_i, ALL, do_shift_i, a, false, false) +static bool do_mov_cond(DisasContext *dc, DisasCompare *cmp, int rd, TCGv src2) +{ + TCGv dst = gen_load_gpr(dc, rd); + + tcg_gen_movcond_tl(cmp->cond, dst, cmp->c1, cmp->c2, src2, dst); + gen_store_gpr(dc, rd, dst); + return advance_pc(dc); +} + +static bool trans_MOVcc(DisasContext *dc, arg_MOVcc *a) +{ + TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + DisasCompare cmp; + + if (src2 == NULL) { + return false; + } + gen_compare(&cmp, a->cc, a->cond, dc); + return do_mov_cond(dc, &cmp, a->rd, src2); +} + +static bool trans_MOVfcc(DisasContext *dc, arg_MOVfcc *a) +{ + TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + DisasCompare cmp; + + if (src2 == NULL) { + return false; + } + gen_fcompare(&cmp, a->cc, a->cond); + return do_mov_cond(dc, &cmp, a->rd, src2); +} + +static bool trans_MOVR(DisasContext *dc, arg_MOVR *a) +{ + TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + DisasCompare cmp; + + if (src2 == NULL) { + return false; + } + gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); + return do_mov_cond(dc, &cmp, a->rd, src2); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4722,66 +4767,12 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) goto illegal_insn; /* WRTBR, WRHPR in decodetree */ #ifdef TARGET_SPARC64 case 0x2c: /* V9 movcc */ - { - int cc = GET_FIELD_SP(insn, 11, 12); - int cond = GET_FIELD_SP(insn, 14, 17); - DisasCompare cmp; - TCGv dst; - - if (insn & (1 << 18)) { - if (cc == 0) { - gen_compare(&cmp, 0, cond, dc); - } else if (cc == 2) { - gen_compare(&cmp, 1, cond, dc); - } else { - goto illegal_insn; - } - } else { - gen_fcompare(&cmp, cc, cond); - } - - /* The get_src2 above loaded the normal 13-bit - immediate field, not the 11-bit field we have - in movcc. But it did handle the reg case. */ - if (IS_IMM) { - simm = GET_FIELD_SPs(insn, 0, 10); - tcg_gen_movi_tl(cpu_src2, simm); - } - - dst = gen_load_gpr(dc, rd); - tcg_gen_movcond_tl(cmp.cond, dst, - cmp.c1, cmp.c2, - cpu_src2, dst); - gen_store_gpr(dc, rd, dst); - break; - } + case 0x2f: /* V9 movr */ + goto illegal_insn; /* in decodetree */ case 0x2e: /* V9 popc */ tcg_gen_ctpop_tl(cpu_dst, cpu_src2); gen_store_gpr(dc, rd, cpu_dst); break; - case 0x2f: /* V9 movr */ - { - int cond = GET_FIELD_SP(insn, 10, 12); - DisasCompare cmp; - TCGv dst; - - gen_compare_reg(&cmp, cond, cpu_src1); - - /* The get_src2 above loaded the normal 13-bit - immediate field, not the 10-bit field we have - in movr. But it did handle the reg case. */ - if (IS_IMM) { - simm = GET_FIELD_SPs(insn, 0, 9); - tcg_gen_movi_tl(cpu_src2, simm); - } - - dst = gen_load_gpr(dc, rd); - tcg_gen_movcond_tl(cmp.cond, dst, - cmp.c1, cmp.c2, - cpu_src2, dst); - gen_store_gpr(dc, rd, dst); - break; - } #endif default: goto illegal_insn; From patchwork Fri Oct 13 21:27:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733282 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678812wrv; Fri, 13 Oct 2023 14:33:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEov1jvbxWf3RAhZos79fgkwMd0d9mo4noMG0xS3aacq57uMV0VxQMmVbIkED942Wy4Qeg9 X-Received: by 2002:a05:620a:22f5:b0:774:1adc:c572 with SMTP id p21-20020a05620a22f500b007741adcc572mr26065543qki.74.1697232792895; Fri, 13 Oct 2023 14:33:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232792; cv=none; d=google.com; s=arc-20160816; b=NgKycd2SSBF9VOrLpamgP53sPzy830UeF5aZXy/w5wd1aKnI6OZLebu4WQ0D7n4g1+ fFfDPpepn4ZRlDvtoC4ETQtgYCVcwRVxPm7JbJeybr5fFjDqgirFepws2lgqBBvOsRn5 18NQKI3ADtVWH4kwxUgIHsnPe47ck12prYx3qu/UrSY4Mh1VR/kYfT5mR7VIBAjQtbrE +IPOZoVQ+NRQ2yD+J7aPdu/QXu0qmVIYRzwA0bZv9n3h8OLdWX8VklDM2UPuFmm2hwmX BOwOhay84NoueN8/uNH9wjWB4/vA5X3L3hbzecOffVw+ASHvQOUe1SOG1pUp00t6h0IH d1+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=x+Po0tdVkDRqVAnCRFhdgPPaFsI/xFw6qDs18ZteNnU=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=YjcjGk3p24xJwA5csx/JOuaxB0DqFc0XIuM2aKJDkeJjybH9c8no/9EXQaor9lFvH3 Wg+qHj/Bjqbu+jPo+6XRMs2y3i2g0yF1C8CQ4Y9836Q8MIcut005oQdzf5buh/3/oSgI xkIpBFxDWFuo9VFIyiPLNDypGtsjo3FFWc0NlLiMr609sW48gflj+LcCDZl+wxNEIzX0 UhbFqpH2NmlWo4pS8svm75Ya0h7lBuvTvQ/AIngfRkiu2Qtu/SFGnv/RaTBOPXjVmu/v IZI7A6i8g+LhwleIGviXxDeQ8vYTshHdE2ZDoIGTFS0YA/gjlXxtf5Wc4ATn7ikx/5Sl aGGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pp4URL4W; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 34/85] target/sparc: Move POPC to decodetree Date: Fri, 13 Oct 2023 14:27:55 -0700 Message-Id: <20231013212846.165724-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 54 +++++---------------------------------- 2 files changed, 8 insertions(+), 47 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1f6dfa210f..7ec1518b54 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -192,6 +192,7 @@ TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri MULScc 10 ..... 100100 ..... . ............. @r_r_ri +POPC 10 rd:5 101110 00000 imm:1 rs2_or_imm:s13 &r_r_ri rs1=0 &shiftr rd rs1 rs2 x:bool @shiftr .. rd:5 ...... rs1:5 . x:1 ....... rs2:5 &shiftr diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 81a2518498..caa2eff626 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -665,6 +665,11 @@ static void gen_op_tsubcctv(TCGv dst, TCGv src1, TCGv src2) gen_helper_tsubcctv(dst, tcg_env, src1, src2); } +static void gen_op_popc(TCGv dst, TCGv src1, TCGv src2) +{ + tcg_gen_ctpop_tl(dst, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -2629,19 +2634,6 @@ static TCGv get_src1(DisasContext *dc, unsigned int insn) return gen_load_gpr(dc, rs1); } -static TCGv get_src2(DisasContext *dc, unsigned int insn) -{ - if (IS_IMM) { /* immediate */ - target_long simm = GET_FIELDs(insn, 19, 31); - TCGv t = tcg_temp_new(); - tcg_gen_movi_tl(t, simm); - return t; - } else { /* register */ - unsigned int rs2 = GET_FIELD(insn, 27, 31); - return gen_load_gpr(dc, rs2); - } -} - #ifdef TARGET_SPARC64 static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { @@ -4188,6 +4180,7 @@ TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL) TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL) TRANS(UDIV, ALL, do_arith, a, gen_op_udiv, NULL) TRANS(SDIV, ALL, do_arith, a, gen_op_sdiv, NULL) +TRANS(POPC, 64, do_arith, a, gen_op_popc, NULL) TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL) TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl) @@ -4744,40 +4737,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) goto illegal_insn; } } else if (xop < 0x36) { - if (xop < 0x20) { - goto illegal_insn; - } else { - cpu_src1 = get_src1(dc, insn); - cpu_src2 = get_src2(dc, insn); - switch (xop) { - case 0x20: /* taddcc */ - case 0x21: /* tsubcc */ - case 0x22: /* taddcctv */ - case 0x23: /* tsubcctv */ - case 0x24: /* mulscc */ - case 0x25: /* sll */ - case 0x26: /* srl */ - case 0x27: /* sra */ - goto illegal_insn; /* in decodetree */ - case 0x30: - goto illegal_insn; /* WRASR in decodetree */ - case 0x32: - goto illegal_insn; /* WRPR in decodetree */ - case 0x33: /* wrtbr, UA2005 wrhpr */ - goto illegal_insn; /* WRTBR, WRHPR in decodetree */ -#ifdef TARGET_SPARC64 - case 0x2c: /* V9 movcc */ - case 0x2f: /* V9 movr */ - goto illegal_insn; /* in decodetree */ - case 0x2e: /* V9 popc */ - tcg_gen_ctpop_tl(cpu_dst, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - break; -#endif - default: - goto illegal_insn; - } - } + goto illegal_insn; /* in decodetree */ } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ #ifdef TARGET_SPARC64 int opf = GET_FIELD_SP(insn, 5, 13); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 35/85] target/sparc: Convert remaining v8 coproc insns to decodetree Date: Fri, 13 Oct 2023 14:27:56 -0700 Message-Id: <20231013212846.165724-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 11 +++++++++++ target/sparc/translate.c | 32 ++++++-------------------------- 2 files changed, 17 insertions(+), 26 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 7ec1518b54..a124fdeaac 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -211,3 +211,14 @@ SRA_i 10 ..... 100111 ..... 1 . 000000 ...... @shifti MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11 MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11 MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10 + +NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 +NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 + +NCP 11 ----- 110000 ----- --------- ----- # v8 LDC +NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR +NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC +NCP 11 ----- 110100 ----- --------- ----- # v8 STC +NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR +NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ +NCP 11 ----- 110111 ----- --------- ----- # v8 STDC diff --git a/target/sparc/translate.c b/target/sparc/translate.c index caa2eff626..72f3cbab47 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4738,8 +4738,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } } else if (xop < 0x36) { goto illegal_insn; /* in decodetree */ - } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */ + } else if (xop == 0x36) { #ifdef TARGET_SPARC64 + /* VIS */ int opf = GET_FIELD_SP(insn, 5, 13); rs1 = GET_FIELD(insn, 13, 17); rs2 = GET_FIELD(insn, 27, 31); @@ -5179,14 +5180,11 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) goto illegal_insn; } #else - goto ncp_insn; -#endif - } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ -#ifdef TARGET_SPARC64 - goto illegal_insn; -#else - goto ncp_insn; + g_assert_not_reached(); /* in decodetree */ #endif + } else if (xop == 0x37) { + /* V8 CPop2, V9 impdep2 */ + goto illegal_insn; /* in decodetree */ #ifdef TARGET_SPARC64 } else if (xop == 0x39) { /* V9 return */ save_state(dc); @@ -5405,13 +5403,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = gen_load_gpr(dc, rd); gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn); break; - -#ifndef TARGET_SPARC64 - case 0x30: /* ldc */ - case 0x31: /* ldcsr */ - case 0x33: /* lddc */ - goto ncp_insn; -#endif #endif #ifdef TARGET_SPARC64 case 0x08: /* V9 ldsw */ @@ -5672,12 +5663,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src2 = gen_load_gpr(dc, rs2); gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd); break; -#else - case 0x34: /* stc */ - case 0x35: /* stcsr */ - case 0x36: /* stdcq */ - case 0x37: /* stdc */ - goto ncp_insn; #endif #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x3c: /* V9 or LEON3 casa */ @@ -5717,11 +5702,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); return; #endif -#ifndef TARGET_SPARC64 - ncp_insn: - gen_exception(dc, TT_NCP_INSN); - return; -#endif } static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) From patchwork Fri Oct 13 21:27:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733267 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678122wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 36/85] target/sparc: Move JMPL, RETT, RETURN to decodetree Date: Fri, 13 Oct 2023 14:27:57 -0700 Message-Id: <20231013212846.165724-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 6 ++ target/sparc/translate.c | 121 +++++++++++++++++++++++--------------- 2 files changed, 79 insertions(+), 48 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a124fdeaac..d8ebebce53 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -212,6 +212,12 @@ MOVcc 10 rd:5 101100 1 cond:4 imm:1 cc:1 0 rs2_or_imm:s11 MOVfcc 10 rd:5 101100 0 cond:4 imm:1 cc:2 rs2_or_imm:s11 MOVR 10 rd:5 101111 rs1:5 imm:1 cond:3 rs2_or_imm:s10 +JMPL 10 ..... 111000 ..... . ............. @r_r_ri +{ + RETT 10 00000 111001 ..... . ............. @n_r_ri + RETURN 10 00000 111001 ..... . ............. @n_r_ri +} + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 72f3cbab47..47a281dc38 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -40,6 +40,7 @@ #define gen_helper_rdpsr(D, E) qemu_build_not_reached() #define gen_helper_wrpsr(E, S) qemu_build_not_reached() #define gen_helper_power_down(E) g_assert_not_reached() +#define gen_helper_rett(E) qemu_build_not_reached() #else #define gen_helper_rdccr(D, E) qemu_build_not_reached() #define gen_helper_rdcwp(D, E) qemu_build_not_reached() @@ -4388,6 +4389,77 @@ static bool trans_MOVR(DisasContext *dc, arg_MOVR *a) return do_mov_cond(dc, &cmp, a->rd, src2); } +static bool do_add_special(DisasContext *dc, arg_r_r_ri *a, + bool (*func)(DisasContext *dc, int rd, TCGv src)) +{ + TCGv src1, src; + + /* For simplicity, we under-decoded the rs2 form. */ + if (!a->imm && a->rs2_or_imm & ~0x1f) { + return false; + } + + src1 = gen_load_gpr(dc, a->rs1); + if (a->rs2_or_imm == 0) { + src = src1; + } else { + src = tcg_temp_new(); + if (a->imm) { + tcg_gen_addi_tl(src, src1, a->rs2_or_imm); + } else { + tcg_gen_add_tl(src, src1, cpu_regs[a->rs2_or_imm]); + } + } + return func(dc, a->rd, src); +} + +static bool do_jmpl(DisasContext *dc, int rd, TCGv src) +{ + gen_check_align(src, 3); + + gen_store_gpr(dc, rd, tcg_constant_tl(dc->pc)); + gen_mov_pc_npc(dc); + tcg_gen_mov_tl(cpu_npc, src); + gen_address_mask(dc, cpu_npc); + + dc->npc = DYNAMIC_PC_LOOKUP; + return true; +} + +TRANS(JMPL, ALL, do_add_special, a, do_jmpl) + +static bool do_rett(DisasContext *dc, int rd, TCGv src) +{ + if (!supervisor(dc)) { + return raise_priv(dc); + } + + gen_check_align(src, 3); + + gen_mov_pc_npc(dc); + tcg_gen_mov_tl(cpu_npc, src); + dc->npc = DYNAMIC_PC; + gen_helper_rett(tcg_env); + return true; +} + +TRANS(RETT, 32, do_add_special, a, do_rett) + +static bool do_return(DisasContext *dc, int rd, TCGv src) +{ + gen_check_align(src, 3); + + gen_mov_pc_npc(dc); + tcg_gen_mov_tl(cpu_npc, src); + gen_address_mask(dc, cpu_npc); + + gen_helper_restore(tcg_env); + dc->npc = DYNAMIC_PC_LOOKUP; + return true; +} + +TRANS(RETURN, 64, do_add_special, a, do_return) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5185,30 +5257,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */ goto illegal_insn; /* in decodetree */ -#ifdef TARGET_SPARC64 - } else if (xop == 0x39) { /* V9 return */ - save_state(dc); - cpu_src1 = get_src1(dc, insn); - cpu_tmp0 = tcg_temp_new(); - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 19, 31); - tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); - } else { /* register */ - rs2 = GET_FIELD(insn, 27, 31); - if (rs2) { - cpu_src2 = gen_load_gpr(dc, rs2); - tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2); - } else { - tcg_gen_mov_tl(cpu_tmp0, cpu_src1); - } - } - gen_helper_restore(tcg_env); - gen_mov_pc_npc(dc); - gen_check_align(cpu_tmp0, 3); - tcg_gen_mov_tl(cpu_npc, cpu_tmp0); - dc->npc = DYNAMIC_PC_LOOKUP; - goto jmp_insn; -#endif } else { cpu_src1 = get_src1(dc, insn); cpu_tmp0 = tcg_temp_new(); @@ -5226,31 +5274,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } switch (xop) { case 0x38: /* jmpl */ - { - TCGv t = gen_dest_gpr(dc, rd); - tcg_gen_movi_tl(t, dc->pc); - gen_store_gpr(dc, rd, t); - - gen_mov_pc_npc(dc); - gen_check_align(cpu_tmp0, 3); - gen_address_mask(dc, cpu_tmp0); - tcg_gen_mov_tl(cpu_npc, cpu_tmp0); - dc->npc = DYNAMIC_PC_LOOKUP; - } - goto jmp_insn; -#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) case 0x39: /* rett, V9 return */ - { - if (!supervisor(dc)) - goto priv_insn; - gen_mov_pc_npc(dc); - gen_check_align(cpu_tmp0, 3); - tcg_gen_mov_tl(cpu_npc, cpu_tmp0); - dc->npc = DYNAMIC_PC; - gen_helper_rett(tcg_env); - } - goto jmp_insn; -#endif + g_assert_not_reached(); /* in decode tree */ case 0x3b: /* flush */ /* nop */ break; From patchwork Fri Oct 13 21:27:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733327 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680309wrv; Fri, 13 Oct 2023 14:38:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF9F7F9Urg57E/E8E7c3SHi6krKgiOZBaUZCYzphQ3rCsf4NDiC93vWieMBSFa9Z9ZzEIl0 X-Received: by 2002:a0c:f0c5:0:b0:65a:f253:24d with SMTP id d5-20020a0cf0c5000000b0065af253024dmr1917061qvl.20.1697233100444; Fri, 13 Oct 2023 14:38:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233100; cv=none; d=google.com; s=arc-20160816; b=y1xyxLNJUGoQ44/bqkYkXRZGmneQww7Z6Hul2xV7vV5+lLxnNbk3q1AQbTTOrdyz55 s4RPn4DwR+na19t0M+zZxcV/OLG0MUtSQDq5SiwQYTY68AR+A8K7vu1ameRuQg7n0CzK xC6UzHoTD+7K8qHWBLFy3HZywSps50W/JQFL/lPoHJISUArcIfJdxA5xCFRgOAi/v1NA tCxGEsFHW63zdpkhNCrTM03Y95l9FzbOQHkc19idG8ZSRGRCB2wCWT9DqSA9rYjQ+06t ERIk9MFXGK09ZbijUh52mFnNbRcrc7abtV/Bjz2YZeKg9vLwCRBJCrGEAAyzFMahJGhz nmsg== ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 37/85] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree Date: Fri, 13 Oct 2023 14:27:58 -0700 Message-Id: <20231013212846.165724-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++++ target/sparc/translate.c | 35 +++++++++++++++++++++++++---------- 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d8ebebce53..b7b60f9919 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -217,6 +217,10 @@ JMPL 10 ..... 111000 ..... . ............. @r_r_ri RETT 10 00000 111001 ..... . ............. @n_r_ri RETURN 10 00000 111001 ..... . ............. @n_r_ri } +NOP 10 00000 111011 ----- 0 00000000----- # FLUSH reg+reg +NOP 10 00000 111011 ----- 1 ------------- # FLUSH reg+imm +SAVE 10 ..... 111100 ..... . ............. @r_r_ri +RESTORE 10 ..... 111101 ..... . ............. @r_r_ri NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 47a281dc38..960a3eabbd 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4092,6 +4092,11 @@ static bool do_saved_restored(DisasContext *dc, void (*func)(TCGv_env)) TRANS(SAVED, 64, do_saved_restored, gen_helper_saved) TRANS(RESTORED, 64, do_saved_restored, gen_helper_restored) +static bool trans_NOP(DisasContext *dc, arg_NOP *a) +{ + return advance_pc(dc); +} + static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a) { /* @@ -4460,6 +4465,24 @@ static bool do_return(DisasContext *dc, int rd, TCGv src) TRANS(RETURN, 64, do_add_special, a, do_return) +static bool do_save(DisasContext *dc, int rd, TCGv src) +{ + gen_helper_save(tcg_env); + gen_store_gpr(dc, rd, src); + return advance_pc(dc); +} + +TRANS(SAVE, ALL, do_add_special, a, do_save) + +static bool do_restore(DisasContext *dc, int rd, TCGv src) +{ + gen_helper_restore(tcg_env); + gen_store_gpr(dc, rd, src); + return advance_pc(dc); +} + +TRANS(RESTORE, ALL, do_add_special, a, do_restore) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5275,18 +5298,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) switch (xop) { case 0x38: /* jmpl */ case 0x39: /* rett, V9 return */ - g_assert_not_reached(); /* in decode tree */ - case 0x3b: /* flush */ - /* nop */ - break; + case 0x3b: /* flush */ case 0x3c: /* save */ - gen_helper_save(tcg_env); - gen_store_gpr(dc, rd, cpu_tmp0); - break; case 0x3d: /* restore */ - gen_helper_restore(tcg_env); - gen_store_gpr(dc, rd, cpu_tmp0); - break; + g_assert_not_reached(); /* in decode tree */ #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) case 0x3e: /* V9 done/retry */ { From patchwork Fri Oct 13 21:27:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733273 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678359wrv; Fri, 13 Oct 2023 14:31:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF8/a3xXPUbI3r2dzFYFYhdfOsyBWEj5uUOy7AYLgg4N5YOiy0PatS/RHC5/EzdGpvQLFMm X-Received: by 2002:a05:620a:170d:b0:767:f1de:293c with SMTP id az13-20020a05620a170d00b00767f1de293cmr33651803qkb.59.1697232711103; Fri, 13 Oct 2023 14:31:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232711; cv=none; d=google.com; s=arc-20160816; b=S9aQ0SNoWOneWTYcbpPe2Yhm7oj3JxvausoijNwzLswbIiNUgg1UGs6cEYd17rm7Wo 3UYa/7YMrhH8Bdsv5B4Dfw34sYnv0Kwpkk2cn5YuRs9FKtRlmMWJKXKa73D/7pboo48w vYs20e985/d8DmRo9Za4oNHjZDHVTdQ+U5TX3uTwldcNGt3j4/JdInMDdBEqF2WfTUML RiTp7+diFbEdVSZq708zQ7RLkSlSDh4e/PjOa0wJiaxqxq6CopRnrSqym8G4wzF7k7fA Wtim62Vxidx+lU4plA6Kh8Zk0zIzAadKOOeIaWbGMuOZPUUlgCMm3O8VvZqS6lPOUmx1 1Cwg== ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 38/85] target/sparc: Move DONE, RETRY to decodetree Date: Fri, 13 Oct 2023 14:27:59 -0700 Message-Id: <20231013212846.165724-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::130; envelope-from=richard.henderson@linaro.org; helo=mail-il1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 99 +++++++++++++++------------------------ 2 files changed, 40 insertions(+), 62 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index b7b60f9919..9f17a11dd0 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -222,6 +222,9 @@ NOP 10 00000 111011 ----- 1 ------------- # FLUSH reg+imm SAVE 10 ..... 111100 ..... . ............. @r_r_ri RESTORE 10 ..... 111101 ..... . ............. @r_r_ri +DONE 10 00000 111110 00000 0 0000000000000 +RETRY 10 00001 111110 00000 0 0000000000000 + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 960a3eabbd..e652bdcac2 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -54,6 +54,8 @@ #define gen_helper_write_softint(E, S) qemu_build_not_reached() #define gen_helper_saved ({ qemu_build_not_reached(); NULL; }) #define gen_helper_restored ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_done(E) qemu_build_not_reached() +#define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() #define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() #endif @@ -4483,6 +4485,36 @@ static bool do_restore(DisasContext *dc, int rd, TCGv src) TRANS(RESTORE, ALL, do_add_special, a, do_restore) +static bool trans_DONE(DisasContext *dc, arg_DONE *a) +{ + if (!avail_64(dc)) { + return false; + } + if (!supervisor(dc)) { + return raise_priv(dc); + } + dc->npc = DYNAMIC_PC; + dc->pc = DYNAMIC_PC; + translator_io_start(&dc->base); + gen_helper_done(tcg_env); + return true; +} + +static bool trans_RETRY(DisasContext *dc, arg_RETRY *a) +{ + if (!avail_64(dc)) { + return false; + } + if (!supervisor(dc)) { + return raise_priv(dc); + } + dc->npc = DYNAMIC_PC; + dc->pc = DYNAMIC_PC; + translator_io_start(&dc->base); + gen_helper_retry(tcg_env); + return true; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4494,7 +4526,8 @@ TRANS(RESTORE, ALL, do_add_special, a, do_restore) static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) { unsigned int opc, rs1, rs2, rd; - TCGv cpu_src1, cpu_src2; + TCGv cpu_src1; + TCGv cpu_src2 __attribute__((unused)); TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; target_long simm; @@ -4509,9 +4542,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) g_assert_not_reached(); /* in decodetree */ case 2: /* FPU & Logical Operations */ { - unsigned int xop __attribute__((unused)) = GET_FIELD(insn, 7, 12); + unsigned int xop = GET_FIELD(insn, 7, 12); TCGv cpu_dst __attribute__((unused)) = tcg_temp_new(); - TCGv cpu_tmp0 __attribute__((unused)); if (xop == 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) { @@ -4831,8 +4863,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) default: goto illegal_insn; } - } else if (xop < 0x36) { - goto illegal_insn; /* in decodetree */ } else if (xop == 0x36) { #ifdef TARGET_SPARC64 /* VIS */ @@ -5274,65 +5304,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) default: goto illegal_insn; } -#else - g_assert_not_reached(); /* in decodetree */ #endif - } else if (xop == 0x37) { - /* V8 CPop2, V9 impdep2 */ - goto illegal_insn; /* in decodetree */ } else { - cpu_src1 = get_src1(dc, insn); - cpu_tmp0 = tcg_temp_new(); - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 19, 31); - tcg_gen_addi_tl(cpu_tmp0, cpu_src1, simm); - } else { /* register */ - rs2 = GET_FIELD(insn, 27, 31); - if (rs2) { - cpu_src2 = gen_load_gpr(dc, rs2); - tcg_gen_add_tl(cpu_tmp0, cpu_src1, cpu_src2); - } else { - tcg_gen_mov_tl(cpu_tmp0, cpu_src1); - } - } - switch (xop) { - case 0x38: /* jmpl */ - case 0x39: /* rett, V9 return */ - case 0x3b: /* flush */ - case 0x3c: /* save */ - case 0x3d: /* restore */ - g_assert_not_reached(); /* in decode tree */ -#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) - case 0x3e: /* V9 done/retry */ - { - switch (rd) { - case 0: - if (!supervisor(dc)) - goto priv_insn; - dc->npc = DYNAMIC_PC; - dc->pc = DYNAMIC_PC; - translator_io_start(&dc->base); - gen_helper_done(tcg_env); - goto jmp_insn; - case 1: - if (!supervisor(dc)) - goto priv_insn; - dc->npc = DYNAMIC_PC; - dc->pc = DYNAMIC_PC; - translator_io_start(&dc->base); - gen_helper_retry(tcg_env); - goto jmp_insn; - default: - goto illegal_insn; - } - } - break; -#endif - default: - goto illegal_insn; - } + goto illegal_insn; /* in decodetree */ } - break; } break; case 3: /* load/store instructions */ @@ -5729,7 +5704,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) illegal_insn: gen_exception(dc, TT_ILL_INSN); return; -#if !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) priv_insn: gen_exception(dc, TT_PRIV_INSN); return; From patchwork Fri Oct 13 21:28:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733343 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680808wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 39/85] target/sparc: Split out resolve_asi Date: Fri, 13 Oct 2023 14:28:00 -0700 Message-Id: <20231013212846.165724-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/translate.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e652bdcac2..42a26671f1 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1815,15 +1815,25 @@ typedef struct { MemOp memop; } DisasASI; -static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) +/* + * Build DisasASI. + * For asi == -1, treat as non-asi. + * For ask == -2, treat as immediate offset (v8 error, v9 %asi). + */ +static DisasASI resolve_asi(DisasContext *dc, int asi, MemOp memop) { - int asi = GET_FIELD(insn, 19, 26); ASIType type = GET_ASI_HELPER; int mem_idx = dc->mem_idx; + if (asi == -1) { + /* Artificial "non-asi" case. */ + type = GET_ASI_DIRECT; + goto done; + } + #ifndef TARGET_SPARC64 /* Before v9, all asis are immediate and privileged. */ - if (IS_IMM) { + if (asi < 0) { gen_exception(dc, TT_ILL_INSN); type = GET_ASI_EXCP; } else if (supervisor(dc) @@ -1866,7 +1876,7 @@ static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) type = GET_ASI_EXCP; } #else - if (IS_IMM) { + if (asi < 0) { asi = dc->asi; } /* With v9, all asis below 0x80 are privileged. */ @@ -2025,9 +2035,16 @@ static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) } #endif + done: return (DisasASI){ type, asi, mem_idx, memop }; } +static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) +{ + int asi = IS_IMM ? -2 : GET_FIELD(insn, 19, 26); + return resolve_asi(dc, asi, memop); +} + static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) { From patchwork Fri Oct 13 21:28:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733319 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680106wrv; Fri, 13 Oct 2023 14:37:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEOqy1Q3NrM+e1oFIvVUFo8GehP7y3gD56aasYBuVw4NNmuY91oAXBt54+1m9GG32OIzaCH X-Received: by 2002:a0c:e144:0:b0:66d:28aa:71d6 with SMTP id c4-20020a0ce144000000b0066d28aa71d6mr1997157qvl.1.1697233051642; Fri, 13 Oct 2023 14:37:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233051; cv=none; d=google.com; s=arc-20160816; b=R0hBYn2xdjN+tTAvFKlZbR7fT+rt/TN8gO04O28XHUN68FXn/HW16KDj+t/9nxehMQ bR6LQnFmX9EVGF3SWAxjsevAgTQTS9WOWMw5lC2KK6MnAo9kIjpzayoiX88ROdm1X8RD hy2B+wugORdLs+0F7v2niMRK3vunwujFSN6rizjypHKn9so1AqmluN7SPWVhdUQL1Lxz 2GwWKsaTzAoTUTg5QrenBz55baWj6pCAs7Nzik/7AwTVqQ5YabJh2lZyrKdnD9ki34bb Pg+3R6O8S+lwkIPqkqi+MgYrsS+anexHbsaGKKrl8C9I2t5GVlinZWKigU73J3kGi8zw St0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=M91yoQdGXBejSl6trWlHpYf1tkOCkHw3ekFimpTrLSg=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=WRIRTu5DTwHat5kI2zmbG69bW6XLK/f1kzhgpwERaWv3EhJPm3bZaIDMSqH1yTFKSQ HRjpEKiHAi3JMkLC0CpqdaJnVydAIqkDs7X52OLNUvzMRrGo+JT3/JG18hR4NsrGn297 gso32JNHRAbPWHwEVtPa6ifS47DW+JQCa8gHVjf8WDcpCzvfSgLKzNKO62iqOn5m7hhB 0IA00PyrMfVjmcl9uXsTExTboqVjtWH+Y80X3YrmU8NJ13HgcYCElSzDv/HzMwvm4Lhk 7ikaVVFRWq9DVb6D/UNAtv2WM4BuLyZmH+GQm6zmIdeD614qutmILS778NgSNaoNayul e9/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="EDAU5/Wd"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 40/85] target/sparc: Drop ifdef around get_asi and friends Date: Fri, 13 Oct 2023 14:28:01 -0700 Message-Id: <20231013212846.165724-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mark some of the functions as unused, temporarily. Fix up some tl vs i64 issues revealed in the process. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 187 +++++++++++++++------------------------ 1 file changed, 70 insertions(+), 117 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 42a26671f1..a6ae031181 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -58,6 +58,18 @@ #define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() #define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() +# ifdef CONFIG_USER_ONLY +static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a, + TCGv_i32 asi, TCGv_i32 mop) +{ + g_assert_not_reached(); +} +static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r, + TCGv_i32 asi, TCGv_i32 mop) +{ + g_assert_not_reached(); +} +# endif #endif /* Dynamic PC, must exit to main loop. */ @@ -1796,7 +1808,6 @@ static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx) } /* asi moves */ -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) typedef enum { GET_ASI_HELPER, GET_ASI_EXCP, @@ -2045,8 +2056,8 @@ static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) return resolve_asi(dc, asi, memop); } -static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, - int insn, MemOp memop) +static void __attribute__((unused)) +gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) { DisasASI da = get_asi(dc, insn, memop); @@ -2080,8 +2091,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, } } -static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, - int insn, MemOp memop) +static void __attribute__((unused)) +gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) { DisasASI da = get_asi(dc, insn, memop); @@ -2156,8 +2167,8 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, } } -static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, - TCGv addr, int insn) +static void __attribute__((unused)) +gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn) { DisasASI da = get_asi(dc, insn, MO_TEUL); @@ -2174,8 +2185,8 @@ static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, } } -static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, - int insn, int rd) +static void __attribute__((unused)) +gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUL); TCGv oldv; @@ -2196,7 +2207,8 @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, } } -static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) +static void __attribute__((unused)) +gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) { DisasASI da = get_asi(dc, insn, MO_UB); @@ -2231,11 +2243,9 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) break; } } -#endif -#ifdef TARGET_SPARC64 -static void gen_ldf_asi(DisasContext *dc, TCGv addr, - int insn, int size, int rd) +static void __attribute__((unused)) +gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ)); TCGv_i32 d32; @@ -2343,8 +2353,8 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, } } -static void gen_stf_asi(DisasContext *dc, TCGv addr, - int insn, int size, int rd) +static void __attribute__((unused)) +gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ)); TCGv_i32 d32; @@ -2426,21 +2436,23 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, } } -static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) +static void __attribute__((unused)) +gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUQ); - TCGv_i64 hi = gen_dest_gpr(dc, rd); - TCGv_i64 lo = gen_dest_gpr(dc, rd + 1); + TCGv hi = gen_dest_gpr(dc, rd); + TCGv lo = gen_dest_gpr(dc, rd + 1); switch (da.type) { case GET_ASI_EXCP: return; case GET_ASI_DTWINX: + assert(TARGET_LONG_BITS == 64); gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_ld_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_ld_tl(lo, addr, da.mem_idx, da.memop); break; case GET_ASI_DIRECT: @@ -2454,9 +2466,9 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) result is byte swapped. Having just performed one 64-bit bswap, we need now to swap the writebacks. */ if ((da.memop & MO_BSWAP) == MO_TE) { - tcg_gen_extr32_i64(lo, hi, tmp); + tcg_gen_extr_i64_tl(lo, hi, tmp); } else { - tcg_gen_extr32_i64(hi, lo, tmp); + tcg_gen_extr_i64_tl(hi, lo, tmp); } } break; @@ -2476,9 +2488,9 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) /* See above. */ if ((da.memop & MO_BSWAP) == MO_TE) { - tcg_gen_extr32_i64(lo, hi, tmp); + tcg_gen_extr_i64_tl(lo, hi, tmp); } else { - tcg_gen_extr32_i64(hi, lo, tmp); + tcg_gen_extr_i64_tl(hi, lo, tmp); } } break; @@ -2488,8 +2500,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) gen_store_gpr(dc, rd + 1, lo); } -static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, - int insn, int rd) +static void __attribute__((unused)) +gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUQ); TCGv lo = gen_load_gpr(dc, rd + 1); @@ -2499,10 +2511,11 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, break; case GET_ASI_DTWINX: + assert(TARGET_LONG_BITS == 64); gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_st_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_tl(lo, addr, da.mem_idx, da.memop); break; case GET_ASI_DIRECT: @@ -2513,15 +2526,37 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, byte swapped. We will perform one 64-bit LE store, so now we must swap the order of the construction. */ if ((da.memop & MO_BSWAP) == MO_TE) { - tcg_gen_concat32_i64(t64, lo, hi); + tcg_gen_concat_tl_i64(t64, lo, hi); } else { - tcg_gen_concat32_i64(t64, hi, lo); + tcg_gen_concat_tl_i64(t64, hi, lo); } gen_address_mask(dc, addr); tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); } break; + case GET_ASI_BFILL: + assert(TARGET_LONG_BITS == 32); + /* Store 32 bytes of T64 to ADDR. */ + /* ??? The original qemu code suggests 8-byte alignment, dropping + the low bits, but the only place I can see this used is in the + Linux kernel with 32 byte alignment, which would make more sense + as a cacheline-style operation. */ + { + TCGv_i64 t64 = tcg_temp_new_i64(); + TCGv d_addr = tcg_temp_new(); + TCGv eight = tcg_constant_tl(8); + int i; + + tcg_gen_concat_tl_i64(t64, lo, hi); + tcg_gen_andi_tl(d_addr, addr, -8); + for (i = 0; i < 32; i += 8) { + tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); + tcg_gen_add_tl(d_addr, d_addr, eight); + } + } + break; + default: /* ??? In theory we've handled all of the ASIs that are valid for stda, and this should raise DAE_invalid_asi. */ @@ -2532,9 +2567,9 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, /* See above. */ if ((da.memop & MO_BSWAP) == MO_TE) { - tcg_gen_concat32_i64(t64, lo, hi); + tcg_gen_concat_tl_i64(t64, lo, hi); } else { - tcg_gen_concat32_i64(t64, hi, lo); + tcg_gen_concat_tl_i64(t64, hi, lo); } save_state(dc); @@ -2544,8 +2579,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, } } -static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, - int insn, int rd) +static void __attribute__((unused)) +gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUQ); TCGv oldv; @@ -2566,88 +2601,6 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, } } -#elif !defined(CONFIG_USER_ONLY) -static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) -{ - /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12, - whereby "rd + 1" elicits "error: array subscript is above array". - Since we have already asserted that rd is even, the semantics - are unchanged. */ - TCGv lo = gen_dest_gpr(dc, rd | 1); - TCGv hi = gen_dest_gpr(dc, rd); - TCGv_i64 t64 = tcg_temp_new_i64(); - DisasASI da = get_asi(dc, insn, MO_TEUQ); - - switch (da.type) { - case GET_ASI_EXCP: - return; - case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); - break; - default: - { - TCGv_i32 r_asi = tcg_constant_i32(da.asi); - TCGv_i32 r_mop = tcg_constant_i32(MO_UQ); - - save_state(dc); - gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop); - } - break; - } - - tcg_gen_extr_i64_i32(lo, hi, t64); - gen_store_gpr(dc, rd | 1, lo); - gen_store_gpr(dc, rd, hi); -} - -static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, - int insn, int rd) -{ - DisasASI da = get_asi(dc, insn, MO_TEUQ); - TCGv lo = gen_load_gpr(dc, rd + 1); - TCGv_i64 t64 = tcg_temp_new_i64(); - - tcg_gen_concat_tl_i64(t64, lo, hi); - - switch (da.type) { - case GET_ASI_EXCP: - break; - case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); - break; - case GET_ASI_BFILL: - /* Store 32 bytes of T64 to ADDR. */ - /* ??? The original qemu code suggests 8-byte alignment, dropping - the low bits, but the only place I can see this used is in the - Linux kernel with 32 byte alignment, which would make more sense - as a cacheline-style operation. */ - { - TCGv d_addr = tcg_temp_new(); - TCGv eight = tcg_constant_tl(8); - int i; - - tcg_gen_andi_tl(d_addr, addr, -8); - for (i = 0; i < 32; i += 8) { - tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); - tcg_gen_add_tl(d_addr, d_addr, eight); - } - } - break; - default: - { - TCGv_i32 r_asi = tcg_constant_i32(da.asi); - TCGv_i32 r_mop = tcg_constant_i32(MO_UQ); - - save_state(dc); - gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop); - } - break; - } -} -#endif - static TCGv get_src1(DisasContext *dc, unsigned int insn) { unsigned int rs1 = GET_FIELD(insn, 13, 17); From patchwork Fri Oct 13 21:28:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733341 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680800wrv; Fri, 13 Oct 2023 14:40:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE4/JmOsYfQEcTFXeIFiEbLLOWikX7xcT2foTI3Ku5ihMK7NnBBO57ZrbKzMfMDaSgXg2eL X-Received: by 2002:a25:ce41:0:b0:d9a:ea52:8f5f with SMTP id x62-20020a25ce41000000b00d9aea528f5fmr5236184ybe.20.1697233223482; Fri, 13 Oct 2023 14:40:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233223; cv=none; d=google.com; s=arc-20160816; b=NoRLzfOqfHhvvKMeoUH3HXrP7xjLRh2Xd6lwRmeBt93umR7bgRUh8rQfY6qp7bJTty i5bLHJLtnpEmeVvCr0xTVaDxJtnvlfP+bFAhg86B2APHL7EB0mR597EkM4ezWV13q+rH D4k0nKZ2N5R6rRUWGijrFG12MrF/A7r5YjHHIPrmNLwVSDAugCt0MVgGjdWW5qqzWhIo /Q1JYM4KL2/HMNTyqqnHDWn9hzW9qmHAA8yQiqThb5cwmABAu6mr7bWFGT49ajY+C832 Y4kpKZHaxQ+/B24ZsSw43AXzl7nEaeN9g5z3sWd4TWo0Ow47FFqyNudLHg5j/wkxR737 UjNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YuLUgEipb18BBz/Gnk6d/FAWi1e7n+BOkrgevJ3GuFE=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=nI87IV1W5EPPPkmp8ffmk5S1oudKWF0vo1VD8UyAggxchmGRKt8bfwBUfpGsIZEfMT kR/1+bk0ixj28EXhbtAjFjIo6u9ozBL6V1AC3x0YUlq8p9L6XupdxdLtQ25nwsFialXL 4pPFcZga3mQ6c+1PGTZXYs3bHmW567Mi+9jiEK/8kg+wiSVnl6PVrsgKytV7VWMsOAeH Ba9WtqnhFeUawFplzm8Dg5p9nT0C0oJzAgYbFhAsxMR06QvJfnUk6gd4JYwqws9ZYaXz Vu7J9aG/xNYj6zQdb4HDT3/mlPdSYzkpI7HkP1BOVjGI920A/9Uk+LY/YdYNckOKjIyM REZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="qn9nM/tm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 41/85] target/sparc: Split out ldst functions with asi pre-computed Date: Fri, 13 Oct 2023 14:28:02 -0700 Message-Id: <20231013212846.165724-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org As an intermediate step in decodetree conversion, create new functions passing in DisasASI and not insn. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 215 ++++++++++++++++++++++----------------- 1 file changed, 123 insertions(+), 92 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a6ae031181..696e60bd30 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2056,25 +2056,21 @@ static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) return resolve_asi(dc, asi, memop); } -static void __attribute__((unused)) -gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) +static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) { - DisasASI da = get_asi(dc, insn, memop); - - switch (da.type) { + switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DTWINX: /* Reserved for ldda. */ gen_exception(dc, TT_ILL_INSN); break; case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_tl(dst, addr, da.mem_idx, da.memop | MO_ALIGN); + tcg_gen_qemu_ld_tl(dst, addr, da->mem_idx, da->memop | MO_ALIGN); break; default: { - TCGv_i32 r_asi = tcg_constant_i32(da.asi); - TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN); + TCGv_i32 r_asi = tcg_constant_i32(da->asi); + TCGv_i32 r_mop = tcg_constant_i32(da->memop | MO_ALIGN); save_state(dc); #ifdef TARGET_SPARC64 @@ -2092,33 +2088,38 @@ gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) } static void __attribute__((unused)) -gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) +gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) { DisasASI da = get_asi(dc, insn, memop); - switch (da.type) { + gen_address_mask(dc, addr); + gen_ld_asi0(dc, &da, dst, addr); +} + +static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr) +{ + switch (da->type) { case GET_ASI_EXCP: break; + case GET_ASI_DTWINX: /* Reserved for stda. */ -#ifndef TARGET_SPARC64 - gen_exception(dc, TT_ILL_INSN); - break; -#else - if (!(dc->def->features & CPU_FEATURE_HYPV)) { + if (TARGET_LONG_BITS == 32) { + gen_exception(dc, TT_ILL_INSN); + break; + } else if (!(dc->def->features & CPU_FEATURE_HYPV)) { /* Pre OpenSPARC CPUs don't have these */ gen_exception(dc, TT_ILL_INSN); - return; + break; } - /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions - * are ST_BLKINIT_ ASIs */ -#endif + /* In OpenSPARC T1+ CPUs TWINX ASIs in store are ST_BLKINIT_ ASIs */ /* fall through */ + case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop | MO_ALIGN); + tcg_gen_qemu_st_tl(src, addr, da->mem_idx, da->memop | MO_ALIGN); break; -#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) + case GET_ASI_BCOPY: + assert(TARGET_LONG_BITS == 32); /* Copy 32 bytes from the address in SRC to ADDR. */ /* ??? The original qemu code suggests 4-byte alignment, dropping the low bits, but the only place I can see this used is in the @@ -2136,18 +2137,18 @@ gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) for (i = 0; i < 32; i += 4) { /* Since the loads and stores are paired, allow the copy to happen in the host endianness. */ - tcg_gen_qemu_ld_i32(tmp, saddr, da.mem_idx, MO_UL); - tcg_gen_qemu_st_i32(tmp, daddr, da.mem_idx, MO_UL); + tcg_gen_qemu_ld_i32(tmp, saddr, da->mem_idx, MO_UL); + tcg_gen_qemu_st_i32(tmp, daddr, da->mem_idx, MO_UL); tcg_gen_add_tl(saddr, saddr, four); tcg_gen_add_tl(daddr, daddr, four); } } break; -#endif + default: { - TCGv_i32 r_asi = tcg_constant_i32(da.asi); - TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN); + TCGv_i32 r_asi = tcg_constant_i32(da->asi); + TCGv_i32 r_mop = tcg_constant_i32(da->memop | MO_ALIGN); save_state(dc); #ifdef TARGET_SPARC64 @@ -2167,16 +2168,49 @@ gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) } } +static void __attribute__((unused)) +gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) +{ + DisasASI da = get_asi(dc, insn, memop); + + gen_address_mask(dc, addr); + gen_st_asi0(dc, &da, src, addr); +} + +static void gen_swap_asi0(DisasContext *dc, DisasASI *da, + TCGv dst, TCGv src, TCGv addr) +{ + switch (da->type) { + case GET_ASI_EXCP: + break; + case GET_ASI_DIRECT: + gen_swap(dc, dst, src, addr, da->mem_idx, da->memop); + break; + default: + /* ??? Should be DAE_invalid_asi. */ + gen_exception(dc, TT_DATA_ACCESS); + break; + } +} + static void __attribute__((unused)) gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn) { DisasASI da = get_asi(dc, insn, MO_TEUL); - switch (da.type) { + gen_address_mask(dc, addr); + gen_swap_asi0(dc, &da, dst, src, addr); +} + +static void gen_cas_asi0(DisasContext *dc, DisasASI *da, + TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr) +{ + switch (da->type) { case GET_ASI_EXCP: - break; + return; case GET_ASI_DIRECT: - gen_swap(dc, dst, src, addr, da.mem_idx, da.memop); + tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, newv, + da->mem_idx, da->memop | MO_ALIGN); break; default: /* ??? Should be DAE_invalid_asi. */ @@ -2189,34 +2223,33 @@ static void __attribute__((unused)) gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUL); - TCGv oldv; + TCGv oldv = gen_dest_gpr(dc, rd); + TCGv newv = gen_load_gpr(dc, rd); - switch (da.type) { - case GET_ASI_EXCP: - return; - case GET_ASI_DIRECT: - oldv = tcg_temp_new(); - tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), - da.mem_idx, da.memop | MO_ALIGN); - gen_store_gpr(dc, rd, oldv); - break; - default: - /* ??? Should be DAE_invalid_asi. */ - gen_exception(dc, TT_DATA_ACCESS); - break; - } + gen_address_mask(dc, addr); + gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr); + gen_store_gpr(dc, rd, oldv); } static void __attribute__((unused)) -gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) +gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { - DisasASI da = get_asi(dc, insn, MO_UB); + DisasASI da = get_asi(dc, insn, MO_TEUQ); + TCGv oldv = gen_dest_gpr(dc, rd); + TCGv newv = gen_load_gpr(dc, rd); - switch (da.type) { + gen_address_mask(dc, addr); + gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr); + gen_store_gpr(dc, rd, oldv); +} + +static void gen_ldstub_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) +{ + switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DIRECT: - gen_ldstub(dc, dst, addr, da.mem_idx); + gen_ldstub(dc, dst, addr, da->mem_idx); break; default: /* ??? In theory, this should be raise DAE_invalid_asi. @@ -2224,7 +2257,7 @@ gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) if (tb_cflags(dc->base.tb) & CF_PARALLEL) { gen_helper_exit_atomic(tcg_env); } else { - TCGv_i32 r_asi = tcg_constant_i32(da.asi); + TCGv_i32 r_asi = tcg_constant_i32(da->asi); TCGv_i32 r_mop = tcg_constant_i32(MO_UB); TCGv_i64 s64, t64; @@ -2244,6 +2277,15 @@ gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) } } +static void __attribute__((unused)) +gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) +{ + DisasASI da = get_asi(dc, insn, MO_UB); + + gen_address_mask(dc, addr); + gen_ldstub_asi0(dc, &da, dst, addr); +} + static void __attribute__((unused)) gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { @@ -2436,36 +2478,32 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) } } -static void __attribute__((unused)) -gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) +static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { - DisasASI da = get_asi(dc, insn, MO_TEUQ); TCGv hi = gen_dest_gpr(dc, rd); TCGv lo = gen_dest_gpr(dc, rd + 1); - switch (da.type) { + switch (da->type) { case GET_ASI_EXCP: return; case GET_ASI_DTWINX: assert(TARGET_LONG_BITS == 64); - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_ld_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_tl(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_ld_tl(lo, addr, da->mem_idx, da->memop); break; case GET_ASI_DIRECT: { TCGv_i64 tmp = tcg_temp_new_i64(); - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(tmp, addr, da.mem_idx, da.memop | MO_ALIGN); + tcg_gen_qemu_ld_i64(tmp, addr, da->mem_idx, da->memop | MO_ALIGN); /* Note that LE ldda acts as if each 32-bit register result is byte swapped. Having just performed one 64-bit bswap, we need now to swap the writebacks. */ - if ((da.memop & MO_BSWAP) == MO_TE) { + if ((da->memop & MO_BSWAP) == MO_TE) { tcg_gen_extr_i64_tl(lo, hi, tmp); } else { tcg_gen_extr_i64_tl(hi, lo, tmp); @@ -2479,15 +2517,15 @@ gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) real hardware allows others. This can be seen with e.g. FreeBSD 10.3 wrt ASI_IC_TAG. */ { - TCGv_i32 r_asi = tcg_constant_i32(da.asi); - TCGv_i32 r_mop = tcg_constant_i32(da.memop); + TCGv_i32 r_asi = tcg_constant_i32(da->asi); + TCGv_i32 r_mop = tcg_constant_i32(da->memop); TCGv_i64 tmp = tcg_temp_new_i64(); save_state(dc); gen_helper_ld_asi(tmp, tcg_env, addr, r_asi, r_mop); /* See above. */ - if ((da.memop & MO_BSWAP) == MO_TE) { + if ((da->memop & MO_BSWAP) == MO_TE) { tcg_gen_extr_i64_tl(lo, hi, tmp); } else { tcg_gen_extr_i64_tl(hi, lo, tmp); @@ -2501,21 +2539,28 @@ gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) } static void __attribute__((unused)) -gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) +gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUQ); + + gen_address_mask(dc, addr); + gen_ldda_asi0(dc, &da, addr, rd); +} + +static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) +{ + TCGv hi = gen_load_gpr(dc, rd); TCGv lo = gen_load_gpr(dc, rd + 1); - switch (da.type) { + switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DTWINX: assert(TARGET_LONG_BITS == 64); - gen_address_mask(dc, addr); - tcg_gen_qemu_st_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_st_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_tl(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_tl(lo, addr, da->mem_idx, da->memop); break; case GET_ASI_DIRECT: @@ -2525,13 +2570,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) /* Note that LE stda acts as if each 32-bit register result is byte swapped. We will perform one 64-bit LE store, so now we must swap the order of the construction. */ - if ((da.memop & MO_BSWAP) == MO_TE) { + if ((da->memop & MO_BSWAP) == MO_TE) { tcg_gen_concat_tl_i64(t64, lo, hi); } else { tcg_gen_concat_tl_i64(t64, hi, lo); } - gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); + tcg_gen_qemu_st_i64(t64, addr, da->mem_idx, da->memop | MO_ALIGN); } break; @@ -2551,7 +2595,7 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) tcg_gen_concat_tl_i64(t64, lo, hi); tcg_gen_andi_tl(d_addr, addr, -8); for (i = 0; i < 32; i += 8) { - tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_i64(t64, d_addr, da->mem_idx, da->memop); tcg_gen_add_tl(d_addr, d_addr, eight); } } @@ -2561,12 +2605,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) /* ??? In theory we've handled all of the ASIs that are valid for stda, and this should raise DAE_invalid_asi. */ { - TCGv_i32 r_asi = tcg_constant_i32(da.asi); - TCGv_i32 r_mop = tcg_constant_i32(da.memop); + TCGv_i32 r_asi = tcg_constant_i32(da->asi); + TCGv_i32 r_mop = tcg_constant_i32(da->memop); TCGv_i64 t64 = tcg_temp_new_i64(); /* See above. */ - if ((da.memop & MO_BSWAP) == MO_TE) { + if ((da->memop & MO_BSWAP) == MO_TE) { tcg_gen_concat_tl_i64(t64, lo, hi); } else { tcg_gen_concat_tl_i64(t64, hi, lo); @@ -2580,25 +2624,12 @@ gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) } static void __attribute__((unused)) -gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) +gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUQ); - TCGv oldv; - switch (da.type) { - case GET_ASI_EXCP: - return; - case GET_ASI_DIRECT: - oldv = tcg_temp_new(); - tcg_gen_atomic_cmpxchg_tl(oldv, addr, cmpv, gen_load_gpr(dc, rd), - da.mem_idx, da.memop | MO_ALIGN); - gen_store_gpr(dc, rd, oldv); - break; - default: - /* ??? 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 42/85] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX Date: Fri, 13 Oct 2023 14:28:03 -0700 Message-Id: <20231013212846.165724-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Perform one atomic 16-byte operation. The atomicity is required for the LDTXA instructions. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 48 +++++++++++++++++++++++++++++++++------- 1 file changed, 40 insertions(+), 8 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 696e60bd30..1b993d3c4f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2488,11 +2488,27 @@ static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) return; case GET_ASI_DTWINX: - assert(TARGET_LONG_BITS == 64); - tcg_gen_qemu_ld_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16); - tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_tl(lo, addr, da->mem_idx, da->memop); +#ifdef TARGET_SPARC64 + { + MemOp mop = (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16; + TCGv_i128 t = tcg_temp_new_i128(); + + tcg_gen_qemu_ld_i128(t, addr, da->mem_idx, mop); + /* + * Note that LE twinx acts as if each 64-bit register result is + * byte swapped. We perform one 128-bit LE load, so must swap + * the order of the writebacks. + */ + if ((mop & MO_BSWAP) == MO_TE) { + tcg_gen_extr_i128_i64(lo, hi, t); + } else { + tcg_gen_extr_i128_i64(hi, lo, t); + } + } break; +#else + g_assert_not_reached(); +#endif case GET_ASI_DIRECT: { @@ -2557,11 +2573,27 @@ static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) break; case GET_ASI_DTWINX: - assert(TARGET_LONG_BITS == 64); - tcg_gen_qemu_st_tl(hi, addr, da->mem_idx, da->memop | MO_ALIGN_16); - tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_tl(lo, addr, da->mem_idx, da->memop); +#ifdef TARGET_SPARC64 + { + MemOp mop = (da->memop & MO_BSWAP) | MO_128 | MO_ALIGN_16; + TCGv_i128 t = tcg_temp_new_i128(); + + /* + * Note that LE twinx acts as if each 64-bit register result is + * byte swapped. We perform one 128-bit LE store, so must swap + * the order of the construction. + */ + if ((mop & MO_BSWAP) == MO_TE) { + tcg_gen_concat_i64_i128(t, lo, hi); + } else { + tcg_gen_concat_i64_i128(t, hi, lo); + } + tcg_gen_qemu_st_i128(t, addr, da->mem_idx, mop); + } break; +#else + g_assert_not_reached(); +#endif case GET_ASI_DIRECT: { From patchwork Fri Oct 13 21:28:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733297 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679321wrv; Fri, 13 Oct 2023 14:34:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEBsHZigT3+xq+pGOH4OrqwP2n8JbIu7yLC8hJnIzFfxFdxLHLJjNo6iW+i3yQkvu7a0DnR X-Received: by 2002:ac8:5c91:0:b0:419:af26:fc72 with SMTP id r17-20020ac85c91000000b00419af26fc72mr36920882qta.27.1697232889549; Fri, 13 Oct 2023 14:34:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232889; cv=none; d=google.com; s=arc-20160816; b=NlNbgBs2yMu0ImT0xScT17QKGHKUjrKuhl5mtIn4lqRIeZ8XyCHkizuGkCeZrFgWcQ L2b9xvcUARZLM/9v3Vbd/AzxRFGiaiCkm+NH1XOnKEECqfgJZM/L0XxnVnzUDmnaSLOY jAKk6EaE4TDIMOg+RFArfEkTprrhTGq954rNPtR3ayuyUQF8HdsVzwlWqeclgW1ZEPkI KxKrGmCrIVFYZcqjbY891yHEAmS989l2QayllG1ZP3eznDIuL+50cjosCyhIvjhsM8g5 zJIfRNAm+DeSKOg6HaplpMNkB6ZjFJHAp6tdFyJTBZwxnmXYgmTYm7ildVHmolPVwhrM 0Zdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KUmwueb7S1DMx35feLpQHLxy/jk7oJXlQISdfgxN4F0=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=vHu8b2vnckUHb46DgZOs0xVhnzIA7W6M+hoTILW15iHgDD4w7R72C/iGXUiSlq566j D+7PPznq54xGpoCmO0eOOIyxQV0mM4jX7evIH9Qz1BYCgCZmlEVENGzltdUcxTyJLuJL DBGP+HhGOFLtP/KKG+gpbmc7t/yeJuyYCBp6vuW4HUwe5AKbwi4/7dpC8sVaQ2eCXw3J IV/ZdODk0fAMKJu24ejL90Cqq4fHbFLqXlMFZ63Hhzx4q7WNxAtxEf63psEXHBsEqYMQ Cv8b4hUdKrrXRkcYbcO34ZC+1q1QbD4y/+Sf5h+QPb2eVW/R9vwCVTM1efrvMLKGCeJn w1Jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PS7fBfgP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 43/85] target/sparc: Move simple integer load/store to decodetree Date: Fri, 13 Oct 2023 14:28:04 -0700 Message-Id: <20231013212846.165724-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move LDUW, LDUB, LDUH, LDD, LDSW, LDSB, LDSH, LDX, STW, STB, STH, STD, STX. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 +++++ target/sparc/translate.c | 196 +++++++++++++++++++++++--------------- 2 files changed, 142 insertions(+), 76 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 9f17a11dd0..41fbda4eb8 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -225,6 +225,28 @@ RESTORE 10 ..... 111101 ..... . ............. @r_r_ri DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 +## +## Major Opcode 11 -- load and store instructions +## + +&r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool +@r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi=-1 + +LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na +LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na +LDUH 11 ..... 000010 ..... . ............. @r_r_ri_na +LDD 11 ..... 000011 ..... . ............. @r_r_ri_na +LDSW 11 ..... 001000 ..... . ............. @r_r_ri_na +LDSB 11 ..... 001001 ..... . ............. @r_r_ri_na +LDSH 11 ..... 001010 ..... . ............. @r_r_ri_na +LDX 11 ..... 001011 ..... . ............. @r_r_ri_na + +STW 11 ..... 000100 ..... . ............. @r_r_ri_na +STB 11 ..... 000101 ..... . ............. @r_r_ri_na +STH 11 ..... 000110 ..... . ............. @r_r_ri_na +STD 11 ..... 000111 ..... . ............. @r_r_ri_na +STX 11 ..... 001110 ..... . ............. @r_r_ri_na + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1b993d3c4f..7b7437dbd8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4548,6 +4548,117 @@ static bool trans_RETRY(DisasContext *dc, arg_RETRY *a) return true; } +/* + * Major opcode 11 -- load and store instructions + */ + +static TCGv gen_ldst_addr(DisasContext *dc, int rs1, bool imm, int rs2_or_imm) +{ + TCGv addr, tmp = NULL; + + /* For simplicity, we under-decoded the rs2 form. */ + if (!imm && rs2_or_imm & ~0x1f) { + return NULL; + } + + addr = gen_load_gpr(dc, rs1); + if (rs2_or_imm) { + tmp = tcg_temp_new(); + if (imm) { + tcg_gen_addi_tl(tmp, addr, rs2_or_imm); + } else { + tcg_gen_add_tl(tmp, addr, cpu_regs[rs2_or_imm]); + } + addr = tmp; + } + if (AM_CHECK(dc)) { + if (!tmp) { + tmp = tcg_temp_new(); + } + tcg_gen_ext32u_tl(tmp, addr); + addr = tmp; + } + return addr; +} + +static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) +{ + TCGv reg, addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + DisasASI da; + + if (addr == NULL) { + return false; + } + da = resolve_asi(dc, a->asi, mop); + + reg = gen_dest_gpr(dc, a->rd); + gen_ld_asi0(dc, &da, reg, addr); + gen_store_gpr(dc, a->rd, reg); + return advance_pc(dc); +} + +TRANS(LDUW, ALL, do_ld_gpr, a, MO_TEUL) +TRANS(LDUB, ALL, do_ld_gpr, a, MO_UB) +TRANS(LDUH, ALL, do_ld_gpr, a, MO_TEUW) +TRANS(LDSB, ALL, do_ld_gpr, a, MO_SB) +TRANS(LDSH, ALL, do_ld_gpr, a, MO_TESW) +TRANS(LDSW, 64, do_ld_gpr, a, MO_TESL) +TRANS(LDX, 64, do_ld_gpr, a, MO_TEUQ) + +static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) +{ + TCGv reg, addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + DisasASI da; + + if (addr == NULL) { + return false; + } + da = resolve_asi(dc, a->asi, mop); + + reg = gen_load_gpr(dc, a->rd); + gen_st_asi0(dc, &da, reg, addr); + return advance_pc(dc); +} + +TRANS(STW, ALL, do_st_gpr, a, MO_TEUL) +TRANS(STB, ALL, do_st_gpr, a, MO_UB) +TRANS(STH, ALL, do_st_gpr, a, MO_TEUW) +TRANS(STX, 64, do_st_gpr, a, MO_TEUQ) + +static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a) +{ + TCGv addr; + DisasASI da; + + if (a->rd & 1) { + return false; + } + addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr == NULL) { + return false; + } + da = resolve_asi(dc, a->asi, MO_TEUQ); + gen_ldda_asi0(dc, &da, addr, a->rd); + return advance_pc(dc); +} + +static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi *a) +{ + TCGv addr; + DisasASI da; + + if (a->rd & 1) { + return false; + } + addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr == NULL) { + return false; + } + da = resolve_asi(dc, a->asi, MO_TEUQ); + gen_stda_asi0(dc, &da, addr, a->rd); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5371,47 +5482,15 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) switch (xop) { case 0x0: /* ld, V9 lduw, load unsigned word */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - break; case 0x1: /* ldub, load unsigned byte */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_UB); - break; case 0x2: /* lduh, load unsigned halfword */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUW | MO_ALIGN); - break; case 0x3: /* ldd, load double word */ - if (rd & 1) - goto illegal_insn; - else { - TCGv_i64 t64; - - gen_address_mask(dc, cpu_addr); - t64 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN); - tcg_gen_trunc_i64_tl(cpu_val, t64); - tcg_gen_ext32u_tl(cpu_val, cpu_val); - gen_store_gpr(dc, rd + 1, cpu_val); - tcg_gen_shri_i64(t64, t64, 32); - tcg_gen_trunc_i64_tl(cpu_val, t64); - tcg_gen_ext32u_tl(cpu_val, cpu_val); - } - break; case 0x9: /* ldsb, load signed byte */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, dc->mem_idx, MO_SB); - break; case 0xa: /* ldsh, load signed halfword */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TESW | MO_ALIGN); - break; + g_assert_not_reached(); /* in decodetree */ + case 0x08: /* V9 ldsw */ + case 0x0b: /* V9 ldx */ + goto illegal_insn; /* in decodetree */ case 0xd: /* ldstub */ gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); break; @@ -5453,16 +5532,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) break; #endif #ifdef TARGET_SPARC64 - case 0x08: /* V9 ldsw */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TESL | MO_ALIGN); - break; - case 0x0b: /* V9 ldx */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_ld_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN); - break; case 0x18: /* V9 ldswa */ gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); break; @@ -5555,38 +5624,18 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || xop == 0xe || xop == 0x1e) { +#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) TCGv cpu_val = gen_load_gpr(dc, rd); +#endif switch (xop) { case 0x4: /* st, store word */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - break; case 0x5: /* stb, store byte */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, dc->mem_idx, MO_UB); - break; case 0x6: /* sth, store halfword */ - gen_address_mask(dc, cpu_addr); - tcg_gen_qemu_st_tl(cpu_val, cpu_addr, - dc->mem_idx, MO_TEUW | MO_ALIGN); - break; case 0x7: /* std, store double word */ - if (rd & 1) - goto illegal_insn; - else { - TCGv_i64 t64; - TCGv lo; - - gen_address_mask(dc, cpu_addr); - lo = gen_load_gpr(dc, rd + 1); - t64 = tcg_temp_new_i64(); - tcg_gen_concat_tl_i64(t64, lo, cpu_val); - tcg_gen_qemu_st_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN); - } - break; + g_assert_not_reached(); /* in decodetree */ + case 0x0e: /* V9 stx */ + goto illegal_insn; /* in decodetree */ #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x14: /* sta, V9 stwa, store word alternate */ gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); @@ -5605,11 +5654,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) break; #endif #ifdef TARGET_SPARC64 - case 0x0e: /* V9 stx */ - gen_address_mask(dc, cpu_addr); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 44/85] target/sparc: Move asi integer load/store to decodetree Date: Fri, 13 Oct 2023 14:28:05 -0700 Message-Id: <20231013212846.165724-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move LDDA, LDSBA, LDSHA, LDSWA, LDUBA, LDUHA, LDUWA, LDXA, STBA, STDA, STHA, STWA, STXA. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 31 +++++++++ target/sparc/translate.c | 128 +++++--------------------------------- 2 files changed, 48 insertions(+), 111 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 41fbda4eb8..fd9e268a0e 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -231,6 +231,9 @@ RETRY 10 00001 111110 00000 0 0000000000000 &r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool @r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi=-1 +@r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0 +@r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ + &r_r_ri_asi imm=1 asi=-2 LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na @@ -247,6 +250,34 @@ STH 11 ..... 000110 ..... . ............. @r_r_ri_na STD 11 ..... 000111 ..... . ............. @r_r_ri_na STX 11 ..... 001110 ..... . ............. @r_r_ri_na +LDUW 11 ..... 010000 ..... . ............. @r_r_r_asi # LDUWA +LDUW 11 ..... 010000 ..... . ............. @r_r_i_asi # LDUWA +LDUB 11 ..... 010001 ..... . ............. @r_r_r_asi # LDUBA +LDUB 11 ..... 010001 ..... . ............. @r_r_i_asi # LDUBA +LDUH 11 ..... 010010 ..... . ............. @r_r_r_asi # LDUHA +LDUH 11 ..... 010010 ..... . ............. @r_r_i_asi # LDUHA +LDD 11 ..... 010011 ..... . ............. @r_r_r_asi # LDDA +LDD 11 ..... 010011 ..... . ............. @r_r_i_asi # LDDA +LDX 11 ..... 011011 ..... . ............. @r_r_r_asi # LDXA +LDX 11 ..... 011011 ..... . ............. @r_r_i_asi # LDXA +LDSB 11 ..... 011001 ..... . ............. @r_r_r_asi # LDSBA +LDSB 11 ..... 011001 ..... . ............. @r_r_i_asi # LDSBA +LDSH 11 ..... 011010 ..... . ............. @r_r_r_asi # LDSHA +LDSH 11 ..... 011010 ..... . ............. @r_r_i_asi # LDSHA +LDSW 11 ..... 011000 ..... . ............. @r_r_r_asi # LDSWA +LDSW 11 ..... 011000 ..... . ............. @r_r_i_asi # LDSWA + +STW 11 ..... 010100 ..... . ............. @r_r_r_asi # STWA +STW 11 ..... 010100 ..... . ............. @r_r_i_asi # STWA +STB 11 ..... 010101 ..... . ............. @r_r_r_asi # STBA +STB 11 ..... 010101 ..... . ............. @r_r_i_asi # STBA +STH 11 ..... 010110 ..... . ............. @r_r_r_asi # STHA +STH 11 ..... 010110 ..... . ............. @r_r_i_asi # STHA +STD 11 ..... 010111 ..... . ............. @r_r_r_asi # STDA +STD 11 ..... 010111 ..... . ............. @r_r_i_asi # STDA +STX 11 ..... 011110 ..... . ............. @r_r_r_asi # STXA +STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 7b7437dbd8..11f885822f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2056,7 +2056,7 @@ static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) return resolve_asi(dc, asi, memop); } -static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) +static void gen_ld_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: @@ -2087,16 +2087,7 @@ static void gen_ld_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) } } -static void __attribute__((unused)) -gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) -{ - DisasASI da = get_asi(dc, insn, memop); - - gen_address_mask(dc, addr); - gen_ld_asi0(dc, &da, dst, addr); -} - -static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr) +static void gen_st_asi(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: @@ -2168,15 +2159,6 @@ static void gen_st_asi0(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr) } } -static void __attribute__((unused)) -gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) -{ - DisasASI da = get_asi(dc, insn, memop); - - gen_address_mask(dc, addr); - gen_st_asi0(dc, &da, src, addr); -} - static void gen_swap_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv src, TCGv addr) { @@ -2478,7 +2460,7 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) } } -static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) +static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi = gen_dest_gpr(dc, rd); TCGv lo = gen_dest_gpr(dc, rd + 1); @@ -2554,16 +2536,7 @@ static void gen_ldda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) gen_store_gpr(dc, rd + 1, lo); } -static void __attribute__((unused)) -gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) -{ - DisasASI da = get_asi(dc, insn, MO_TEUQ); - - gen_address_mask(dc, addr); - gen_ldda_asi0(dc, &da, addr, rd); -} - -static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) +static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi = gen_load_gpr(dc, rd); TCGv lo = gen_load_gpr(dc, rd + 1); @@ -2655,15 +2628,6 @@ static void gen_stda_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) } } -static void __attribute__((unused)) -gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) -{ - DisasASI da = get_asi(dc, insn, MO_TEUQ); - - gen_address_mask(dc, addr); - gen_stda_asi0(dc, &da, addr, rd); -} - static TCGv get_src1(DisasContext *dc, unsigned int insn) { unsigned int rs1 = GET_FIELD(insn, 13, 17); @@ -4592,7 +4556,7 @@ static bool do_ld_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) da = resolve_asi(dc, a->asi, mop); reg = gen_dest_gpr(dc, a->rd); - gen_ld_asi0(dc, &da, reg, addr); + gen_ld_asi(dc, &da, reg, addr); gen_store_gpr(dc, a->rd, reg); return advance_pc(dc); } @@ -4616,7 +4580,7 @@ static bool do_st_gpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) da = resolve_asi(dc, a->asi, mop); reg = gen_load_gpr(dc, a->rd); - gen_st_asi0(dc, &da, reg, addr); + gen_st_asi(dc, &da, reg, addr); return advance_pc(dc); } @@ -4638,7 +4602,7 @@ static bool trans_LDD(DisasContext *dc, arg_r_r_ri_asi *a) return false; } da = resolve_asi(dc, a->asi, MO_TEUQ); - gen_ldda_asi0(dc, &da, addr, a->rd); + gen_ldda_asi(dc, &da, addr, a->rd); return advance_pc(dc); } @@ -4655,7 +4619,7 @@ static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi *a) return false; } da = resolve_asi(dc, a->asi, MO_TEUQ); - gen_stda_asi0(dc, &da, addr, a->rd); + gen_stda_asi(dc, &da, addr, a->rd); return advance_pc(dc); } @@ -5487,9 +5451,17 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x3: /* ldd, load double word */ case 0x9: /* ldsb, load signed byte */ case 0xa: /* ldsh, load signed halfword */ + case 0x10: /* lda, V9 lduwa, load word alternate */ + case 0x11: /* lduba, load unsigned byte alternate */ + case 0x12: /* lduha, load unsigned halfword alternate */ + case 0x13: /* ldda, load double word alternate */ + case 0x19: /* ldsba, load signed byte alternate */ + case 0x1a: /* ldsha, load signed halfword alternate */ g_assert_not_reached(); /* in decodetree */ case 0x08: /* V9 ldsw */ case 0x0b: /* V9 ldx */ + case 0x18: /* V9 ldswa */ + case 0x1b: /* V9 ldxa */ goto illegal_insn; /* in decodetree */ case 0xd: /* ldstub */ gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); @@ -5501,27 +5473,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) dc->mem_idx, MO_TEUL); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - case 0x10: /* lda, V9 lduwa, load word alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); - break; - case 0x11: /* lduba, load unsigned byte alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_UB); - break; - case 0x12: /* lduha, load unsigned halfword alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); - break; - case 0x13: /* ldda, load double word alternate */ - if (rd & 1) { - goto illegal_insn; - } - gen_ldda_asi(dc, cpu_addr, insn, rd); - goto skip_move; - case 0x19: /* ldsba, load signed byte alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_SB); - break; - case 0x1a: /* ldsha, load signed halfword alternate */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESW); - break; case 0x1d: /* ldstuba -- XXX: should be atomically */ gen_ldstub_asi(dc, cpu_val, cpu_addr, insn); break; @@ -5532,12 +5483,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) break; #endif #ifdef TARGET_SPARC64 - case 0x18: /* V9 ldswa */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TESL); - break; - case 0x1b: /* V9 ldxa */ - gen_ld_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); - break; case 0x2d: /* V9 prefetch, no effect */ goto skip_move; case 0x30: /* V9 ldfa */ @@ -5569,7 +5514,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) goto illegal_insn; } gen_store_gpr(dc, rd, cpu_val); -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) +#if defined(TARGET_SPARC64) skip_move: ; #endif } else if (xop >= 0x20 && xop < 0x24) { @@ -5622,45 +5567,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) default: goto illegal_insn; } - } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || - xop == 0xe || xop == 0x1e) { -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - TCGv cpu_val = gen_load_gpr(dc, rd); -#endif - - switch (xop) { - case 0x4: /* st, store word */ - case 0x5: /* stb, store byte */ - case 0x6: /* sth, store halfword */ - case 0x7: /* std, store double word */ - g_assert_not_reached(); /* in decodetree */ - case 0x0e: /* V9 stx */ - goto illegal_insn; /* in decodetree */ -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - case 0x14: /* sta, V9 stwa, store word alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUL); - break; - case 0x15: /* stba, store byte alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_UB); - break; - case 0x16: /* stha, store halfword alternate */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUW); - break; - case 0x17: /* stda, store double word alternate */ - if (rd & 1) { - goto illegal_insn; - } - gen_stda_asi(dc, cpu_val, cpu_addr, insn, rd); - break; -#endif -#ifdef TARGET_SPARC64 - case 0x1e: /* V9 stxa */ - gen_st_asi(dc, cpu_val, cpu_addr, insn, MO_TEUQ); - break; -#endif - default: - goto illegal_insn; - } } else if (xop > 0x23 && xop < 0x28) { if (gen_trap_ifnofpu(dc)) { goto jmp_insn; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 45/85] target/sparc: Move LDSTUB, LDSTUBA to decodetree Date: Fri, 13 Oct 2023 14:28:06 -0700 Message-Id: <20231013212846.165724-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove gen_ldstub_asi. Rename gen_ldstub_asi0 to gen_ldstub_asi. Merge gen_ldstub into gen_ldstub_asi. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 ++++ target/sparc/translate.c | 46 +++++++++++++++++++-------------------- 2 files changed, 26 insertions(+), 24 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index fd9e268a0e..0d3bb3b588 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -278,6 +278,10 @@ STD 11 ..... 010111 ..... . ............. @r_r_i_asi # STDA STX 11 ..... 011110 ..... . ............. @r_r_r_asi # STXA STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA +LDSTUB 11 ..... 001101 ..... . ............. @r_r_ri_na +LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LDSTUBA +LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LDSTUBA + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 11f885822f..052000e4f7 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1800,13 +1800,6 @@ static void gen_swap(DisasContext *dc, TCGv dst, TCGv src, tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN); } -static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx) -{ - TCGv m1 = tcg_constant_tl(0xff); - gen_address_mask(dc, addr); - tcg_gen_atomic_xchg_tl(dst, addr, m1, mmu_idx, MO_UB); -} - /* asi moves */ typedef enum { GET_ASI_HELPER, @@ -2225,13 +2218,14 @@ gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) gen_store_gpr(dc, rd, oldv); } -static void gen_ldstub_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) +static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DIRECT: - gen_ldstub(dc, dst, addr, da->mem_idx); + tcg_gen_atomic_xchg_tl(dst, addr, tcg_constant_tl(0xff), + da->mem_idx, MO_UB); break; default: /* ??? In theory, this should be raise DAE_invalid_asi. @@ -2259,15 +2253,6 @@ static void gen_ldstub_asi0(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) } } -static void __attribute__((unused)) -gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) -{ - DisasASI da = get_asi(dc, insn, MO_UB); - - gen_address_mask(dc, addr); - gen_ldstub_asi0(dc, &da, dst, addr); -} - static void __attribute__((unused)) gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { @@ -4623,6 +4608,23 @@ static bool trans_STD(DisasContext *dc, arg_r_r_ri_asi *a) return advance_pc(dc); } +static bool trans_LDSTUB(DisasContext *dc, arg_r_r_ri_asi *a) +{ + TCGv addr, reg; + DisasASI da; + + addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr == NULL) { + return false; + } + da = resolve_asi(dc, a->asi, MO_UB); + + reg = gen_dest_gpr(dc, a->rd); + gen_ldstub_asi(dc, &da, reg, addr); + gen_store_gpr(dc, a->rd, reg); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5451,21 +5453,20 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x3: /* ldd, load double word */ case 0x9: /* ldsb, load signed byte */ case 0xa: /* ldsh, load signed halfword */ + case 0xd: /* ldstub */ case 0x10: /* lda, V9 lduwa, load word alternate */ case 0x11: /* lduba, load unsigned byte alternate */ case 0x12: /* lduha, load unsigned halfword alternate */ case 0x13: /* ldda, load double word alternate */ case 0x19: /* ldsba, load signed byte alternate */ case 0x1a: /* ldsha, load signed halfword alternate */ + case 0x1d: /* ldstuba */ g_assert_not_reached(); /* in decodetree */ case 0x08: /* V9 ldsw */ case 0x0b: /* V9 ldx */ case 0x18: /* V9 ldswa */ case 0x1b: /* V9 ldxa */ goto illegal_insn; /* in decodetree */ - case 0xd: /* ldstub */ - gen_ldstub(dc, cpu_val, cpu_addr, dc->mem_idx); - break; case 0x0f: /* swap, swap register with memory. Also atomically */ cpu_src1 = gen_load_gpr(dc, rd); @@ -5473,9 +5474,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) dc->mem_idx, MO_TEUL); break; #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - case 0x1d: /* ldstuba -- XXX: should be atomically */ - gen_ldstub_asi(dc, cpu_val, cpu_addr, insn); - break; case 0x1f: /* swapa, swap reg with alt. memory. Also atomically */ cpu_src1 = gen_load_gpr(dc, rd); From patchwork Fri Oct 13 21:28:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733342 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680807wrv; Fri, 13 Oct 2023 14:40:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFpMrnXBPnVEMelYG4NqLPhn6TQOi9f3IvIAUVZ3a3y+ilqAcvE1oOxtI9h6NTv94/wDxDM X-Received: by 2002:a0c:f5d3:0:b0:66d:bd0:bbea with SMTP id q19-20020a0cf5d3000000b0066d0bd0bbeamr7490716qvm.39.1697233224245; Fri, 13 Oct 2023 14:40:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233224; cv=none; d=google.com; s=arc-20160816; b=ovypKVLhYDm3l1OMWhJErZAp6dkeYUoskF2o275lcFphtNMHhNSpfEKvlo7gl6VbUR W6RJJ9+NSpfBdOg4vf3BXiUc+qRNq1HWJFGHkLrf5weE0LE8nTPoe04hMuUNb9U2rVTH U3zalcI4qS2WBhn+jxTZhBLVkUDHnQoVThiO2bYb1jwO0S80bf6Uu7R66bzXq9H8ll4c 2EkD/kGseCwzM7FG1XWCf6CCegNgqSAn9ZIcsKxfFGS7AMbMkXdWUOpr+QWJ7M4Occ9X wxUbq/Lp9eT+i7TotR1AOTSNephVzDUYjR9QYufmAMzuHkiO+65+izJPogcy9/1P/o+H PdhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=o2tZIMoWcJ+ouO8WmQvus2WeYIFRqRhPouWYg0dDoyQ=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=Y10sZwMzJWLQUJKrWJb3TEh/T2tryFGtscHi+VkzM+YEXMV0GnBwMPEnYXXUIFLYJo EjEv+gPNHduIvqRLuZIBeu5BJWSCZhCvkcGMDGPdYLiVWlBf8TfFxnSX1An4wcBdLl8A zd/v8vbpIjpzO/8Br/shrlfb4CCceslseWmD8iIIQoamP8+8X78gbWhVQBz9TtTj0Oca DWSQj72HzDuoxOl93wBG+SO6hFAxVgUnmHGeIHNQljt2ijEROzppAQd1Hvfq2tJUHuKg rNhobnf9hr+AbpIYg7t5qrXx+U8m+dtwRppBQBeVlbdN2hbsFFFmD0CqmsQPEcXHxvnE meyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PcVZr3sa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 46/85] target/sparc: Move SWAP, SWAPA to decodetree Date: Fri, 13 Oct 2023 14:28:07 -0700 Message-Id: <20231013212846.165724-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove gen_swap_asi. Rename gen_swap_asi0 to gen_swap_asi. Merge gen_swap into gen_swap_asi. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 58 +++++++++++++++++---------------------- 2 files changed, 29 insertions(+), 33 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 0d3bb3b588..4f678b4895 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -282,6 +282,10 @@ LDSTUB 11 ..... 001101 ..... . ............. @r_r_ri_na LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LDSTUBA LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LDSTUBA +SWAP 11 ..... 001111 ..... . ............. @r_r_ri_na +SWAP 11 ..... 011111 ..... . ............. @r_r_r_asi # SWAPA +SWAP 11 ..... 011111 ..... . ............. @r_r_i_asi # SWAPA + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 052000e4f7..d640883985 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1793,13 +1793,6 @@ static void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, gen_update_fprs_dirty(dc, QFPREG(rd)); } -static void gen_swap(DisasContext *dc, TCGv dst, TCGv src, - TCGv addr, int mmu_idx, MemOp memop) -{ - gen_address_mask(dc, addr); - tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN); -} - /* asi moves */ typedef enum { GET_ASI_HELPER, @@ -2152,14 +2145,15 @@ static void gen_st_asi(DisasContext *dc, DisasASI *da, TCGv src, TCGv addr) } } -static void gen_swap_asi0(DisasContext *dc, DisasASI *da, - TCGv dst, TCGv src, TCGv addr) +static void gen_swap_asi(DisasContext *dc, DisasASI *da, + TCGv dst, TCGv src, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DIRECT: - gen_swap(dc, dst, src, addr, da->mem_idx, da->memop); + tcg_gen_atomic_xchg_tl(dst, addr, src, + da->mem_idx, da->memop | MO_ALIGN); break; default: /* ??? Should be DAE_invalid_asi. */ @@ -2168,15 +2162,6 @@ static void gen_swap_asi0(DisasContext *dc, DisasASI *da, } } -static void __attribute__((unused)) -gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn) -{ - DisasASI da = get_asi(dc, insn, MO_TEUL); - - gen_address_mask(dc, addr); - gen_swap_asi0(dc, &da, dst, src, addr); -} - static void gen_cas_asi0(DisasContext *dc, DisasASI *da, TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr) { @@ -4625,6 +4610,24 @@ static bool trans_LDSTUB(DisasContext *dc, arg_r_r_ri_asi *a) return advance_pc(dc); } +static bool trans_SWAP(DisasContext *dc, arg_r_r_ri_asi *a) +{ + TCGv addr, dst, src; + DisasASI da; + + addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr == NULL) { + return false; + } + da = resolve_asi(dc, a->asi, MO_TEUL); + + dst = gen_dest_gpr(dc, a->rd); + src = gen_load_gpr(dc, a->rd); + gen_swap_asi(dc, &da, dst, src, addr); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4636,7 +4639,7 @@ static bool trans_LDSTUB(DisasContext *dc, arg_r_r_ri_asi *a) static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) { unsigned int opc, rs1, rs2, rd; - TCGv cpu_src1; + TCGv cpu_src1 __attribute__((unused)); TCGv cpu_src2 __attribute__((unused)); TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; @@ -5454,6 +5457,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x9: /* ldsb, load signed byte */ case 0xa: /* ldsh, load signed halfword */ case 0xd: /* ldstub */ + case 0x0f: /* swap */ case 0x10: /* lda, V9 lduwa, load word alternate */ case 0x11: /* lduba, load unsigned byte alternate */ case 0x12: /* lduha, load unsigned halfword alternate */ @@ -5461,25 +5465,13 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x19: /* ldsba, load signed byte alternate */ case 0x1a: /* ldsha, load signed halfword alternate */ case 0x1d: /* ldstuba */ + case 0x1f: /* swapa */ g_assert_not_reached(); /* in decodetree */ case 0x08: /* V9 ldsw */ case 0x0b: /* V9 ldx */ case 0x18: /* V9 ldswa */ case 0x1b: /* V9 ldxa */ goto illegal_insn; /* in decodetree */ - case 0x0f: - /* swap, swap register with memory. Also atomically */ - cpu_src1 = gen_load_gpr(dc, rd); - gen_swap(dc, cpu_val, cpu_src1, cpu_addr, - dc->mem_idx, MO_TEUL); - break; -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) - case 0x1f: /* swapa, swap reg with alt. memory. Also - atomically */ - cpu_src1 = gen_load_gpr(dc, rd); - gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn); - break; -#endif #ifdef TARGET_SPARC64 case 0x2d: /* V9 prefetch, no effect */ goto skip_move; From patchwork Fri Oct 13 21:28:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733313 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679905wrv; Fri, 13 Oct 2023 14:36:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGsp95WbYnDj5UajZQqdcBZ+lj/kb+MJCIGvJP99Owg1SZfX96XJS3Fi1yKJhk64YX9yZCt X-Received: by 2002:a9d:6c85:0:b0:6c6:19a6:29bf with SMTP id c5-20020a9d6c85000000b006c619a629bfmr31147990otr.7.1697233013189; Fri, 13 Oct 2023 14:36:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233013; cv=none; d=google.com; s=arc-20160816; b=0XRi9BFcTauRWO1Wt3S8+MqslKzdxdlAj9SYS7XhNZl4mAsuSZqFE+xn+kscCuiEnh DLXX0NJkG0dL97FlMdJ2nzOtk/7DCMs1Bsb6aaoyYBFOQKSwvmEgrD6XnYykJPBFDWiv bgrFFAElDGHu75XA8du9Fs1RdByScN7BSmWuf/vpF7/xINH9QOjUV5P8gp9FM38mPhOZ DRSd6wizRO71PcOGf5tohr0oyeizM3WjsL2v6loiclfkNjjlRR3DUzQKMJ2h4yEPJTxh rVQiMepxjaUwzw5w5ea17HnFxwbS6EZVzjsv9yR8dyR+Nm64v46dL3GroXykNCMF1f2u 07Lw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PV4t/VRrhLEceDN9THQ4ugjHJbP6z3ZqwmY3rLJYAvM=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=Ega362qwXTaemj3DIvjlHqT/qDfv1rKmAMZ2/9wIJEGuXnqD0Dju05x6iIIwBulmpu AJV+uKCL70J5yJic74F0EXftjwIzkZr6OLOkVeATgKWm+6Z5yLyepW8I0oH283Ry35ql +npqgPXo7SdMpu4I1OvWDLJtnLSASQ5MAOWotrg8Zj6lfmJEBQ9e5A/K1W89YS3Rwrvu 2uJi3QSOjIUGpRfCHBSR09pS0edE5P3NLldVwcrhWwqCPyyX68OIzH/vGsZ4G7p0hiNl 61Cwt51ugPswDk0vh9UkGi1yNPh7ndG61sBzRAnEDhk4njxsWFQi2fYlF2LV4Us3Fcg1 +AMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i4j7AepH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 47/85] target/sparc: Move CASA, CASXA to decodetree Date: Fri, 13 Oct 2023 14:28:08 -0700 Message-Id: <20231013212846.165724-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove gen_cas_asi, gen_casx_asi. Rename gen_cas_asi0 to gen_cas_asi. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 ++++ target/sparc/translate.c | 71 +++++++++++++++------------------------ 2 files changed, 35 insertions(+), 43 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 4f678b4895..1a641248ce 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -234,6 +234,8 @@ RETRY 10 00001 111110 00000 0 0000000000000 @r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0 @r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ &r_r_ri_asi imm=1 asi=-2 +@casa_imm .. rd:5 ...... rs1:5 1 00000000 rs2_or_imm:5 \ + &r_r_ri_asi imm=1 asi=-2 LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na @@ -286,6 +288,11 @@ SWAP 11 ..... 001111 ..... . ............. @r_r_ri_na SWAP 11 ..... 011111 ..... . ............. @r_r_r_asi # SWAPA SWAP 11 ..... 011111 ..... . ............. @r_r_i_asi # SWAPA +CASA 11 ..... 111100 ..... . ............. @r_r_r_asi +CASA 11 ..... 111100 ..... . ............. @casa_imm +CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi +CASXA 11 ..... 111110 ..... . ............. @casa_imm + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d640883985..beb42b9fb7 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2162,8 +2162,8 @@ static void gen_swap_asi(DisasContext *dc, DisasASI *da, } } -static void gen_cas_asi0(DisasContext *dc, DisasASI *da, - TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr) +static void gen_cas_asi(DisasContext *dc, DisasASI *da, + TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr) { switch (da->type) { case GET_ASI_EXCP: @@ -2179,30 +2179,6 @@ static void gen_cas_asi0(DisasContext *dc, DisasASI *da, } } -static void __attribute__((unused)) -gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) -{ - DisasASI da = get_asi(dc, insn, MO_TEUL); - TCGv oldv = gen_dest_gpr(dc, rd); - TCGv newv = gen_load_gpr(dc, rd); - - gen_address_mask(dc, addr); - gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr); - gen_store_gpr(dc, rd, oldv); -} - -static void __attribute__((unused)) -gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) -{ - DisasASI da = get_asi(dc, insn, MO_TEUQ); - TCGv oldv = gen_dest_gpr(dc, rd); - TCGv newv = gen_load_gpr(dc, rd); - - gen_address_mask(dc, addr); - gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr); - gen_store_gpr(dc, rd, oldv); -} - static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) { switch (da->type) { @@ -2812,6 +2788,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) # define avail_64(C) false #endif #define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17) +#define avail_CASA(C) ((C)->def->features & CPU_FEATURE_CASA) #define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) #define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) #define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN) @@ -4628,6 +4605,28 @@ static bool trans_SWAP(DisasContext *dc, arg_r_r_ri_asi *a) return advance_pc(dc); } +static bool do_casa(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) +{ + TCGv addr, o, n, c; + DisasASI da; + + addr = gen_ldst_addr(dc, a->rs1, true, 0); + if (addr == NULL) { + return false; + } + da = resolve_asi(dc, a->asi, mop); + + o = gen_dest_gpr(dc, a->rd); + n = gen_load_gpr(dc, a->rd); + c = gen_load_gpr(dc, a->rs2_or_imm); + gen_cas_asi(dc, &da, o, n, c, addr); + gen_store_gpr(dc, a->rd, o); + return advance_pc(dc); +} + +TRANS(CASA, CASA, do_casa, a, MO_TEUL) +TRANS(CASXA, 64, do_casa, a, MO_TEUQ) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5431,9 +5430,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv cpu_addr = tcg_temp_new(); tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn)); - if (xop == 0x3c || xop == 0x3e) { - /* V9 casa/casxa : no offset */ - } else if (IS_IMM) { /* immediate */ + if (IS_IMM) { /* immediate */ simm = GET_FIELDs(insn, 19, 31); if (simm != 0) { tcg_gen_addi_tl(cpu_addr, cpu_addr, simm); @@ -5646,22 +5643,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); break; +#endif case 0x3e: /* V9 casxa */ - rs2 = GET_FIELD(insn, 27, 31); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd); - break; -#endif -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) case 0x3c: /* V9 or LEON3 casa */ -#ifndef TARGET_SPARC64 - CHECK_IU_FEATURE(dc, CASA); -#endif - rs2 = GET_FIELD(insn, 27, 31); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd); - break; -#endif + goto illegal_insn; /* in decodetree */ default: goto illegal_insn; } From patchwork Fri Oct 13 21:28:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733340 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680743wrv; Fri, 13 Oct 2023 14:40:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFEw2cE5KF6NOno470zBea70Eh1qWIKpaLF9V5oMUmjhyKe3O15NZtgc6b9UPdPKjE/Z93B X-Received: by 2002:a05:620a:29d2:b0:772:63b3:2423 with SMTP id s18-20020a05620a29d200b0077263b32423mr1601902qkp.0.1697233212212; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 48/85] target/sparc: Move PREFETCH, PREFETCHA to decodetree Date: Fri, 13 Oct 2023 14:28:09 -0700 Message-Id: <20231013212846.165724-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 8 ++++++-- target/sparc/translate.c | 14 ++++++++++---- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1a641248ce..c032b81c16 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -225,6 +225,9 @@ RESTORE 10 ..... 111101 ..... . ............. @r_r_ri DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 +NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 +NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 + ## ## Major Opcode 11 -- load and store instructions ## @@ -293,8 +296,9 @@ CASA 11 ..... 111100 ..... . ............. @casa_imm CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi CASXA 11 ..... 111110 ..... . ............. @casa_imm -NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 -NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 +NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH +NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH +NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA NCP 11 ----- 110000 ----- --------- ----- # v8 LDC NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR diff --git a/target/sparc/translate.c b/target/sparc/translate.c index beb42b9fb7..02030bd99b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4055,6 +4055,14 @@ static bool trans_NOP_v7(DisasContext *dc, arg_NOP_v7 *a) return false; } +static bool trans_NOP_v9(DisasContext *dc, arg_NOP_v9 *a) +{ + if (avail_64(dc)) { + return advance_pc(dc); + } + return false; +} + static bool do_cc_arith(DisasContext *dc, arg_r_r_ri *a, int cc_op, void (*func)(TCGv, TCGv, TCGv), void (*funci)(TCGv, TCGv, target_long)) @@ -5468,10 +5476,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x0b: /* V9 ldx */ case 0x18: /* V9 ldswa */ case 0x1b: /* V9 ldxa */ + case 0x2d: /* V9 prefetch */ + case 0x3d: /* V9 prefetcha */ goto illegal_insn; /* in decodetree */ #ifdef TARGET_SPARC64 - case 0x2d: /* V9 prefetch, no effect */ - goto skip_move; case 0x30: /* V9 ldfa */ if (gen_trap_ifnofpu(dc)) { goto jmp_insn; @@ -5486,8 +5494,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); gen_update_fprs_dirty(dc, DFPREG(rd)); goto skip_move; - case 0x3d: /* V9 prefetcha, no effect */ - goto skip_move; case 0x32: /* V9 ldqfa */ CHECK_FPU_FEATURE(dc, FLOAT128); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 49/85] target/sparc: Split out fp ldst functions with asi precomputed Date: Fri, 13 Oct 2023 14:28:10 -0700 Message-Id: <20231013212846.165724-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Take the operation size from the MemOp instead of a separate parameter. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 136 ++++++++++++++++++++++----------------- 1 file changed, 78 insertions(+), 58 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 02030bd99b..973b864ca0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2214,35 +2214,40 @@ static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) } } -static void __attribute__((unused)) -gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) +static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { - DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ)); + MemOp memop = da->memop; + MemOp size = memop & MO_SIZE; TCGv_i32 d32; TCGv_i64 d64; - switch (da.type) { + /* TODO: Use 128-bit load/store below. */ + if (size == MO_128) { + memop = (memop & ~MO_SIZE) | MO_64; + } + + switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DIRECT: - gen_address_mask(dc, addr); + memop |= MO_ALIGN_4; switch (size) { - case 4: + case MO_32: d32 = gen_dest_fpr_F(dc); - tcg_gen_qemu_ld_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN); + tcg_gen_qemu_ld_i32(d32, addr, da->mem_idx, memop); gen_store_fpr_F(dc, rd, d32); break; - case 8: - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN_4); + + case MO_64: + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop); break; - case 16: + + case MO_128: d64 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(d64, addr, da.mem_idx, da.memop | MO_ALIGN_4); + tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, - da.memop | MO_ALIGN_4); + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, memop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; default: @@ -2252,24 +2257,19 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) case GET_ASI_BLOCK: /* Valid for lddfa on aligned registers only. */ - if (size == 8 && (rd & 7) == 0) { - MemOp memop; + if (size == MO_64 && (rd & 7) == 0) { TCGv eight; int i; - gen_address_mask(dc, addr); - /* The first operation checks required alignment. */ - memop = da.memop | MO_ALIGN_64; eight = tcg_constant_tl(8); for (i = 0; ; ++i) { - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, - da.mem_idx, memop); + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, + memop | (i == 0 ? MO_ALIGN_64 : 0)); if (i == 7) { break; } tcg_gen_add_tl(addr, addr, eight); - memop = da.memop; } } else { gen_exception(dc, TT_ILL_INSN); @@ -2278,10 +2278,9 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) case GET_ASI_SHORT: /* Valid for lddfa only. */ - if (size == 8) { - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN); + if (size == MO_64) { + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2289,8 +2288,8 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) default: { - TCGv_i32 r_asi = tcg_constant_i32(da.asi); - TCGv_i32 r_mop = tcg_constant_i32(da.memop | MO_ALIGN); + TCGv_i32 r_asi = tcg_constant_i32(da->asi); + TCGv_i32 r_mop = tcg_constant_i32(memop | MO_ALIGN); save_state(dc); /* According to the table in the UA2011 manual, the only @@ -2298,21 +2297,23 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) the NO_FAULT asis. We still need a helper for these, but we can just use the integer asi helper for them. */ switch (size) { - case 4: + case MO_32: d64 = tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); d32 = gen_dest_fpr_F(dc); tcg_gen_extrl_i64_i32(d32, d64); gen_store_fpr_F(dc, rd, d32); break; - case 8: - gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, r_asi, r_mop); + case MO_64: + gen_helper_ld_asi(cpu_fpr[rd / 2], tcg_env, addr, + r_asi, r_mop); break; - case 16: + case MO_128: d64 = tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); tcg_gen_addi_tl(addr, addr, 8); - gen_helper_ld_asi(cpu_fpr[rd/2+1], tcg_env, addr, r_asi, r_mop); + gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr, + r_asi, r_mop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; default: @@ -2324,36 +2325,51 @@ gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) } static void __attribute__((unused)) -gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) +gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { - DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ)); + DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : + size == 8 ? MO_TEUQ : MO_TE | MO_128)); + + gen_address_mask(dc, addr); + gen_ldf_asi0(dc, &da, addr, rd); +} + +static void gen_stf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) +{ + MemOp memop = da->memop; + MemOp size = memop & MO_SIZE; TCGv_i32 d32; - switch (da.type) { + /* TODO: Use 128-bit load/store below. */ + if (size == MO_128) { + memop = (memop & ~MO_SIZE) | MO_64; + } + + switch (da->type) { case GET_ASI_EXCP: break; case GET_ASI_DIRECT: - gen_address_mask(dc, addr); + memop |= MO_ALIGN_4; switch (size) { - case 4: + case MO_32: d32 = gen_load_fpr_F(dc, rd); - tcg_gen_qemu_st_i32(d32, addr, da.mem_idx, da.memop | MO_ALIGN); + tcg_gen_qemu_st_i32(d32, addr, da->mem_idx, memop | MO_ALIGN); break; - case 8: - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN_4); + case MO_64: + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN_4); break; - case 16: + case MO_128: /* Only 4-byte alignment required. However, it is legal for the cpu to signal the alignment fault, and the OS trap handler is required to fix it up. Requiring 16-byte alignment here avoids having to probe the second page before performing the first write. */ - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN_16); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_i64(cpu_fpr[rd/2+1], addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, memop); break; default: g_assert_not_reached(); @@ -2362,24 +2378,19 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) case GET_ASI_BLOCK: /* Valid for stdfa on aligned registers only. */ - if (size == 8 && (rd & 7) == 0) { - MemOp memop; + if (size == MO_64 && (rd & 7) == 0) { TCGv eight; int i; - gen_address_mask(dc, addr); - /* The first operation checks required alignment. */ - memop = da.memop | MO_ALIGN_64; eight = tcg_constant_tl(8); for (i = 0; ; ++i) { - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, - da.mem_idx, memop); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, + memop | (i == 0 ? MO_ALIGN_64 : 0)); if (i == 7) { break; } tcg_gen_add_tl(addr, addr, eight); - memop = da.memop; } } else { gen_exception(dc, TT_ILL_INSN); @@ -2388,10 +2399,9 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) case GET_ASI_SHORT: /* Valid for stdfa only. */ - if (size == 8) { - gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da.mem_idx, - da.memop | MO_ALIGN); + if (size == MO_64) { + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, + memop | MO_ALIGN); } else { gen_exception(dc, TT_ILL_INSN); } @@ -2406,6 +2416,16 @@ gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) } } +static void __attribute__((unused)) +gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) +{ + DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : + size == 8 ? MO_TEUQ : MO_TE | MO_128)); + + gen_address_mask(dc, addr); + gen_stf_asi0(dc, &da, addr, rd); +} + static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi = gen_dest_gpr(dc, rd); From patchwork Fri Oct 13 21:28:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733312 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679844wrv; Fri, 13 Oct 2023 14:36:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGb7yW6BD6o2c5Z37BC3g0rZkuTx0qky7OLe0FxV+ZPH73TY3DPqKN3l9OJrsKibADq8IM+ X-Received: by 2002:ae9:c103:0:b0:774:108a:b537 with SMTP id z3-20020ae9c103000000b00774108ab537mr25249713qki.42.1697233001678; Fri, 13 Oct 2023 14:36:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233001; cv=none; d=google.com; s=arc-20160816; b=S2zWuXF1p+IzRW8bhnCv12XHDOLV72+fNwPi59Sx+AfTi4Ucyi652noSxgukeKh9oq wqrElVfyAWRHv8JKNjFosOFQzg/tGxRHZRIhEXCvbF+N/L/0MOD7mfZISjMg7LwTde1G GL7OzO6rmaLVrGRpxVoYCbCalGHk/bJwhT/PTfGVUbtmp+A025/LiF5LT7Mg0vja4ZwI HvSY9orY0xCDNfp1fgC2HthGFagKyB2Dk2iNLE+jEjBUZWSSO2SdgP2wMd0M8sv27AEz Sc9IwPSQmpHHbKt6uPQi2iNkErmJdnA6GY8xmXLRH4+5bFdyVmDFKmsVh7GWdNzdByun usKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0RzAz50THQD1iZE/JylX1mkUWArqn49qgYZr3wJzfSM=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=eI8ZapRR8emSPEBKrTuC+ioTOcrOzGPBrE7uYQz0X7iEph0joqs/BMRN5zbav6mLgG xJjKyc67T3rXWMB1sWn5GKEmfVjwtGtG+5o8I2XqyfeKCDnmuIMUBHENhMy7IlU9Foj0 lzQ0M/WrOXaMt4B4TRfvNSVGWBL24BWrISI2zvGrNOYZPTPXB97hkiLvNRPn5TNCZhUV 7ZQaHBToJDdHtmUP2selZnUqfEj3Gsmhc+kvtQRGzNyHGEwuqQrTA/47Qlm7uK5HiqZW CPIWFCtSNLI66qAOSQZeOYSsmJAyHY9BCCPdsCZBHvadX419txDcRSzxiKb71wi3+V1U ERng== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Mv/d2K5h"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 50/85] target/sparc: Move simple fp load/store to decodetree Date: Fri, 13 Oct 2023 14:28:11 -0700 Message-Id: <20231013212846.165724-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 19 ++++ target/sparc/translate.c | 194 ++++++++++++++++++-------------------- 2 files changed, 113 insertions(+), 100 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index c032b81c16..00ddc7a93b 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -232,8 +232,16 @@ NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 ## Major Opcode 11 -- load and store instructions ## +%dfp_rd 25:5 !function=extract_dfpreg +%qfp_rd 25:5 !function=extract_qfpreg + &r_r_ri_asi rd rs1 rs2_or_imm asi imm:bool @r_r_ri_na .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri_asi asi=-1 +@d_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \ + &r_r_ri_asi rd=%dfp_rd asi=-1 +@q_r_ri_na .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 \ + &r_r_ri_asi rd=%qfp_rd asi=-1 + @r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0 @r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ &r_r_ri_asi imm=1 asi=-2 @@ -283,6 +291,17 @@ STD 11 ..... 010111 ..... . ............. @r_r_i_asi # STDA STX 11 ..... 011110 ..... . ............. @r_r_r_asi # STXA STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA +LDF 11 ..... 100000 ..... . ............. @r_r_ri_na +LDQF 11 ..... 100010 ..... . ............. @q_r_ri_na +LDDF 11 ..... 100011 ..... . ............. @d_r_ri_na + +STF 11 ..... 100100 ..... . ............. @r_r_ri_na +{ + STQF 11 ..... 100110 ..... . ............. @q_r_ri_na + STDFQ 11 ----- 100110 ----- - ------------- +} +STDF 11 ..... 100111 ..... . ............. @d_r_ri_na + LDSTUB 11 ..... 001101 ..... . ............. @r_r_ri_na LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LDSTUBA LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LDSTUBA diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 973b864ca0..abf6c7fc32 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -243,29 +243,7 @@ static void gen_op_store_QT0_fpr(unsigned int dst) offsetof(CPU_QuadU, ll.lower)); } -static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, - TCGv_i64 v1, TCGv_i64 v2) -{ - dst = QFPREG(dst); - - tcg_gen_mov_i64(cpu_fpr[dst / 2], v1); - tcg_gen_mov_i64(cpu_fpr[dst / 2 + 1], v2); - gen_update_fprs_dirty(dc, dst); -} - #ifdef TARGET_SPARC64 -static TCGv_i64 gen_load_fpr_Q0(DisasContext *dc, unsigned int src) -{ - src = QFPREG(src); - return cpu_fpr[src / 2]; -} - -static TCGv_i64 gen_load_fpr_Q1(DisasContext *dc, unsigned int src) -{ - src = QFPREG(src); - return cpu_fpr[src / 2 + 1]; -} - static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) { rd = QFPREG(rd); @@ -2792,6 +2770,16 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) } #endif +static int extract_dfpreg(DisasContext *dc, int x) +{ + return DFPREG(x); +} + +static int extract_qfpreg(DisasContext *dc, int x) +{ + return QFPREG(x); +} + /* Include the auto-generated decoder. */ #include "decode-insns.c.inc" @@ -2918,6 +2906,20 @@ static bool raise_priv(DisasContext *dc) return true; } +static bool raise_unimpfpop(DisasContext *dc) +{ + gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); + return true; +} + +static bool gen_trap_float128(DisasContext *dc) +{ + if (dc->def->features & CPU_FEATURE_FLOAT128) { + return false; + } + return raise_unimpfpop(dc); +} + static bool do_bpcc(DisasContext *dc, arg_bcc *a) { target_long target = dc->pc + a->i * 4; @@ -4655,6 +4657,68 @@ static bool do_casa(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) TRANS(CASA, CASA, do_casa, a, MO_TEUL) TRANS(CASXA, 64, do_casa, a, MO_TEUQ) +static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) +{ + TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + DisasASI da; + + if (addr == NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + if ((mop & MO_SIZE) == MO_128 && gen_trap_float128(dc)) { + return true; + } + da = resolve_asi(dc, a->asi, mop); + gen_ldf_asi0(dc, &da, addr, a->rd); + gen_update_fprs_dirty(dc, a->rd); + return advance_pc(dc); +} + +TRANS(LDF, ALL, do_ld_fpr, a, MO_TEUL) +TRANS(LDDF, ALL, do_ld_fpr, a, MO_TEUQ) +TRANS(LDQF, ALL, do_ld_fpr, a, MO_TE | MO_128) + +static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) +{ + TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + DisasASI da; + + if (addr == NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + if ((mop & MO_SIZE) == MO_128 && gen_trap_float128(dc)) { + return true; + } + da = resolve_asi(dc, a->asi, mop); + gen_stf_asi0(dc, &da, addr, a->rd); + return advance_pc(dc); +} + +TRANS(STF, ALL, do_st_fpr, a, MO_TEUL) +TRANS(STDF, ALL, do_st_fpr, a, MO_TEUQ) +TRANS(STQF, ALL, do_st_fpr, a, MO_TE | MO_128) + +static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a) +{ + if (!avail_32(dc)) { + return false; + } + if (!supervisor(dc)) { + return raise_priv(dc); + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); + return true; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4669,7 +4733,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv cpu_src1 __attribute__((unused)); TCGv cpu_src2 __attribute__((unused)); TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; - TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; + TCGv_i64 cpu_src1_64, cpu_src2_64; + TCGv_i64 cpu_dst_64 __attribute__((unused)); target_long simm; opc = GET_FIELD(insn, 0, 1); @@ -5536,12 +5601,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } switch (xop) { case 0x20: /* ldf, load fpreg */ - gen_address_mask(dc, cpu_addr); - cpu_dst_32 = gen_dest_fpr_F(dc); - tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - gen_store_fpr_F(dc, rd, cpu_dst_32); - break; + case 0x22: /* ldqf, load quad fpreg */ + case 0x23: /* lddf, load double fpreg */ + g_assert_not_reached(); /* in decodetree */ case 0x21: /* ldfsr, V9 ldxfsr */ #ifdef TARGET_SPARC64 gen_address_mask(dc, cpu_addr); @@ -5558,25 +5620,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) dc->mem_idx, MO_TEUL | MO_ALIGN); gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, cpu_dst_32); break; - case 0x22: /* ldqf, load quad fpreg */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_address_mask(dc, cpu_addr); - cpu_src1_64 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(cpu_src1_64, cpu_addr, dc->mem_idx, - MO_TEUQ | MO_ALIGN_4); - tcg_gen_addi_tl(cpu_addr, cpu_addr, 8); - cpu_src2_64 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(cpu_src2_64, cpu_addr, dc->mem_idx, - MO_TEUQ | MO_ALIGN_4); - gen_store_fpr_Q(dc, rd, cpu_src1_64, cpu_src2_64); - break; - case 0x23: /* lddf, load double fpreg */ - gen_address_mask(dc, cpu_addr); - cpu_dst_64 = gen_dest_fpr_D(dc, rd); - tcg_gen_qemu_ld_i64(cpu_dst_64, cpu_addr, dc->mem_idx, - MO_TEUQ | MO_ALIGN_4); - gen_store_fpr_D(dc, rd, cpu_dst_64); - break; default: goto illegal_insn; } @@ -5586,11 +5629,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } switch (xop) { case 0x24: /* stf, store fpreg */ - gen_address_mask(dc, cpu_addr); - cpu_src1_32 = gen_load_fpr_F(dc, rd); - tcg_gen_qemu_st_i32(cpu_src1_32, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - break; + case 0x26: /* v9 stqf, v8 stdfq */ + case 0x27: /* stdf, store double fpreg */ + g_assert_not_reached(); case 0x25: /* stfsr, V9 stxfsr */ { #ifdef TARGET_SPARC64 @@ -5605,43 +5646,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) dc->mem_idx, MO_TEUL | MO_ALIGN); } break; - case 0x26: -#ifdef TARGET_SPARC64 - /* V9 stqf, store quad fpreg */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_address_mask(dc, cpu_addr); - /* ??? While stqf only requires 4-byte alignment, it is - legal for the cpu to signal the unaligned exception. - The OS trap handler is then required to fix it up. - For qemu, this avoids having to probe the second page - before performing the first write. */ - cpu_src1_64 = gen_load_fpr_Q0(dc, rd); - tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN_16); - tcg_gen_addi_tl(cpu_addr, cpu_addr, 8); - cpu_src2_64 = gen_load_fpr_Q1(dc, rd); - tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, - dc->mem_idx, MO_TEUQ); - break; -#else /* !TARGET_SPARC64 */ - /* stdfq, store floating point queue */ -#if defined(CONFIG_USER_ONLY) - goto illegal_insn; -#else - if (!supervisor(dc)) - goto priv_insn; - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - goto nfq_insn; -#endif -#endif - case 0x27: /* stdf, store double fpreg */ - gen_address_mask(dc, cpu_addr); - cpu_src1_64 = gen_load_fpr_D(dc, rd); - tcg_gen_qemu_st_i64(cpu_src1_64, cpu_addr, dc->mem_idx, - MO_TEUQ | MO_ALIGN_4); - break; default: goto illegal_insn; } @@ -5688,19 +5692,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) illegal_insn: gen_exception(dc, TT_ILL_INSN); return; -#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) - priv_insn: - gen_exception(dc, TT_PRIV_INSN); - return; -#endif nfpu_insn: gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); return; -#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) - nfq_insn: - gen_op_fpexception_im(dc, FSR_FTT_SEQ_ERROR); - return; -#endif } static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) From patchwork Fri Oct 13 21:28:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733316 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679948wrv; Fri, 13 Oct 2023 14:37:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGloPiM0UzSHROh0He3Fn4w7f1yY19+NJ6TBmFRlgJ4cRCGB1JR3UXoc7RCkXIgWs/bR8DM X-Received: by 2002:a05:620a:2547:b0:765:aa35:f03f with SMTP id s7-20020a05620a254700b00765aa35f03fmr29789014qko.37.1697233022005; Fri, 13 Oct 2023 14:37:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233021; cv=none; d=google.com; s=arc-20160816; b=Knk3fk6LOI/A4VUFlWKgs7jrOxTdKitutTnRWrJJCoSUr0dxSInXk9BDQLSMwfMXRW d3LYGv5cIq0L4OGV6X/biFoX1lxudYDiBEZSeP8HQjCr/uvSkr1gefGHmt8EcoBMVhhR Y3s4Nm2rVLkGXLkeVgh4w0EnnXCSPk3ArEw84/FbgMBntCfozymfpIfDCVxrE6mFj9wN +MVNtvvbRf3qgLOD5ef8wkBR0DKiY0pf2mn4Zu3hivTC1932t9Ucd4D1V+/4q29inqNk jlL1qnBa3uurq3/2wRKmpcA8CgFKTZ50myhzHmLkcs47/2SZ5cin4zP9b3IKDbcpYS2Y xY5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8+NgySZzPFDTGs1XP+LEiHgXbVzLT4/zRq+iTuScaFk=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=FULAMIYt9Fw3J+UeWWHGVlBfJyzmPNug1igr0KhhPWmTKL8m5FfCYEK71hvFmJqk+O yZUoaqZQoUN86+bJHfqCY6pCBAylr+2kv9j6iCDvwMgh2gFeT7o4ao09gvI7xy7P23W2 vCdT/rPnq+dIayXmblvAn05mvjF2OHIjb3GQCmqAGc06LQ5YOQ9uYY9j48ZDQTfOoKwy cF1dkxUupthyxUrMuw+yRZJ1aOKWE9W0ZxMxsrXuuxym/HpCR6kw70Ffrj2MKxSk4tXO 9Gqq9RBvOTPWKcKKu3zBijF8orrDKW8L1m+ywz3402u8ks5Bfr4+VmryNM4hh7VolqiE T1Nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I1El1tx+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 51/85] target/sparc: Move asi fp load/store to decodetree Date: Fri, 13 Oct 2023 14:28:12 -0700 Message-Id: <20231013212846.165724-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 51 ++++++++++-- target/sparc/translate.c | 169 ++++++++------------------------------ 2 files changed, 79 insertions(+), 141 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 00ddc7a93b..b354bb97c4 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -245,6 +245,14 @@ NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 @r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0 @r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \ &r_r_ri_asi imm=1 asi=-2 +@d_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \ + &r_r_ri_asi rd=%dfp_rd imm=0 +@d_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \ + &r_r_ri_asi rd=%dfp_rd imm=1 asi=-2 +@q_r_r_asi .. ..... ...... rs1:5 0 asi:8 rs2_or_imm:5 \ + &r_r_ri_asi rd=%qfp_rd imm=0 +@q_r_i_asi .. ..... ...... rs1:5 1 rs2_or_imm:s13 \ + &r_r_ri_asi rd=%qfp_rd imm=1 asi=-2 @casa_imm .. rd:5 ...... rs1:5 1 00000000 rs2_or_imm:5 \ &r_r_ri_asi imm=1 asi=-2 @@ -319,10 +327,43 @@ NOP_v9 11 ----- 101101 ----- 0 00000000 ----- # PREFETCH NOP_v9 11 ----- 101101 ----- 1 ------------- # PREFETCH NOP_v9 11 ----- 111101 ----- - ------------- # PREFETCHA -NCP 11 ----- 110000 ----- --------- ----- # v8 LDC +{ + [ + LDFA 11 ..... 110000 ..... . ............. @r_r_r_asi + LDFA 11 ..... 110000 ..... . ............. @r_r_i_asi + ] + NCP 11 ----- 110000 ----- --------- ----- # v8 LDC +} NCP 11 ----- 110001 ----- --------- ----- # v8 LDCSR -NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC -NCP 11 ----- 110100 ----- --------- ----- # v8 STC +LDQFA 11 ..... 110010 ..... . ............. @q_r_r_asi +LDQFA 11 ..... 110010 ..... . ............. @q_r_i_asi +{ + [ + LDDFA 11 ..... 110011 ..... . ............. @d_r_r_asi + LDDFA 11 ..... 110011 ..... . ............. @d_r_i_asi + ] + NCP 11 ----- 110011 ----- --------- ----- # v8 LDDC +} + +{ + [ + STFA 11 ..... 110100 ..... . ............. @r_r_r_asi + STFA 11 ..... 110100 ..... . ............. @r_r_i_asi + ] + NCP 11 ----- 110100 ----- --------- ----- # v8 STC +} NCP 11 ----- 110101 ----- --------- ----- # v8 STCSR -NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ -NCP 11 ----- 110111 ----- --------- ----- # v8 STDC +{ + [ + STQFA 11 ..... 110110 ..... . ............. @q_r_r_asi + STQFA 11 ..... 110110 ..... . ............. @q_r_i_asi + ] + NCP 11 ----- 110110 ----- --------- ----- # v8 STDCQ +} +{ + [ + STDFA 11 ..... 110111 ..... . ............. @d_r_r_asi + STDFA 11 ..... 110111 ..... . ............. @d_r_i_asi + ] + NCP 11 ----- 110111 ----- --------- ----- # v8 STDC +} diff --git a/target/sparc/translate.c b/target/sparc/translate.c index abf6c7fc32..f53b45aa38 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2014,12 +2014,6 @@ static DisasASI resolve_asi(DisasContext *dc, int asi, MemOp memop) return (DisasASI){ type, asi, mem_idx, memop }; } -static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) -{ - int asi = IS_IMM ? -2 : GET_FIELD(insn, 19, 26); - return resolve_asi(dc, asi, memop); -} - static void gen_ld_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) { switch (da->type) { @@ -2192,12 +2186,13 @@ static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr) } } -static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) +static void gen_ldf_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { MemOp memop = da->memop; MemOp size = memop & MO_SIZE; TCGv_i32 d32; TCGv_i64 d64; + TCGv addr_tmp; /* TODO: Use 128-bit load/store below. */ if (size == MO_128) { @@ -2224,8 +2219,9 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) case MO_128: d64 = tcg_temp_new_i64(); tcg_gen_qemu_ld_i64(d64, addr, da->mem_idx, memop); - tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, memop); + addr_tmp = tcg_temp_new(); + tcg_gen_addi_tl(addr_tmp, addr, 8); + tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx, memop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; default: @@ -2236,18 +2232,16 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) case GET_ASI_BLOCK: /* Valid for lddfa on aligned registers only. */ if (size == MO_64 && (rd & 7) == 0) { - TCGv eight; - int i; - /* The first operation checks required alignment. */ - eight = tcg_constant_tl(8); - for (i = 0; ; ++i) { + addr_tmp = tcg_temp_new(); + for (int i = 0; ; ++i) { tcg_gen_qemu_ld_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, memop | (i == 0 ? MO_ALIGN_64 : 0)); if (i == 7) { break; } - tcg_gen_add_tl(addr, addr, eight); + tcg_gen_addi_tl(addr_tmp, addr, 8); + addr = addr_tmp; } } else { gen_exception(dc, TT_ILL_INSN); @@ -2289,8 +2283,9 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) case MO_128: d64 = tcg_temp_new_i64(); gen_helper_ld_asi(d64, tcg_env, addr, r_asi, r_mop); - tcg_gen_addi_tl(addr, addr, 8); - gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr, + addr_tmp = tcg_temp_new(); + tcg_gen_addi_tl(addr_tmp, addr, 8); + gen_helper_ld_asi(cpu_fpr[rd / 2 + 1], tcg_env, addr_tmp, r_asi, r_mop); tcg_gen_mov_i64(cpu_fpr[rd / 2], d64); break; @@ -2302,21 +2297,12 @@ static void gen_ldf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) } } -static void __attribute__((unused)) -gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) -{ - DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : - size == 8 ? MO_TEUQ : MO_TE | MO_128)); - - gen_address_mask(dc, addr); - gen_ldf_asi0(dc, &da, addr, rd); -} - -static void gen_stf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) +static void gen_stf_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { MemOp memop = da->memop; MemOp size = memop & MO_SIZE; TCGv_i32 d32; + TCGv addr_tmp; /* TODO: Use 128-bit load/store below. */ if (size == MO_128) { @@ -2346,8 +2332,9 @@ static void gen_stf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) write. */ tcg_gen_qemu_st_i64(cpu_fpr[rd / 2], addr, da->mem_idx, memop | MO_ALIGN_16); - tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr, da->mem_idx, memop); + addr_tmp = tcg_temp_new(); + tcg_gen_addi_tl(addr_tmp, addr, 8); + tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + 1], addr_tmp, da->mem_idx, memop); break; default: g_assert_not_reached(); @@ -2357,18 +2344,16 @@ static void gen_stf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) case GET_ASI_BLOCK: /* Valid for stdfa on aligned registers only. */ if (size == MO_64 && (rd & 7) == 0) { - TCGv eight; - int i; - /* The first operation checks required alignment. */ - eight = tcg_constant_tl(8); - for (i = 0; ; ++i) { + addr_tmp = tcg_temp_new(); + for (int i = 0; ; ++i) { tcg_gen_qemu_st_i64(cpu_fpr[rd / 2 + i], addr, da->mem_idx, memop | (i == 0 ? MO_ALIGN_64 : 0)); if (i == 7) { break; } - tcg_gen_add_tl(addr, addr, eight); + tcg_gen_addi_tl(addr_tmp, addr, 8); + addr = addr_tmp; } } else { gen_exception(dc, TT_ILL_INSN); @@ -2394,16 +2379,6 @@ static void gen_stf_asi0(DisasContext *dc, DisasASI *da, TCGv addr, int rd) } } -static void __attribute__((unused)) -gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) -{ - DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : - size == 8 ? MO_TEUQ : MO_TE | MO_128)); - - gen_address_mask(dc, addr); - gen_stf_asi0(dc, &da, addr, rd); -} - static void gen_ldda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) { TCGv hi = gen_dest_gpr(dc, rd); @@ -4672,7 +4647,7 @@ static bool do_ld_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) return true; } da = resolve_asi(dc, a->asi, mop); - gen_ldf_asi0(dc, &da, addr, a->rd); + gen_ldf_asi(dc, &da, addr, a->rd); gen_update_fprs_dirty(dc, a->rd); return advance_pc(dc); } @@ -4681,6 +4656,10 @@ TRANS(LDF, ALL, do_ld_fpr, a, MO_TEUL) TRANS(LDDF, ALL, do_ld_fpr, a, MO_TEUQ) TRANS(LDQF, ALL, do_ld_fpr, a, MO_TE | MO_128) +TRANS(LDFA, 64, do_ld_fpr, a, MO_TEUL) +TRANS(LDDFA, 64, do_ld_fpr, a, MO_TEUQ) +TRANS(LDQFA, 64, do_ld_fpr, a, MO_TE | MO_128) + static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) { TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); @@ -4696,7 +4675,7 @@ static bool do_st_fpr(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop) return true; } da = resolve_asi(dc, a->asi, mop); - gen_stf_asi0(dc, &da, addr, a->rd); + gen_stf_asi(dc, &da, addr, a->rd); return advance_pc(dc); } @@ -4704,6 +4683,10 @@ TRANS(STF, ALL, do_st_fpr, a, MO_TEUL) TRANS(STDF, ALL, do_st_fpr, a, MO_TEUQ) TRANS(STQF, ALL, do_st_fpr, a, MO_TE | MO_128) +TRANS(STFA, 64, do_st_fpr, a, MO_TEUL) +TRANS(STDFA, 64, do_st_fpr, a, MO_TEUQ) +TRANS(STQFA, 64, do_st_fpr, a, MO_TE | MO_128) + static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a) { if (!avail_32(dc)) { @@ -5537,64 +5520,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || (xop > 0x17 && xop <= 0x1d ) || (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { - TCGv cpu_val = gen_dest_gpr(dc, rd); - - switch (xop) { - case 0x0: /* ld, V9 lduw, load unsigned word */ - case 0x1: /* ldub, load unsigned byte */ - case 0x2: /* lduh, load unsigned halfword */ - case 0x3: /* ldd, load double word */ - case 0x9: /* ldsb, load signed byte */ - case 0xa: /* ldsh, load signed halfword */ - case 0xd: /* ldstub */ - case 0x0f: /* swap */ - case 0x10: /* lda, V9 lduwa, load word alternate */ - case 0x11: /* lduba, load unsigned byte alternate */ - case 0x12: /* lduha, load unsigned halfword alternate */ - case 0x13: /* ldda, load double word alternate */ - case 0x19: /* ldsba, load signed byte alternate */ - case 0x1a: /* ldsha, load signed halfword alternate */ - case 0x1d: /* ldstuba */ - case 0x1f: /* swapa */ - g_assert_not_reached(); /* in decodetree */ - case 0x08: /* V9 ldsw */ - case 0x0b: /* V9 ldx */ - case 0x18: /* V9 ldswa */ - case 0x1b: /* V9 ldxa */ - case 0x2d: /* V9 prefetch */ - case 0x3d: /* V9 prefetcha */ - goto illegal_insn; /* in decodetree */ -#ifdef TARGET_SPARC64 - case 0x30: /* V9 ldfa */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_ldf_asi(dc, cpu_addr, insn, 4, rd); - gen_update_fprs_dirty(dc, rd); - goto skip_move; - case 0x33: /* V9 lddfa */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_ldf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); - gen_update_fprs_dirty(dc, DFPREG(rd)); - goto skip_move; - case 0x32: /* V9 ldqfa */ - CHECK_FPU_FEATURE(dc, FLOAT128); - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_ldf_asi(dc, cpu_addr, insn, 16, QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); - goto skip_move; -#endif - default: - goto illegal_insn; - } - gen_store_gpr(dc, rd, cpu_val); -#if defined(TARGET_SPARC64) - skip_move: ; -#endif + goto illegal_insn; /* in decodetree */ } else if (xop >= 0x20 && xop < 0x24) { if (gen_trap_ifnofpu(dc)) { goto jmp_insn; @@ -5650,36 +5576,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) goto illegal_insn; } } else if (xop > 0x33 && xop < 0x3f) { - switch (xop) { -#ifdef TARGET_SPARC64 - case 0x34: /* V9 stfa */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_stf_asi(dc, cpu_addr, insn, 4, rd); - break; - case 0x36: /* V9 stqfa */ - { - CHECK_FPU_FEATURE(dc, FLOAT128); - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_stf_asi(dc, cpu_addr, insn, 16, QFPREG(rd)); - } - break; - case 0x37: /* V9 stdfa */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd)); - break; -#endif - case 0x3e: /* V9 casxa */ - case 0x3c: /* V9 or LEON3 casa */ - goto illegal_insn; /* in decodetree */ - default: - goto illegal_insn; - } + goto illegal_insn; /* in decodetree */ } else { goto illegal_insn; } From patchwork Fri Oct 13 21:28:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733300 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679336wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 52/85] target/sparc: Move LDFSR, STFSR to decodetree Date: Fri, 13 Oct 2023 14:28:13 -0700 Message-Id: <20231013212846.165724-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 + target/sparc/translate.c | 152 +++++++++++++++----------------------- 2 files changed, 64 insertions(+), 92 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index b354bb97c4..185bcadab7 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -300,10 +300,14 @@ STX 11 ..... 011110 ..... . ............. @r_r_r_asi # STXA STX 11 ..... 011110 ..... . ............. @r_r_i_asi # STXA LDF 11 ..... 100000 ..... . ............. @r_r_ri_na +LDFSR 11 00000 100001 ..... . ............. @n_r_ri +LDXFSR 11 00001 100001 ..... . ............. @n_r_ri LDQF 11 ..... 100010 ..... . ............. @q_r_ri_na LDDF 11 ..... 100011 ..... . ............. @d_r_ri_na STF 11 ..... 100100 ..... . ............. @r_r_ri_na +STFSR 11 00000 100101 ..... . ............. @n_r_ri +STXFSR 11 00001 100101 ..... . ............. @n_r_ri { STQF 11 ..... 100110 ..... . ............. @q_r_ri_na STDFQ 11 ----- 100110 ----- - ------------- diff --git a/target/sparc/translate.c b/target/sparc/translate.c index f53b45aa38..9384815f0b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -58,6 +58,7 @@ #define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() #define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() +#define gen_helper_ldxfsr(R, E, X, Y) qemu_build_not_reached() # ifdef CONFIG_USER_ONLY static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a, TCGv_i32 asi, TCGv_i32 mop) @@ -153,12 +154,6 @@ typedef struct { #define UA2005_HTRAP_MASK 0xff #define V8_TRAP_MASK 0x7f -static int sign_extend(int x, int len) -{ - len = 32 - len; - return (x << len) >> len; -} - #define IS_IMM (insn & (1<<13)) static void gen_update_fprs_dirty(DisasContext *dc, int rd) @@ -2547,13 +2542,13 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) } } +#ifdef TARGET_SPARC64 static TCGv get_src1(DisasContext *dc, unsigned int insn) { unsigned int rs1 = GET_FIELD(insn, 13, 17); return gen_load_gpr(dc, rs1); } -#ifdef TARGET_SPARC64 static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { TCGv_i32 c32, zero, dst, s1, s2; @@ -4702,6 +4697,61 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a) return true; } +static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv addr; + TCGv_i32 tmp; + + addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr == NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + tmp = tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN); + gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, tmp); + return advance_pc(dc); +} + +static bool trans_LDXFSR(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv addr; + TCGv_i64 tmp; + + if (!avail_64(dc)) { + return false; + } + addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr == NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + tmp = tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(tmp, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN); + gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, tmp); + return advance_pc(dc); +} + +static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) +{ + TCGv addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + if (addr == NULL) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + tcg_gen_qemu_st_tl(cpu_fsr, addr, dc->mem_idx, mop | MO_ALIGN); + return advance_pc(dc); +} + +TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL) +TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4715,10 +4765,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) unsigned int opc, rs1, rs2, rd; TCGv cpu_src1 __attribute__((unused)); TCGv cpu_src2 __attribute__((unused)); - TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32; + TCGv_i32 cpu_src1_32, cpu_src2_32; TCGv_i64 cpu_src1_64, cpu_src2_64; + TCGv_i32 cpu_dst_32 __attribute__((unused)); TCGv_i64 cpu_dst_64 __attribute__((unused)); - target_long simm; opc = GET_FIELD(insn, 0, 1); rd = GET_FIELD(insn, 2, 6); @@ -5499,89 +5549,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } break; case 3: /* load/store instructions */ - { - unsigned int xop = GET_FIELD(insn, 7, 12); - /* ??? gen_address_mask prevents us from using a source - register directly. Always generate a temporary. */ - TCGv cpu_addr = tcg_temp_new(); - - tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn)); - if (IS_IMM) { /* immediate */ - simm = GET_FIELDs(insn, 19, 31); - if (simm != 0) { - tcg_gen_addi_tl(cpu_addr, cpu_addr, simm); - } - } else { /* register */ - rs2 = GET_FIELD(insn, 27, 31); - if (rs2 != 0) { - tcg_gen_add_tl(cpu_addr, cpu_addr, gen_load_gpr(dc, rs2)); - } - } - if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || - (xop > 0x17 && xop <= 0x1d ) || - (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { - goto illegal_insn; /* in decodetree */ - } else if (xop >= 0x20 && xop < 0x24) { - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - switch (xop) { - case 0x20: /* ldf, load fpreg */ - case 0x22: /* ldqf, load quad fpreg */ - case 0x23: /* lddf, load double fpreg */ - g_assert_not_reached(); /* in decodetree */ - case 0x21: /* ldfsr, V9 ldxfsr */ -#ifdef TARGET_SPARC64 - gen_address_mask(dc, cpu_addr); - if (rd == 1) { - TCGv_i64 t64 = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t64, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN); - gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, t64); - break; - } -#endif - cpu_dst_32 = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(cpu_dst_32, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, cpu_dst_32); - break; - default: - goto illegal_insn; - } - } else if (xop > 0x23 && xop < 0x28) { - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - switch (xop) { - case 0x24: /* stf, store fpreg */ - case 0x26: /* v9 stqf, v8 stdfq */ - case 0x27: /* stdf, store double fpreg */ - g_assert_not_reached(); - case 0x25: /* stfsr, V9 stxfsr */ - { -#ifdef TARGET_SPARC64 - gen_address_mask(dc, cpu_addr); - if (rd == 1) { - tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr, - dc->mem_idx, MO_TEUQ | MO_ALIGN); - break; - } -#endif - tcg_gen_qemu_st_tl(cpu_fsr, cpu_addr, - dc->mem_idx, MO_TEUL | MO_ALIGN); - } - break; - default: - goto illegal_insn; - } - } else if (xop > 0x33 && xop < 0x3f) { - goto illegal_insn; /* in decodetree */ - } else { - goto illegal_insn; - } - } - break; + goto illegal_insn; /* in decodetree */ } advance_pc(dc); jmp_insn: From patchwork Fri Oct 13 21:28:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733333 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680375wrv; Fri, 13 Oct 2023 14:38:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEbqE7JPsue+Jd1nUHotIi5w0kWlmWugne7dhswsMRgBgOZhS7L0ke06b21pqZwAbA2pTf9 X-Received: by 2002:a05:620a:44d0:b0:775:d42e:3e6f with SMTP id y16-20020a05620a44d000b00775d42e3e6fmr33811929qkp.65.1697233116446; Fri, 13 Oct 2023 14:38:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233116; cv=none; d=google.com; s=arc-20160816; b=aUH5p8znNme7UpJyTOPPLnE69YB5TtPruqvjpEm7aRDC1v/n0MOHAehusV3fH85TAM j0Md2BG9NeWKNhm/vT22ldGybNNcwy5+YGhVl9JJ1OKAg91TYZ+k2c1RUXIwDbtJcU6W DVVuI5TKGFhRsbB7aKNoAKroNy8lItcb1S1NehjG79CG0I/eYk3Utma+MU1jHrY9rLoz NyPpFEWvgD/SEVyu3QGVSdOMkhzHSafBZTM2RZdSAamVS/Jed9QHlJ/0m830ngc6J9gG 8DOhqXS20apSlV3uVi13Qm2lepJZLpvyEpTmpz2w5RG08he0jBmfJJ8ij9NJorKIOeky yEvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NJxggpztU3KPwg7VLkcWECSwJVSbFoVhSChqLE3M3kU=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=q3rXmhtkRGbpyBF7G0am1epVN2jiYQE2SS7GMhuWnwWsdVXCz8SJzLv5wYRBHeLEdB PuN71T1KXzYaWJ0+qMPIsWFkmaH3xta+XN6h26Fe4+yxyoHsXDkQUlcm/IR3U0+vn3Mu EDklCMXQRZcThao86vBu93QnEyL1XDhMhBnw54uBhgLjjmDwbvr/1gftUN+6Cvzn326S c61GxIfKzw8pL55soduP33F0o0UkFUT+qUTfS3msA01PLF/mQB3cC5RMMcfhIB37brGz rXDd/oFgTV14PYf+Qf02kic7Iq5QlwIMNisU4SlRemVGa4wI9+rXD7x+0EXZows26Idy GDTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rp7Z46GD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 53/85] target/sparc: Merge LDFSR, LDXFSR implementations Date: Fri, 13 Oct 2023 14:28:14 -0700 Message-Id: <20231013212846.165724-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Combine the helper to a single set_fsr(). Perform the mask and merge inline. Signed-off-by: Richard Henderson --- target/sparc/helper.h | 3 +-- target/sparc/fop_helper.c | 17 ++-------------- target/sparc/translate.c | 42 ++++++++++++--------------------------- 3 files changed, 16 insertions(+), 46 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index b8f1e78c75..a9ee8e6b9f 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -43,7 +43,7 @@ DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32) DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32) #endif DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env) -DEF_HELPER_FLAGS_3(ldfsr, TCG_CALL_NO_RWG, tl, env, tl, i32) +DEF_HELPER_FLAGS_2(set_fsr, TCG_CALL_NO_RWG, void, env, tl) DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32) DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32) DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64) @@ -55,7 +55,6 @@ DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env) DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env) #ifdef TARGET_SPARC64 -DEF_HELPER_FLAGS_3(ldxfsr, TCG_CALL_NO_RWG, tl, env, tl, i64) DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_NO_RWG_SE, f64, f64) DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32) DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index f54fa9b959..0f8aa3abcd 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -382,20 +382,7 @@ static void set_fsr(CPUSPARCState *env, target_ulong fsr) set_float_rounding_mode(rnd_mode, &env->fp_status); } -target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr, - uint32_t new_fsr) +void helper_set_fsr(CPUSPARCState *env, target_ulong fsr) { - old_fsr = (new_fsr & FSR_LDFSR_MASK) | (old_fsr & FSR_LDFSR_OLDMASK); - set_fsr(env, old_fsr); - return old_fsr; + set_fsr(env, fsr); } - -#ifdef TARGET_SPARC64 -target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr, - uint64_t new_fsr) -{ - old_fsr = (new_fsr & FSR_LDXFSR_MASK) | (old_fsr & FSR_LDXFSR_OLDMASK); - set_fsr(env, old_fsr); - return old_fsr; -} -#endif diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9384815f0b..6598557bb5 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -58,7 +58,8 @@ #define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() #define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() -#define gen_helper_ldxfsr(R, E, X, Y) qemu_build_not_reached() +#define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; }) +#define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; }) # ifdef CONFIG_USER_ONLY static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a, TCGv_i32 asi, TCGv_i32 mop) @@ -4697,44 +4698,27 @@ static bool trans_STDFQ(DisasContext *dc, arg_STDFQ *a) return true; } -static bool trans_LDFSR(DisasContext *dc, arg_r_r_ri *a) +static bool do_ldfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop, + target_ulong new_mask, target_ulong old_mask) { - TCGv addr; - TCGv_i32 tmp; - - addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); + TCGv tmp, addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); if (addr == NULL) { return false; } if (gen_trap_ifnofpu(dc)) { return true; } - tmp = tcg_temp_new_i32(); - tcg_gen_qemu_ld_i32(tmp, addr, dc->mem_idx, MO_TEUL | MO_ALIGN); - gen_helper_ldfsr(cpu_fsr, tcg_env, cpu_fsr, tmp); + tmp = tcg_temp_new(); + tcg_gen_qemu_ld_tl(tmp, addr, dc->mem_idx, mop | MO_ALIGN); + tcg_gen_andi_tl(tmp, tmp, new_mask); + tcg_gen_andi_tl(cpu_fsr, cpu_fsr, old_mask); + tcg_gen_or_tl(cpu_fsr, cpu_fsr, tmp); + gen_helper_set_fsr(tcg_env, cpu_fsr); return advance_pc(dc); } -static bool trans_LDXFSR(DisasContext *dc, arg_r_r_ri *a) -{ - TCGv addr; - TCGv_i64 tmp; - - if (!avail_64(dc)) { - return false; - } - addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm); - if (addr == NULL) { - return false; - } - if (gen_trap_ifnofpu(dc)) { - return true; - } - tmp = tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(tmp, addr, dc->mem_idx, MO_TEUQ | MO_ALIGN); - gen_helper_ldxfsr(cpu_fsr, tcg_env, cpu_fsr, tmp); - return advance_pc(dc); -} +TRANS(LDFSR, ALL, do_ldfsr, a, MO_TEUL, FSR_LDFSR_MASK, FSR_LDFSR_OLDMASK) +TRANS(LDXFSR, 64, do_ldfsr, a, MO_TEUQ, FSR_LDXFSR_MASK, FSR_LDXFSR_OLDMASK) static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) { From patchwork Fri Oct 13 21:28:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733337 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680613wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 54/85] target/sparc: Move EDGE* to decodetree Date: Fri, 13 Oct 2023 14:28:15 -0700 Message-Id: <20231013212846.165724-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 22 ++- target/sparc/translate.c | 272 ++++++++++++++++---------------------- 2 files changed, 134 insertions(+), 160 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 185bcadab7..b4bbdd43ec 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -30,6 +30,9 @@ CALL 01 i:s30 @n_r_ri .. ..... ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri rd=0 @r_r_ri .. rd:5 ...... rs1:5 imm:1 rs2_or_imm:s13 &r_r_ri +&r_r_r rd rs1 rs2 +@r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 Tcc_i 10 0 cond:4 111010 rs1:5 1 cc:1 0000 i:8 @@ -225,7 +228,24 @@ RESTORE 10 ..... 111101 ..... . ............. @r_r_ri DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 -NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 +{ + [ + EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r + EDGE8N 10 ..... 110110 ..... 0 0000 0001 ..... @r_r_r + EDGE8Lcc 10 ..... 110110 ..... 0 0000 0010 ..... @r_r_r + EDGE8LN 10 ..... 110110 ..... 0 0000 0011 ..... @r_r_r + EDGE16cc 10 ..... 110110 ..... 0 0000 0100 ..... @r_r_r + EDGE16N 10 ..... 110110 ..... 0 0000 0101 ..... @r_r_r + EDGE16Lcc 10 ..... 110110 ..... 0 0000 0110 ..... @r_r_r + EDGE16LN 10 ..... 110110 ..... 0 0000 0111 ..... @r_r_r + EDGE32cc 10 ..... 110110 ..... 0 0000 1000 ..... @r_r_r + EDGE32N 10 ..... 110110 ..... 0 0000 1001 ..... @r_r_r + EDGE32Lcc 10 ..... 110110 ..... 0 0000 1010 ..... @r_r_r + EDGE32LN 10 ..... 110110 ..... 0 0000 1011 ..... @r_r_r + ] + NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 +} + NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2 ## diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6598557bb5..56f32551af 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2620,93 +2620,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr) } } -static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, - int width, bool cc, bool left) -{ - TCGv lo1, lo2; - uint64_t amask, tabl, tabr; - int shift, imask, omask; - - if (cc) { - tcg_gen_mov_tl(cpu_cc_src, s1); - tcg_gen_mov_tl(cpu_cc_src2, s2); - tcg_gen_sub_tl(cpu_cc_dst, s1, s2); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); - dc->cc_op = CC_OP_SUB; - } - - /* Theory of operation: there are two tables, left and right (not to - be confused with the left and right versions of the opcode). These - are indexed by the low 3 bits of the inputs. To make things "easy", - these tables are loaded into two constants, TABL and TABR below. - The operation index = (input & imask) << shift calculates the index - into the constant, while val = (table >> index) & omask calculates - the value we're looking for. */ - switch (width) { - case 8: - imask = 0x7; - shift = 3; - omask = 0xff; - if (left) { - tabl = 0x80c0e0f0f8fcfeffULL; - tabr = 0xff7f3f1f0f070301ULL; - } else { - tabl = 0x0103070f1f3f7fffULL; - tabr = 0xfffefcf8f0e0c080ULL; - } - break; - case 16: - imask = 0x6; - shift = 1; - omask = 0xf; - if (left) { - tabl = 0x8cef; - tabr = 0xf731; - } else { - tabl = 0x137f; - tabr = 0xfec8; - } - break; - case 32: - imask = 0x4; - shift = 0; - omask = 0x3; - if (left) { - tabl = (2 << 2) | 3; - tabr = (3 << 2) | 1; - } else { - tabl = (1 << 2) | 3; - tabr = (3 << 2) | 2; - } - break; - default: - abort(); - } - - lo1 = tcg_temp_new(); - lo2 = tcg_temp_new(); - tcg_gen_andi_tl(lo1, s1, imask); - tcg_gen_andi_tl(lo2, s2, imask); - tcg_gen_shli_tl(lo1, lo1, shift); - tcg_gen_shli_tl(lo2, lo2, shift); - - tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1); - tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2); - tcg_gen_andi_tl(lo1, lo1, omask); - tcg_gen_andi_tl(lo2, lo2, omask); - - amask = -8; - if (AM_CHECK(dc)) { - amask &= 0xffffffffULL; - } - tcg_gen_andi_tl(s1, s1, amask); - tcg_gen_andi_tl(s2, s2, amask); - - /* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */ - tcg_gen_and_tl(lo2, lo2, lo1); - tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2); -} - static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) { TCGv tmp = tcg_temp_new(); @@ -2771,6 +2684,8 @@ static int extract_qfpreg(DisasContext *dc, int x) #define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL) #define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV) #define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN) +#define avail_VIS1(C) ((C)->def->features & CPU_FEATURE_VIS1) +#define avail_VIS2(C) ((C)->def->features & CPU_FEATURE_VIS2) /* Default case for non jump instructions. */ static bool advance_pc(DisasContext *dc) @@ -4219,6 +4134,116 @@ static bool trans_MULScc(DisasContext *dc, arg_r_r_ri *a) return do_cc_arith(dc, a, CC_OP_ADD, gen_op_mulscc, NULL); } +static bool gen_edge(DisasContext *dc, arg_r_r_r *a, + int width, bool cc, bool left) +{ + TCGv dst, s1, s2, lo1, lo2; + uint64_t amask, tabl, tabr; + int shift, imask, omask; + + dst = gen_dest_gpr(dc, a->rd); + s1 = gen_load_gpr(dc, a->rs1); + s2 = gen_load_gpr(dc, a->rs2); + + if (cc) { + tcg_gen_mov_tl(cpu_cc_src, s1); + tcg_gen_mov_tl(cpu_cc_src2, s2); + tcg_gen_sub_tl(cpu_cc_dst, s1, s2); + tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB); + dc->cc_op = CC_OP_SUB; + } + + /* + * Theory of operation: there are two tables, left and right (not to + * be confused with the left and right versions of the opcode). These + * are indexed by the low 3 bits of the inputs. To make things "easy", + * these tables are loaded into two constants, TABL and TABR below. + * The operation index = (input & imask) << shift calculates the index + * into the constant, while val = (table >> index) & omask calculates + * the value we're looking for. + */ + switch (width) { + case 8: + imask = 0x7; + shift = 3; + omask = 0xff; + if (left) { + tabl = 0x80c0e0f0f8fcfeffULL; + tabr = 0xff7f3f1f0f070301ULL; + } else { + tabl = 0x0103070f1f3f7fffULL; + tabr = 0xfffefcf8f0e0c080ULL; + } + break; + case 16: + imask = 0x6; + shift = 1; + omask = 0xf; + if (left) { + tabl = 0x8cef; + tabr = 0xf731; + } else { + tabl = 0x137f; + tabr = 0xfec8; + } + break; + case 32: + imask = 0x4; + shift = 0; + omask = 0x3; + if (left) { + tabl = (2 << 2) | 3; + tabr = (3 << 2) | 1; + } else { + tabl = (1 << 2) | 3; + tabr = (3 << 2) | 2; + } + break; + default: + abort(); + } + + lo1 = tcg_temp_new(); + lo2 = tcg_temp_new(); + tcg_gen_andi_tl(lo1, s1, imask); + tcg_gen_andi_tl(lo2, s2, imask); + tcg_gen_shli_tl(lo1, lo1, shift); + tcg_gen_shli_tl(lo2, lo2, shift); + + tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1); + tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2); + tcg_gen_andi_tl(lo1, lo1, omask); + tcg_gen_andi_tl(lo2, lo2, omask); + + amask = -8; + if (AM_CHECK(dc)) { + amask &= 0xffffffffULL; + } + tcg_gen_andi_tl(s1, s1, amask); + tcg_gen_andi_tl(s2, s2, amask); + + /* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */ + tcg_gen_and_tl(lo2, lo2, lo1); + tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2); + + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(EDGE8cc, VIS1, gen_edge, a, 8, 1, 0) +TRANS(EDGE8Lcc, VIS1, gen_edge, a, 8, 1, 1) +TRANS(EDGE16cc, VIS1, gen_edge, a, 16, 1, 0) +TRANS(EDGE16Lcc, VIS1, gen_edge, a, 16, 1, 1) +TRANS(EDGE32cc, VIS1, gen_edge, a, 32, 1, 0) +TRANS(EDGE32Lcc, VIS1, gen_edge, a, 32, 1, 1) + +TRANS(EDGE8N, VIS2, gen_edge, a, 8, 0, 0) +TRANS(EDGE8LN, VIS2, gen_edge, a, 8, 0, 1) +TRANS(EDGE16N, VIS2, gen_edge, a, 16, 0, 0) +TRANS(EDGE16LN, VIS2, gen_edge, a, 16, 0, 1) +TRANS(EDGE32N, VIS2, gen_edge, a, 32, 0, 0) +TRANS(EDGE32LN, VIS2, gen_edge, a, 32, 0, 1) + static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) { TCGv dst, src1, src2; @@ -5097,89 +5122,18 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) switch (opf) { case 0x000: /* VIS I edge8cc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x001: /* VIS II edge8n */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x002: /* VIS I edge8lcc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 1, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x003: /* VIS II edge8ln */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 8, 0, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x004: /* VIS I edge16cc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x005: /* VIS II edge16n */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x006: /* VIS I edge16lcc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 1, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x007: /* VIS II edge16ln */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 16, 0, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x008: /* VIS I edge32cc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x009: /* VIS II edge32n */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x00a: /* VIS I edge32lcc */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 1, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x00b: /* VIS II edge32ln */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_edge(dc, cpu_dst, cpu_src1, cpu_src2, 32, 0, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x010: /* VIS I array8 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = gen_load_gpr(dc, rs1); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 55/85] target/sparc: Move ARRAY* to decodetree Date: Fri, 13 Oct 2023 14:28:16 -0700 Message-Id: <20231013212846.165724-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d29; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 54 ++++++++++++++++++++++++--------------- 2 files changed, 37 insertions(+), 21 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index b4bbdd43ec..e8d49de888 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -242,6 +242,10 @@ RETRY 10 00001 111110 00000 0 0000000000000 EDGE32N 10 ..... 110110 ..... 0 0000 1001 ..... @r_r_r EDGE32Lcc 10 ..... 110110 ..... 0 0000 1010 ..... @r_r_r EDGE32LN 10 ..... 110110 ..... 0 0000 1011 ..... @r_r_r + + ARRAY8 10 ..... 110110 ..... 0 0001 0000 ..... @r_r_r + ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r + ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 56f32551af..c8685c6837 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -72,6 +72,10 @@ static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r, g_assert_not_reached(); } # endif +static void gen_helper_array8(TCGv r, TCGv a, TCGv b) +{ + g_assert_not_reached(); +} #endif /* Dynamic PC, must exit to main loop. */ @@ -659,6 +663,18 @@ static void gen_op_popc(TCGv dst, TCGv src1, TCGv src2) tcg_gen_ctpop_tl(dst, src2); } +static void gen_op_array16(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_array8(dst, src1, src2); + tcg_gen_shli_tl(dst, dst, 1); +} + +static void gen_op_array32(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_array8(dst, src1, src2); + tcg_gen_shli_tl(dst, dst, 2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -4244,6 +4260,22 @@ TRANS(EDGE16LN, VIS2, gen_edge, a, 16, 0, 1) TRANS(EDGE32N, VIS2, gen_edge, a, 32, 0, 0) TRANS(EDGE32LN, VIS2, gen_edge, a, 32, 0, 1) +static bool do_rrr(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv, TCGv, TCGv)) +{ + TCGv dst = gen_dest_gpr(dc, a->rd); + TCGv src1 = gen_load_gpr(dc, a->rs1); + TCGv src2 = gen_load_gpr(dc, a->rs2); + + func(dst, src1, src2); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(ARRAY8, VIS1, do_rrr, a, gen_helper_array8) +TRANS(ARRAY16, VIS1, do_rrr, a, gen_op_array16) +TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32) + static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) { TCGv dst, src1, src2; @@ -5133,30 +5165,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x009: /* VIS II edge32n */ case 0x00a: /* VIS I edge32lcc */ case 0x00b: /* VIS II edge32ln */ - g_assert_not_reached(); /* in decodetree */ case 0x010: /* VIS I array8 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x012: /* VIS I array16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_shli_i64(cpu_dst, cpu_dst, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x014: /* VIS I array32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_shli_i64(cpu_dst, cpu_dst, 2); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x018: /* VIS I alignaddr */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = gen_load_gpr(dc, rs1); From patchwork Fri Oct 13 21:28:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733332 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680376wrv; Fri, 13 Oct 2023 14:38:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH9ojvwPGwL9N85ynFvONOJOKk+ibSg3pBB4P0Z38gwF3ouyeqtz8bl4JnCR54110Oh6Mql X-Received: by 2002:a05:620a:678:b0:76f:20df:f032 with SMTP id a24-20020a05620a067800b0076f20dff032mr23493285qkh.69.1697233116449; Fri, 13 Oct 2023 14:38:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233116; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 56/85] target/sparc: Move ADDRALIGN* to decodetree Date: Fri, 13 Oct 2023 14:28:17 -0700 Message-Id: <20231013212846.165724-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 56 ++++++++++++++++++++++----------------- 2 files changed, 34 insertions(+), 25 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index e8d49de888..f6ac8672c8 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -246,6 +246,9 @@ RETRY 10 00001 111110 00000 0 0000000000000 ARRAY8 10 ..... 110110 ..... 0 0001 0000 ..... @r_r_r ARRAY16 10 ..... 110110 ..... 0 0001 0010 ..... @r_r_r ARRAY32 10 ..... 110110 ..... 0 0001 0100 ..... @r_r_r + + ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r + ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index c8685c6837..0392ef7cda 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2636,18 +2636,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr) } } -static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) -{ - TCGv tmp = tcg_temp_new(); - - tcg_gen_add_tl(tmp, s1, s2); - tcg_gen_andi_tl(dst, tmp, -8); - if (left) { - tcg_gen_neg_tl(tmp, tmp); - } - tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); -} - static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) { TCGv t1, t2, shift; @@ -4276,6 +4264,36 @@ TRANS(ARRAY8, VIS1, do_rrr, a, gen_helper_array8) TRANS(ARRAY16, VIS1, do_rrr, a, gen_op_array16) TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32) +static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2) +{ +#ifdef TARGET_SPARC64 + TCGv tmp = tcg_temp_new(); + + tcg_gen_add_tl(tmp, s1, s2); + tcg_gen_andi_tl(dst, tmp, -8); + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); +#else + g_assert_not_reached(); +#endif +} + +static void gen_op_alignaddrl(TCGv dst, TCGv s1, TCGv s2) +{ +#ifdef TARGET_SPARC64 + TCGv tmp = tcg_temp_new(); + + tcg_gen_add_tl(tmp, s1, s2); + tcg_gen_andi_tl(dst, tmp, -8); + tcg_gen_neg_tl(tmp, tmp); + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, tmp, 0, 3); +#else + g_assert_not_reached(); +#endif +} + +TRANS(ALIGNADDR, VIS1, do_rrr, a, gen_op_alignaddr) +TRANS(ALIGNADDRL, VIS1, do_rrr, a, gen_op_alignaddrl) + static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) { TCGv dst, src1, src2; @@ -5168,21 +5186,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x010: /* VIS I array8 */ case 0x012: /* VIS I array16 */ case 0x014: /* VIS I array32 */ - g_assert_not_reached(); /* in decodetree */ case 0x018: /* VIS I alignaddr */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 0); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x01a: /* VIS I alignaddrl */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - gen_alignaddr(cpu_dst, cpu_src1, cpu_src2, 1); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x019: /* VIS II bmask */ CHECK_FPU_FEATURE(dc, VIS2); cpu_src1 = gen_load_gpr(dc, rs1); From patchwork Fri Oct 13 21:28:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733317 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680061wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 57/85] target/sparc: Move BMASK to decodetree Date: Fri, 13 Oct 2023 14:28:18 -0700 Message-Id: <20231013212846.165724-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 22 +++++++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f6ac8672c8..1418e45172 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -249,6 +249,8 @@ RETRY 10 00001 111110 00000 0 0000000000000 ALIGNADDR 10 ..... 110110 ..... 0 0001 1000 ..... @r_r_r ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r + + BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 0392ef7cda..d0efe9f72b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4294,6 +4294,18 @@ static void gen_op_alignaddrl(TCGv dst, TCGv s1, TCGv s2) TRANS(ALIGNADDR, VIS1, do_rrr, a, gen_op_alignaddr) TRANS(ALIGNADDRL, VIS1, do_rrr, a, gen_op_alignaddrl) +static void gen_op_bmask(TCGv dst, TCGv s1, TCGv s2) +{ +#ifdef TARGET_SPARC64 + tcg_gen_add_tl(dst, s1, s2); + tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, dst, 32, 32); +#else + g_assert_not_reached(); +#endif +} + +TRANS(BMASK, VIS2, do_rrr, a, gen_op_bmask) + static bool do_shift_r(DisasContext *dc, arg_shiftr *a, bool l, bool u) { TCGv dst, src1, src2; @@ -4823,7 +4835,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) { unsigned int opc, rs1, rs2, rd; TCGv cpu_src1 __attribute__((unused)); - TCGv cpu_src2 __attribute__((unused)); TCGv_i32 cpu_src1_32, cpu_src2_32; TCGv_i64 cpu_src1_64, cpu_src2_64; TCGv_i32 cpu_dst_32 __attribute__((unused)); @@ -5188,15 +5199,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x014: /* VIS I array32 */ case 0x018: /* VIS I alignaddr */ case 0x01a: /* VIS I alignaddrl */ - g_assert_not_reached(); /* in decodetree */ case 0x019: /* VIS II bmask */ - CHECK_FPU_FEATURE(dc, VIS2); - cpu_src1 = gen_load_gpr(dc, rs1); - cpu_src2 = gen_load_gpr(dc, rs2); - tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_deposit_tl(cpu_gsr, cpu_gsr, cpu_dst, 32, 32); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 = gen_load_fpr_D(dc, rs1); From patchwork Fri Oct 13 21:28:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733323 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680179wrv; Fri, 13 Oct 2023 14:37:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG/5BqnN+30BYAbPFzau320DPYvasLhJ06h+svarpeLe1V2wNN8v1QMtLxctr3KzqrpDQ9x X-Received: by 2002:a05:620a:e07:b0:773:c4c8:2d58 with SMTP id y7-20020a05620a0e0700b00773c4c82d58mr24447631qkm.59.1697233068985; Fri, 13 Oct 2023 14:37:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233068; cv=none; d=google.com; s=arc-20160816; b=T4QjPULbvZwRzwWt+hqGN1bsDdJryxDLXgJ/QyMkJjexBVtTzvIrs05h2Bmes1VJdX 4dRjBV27AtwTpZ2oYj2IMa8Di8uyKRBJt99GofYw27cA9NZkkx3+Q7Gl1Fe2lTQAZMTW xEum2A1eRuRGiAdOfJps9AVm7teJUDvQSpvK94IvrS6fo3pRHf8sGQFQU7pmCRu5AbBS fverKhXeV3Gnsg0P156dIsZDyqHtryuoF2SHUt52D8R5WlN05C/70P5TIGLZII7oaFtU L8a3Z6Gzx1aMxea5B9Yax53waA1YCQ0QoAGl690aUJbwmzxQVWcfsXUIoE9JOd46I2ZV tyIw== ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 58/85] target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree Date: Fri, 13 Oct 2023 14:28:19 -0700 Message-Id: <20231013212846.165724-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 13 ++++++++ target/sparc/translate.c | 64 ++++++++++++++++----------------------- 2 files changed, 39 insertions(+), 38 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 1418e45172..2072930bd7 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -33,6 +33,10 @@ CALL 01 i:s30 &r_r_r rd rs1 rs2 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r +&r_r rd rs +@r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r +@r_r2 .. rd:5 ...... ..... . ........ rs:5 &r_r + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 Tcc_i 10 0 cond:4 111010 rs1:5 1 cc:1 0000 i:8 @@ -228,6 +232,10 @@ RESTORE 10 ..... 111101 ..... . ............. @r_r_ri DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 +FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2 +FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 +FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 + { [ EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r @@ -251,6 +259,11 @@ RETRY 10 00001 111110 00000 0 0000000000000 ALIGNADDRL 10 ..... 110110 ..... 0 0001 1010 ..... @r_r_r BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r + + FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s + FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s + FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s + FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d0efe9f72b..c2fe193b6d 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1481,19 +1481,6 @@ static void gen_fop_FF(DisasContext *dc, int rd, int rs, gen_store_fpr_F(dc, rd, dst); } -static void gen_ne_fop_FF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_i32)) -{ - TCGv_i32 dst, src; - - src = gen_load_fpr_F(dc, rs); - dst = gen_dest_fpr_F(dc); - - gen(dst, src); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32)) { @@ -4823,6 +4810,27 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL) TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ) +static bool do_ff(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + tmp = gen_load_fpr_F(dc, a->rs); + func(tmp, tmp); + gen_store_fpr_F(dc, a->rd, tmp); + return advance_pc(dc); +} + +TRANS(FMOVs, ALL, do_ff, a, tcg_gen_mov_i32) +TRANS(FNEGs, ALL, do_ff, a, gen_helper_fnegs) +TRANS(FABSs, ALL, do_ff, a, gen_helper_fabss) +TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) +TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4864,15 +4872,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) switch (xop) { case 0x1: /* fmovs */ - cpu_src1_32 = gen_load_fpr_F(dc, rs2); - gen_store_fpr_F(dc, rd, cpu_src1_32); - break; case 0x5: /* fnegs */ - gen_ne_fop_FF(dc, rd, rs2, gen_helper_fnegs); - break; case 0x9: /* fabss */ - gen_ne_fop_FF(dc, rd, rs2, gen_helper_fabss); - break; + g_assert_not_reached(); /* in decodetree */ case 0x29: /* fsqrts */ gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); break; @@ -5200,6 +5202,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x018: /* VIS I alignaddr */ case 0x01a: /* VIS I alignaddrl */ case 0x019: /* VIS II bmask */ + case 0x067: /* VIS I fnot2s */ + case 0x06b: /* VIS I fnot1s */ + case 0x075: /* VIS I fsrc1s */ + case 0x079: /* VIS I fsrc2s */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5387,10 +5393,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64); break; - case 0x067: /* VIS I fnot2s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FF(dc, rd, rs2, tcg_gen_not_i32); - break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); @@ -5403,10 +5405,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64); break; - case 0x06b: /* VIS I fnot1s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FF(dc, rd, rs1, tcg_gen_not_i32); - break; case 0x06c: /* VIS I fxor */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); @@ -5444,11 +5442,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1_64 = gen_load_fpr_D(dc, rs1); gen_store_fpr_D(dc, rd, cpu_src1_64); break; - case 0x075: /* VIS I fsrc1s */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_32 = gen_load_fpr_F(dc, rs1); - gen_store_fpr_F(dc, rd, cpu_src1_32); - break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64); @@ -5462,11 +5455,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1_64 = gen_load_fpr_D(dc, rs2); gen_store_fpr_D(dc, rd, cpu_src1_64); break; - case 0x079: /* VIS I fsrc2s */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_32 = gen_load_fpr_F(dc, rs2); - gen_store_fpr_F(dc, rd, cpu_src1_32); - break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); From patchwork Fri Oct 13 21:28:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733318 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680071wrv; Fri, 13 Oct 2023 14:37:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG6miLMIDpoIi0WTRi6HPn/fsN31M1Q2SfHmr7s6dCzDrbPazAMjbkzQ60IwRss8wVkMdaj X-Received: by 2002:a05:6808:1306:b0:3ae:1e08:4209 with SMTP id y6-20020a056808130600b003ae1e084209mr38847376oiv.39.1697233045547; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 59/85] target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree Date: Fri, 13 Oct 2023 14:28:20 -0700 Message-Id: <20231013212846.165724-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 ++++ target/sparc/translate.c | 73 +++++++++++++++++---------------------- 2 files changed, 38 insertions(+), 42 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 2072930bd7..362aa00300 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -233,8 +233,11 @@ DONE 10 00000 111110 00000 0 0000000000000 RETRY 10 00001 111110 00000 0 0000000000000 FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2 +FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2 FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 +FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 +FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 { [ @@ -260,9 +263,13 @@ FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r + FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s + FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s + FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @r_r1 # FNOT1d FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s + FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index c2fe193b6d..0a1ebb62e3 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -54,6 +54,8 @@ #define gen_helper_write_softint(E, S) qemu_build_not_reached() #define gen_helper_saved ({ qemu_build_not_reached(); NULL; }) #define gen_helper_restored ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_fnegd ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_fabsd ({ qemu_build_not_reached(); NULL; }) #define gen_helper_done(E) qemu_build_not_reached() #define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() @@ -1526,21 +1528,6 @@ static void gen_fop_DD(DisasContext *dc, int rd, int rs, gen_store_fpr_D(dc, rd, dst); } -#ifdef TARGET_SPARC64 -static void gen_ne_fop_DD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_i64)) -{ - TCGv_i64 dst, src; - - src = gen_load_fpr_D(dc, rs); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, src); - - gen_store_fpr_D(dc, rd, dst); -} -#endif - static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64)) { @@ -4831,6 +4818,28 @@ TRANS(FABSs, ALL, do_ff, a, gen_helper_fabss) TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) +static bool do_dd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i64, TCGv_i64)) +{ + TCGv_i64 dst, src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = gen_dest_fpr_D(dc, a->rd); + src = gen_load_fpr_D(dc, a->rs); + func(dst, src); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FMOVd, 64, do_dd, a, tcg_gen_mov_i64) +TRANS(FNEGd, 64, do_dd, a, gen_helper_fnegd) +TRANS(FABSd, 64, do_dd, a, gen_helper_fabsd) +TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64) +TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4874,6 +4883,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x1: /* fmovs */ case 0x5: /* fnegs */ case 0x9: /* fabss */ + case 0x2: /* V9 fmovd */ + case 0x6: /* V9 fnegd */ + case 0xa: /* V9 fabsd */ g_assert_not_reached(); /* in decodetree */ case 0x29: /* fsqrts */ gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); @@ -4976,24 +4988,14 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi); break; #ifdef TARGET_SPARC64 - case 0x2: /* V9 fmovd */ - cpu_src1_64 = gen_load_fpr_D(dc, rs2); - gen_store_fpr_D(dc, rd, cpu_src1_64); - break; case 0x3: /* V9 fmovq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_move_Q(dc, rd, rs2); break; - case 0x6: /* V9 fnegd */ - gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd); - break; case 0x7: /* V9 fnegq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq); break; - case 0xa: /* V9 fabsd */ - gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd); - break; case 0xb: /* V9 fabsq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); @@ -5206,6 +5208,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x06b: /* VIS I fnot1s */ case 0x075: /* VIS I fsrc1s */ case 0x079: /* VIS I fsrc2s */ + case 0x066: /* VIS I fnot2 */ + case 0x06a: /* VIS I fnot1 */ + case 0x074: /* VIS I fsrc1 */ + case 0x078: /* VIS I fsrc2 */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5389,10 +5395,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32); break; - case 0x066: /* VIS I fnot2 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64); - break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); @@ -5401,10 +5403,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32); break; - case 0x06a: /* VIS I fnot1 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64); - break; case 0x06c: /* VIS I fxor */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); @@ -5437,10 +5435,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32); break; - case 0x074: /* VIS I fsrc1 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - gen_store_fpr_D(dc, rd, cpu_src1_64); break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5450,11 +5444,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32); break; - case 0x078: /* VIS I fsrc2 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs2); - gen_store_fpr_D(dc, rd, cpu_src1_64); - break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); From patchwork Fri Oct 13 21:28:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733335 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680432wrv; Fri, 13 Oct 2023 14:38:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHo5aUJ427SgQ75flb0z/Su0RuPT8re3VTrhsJzz1IJNODE7hmvETljCoiveNm24RsQHb8g X-Received: by 2002:a25:c705:0:b0:d9a:c61f:e5f1 with SMTP id w5-20020a25c705000000b00d9ac61fe5f1mr5434826ybe.32.1697233132548; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 60/85] target/sparc: Use tcg_gen_vec_{add,sub}* Date: Fri, 13 Oct 2023 14:28:21 -0700 Message-Id: <20231013212846.165724-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the local helpers for the same integer operations. Signed-off-by: Richard Henderson --- target/sparc/helper.h | 12 -------- target/sparc/translate.c | 15 +++++----- target/sparc/vis_helper.c | 59 --------------------------------------- 3 files changed, 7 insertions(+), 79 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index a9ee8e6b9f..8d20258d08 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -138,18 +138,6 @@ DEF_HELPER_FLAGS_2(fpack16, TCG_CALL_NO_RWG_SE, i32, i64, i64) DEF_HELPER_FLAGS_3(fpack32, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(fpackfix, TCG_CALL_NO_RWG_SE, i32, i64, i64) DEF_HELPER_FLAGS_3(bshuffle, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) -#define VIS_HELPER(name) \ - DEF_HELPER_FLAGS_2(f ## name ## 16, TCG_CALL_NO_RWG_SE, \ - i64, i64, i64) \ - DEF_HELPER_FLAGS_2(f ## name ## 16s, TCG_CALL_NO_RWG_SE, \ - i32, i32, i32) \ - DEF_HELPER_FLAGS_2(f ## name ## 32, TCG_CALL_NO_RWG_SE, \ - i64, i64, i64) \ - DEF_HELPER_FLAGS_2(f ## name ## 32s, TCG_CALL_NO_RWG_SE, \ - i32, i32, i32) - -VIS_HELPER(padd) -VIS_HELPER(psub) #define VIS_CMPHELPER(name) \ DEF_HELPER_FLAGS_2(f##name##16, TCG_CALL_NO_RWG_SE, \ i64, i64, i64) \ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 0a1ebb62e3..3b6f4bef95 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -25,9 +25,8 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" - +#include "tcg/tcg-op-gvec.h" #include "exec/helper-gen.h" - #include "exec/translator.h" #include "exec/log.h" #include "asi.h" @@ -5337,15 +5336,15 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) break; case 0x050: /* VIS I fpadd16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd16); + gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add16_i64); break; case 0x051: /* VIS I fpadd16s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpadd16s); + gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_add16_i32); break; case 0x052: /* VIS I fpadd32 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpadd32); + gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64); break; case 0x053: /* VIS I fpadd32s */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5353,15 +5352,15 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) break; case 0x054: /* VIS I fpsub16 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub16); + gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i64); break; case 0x055: /* VIS I fpsub16s */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, gen_helper_fpsub16s); + gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i32); break; case 0x056: /* VIS I fpsub32 */ CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpsub32); + gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64); break; case 0x057: /* VIS I fpsub32s */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target/sparc/vis_helper.c b/target/sparc/vis_helper.c index 3afdc6975c..7763b16c24 100644 --- a/target/sparc/vis_helper.c +++ b/target/sparc/vis_helper.c @@ -275,65 +275,6 @@ uint64_t helper_fexpand(uint64_t src1, uint64_t src2) return d.ll; } -#define VIS_HELPER(name, F) \ - uint64_t name##16(uint64_t src1, uint64_t src2) \ - { \ - VIS64 s, d; \ - \ - s.ll = src1; \ - d.ll = src2; \ - \ - d.VIS_W64(0) = F(d.VIS_W64(0), s.VIS_W64(0)); \ - d.VIS_W64(1) = F(d.VIS_W64(1), s.VIS_W64(1)); \ - d.VIS_W64(2) = F(d.VIS_W64(2), s.VIS_W64(2)); \ - d.VIS_W64(3) = F(d.VIS_W64(3), s.VIS_W64(3)); \ - \ - return d.ll; \ - } \ - \ - uint32_t name##16s(uint32_t src1, uint32_t src2) \ - { \ - VIS32 s, d; \ - \ - s.l = src1; \ - d.l = src2; \ - \ - d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \ - d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \ - \ - return d.l; \ - } \ - \ - uint64_t name##32(uint64_t src1, uint64_t src2) \ - { \ - VIS64 s, d; \ - \ - s.ll = src1; \ - d.ll = src2; \ - \ - d.VIS_L64(0) = F(d.VIS_L64(0), s.VIS_L64(0)); \ - d.VIS_L64(1) = F(d.VIS_L64(1), s.VIS_L64(1)); \ - \ - return d.ll; \ - } \ - \ - uint32_t name##32s(uint32_t src1, uint32_t src2) \ - { \ - VIS32 s, d; \ - \ - s.l = src1; \ - d.l = src2; \ - \ - d.l = F(d.l, s.l); \ - \ - return d.l; \ - } - -#define FADD(a, b) ((a) + (b)) -#define FSUB(a, b) ((a) - (b)) -VIS_HELPER(helper_fpadd, FADD) -VIS_HELPER(helper_fpsub, FSUB) - #define VIS_CMPHELPER(name, F) \ uint64_t name##16(uint64_t src1, uint64_t src2) \ { \ From patchwork Fri Oct 13 21:28:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733326 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680237wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 61/85] target/sparc: Move gen_ne_fop_FFF insns to decodetree Date: Fri, 13 Oct 2023 14:28:22 -0700 Message-Id: <20231013212846.165724-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move FANDNOT1s, FANDNOT2s, FANDs, FNANDs, FNORs, FORNOT1s, FORNOT2s, FORs, FPADD16s, FPADD32s, FPSUB16s, FPSUB32s, FXNORs, FXORs. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 16 ++++++ target/sparc/translate.c | 116 ++++++++++++++------------------------ 2 files changed, 59 insertions(+), 73 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 362aa00300..96ba61865a 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -32,6 +32,7 @@ CALL 01 i:s30 &r_r_r rd rs1 rs2 @r_r_r .. rd:5 ...... rs1:5 . ........ rs2:5 &r_r_r +@r_r_r_swap .. rd:5 ...... rs2:5 . ........ rs1:5 &r_r_r &r_r rd rs @r_r1 .. rd:5 ...... rs:5 . ........ ..... &r_r @@ -271,6 +272,21 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s + + FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r + FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r + FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r + FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r + FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r + FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FANDNOT2s + FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # ... 1s + FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r + FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r + FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r + FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r + FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FORNOT2s + FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # ... 1s + FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3b6f4bef95..30329b94dd 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1497,22 +1497,6 @@ static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_F(dc, rd, dst); } -#ifdef TARGET_SPARC64 -static void gen_ne_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) -{ - TCGv_i32 dst, src1, src2; - - src1 = gen_load_fpr_F(dc, rs1); - src2 = gen_load_fpr_F(dc, rs2); - dst = gen_dest_fpr_F(dc); - - gen(dst, src1, src2); - - gen_store_fpr_F(dc, rd, dst); -} -#endif - static void gen_fop_DD(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64)) { @@ -4839,6 +4823,35 @@ TRANS(FABSd, 64, do_dd, a, gen_helper_fabsd) TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64) TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64) +static bool do_fff(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + src1 = gen_load_fpr_F(dc, a->rs1); + src2 = gen_load_fpr_F(dc, a->rs2); + func(src1, src1, src2); + gen_store_fpr_F(dc, a->rd, src1); + return advance_pc(dc); +} + +TRANS(FPADD16s, VIS1, do_fff, a, tcg_gen_vec_add16_i32) +TRANS(FPADD32s, VIS1, do_fff, a, tcg_gen_add_i32) +TRANS(FPSUB16s, VIS1, do_fff, a, tcg_gen_vec_sub16_i32) +TRANS(FPSUB32s, VIS1, do_fff, a, tcg_gen_sub_i32) +TRANS(FNORs, VIS1, do_fff, a, tcg_gen_nor_i32) +TRANS(FANDNOTs, VIS1, do_fff, a, tcg_gen_andc_i32) +TRANS(FXORs, VIS1, do_fff, a, tcg_gen_xor_i32) +TRANS(FNANDs, VIS1, do_fff, a, tcg_gen_nand_i32) +TRANS(FANDs, VIS1, do_fff, a, tcg_gen_and_i32) +TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32) +TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32) +TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5211,6 +5224,20 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x06a: /* VIS I fnot1 */ case 0x074: /* VIS I fsrc1 */ case 0x078: /* VIS I fsrc2 */ + case 0x051: /* VIS I fpadd16s */ + case 0x053: /* VIS I fpadd32s */ + case 0x055: /* VIS I fpsub16s */ + case 0x057: /* VIS I fpsub32s */ + case 0x063: /* VIS I fnors */ + case 0x065: /* VIS I fandnot2s */ + case 0x069: /* VIS I fandnot1s */ + case 0x06d: /* VIS I fxors */ + case 0x06f: /* VIS I fnands */ + case 0x071: /* VIS I fands */ + case 0x073: /* VIS I fxnors */ + case 0x077: /* VIS I fornot2s */ + case 0x07b: /* VIS I fornot1s */ + case 0x07d: /* VIS I fors */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5338,34 +5365,18 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add16_i64); break; - case 0x051: /* VIS I fpadd16s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_add16_i32); - break; case 0x052: /* VIS I fpadd32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64); break; - case 0x053: /* VIS I fpadd32s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_add_i32); - break; case 0x054: /* VIS I fpsub16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i64); break; - case 0x055: /* VIS I fpsub16s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i32); - break; case 0x056: /* VIS I fpsub32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64); break; - case 0x057: /* VIS I fpsub32s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_sub_i32); - break; case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 = gen_dest_fpr_D(dc, rd); @@ -5382,83 +5393,42 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64); break; - case 0x063: /* VIS I fnors */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nor_i32); - break; case 0x064: /* VIS I fandnot2 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64); break; - case 0x065: /* VIS I fandnot2s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32); - break; case 0x068: /* VIS I fandnot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); break; - case 0x069: /* VIS I fandnot1s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32); - break; case 0x06c: /* VIS I fxor */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); break; - case 0x06d: /* VIS I fxors */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_xor_i32); - break; case 0x06e: /* VIS I fnand */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64); break; - case 0x06f: /* VIS I fnands */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_nand_i32); - break; case 0x070: /* VIS I fand */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64); break; - case 0x071: /* VIS I fands */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_and_i32); - break; case 0x072: /* VIS I fxnor */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64); break; - case 0x073: /* VIS I fxnors */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32); - break; - break; case 0x076: /* VIS I fornot2 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64); break; - case 0x077: /* VIS I fornot2s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32); - break; case 0x07a: /* VIS I fornot1 */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); break; - case 0x07b: /* VIS I fornot1s */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_orc_i32); - break; case 0x07c: /* VIS I for */ CHECK_FPU_FEATURE(dc, VIS1); gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64); break; - case 0x07d: /* VIS I fors */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_or_i32); - break; case 0x07e: /* VIS I fone */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 = gen_dest_fpr_D(dc, rd); From patchwork Fri Oct 13 21:28:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733331 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680365wrv; Fri, 13 Oct 2023 14:38:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEHU2B+xaXd+9CyLrVWcgi0MOWEUOluPkqBwHdRuZ254DVZQR30NDZAdnzo9YNEq+aOFsAM X-Received: by 2002:a05:6808:cd:b0:3a8:7c67:7cd with SMTP id t13-20020a05680800cd00b003a87c6707cdmr29165817oic.24.1697233114065; Fri, 13 Oct 2023 14:38:34 -0700 (PDT) ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 62/85] target/sparc: Move gen_ne_fop_DDD insns to decodetree Date: Fri, 13 Oct 2023 14:28:23 -0700 Message-Id: <20231013212846.165724-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2b; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move FMUL8x16, FMUL8x16AU, FMUL8x16AL, FMUL8SUx16, FMUL8ULx16, FMULD8SUx16, FMULD8ULx16, FPMERGE, FEXPAND, FANDNOT1d, FANDNOT2d, FANDd, FNANDd, FNORd, FORNOT1d, FORNOT2d, FORd, FPADD16d, FPADD32d, FPSUB16d, FPSUB32d, FXNORd, FXORd. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 26 ++++++ target/sparc/translate.c | 178 +++++++++++++++----------------------- 2 files changed, 98 insertions(+), 106 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 96ba61865a..576349a719 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -264,6 +264,17 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r + FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r + FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r + FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r + FMUL8SUx16 10 ..... 110110 ..... 0 0011 0110 ..... @r_r_r + FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r + FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r + FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r + + FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r + FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r + FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d @@ -273,19 +284,34 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s + FPADD16 10 ..... 110110 ..... 0 0101 0000 ..... @r_r_r FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r + FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @r_r_r FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r + FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @r_r_r FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r + FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @r_r_r FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r + + FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @r_r_r FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r + FANDNOTd 10 ..... 110110 ..... 0 0110 0100 ..... @r_r_r # FANDNOT2d FANDNOTs 10 ..... 110110 ..... 0 0110 0101 ..... @r_r_r # FANDNOT2s + FANDNOTd 10 ..... 110110 ..... 0 0110 1000 ..... @r_r_r_swap # ... 1d FANDNOTs 10 ..... 110110 ..... 0 0110 1001 ..... @r_r_r_swap # ... 1s + FXORd 10 ..... 110110 ..... 0 0110 1100 ..... @r_r_r FXORs 10 ..... 110110 ..... 0 0110 1101 ..... @r_r_r + FNANDd 10 ..... 110110 ..... 0 0110 1110 ..... @r_r_r FNANDs 10 ..... 110110 ..... 0 0110 1111 ..... @r_r_r + FANDd 10 ..... 110110 ..... 0 0111 0000 ..... @r_r_r FANDs 10 ..... 110110 ..... 0 0111 0001 ..... @r_r_r + FXNORd 10 ..... 110110 ..... 0 0111 0010 ..... @r_r_r FXNORs 10 ..... 110110 ..... 0 0111 0011 ..... @r_r_r + FORNOTd 10 ..... 110110 ..... 0 0111 0110 ..... @r_r_r # FORNOT2d FORNOTs 10 ..... 110110 ..... 0 0111 0111 ..... @r_r_r # FORNOT2s + FORNOTd 10 ..... 110110 ..... 0 0111 1010 ..... @r_r_r_swap # ... 1d FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # ... 1s + FORd 10 ..... 110110 ..... 0 0111 1100 ..... @r_r_r FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 30329b94dd..8b16772a71 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -59,6 +59,15 @@ #define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() #define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() +#define gen_helper_fmul8x16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmul8x16au ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmul8x16al ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmul8sux16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmul8ulx16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmuld8sux16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fmuld8ulx16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fpmerge ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fexpand ({ g_assert_not_reached(); NULL; }) #define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; }) #define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; }) # ifdef CONFIG_USER_ONLY @@ -1527,20 +1536,6 @@ static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, } #ifdef TARGET_SPARC64 -static void gen_ne_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 dst, src1, src2; - - src1 = gen_load_fpr_D(dc, rs1); - src2 = gen_load_fpr_D(dc, rs2); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, src1, src2); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -4852,6 +4847,46 @@ TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32) TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32) TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32) +static bool do_ddd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 dst, src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = gen_dest_fpr_D(dc, a->rd); + src1 = gen_load_fpr_D(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + func(dst, src1, src2); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FMUL8x16, VIS1, do_ddd, a, gen_helper_fmul8x16) +TRANS(FMUL8x16AU, VIS1, do_ddd, a, gen_helper_fmul8x16au) +TRANS(FMUL8x16AL, VIS1, do_ddd, a, gen_helper_fmul8x16al) +TRANS(FMUL8SUx16, VIS1, do_ddd, a, gen_helper_fmul8sux16) +TRANS(FMUL8ULx16, VIS1, do_ddd, a, gen_helper_fmul8ulx16) +TRANS(FMULD8SUx16, VIS1, do_ddd, a, gen_helper_fmuld8sux16) +TRANS(FMULD8ULx16, VIS1, do_ddd, a, gen_helper_fmuld8ulx16) +TRANS(FPMERGE, VIS1, do_ddd, a, gen_helper_fpmerge) +TRANS(FEXPAND, VIS1, do_ddd, a, gen_helper_fexpand) + +TRANS(FPADD16, VIS1, do_ddd, a, tcg_gen_vec_add16_i64) +TRANS(FPADD32, VIS1, do_ddd, a, tcg_gen_vec_add32_i64) +TRANS(FPSUB16, VIS1, do_ddd, a, tcg_gen_vec_sub16_i64) +TRANS(FPSUB32, VIS1, do_ddd, a, tcg_gen_vec_sub32_i64) +TRANS(FNORd, VIS1, do_ddd, a, tcg_gen_nor_i64) +TRANS(FANDNOTd, VIS1, do_ddd, a, tcg_gen_andc_i64) +TRANS(FXORd, VIS1, do_ddd, a, tcg_gen_xor_i64) +TRANS(FNANDd, VIS1, do_ddd, a, tcg_gen_nand_i64) +TRANS(FANDd, VIS1, do_ddd, a, tcg_gen_and_i64) +TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64) +TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64) +TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5238,6 +5273,29 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x077: /* VIS I fornot2s */ case 0x07b: /* VIS I fornot1s */ case 0x07d: /* VIS I fors */ + case 0x050: /* VIS I fpadd16 */ + case 0x052: /* VIS I fpadd32 */ + case 0x054: /* VIS I fpsub16 */ + case 0x056: /* VIS I fpsub32 */ + case 0x062: /* VIS I fnor */ + case 0x064: /* VIS I fandnot2 */ + case 0x068: /* VIS I fandnot1 */ + case 0x06c: /* VIS I fxor */ + case 0x06e: /* VIS I fnand */ + case 0x070: /* VIS I fand */ + case 0x072: /* VIS I fxnor */ + case 0x076: /* VIS I fornot2 */ + case 0x07a: /* VIS I fornot1 */ + case 0x07c: /* VIS I for */ + case 0x031: /* VIS I fmul8x16 */ + case 0x033: /* VIS I fmul8x16au */ + case 0x035: /* VIS I fmul8x16al */ + case 0x036: /* VIS I fmul8sux16 */ + case 0x037: /* VIS I fmul8ulx16 */ + case 0x038: /* VIS I fmuld8sux16 */ + case 0x039: /* VIS I fmuld8ulx16 */ + case 0x04b: /* VIS I fpmerge */ + case 0x04d: /* VIS I fexpand */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5295,34 +5353,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); gen_store_gpr(dc, rd, cpu_dst); break; - case 0x031: /* VIS I fmul8x16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16); - break; - case 0x033: /* VIS I fmul8x16au */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16au); - break; - case 0x035: /* VIS I fmul8x16al */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8x16al); - break; - case 0x036: /* VIS I fmul8sux16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8sux16); - break; - case 0x037: /* VIS I fmul8ulx16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmul8ulx16); - break; - case 0x038: /* VIS I fmuld8sux16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8sux16); - break; - case 0x039: /* VIS I fmuld8ulx16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld8ulx16); - break; case 0x03a: /* VIS I fpack32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32); @@ -5349,34 +5379,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, VIS1); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); break; - case 0x04b: /* VIS I fpmerge */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpmerge); - break; case 0x04c: /* VIS II bshuffle */ CHECK_FPU_FEATURE(dc, VIS2); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); break; - case 0x04d: /* VIS I fexpand */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, gen_helper_fexpand); - break; - case 0x050: /* VIS I fpadd16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add16_i64); - break; - case 0x052: /* VIS I fpadd32 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64); - break; - case 0x054: /* VIS I fpsub16 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_sub16_i64); - break; - case 0x056: /* VIS I fpsub32 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_vec_add32_i64); - break; case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 = gen_dest_fpr_D(dc, rd); @@ -5389,46 +5395,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) tcg_gen_movi_i32(cpu_dst_32, 0); gen_store_fpr_F(dc, rd, cpu_dst_32); break; - case 0x062: /* VIS I fnor */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nor_i64); - break; - case 0x064: /* VIS I fandnot2 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_andc_i64); - break; - case 0x068: /* VIS I fandnot1 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64); - break; - case 0x06c: /* VIS I fxor */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64); - break; - case 0x06e: /* VIS I fnand */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_nand_i64); - break; - case 0x070: /* VIS I fand */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_and_i64); - break; - case 0x072: /* VIS I fxnor */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_eqv_i64); - break; - case 0x076: /* VIS I fornot2 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_orc_i64); - break; - case 0x07a: /* VIS I fornot1 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64); - break; - case 0x07c: /* VIS I for */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_or_i64); - break; case 0x07e: /* VIS I fone */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 = gen_dest_fpr_D(dc, rd); From patchwork Fri Oct 13 21:28:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733324 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680197wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 63/85] target/sparc: Move PDIST to decodetree Date: Fri, 13 Oct 2023 14:28:24 -0700 Message-Id: <20231013212846.165724-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 41 +++++++++++++++++++++------------------ 2 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 576349a719..12db108a31 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -271,6 +271,7 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r + PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 8b16772a71..5da3170978 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -68,6 +68,7 @@ #define gen_helper_fmuld8ulx16 ({ g_assert_not_reached(); NULL; }) #define gen_helper_fpmerge ({ g_assert_not_reached(); NULL; }) #define gen_helper_fexpand ({ g_assert_not_reached(); NULL; }) +#define gen_helper_pdist ({ g_assert_not_reached(); NULL; }) #define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; }) #define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; }) # ifdef CONFIG_USER_ONLY @@ -1549,21 +1550,6 @@ static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } - -static void gen_ne_fop_DDDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 dst, src0, src1, src2; - - src1 = gen_load_fpr_D(dc, rs1); - src2 = gen_load_fpr_D(dc, rs2); - src0 = gen_load_fpr_D(dc, rd); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, src0, src1, src2); - - gen_store_fpr_D(dc, rd, dst); -} #endif static void gen_fop_QQ(DisasContext *dc, int rd, int rs, @@ -4887,6 +4873,26 @@ TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64) TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64) TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64) +static bool do_dddd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 dst, src0, src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = gen_dest_fpr_D(dc, a->rd); + src0 = gen_load_fpr_D(dc, a->rd); + src1 = gen_load_fpr_D(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + func(dst, src0, src1, src2); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5296,6 +5302,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x039: /* VIS I fmuld8ulx16 */ case 0x04b: /* VIS I fpmerge */ case 0x04d: /* VIS I fexpand */ + case 0x03e: /* VIS I pdist */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5371,10 +5378,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); gen_store_fpr_F(dc, rd, cpu_dst_32); break; - case 0x03e: /* VIS I pdist */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_ne_fop_DDDD(dc, rd, rs1, rs2, gen_helper_pdist); - break; case 0x048: /* VIS I faligndata */ CHECK_FPU_FEATURE(dc, VIS1); gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); From patchwork Fri Oct 13 21:28:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733293 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679176wrv; Fri, 13 Oct 2023 14:34:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGaTMRfAdixA/b6rVoO0GItXw+FgXA2CWgVOqmRa0Kp85KzDnUGNRVay520wf3S9ZDq3W85 X-Received: by 2002:a05:620a:134d:b0:774:111b:7fb8 with SMTP id c13-20020a05620a134d00b00774111b7fb8mr26186149qkl.73.1697232863660; Fri, 13 Oct 2023 14:34:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232863; cv=none; d=google.com; s=arc-20160816; b=CQX416T5BHZ1O/iZHe7h91Igw+kmPGV+5Xf4XGzEB5GqO9C7exLmOMSuv8nhUWOK5B 6pvrlr5oIjKEk8et9dX+6r/WVC0HI9JeSuX9aPDKDffwR6IBYvdy5xn/P71ZgJTGb75b yog3YJMc82sBxRpUfCIUt2rgiNaZ34Rn0/+HdkTrDv8w/iUEhVCQQ80RbQ5VJRqHNGxJ hlH90yHjsVbhX/0lLcsHjeRK6AO3PTFeHp0wCjKPxnQNdPrKgCvSYtlDWKcvkBdpvReM cU3fuks8XsS+XJjt321RZ9C81jUabC4fiBos8DJ4Zao8ruOIOuV+BtB3qtloDFycsepp kg7Q== ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 64/85] target/sparc: Move gen_gsr_fop_DDD insns to decodetree Date: Fri, 13 Oct 2023 14:28:25 -0700 Message-Id: <20231013212846.165724-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move FPACK32, FALIGNDATA, BSHUFFLE. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 101 ++++++++++++++++++++------------------ 2 files changed, 55 insertions(+), 49 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 12db108a31..541b95c2dd 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -271,9 +271,12 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FMUL8ULx16 10 ..... 110110 ..... 0 0011 0111 ..... @r_r_r FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r + FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r + FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @r_r_r + BSHUFFLE 10 ..... 110110 ..... 0 0100 1100 ..... @r_r_r FEXPAND 10 ..... 110110 ..... 0 0100 1101 ..... @r_r_r FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5da3170978..605a218255 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -686,6 +686,51 @@ static void gen_op_array32(TCGv dst, TCGv src1, TCGv src2) tcg_gen_shli_tl(dst, dst, 2); } +static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2) +{ +#ifdef TARGET_SPARC64 + gen_helper_fpack32(dst, cpu_gsr, src1, src2); +#else + g_assert_not_reached(); +#endif +} + +static void gen_op_faligndata(TCGv_i64 dst, TCGv_i64 s1, TCGv_i64 s2) +{ +#ifdef TARGET_SPARC64 + TCGv t1, t2, shift; + + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + shift = tcg_temp_new(); + + tcg_gen_andi_tl(shift, cpu_gsr, 7); + tcg_gen_shli_tl(shift, shift, 3); + tcg_gen_shl_tl(t1, s1, shift); + + /* + * A shift of 64 does not produce 0 in TCG. Divide this into a + * shift of (up to 63) followed by a constant shift of 1. + */ + tcg_gen_xori_tl(shift, shift, 63); + tcg_gen_shr_tl(t2, s2, shift); + tcg_gen_shri_tl(t2, t2, 1); + + tcg_gen_or_tl(dst, t1, t2); +#else + g_assert_not_reached(); +#endif +} + +static void gen_op_bshuffle(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2) +{ +#ifdef TARGET_SPARC64 + gen_helper_bshuffle(dst, cpu_gsr, src1, src2); +#else + g_assert_not_reached(); +#endif +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -1536,22 +1581,6 @@ static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } -#ifdef TARGET_SPARC64 -static void gen_gsr_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 dst, src1, src2; - - src1 = gen_load_fpr_D(dc, rs1); - src2 = gen_load_fpr_D(dc, rs2); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, cpu_gsr, src1, src2); - - gen_store_fpr_D(dc, rd, dst); -} -#endif - static void gen_fop_QQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr)) { @@ -2573,27 +2602,6 @@ static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr) tcg_gen_add_ptr(r_tsptr, r_tsptr, r_tl_tmp); } } - -static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) -{ - TCGv t1, t2, shift; - - t1 = tcg_temp_new(); - t2 = tcg_temp_new(); - shift = tcg_temp_new(); - - tcg_gen_andi_tl(shift, gsr, 7); - tcg_gen_shli_tl(shift, shift, 3); - tcg_gen_shl_tl(t1, s1, shift); - - /* A shift of 64 does not produce 0 in TCG. Divide this into a - shift of (up to 63) followed by a constant shift of 1. */ - tcg_gen_xori_tl(shift, shift, 63); - tcg_gen_shr_tl(t2, s2, shift); - tcg_gen_shri_tl(t2, t2, 1); - - tcg_gen_or_tl(dst, t1, t2); -} #endif static int extract_dfpreg(DisasContext *dc, int x) @@ -4873,6 +4881,10 @@ TRANS(FXNORd, VIS1, do_ddd, a, tcg_gen_eqv_i64) TRANS(FORNOTd, VIS1, do_ddd, a, tcg_gen_orc_i64) TRANS(FORd, VIS1, do_ddd, a, tcg_gen_or_i64) +TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32) +TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata) +TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle) + static bool do_dddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -5303,6 +5315,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x04b: /* VIS I fpmerge */ case 0x04d: /* VIS I fexpand */ case 0x03e: /* VIS I pdist */ + case 0x03a: /* VIS I fpack32 */ + case 0x048: /* VIS I faligndata */ + case 0x04c: /* VIS II bshuffle */ g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ CHECK_FPU_FEATURE(dc, VIS1); @@ -5360,10 +5375,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); gen_store_gpr(dc, rd, cpu_dst); break; - case 0x03a: /* VIS I fpack32 */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_fpack32); - break; case 0x03b: /* VIS I fpack16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 = gen_load_fpr_D(dc, rs2); @@ -5378,14 +5389,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); gen_store_fpr_F(dc, rd, cpu_dst_32); break; - case 0x048: /* VIS I faligndata */ - CHECK_FPU_FEATURE(dc, VIS1); - gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); - break; - case 0x04c: /* VIS II bshuffle */ - CHECK_FPU_FEATURE(dc, VIS2); - gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_helper_bshuffle); - break; case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); cpu_dst_64 = gen_dest_fpr_D(dc, rd); From patchwork Fri Oct 13 21:28:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733328 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680310wrv; Fri, 13 Oct 2023 14:38:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEqpvLXqD1yc162jJEbDCL3aVKRF97oW8T3Ump56Ge8ozYQLylT9Lo7RrwVIcKZCy6NQ8bS X-Received: by 2002:a05:622a:15cd:b0:400:926f:4585 with SMTP id d13-20020a05622a15cd00b00400926f4585mr33651784qty.66.1697233100470; Fri, 13 Oct 2023 14:38:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233100; cv=none; d=google.com; s=arc-20160816; b=lmD9hFv16Nsq2DF6vcY++KEDxXPeDvNI3ACZ+Tv2cPL9M8yO0KBV7rmI+wwsyiZ8DG XwggqZ0t+cq8xEnMBvX2HDdCjnlVCtwGIGRuqLikF0gCL4ueH8P9Yn6gTue0AocCP2Ox CQidh8yH8z7SayYBXVagVhnfGxu7bdc5GJjiAmCWoLp5zb+8HSB3on6yI9n+mAgZYj95 OJh/g9m+nDes5ej8fp9OSFgUYDEQ+D4+0I/QPtDcG2g/g2JHl85ujfTuOhYYkB9g625S rfseaP8dwx194sNtXQI1yrqD8JLO2gy9VNJdAoLAps+OLiXiGOpmZzId0Cn03ZtjzgzZ eOAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2kTNjNuwiDDC9iwCgH8a1SDO2GFjbjTqvujftlbwQE4=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=UjhcqhCaOcpHsyN75KqubWFM+X0IBVmsI3muZxGlEtAceQbPdzBGr5oygv1ri8XAte 0YuMtwGEqjvSW62QNqqfohvV9HvrCj8kdRxJK4u7YfJLz7QvVP1A4kz2gBtA/362+f7b 5PmLgsPIZ60M8a7hHnqBV14vEegQfuz3AHkCMdLNwAjlS56sJRItfVKqLdLFZRDEwfU4 q9kRehBqW/AnyZvnZYLG7hrglLYZwGXlXo3+7Rud6NHl9H5FMqZVZoeQHQkvqFBDsQar B0Mv94s6RSLyIEgYxqYlFmRGe8M9c/RnLuk5sx8ZolH0CtKZognMD7K1a8bE3n8QkTiA Y+Og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eC0t5uDp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 65/85] target/sparc: Move gen_fop_FF insns to decodetree Date: Fri, 13 Oct 2023 14:28:26 -0700 Message-Id: <20231013212846.165724-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move FSQRTs, FiTOs, FsTOi. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 47 ++++++++++++++++++++------------------- 2 files changed, 27 insertions(+), 23 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 541b95c2dd..5dd05bb211 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -239,6 +239,9 @@ FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 +FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 +FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 +FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 { [ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 605a218255..bad929d2da 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1523,20 +1523,6 @@ static void gen_op_clear_ieee_excp_and_FTT(void) tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); } -static void gen_fop_FF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32)) -{ - TCGv_i32 dst, src; - - src = gen_load_fpr_F(dc, rs); - dst = gen_dest_fpr_F(dc); - - gen(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32)) { @@ -4790,6 +4776,27 @@ TRANS(FABSs, ALL, do_ff, a, gen_helper_fabss) TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) +static bool do_env_ff(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + tmp = gen_load_fpr_F(dc, a->rs); + func(tmp, tcg_env, tmp); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_F(dc, a->rd, tmp); + return advance_pc(dc); +} + +TRANS(FSQRTs, ALL, do_env_ff, a, gen_helper_fsqrts) +TRANS(FiTOs, ALL, do_env_ff, a, gen_helper_fitos) +TRANS(FsTOi, ALL, do_env_ff, a, gen_helper_fstoi) + static bool do_dd(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_i64, TCGv_i64)) { @@ -4951,10 +4958,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x2: /* V9 fmovd */ case 0x6: /* V9 fnegd */ case 0xa: /* V9 fabsd */ - g_assert_not_reached(); /* in decodetree */ case 0x29: /* fsqrts */ - gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts); - break; + case 0xc4: /* fitos */ + case 0xd1: /* fstoi */ + g_assert_not_reached(); /* in decodetree */ case 0x2a: /* fsqrtd */ gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); break; @@ -5010,9 +5017,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq); break; - case 0xc4: /* fitos */ - gen_fop_FF(dc, rd, rs2, gen_helper_fitos); - break; case 0xc6: /* fdtos */ gen_fop_FD(dc, rd, rs2, gen_helper_fdtos); break; @@ -5042,9 +5046,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); break; - case 0xd1: /* fstoi */ - gen_fop_FF(dc, rd, rs2, gen_helper_fstoi); - break; case 0xd2: /* fdtoi */ gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi); break; From patchwork Fri Oct 13 21:28:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733285 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678967wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 66/85] target/sparc: Move gen_fop_DD insns to decodetree Date: Fri, 13 Oct 2023 14:28:27 -0700 Message-Id: <20231013212846.165724-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move FSQRTd, FxTOd, FdTOx. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 50 +++++++++++++++++++++------------------ 2 files changed, 30 insertions(+), 23 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5dd05bb211..d3badc6db3 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -240,6 +240,9 @@ FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 +FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 +FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 +FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bad929d2da..23b287cd38 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -55,6 +55,8 @@ #define gen_helper_restored ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fnegd ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fabsd ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_fdtox ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_fxtod ({ qemu_build_not_reached(); NULL; }) #define gen_helper_done(E) qemu_build_not_reached() #define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() @@ -1538,20 +1540,6 @@ static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_F(dc, rd, dst); } -static void gen_fop_DD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64)) -{ - TCGv_i64 dst, src; - - src = gen_load_fpr_D(dc, rs); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64)) { @@ -4819,6 +4807,28 @@ TRANS(FABSd, 64, do_dd, a, gen_helper_fabsd) TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64) TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64) +static bool do_env_dd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) +{ + TCGv_i64 dst, src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + dst = gen_dest_fpr_D(dc, a->rd); + src = gen_load_fpr_D(dc, a->rs); + func(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd) +TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod) +TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -4961,10 +4971,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x29: /* fsqrts */ case 0xc4: /* fitos */ case 0xd1: /* fstoi */ - g_assert_not_reached(); /* in decodetree */ case 0x2a: /* fsqrtd */ - gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); - break; + case 0x82: /* V9 fdtox */ + case 0x88: /* V9 fxtod */ + g_assert_not_reached(); /* in decodetree */ case 0x2b: /* fsqrtq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq); @@ -5069,9 +5079,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x81: /* V9 fstox */ gen_fop_DF(dc, rd, rs2, gen_helper_fstox); break; - case 0x82: /* V9 fdtox */ - gen_fop_DD(dc, rd, rs2, gen_helper_fdtox); - break; case 0x83: /* V9 fqtox */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); @@ -5079,9 +5086,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x84: /* V9 fxtos */ gen_fop_FD(dc, rd, rs2, gen_helper_fxtos); break; - case 0x88: /* V9 fxtod */ - gen_fop_DD(dc, rd, rs2, gen_helper_fxtod); - break; case 0x8c: /* V9 fxtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); From patchwork Fri Oct 13 21:28:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733299 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679327wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 67/85] target/sparc: Move FSQRTq to decodetree Date: Fri, 13 Oct 2023 14:28:28 -0700 Message-Id: <20231013212846.165724-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 39 +++++++++++++++++++++++---------------- 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d3badc6db3..31d84f0cb3 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -241,6 +241,7 @@ FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 +FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 23b287cd38..d318c8a6e3 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -71,6 +71,7 @@ #define gen_helper_fpmerge ({ g_assert_not_reached(); NULL; }) #define gen_helper_fexpand ({ g_assert_not_reached(); NULL; }) #define gen_helper_pdist ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fsqrtq ({ g_assert_not_reached(); NULL; }) #define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; }) #define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; }) # ifdef CONFIG_USER_ONLY @@ -1555,18 +1556,6 @@ static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } -static void gen_fop_QQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr)) -{ - gen_op_load_fpr_QT1(QFPREG(rs)); - - gen(tcg_env); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - #ifdef TARGET_SPARC64 static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr)) @@ -4829,6 +4818,27 @@ TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd) TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod) TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox) +static bool do_env_qq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_env)) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT1(QFPREG(a->rs)); + func(tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FSQRTq, ALL, do_env_qq, a, gen_helper_fsqrtq) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -4974,11 +4984,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x2a: /* fsqrtd */ case 0x82: /* V9 fdtox */ case 0x88: /* V9 fxtod */ - g_assert_not_reached(); /* in decodetree */ case 0x2b: /* fsqrtq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq); - break; + g_assert_not_reached(); /* in decodetree */ case 0x41: /* fadds */ gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds); break; From patchwork Fri Oct 13 21:28:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733288 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679049wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 68/85] target/sparc: Move gen_fop_FFF insns to decodetree Date: Fri, 13 Oct 2023 14:28:29 -0700 Message-Id: <20231013212846.165724-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move FADDs, FSUBs, FMULs, FDIVs. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 54 +++++++++++++++++++-------------------- 2 files changed, 31 insertions(+), 27 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 31d84f0cb3..fcf4704ef8 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -242,6 +242,10 @@ FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 +FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r +FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r +FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r +FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d318c8a6e3..9d68c8cc20 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1526,21 +1526,6 @@ static void gen_op_clear_ieee_excp_and_FTT(void) tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); } -static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32)) -{ - TCGv_i32 dst, src1, src2; - - src1 = gen_load_fpr_F(dc, rs1); - src2 = gen_load_fpr_F(dc, rs2); - dst = gen_dest_fpr_F(dc); - - gen(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64)) { @@ -4868,6 +4853,29 @@ TRANS(FXNORs, VIS1, do_fff, a, tcg_gen_eqv_i32) TRANS(FORNOTs, VIS1, do_fff, a, tcg_gen_orc_i32) TRANS(FORs, VIS1, do_fff, a, tcg_gen_or_i32) +static bool do_env_fff(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src1 = gen_load_fpr_F(dc, a->rs1); + src2 = gen_load_fpr_F(dc, a->rs2); + func(src1, tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_F(dc, a->rd, src1); + return advance_pc(dc); +} + +TRANS(FADDs, ALL, do_env_fff, a, gen_helper_fadds) +TRANS(FSUBs, ALL, do_env_fff, a, gen_helper_fsubs) +TRANS(FMULs, ALL, do_env_fff, a, gen_helper_fmuls) +TRANS(FDIVs, ALL, do_env_fff, a, gen_helper_fdivs) + static bool do_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -4985,10 +4993,11 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x82: /* V9 fdtox */ case 0x88: /* V9 fxtod */ case 0x2b: /* fsqrtq */ - g_assert_not_reached(); /* in decodetree */ case 0x41: /* fadds */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds); - break; + case 0x45: /* fsubs */ + case 0x49: /* fmuls */ + case 0x4d: /* fdivs */ + g_assert_not_reached(); /* in decodetree */ case 0x42: /* faddd */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd); break; @@ -4996,9 +5005,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); break; - case 0x45: /* fsubs */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fsubs); - break; case 0x46: /* fsubd */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd); break; @@ -5006,9 +5012,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); break; - case 0x49: /* fmuls */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fmuls); - break; case 0x4a: /* fmuld */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); break; @@ -5016,9 +5019,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); break; - case 0x4d: /* fdivs */ - gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fdivs); - break; case 0x4e: /* fdivd */ gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd); break; From patchwork Fri Oct 13 21:28:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733286 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679010wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 69/85] target/sparc: Move gen_fop_DDD insns to decodetree Date: Fri, 13 Oct 2023 14:28:30 -0700 Message-Id: <20231013212846.165724-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move FADDd, FSUBd, FMULd, FDIVd. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 55 ++++++++++++++++++++------------------- 2 files changed, 32 insertions(+), 27 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index fcf4704ef8..5c7b918462 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -243,9 +243,13 @@ FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r +FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r +FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r +FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r +FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9d68c8cc20..b7e0207405 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1526,21 +1526,6 @@ static void gen_op_clear_ieee_excp_and_FTT(void) tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); } -static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 dst, src1, src2; - - src1 = gen_load_fpr_D(dc, rs1); - src2 = gen_load_fpr_D(dc, rs2); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} - #ifdef TARGET_SPARC64 static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr)) @@ -4920,6 +4905,30 @@ TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32) TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata) TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle) +static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) +{ + TCGv_i64 dst, src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + dst = gen_dest_fpr_D(dc, a->rd); + src1 = gen_load_fpr_D(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + func(dst, tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FADDd, ALL, do_env_ddd, a, gen_helper_faddd) +TRANS(FSUBd, ALL, do_env_ddd, a, gen_helper_fsubd) +TRANS(FMULd, ALL, do_env_ddd, a, gen_helper_fmuld) +TRANS(FDIVd, ALL, do_env_ddd, a, gen_helper_fdivd) + static bool do_dddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -4997,31 +5006,23 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x45: /* fsubs */ case 0x49: /* fmuls */ case 0x4d: /* fdivs */ - g_assert_not_reached(); /* in decodetree */ case 0x42: /* faddd */ - gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_faddd); - break; + case 0x46: /* fsubd */ + case 0x4a: /* fmuld */ + case 0x4e: /* fdivd */ + g_assert_not_reached(); /* in decodetree */ case 0x43: /* faddq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); break; - case 0x46: /* fsubd */ - gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fsubd); - break; case 0x47: /* fsubq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); break; - case 0x4a: /* fmuld */ - gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fmuld); - break; case 0x4b: /* fmulq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); break; - case 0x4e: /* fdivd */ - gen_fop_DDD(dc, rd, rs1, rs2, gen_helper_fdivd); - break; case 0x4f: /* fdivq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq); From patchwork Fri Oct 13 21:28:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733309 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679761wrv; Fri, 13 Oct 2023 14:36:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGAzXDh2MI/tgvy7xmZnvCf0WzODIRDQJfzwEGvMofXCyU/zH3hjTPE9NexXMJ61lL2I4fj X-Received: by 2002:ac8:5a83:0:b0:417:9994:eb75 with SMTP id c3-20020ac85a83000000b004179994eb75mr30038605qtc.21.1697232984696; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 70/85] target/sparc: Move gen_fop_QQQ insns to decodetree Date: Fri, 13 Oct 2023 14:28:31 -0700 Message-Id: <20231013212846.165724-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move FADDq, FSUBq, FMULq, FDIVq. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 52 +++++++++++++++++++-------------------- 2 files changed, 30 insertions(+), 26 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5c7b918462..036e2b01d4 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -244,12 +244,16 @@ FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 FADDs 10 ..... 110100 ..... 0 0100 0001 ..... @r_r_r FADDd 10 ..... 110100 ..... 0 0100 0010 ..... @r_r_r +FADDq 10 ..... 110100 ..... 0 0100 0011 ..... @r_r_r FSUBs 10 ..... 110100 ..... 0 0100 0101 ..... @r_r_r FSUBd 10 ..... 110100 ..... 0 0100 0110 ..... @r_r_r +FSUBq 10 ..... 110100 ..... 0 0100 0111 ..... @r_r_r FMULs 10 ..... 110100 ..... 0 0100 1001 ..... @r_r_r FMULd 10 ..... 110100 ..... 0 0100 1010 ..... @r_r_r +FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @r_r_r FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r +FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b7e0207405..3446821a50 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1539,19 +1539,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, } #endif -static void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_ptr)) -{ - gen_op_load_fpr_QT0(QFPREG(rs1)); - gen_op_load_fpr_QT1(QFPREG(rs2)); - - gen(tcg_env); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - static void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32)) { @@ -4949,6 +4936,31 @@ static bool do_dddd(DisasContext *dc, arg_r_r_r *a, TRANS(PDIST, VIS1, do_dddd, a, gen_helper_pdist) +static bool do_env_qqq(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_env)) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT0(QFPREG(a->rs1)); + gen_op_load_fpr_QT1(QFPREG(a->rs2)); + func(tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FADDq, ALL, do_env_qqq, a, gen_helper_faddq) +TRANS(FSUBq, ALL, do_env_qqq, a, gen_helper_fsubq) +TRANS(FMULq, ALL, do_env_qqq, a, gen_helper_fmulq) +TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5010,23 +5022,11 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x46: /* fsubd */ case 0x4a: /* fmuld */ case 0x4e: /* fdivd */ - g_assert_not_reached(); /* in decodetree */ case 0x43: /* faddq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_faddq); - break; case 0x47: /* fsubq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fsubq); - break; case 0x4b: /* fmulq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fmulq); - break; case 0x4f: /* fdivq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQQ(dc, rd, rs1, rs2, gen_helper_fdivq); - break; + g_assert_not_reached(); /* in decodetree */ case 0x69: /* fsmuld */ CHECK_FPU_FEATURE(dc, FSMULD); gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld); From patchwork Fri Oct 13 21:28:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733315 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679934wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 71/85] target/sparc: Move FSMULD to decodetree Date: Fri, 13 Oct 2023 14:28:32 -0700 Message-Id: <20231013212846.165724-72-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 43 +++++++++++++++++++++------------------ 2 files changed, 24 insertions(+), 20 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 036e2b01d4..a52fac9352 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -254,6 +254,7 @@ FMULq 10 ..... 110100 ..... 0 0100 1011 ..... @r_r_r FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r +FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 3446821a50..4b37a171ff 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1539,22 +1539,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, } #endif -static void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32, TCGv_i32)) -{ - TCGv_i64 dst; - TCGv_i32 src1, src2; - - src1 = gen_load_fpr_F(dc, rs1); - src2 = gen_load_fpr_F(dc, rs2); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64)) { @@ -4916,6 +4900,28 @@ TRANS(FSUBd, ALL, do_env_ddd, a, gen_helper_fsubd) TRANS(FMULd, ALL, do_env_ddd, a, gen_helper_fmuld) TRANS(FDIVd, ALL, do_env_ddd, a, gen_helper_fdivd) +static bool trans_FsMULd(DisasContext *dc, arg_r_r_r *a) +{ + TCGv_i64 dst; + TCGv_i32 src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (!(dc->def->features & CPU_FEATURE_FSMULD)) { + return raise_unimpfpop(dc); + } + + gen_op_clear_ieee_excp_and_FTT(); + dst = gen_dest_fpr_D(dc, a->rd); + src1 = gen_load_fpr_F(dc, a->rs1); + src2 = gen_load_fpr_F(dc, a->rs2); + gen_helper_fsmuld(dst, tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + static bool do_dddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64)) { @@ -5026,11 +5032,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x47: /* fsubq */ case 0x4b: /* fmulq */ case 0x4f: /* fdivq */ - g_assert_not_reached(); /* in decodetree */ case 0x69: /* fsmuld */ - CHECK_FPU_FEATURE(dc, FSMULD); - gen_fop_DFF(dc, rd, rs1, rs2, gen_helper_fsmuld); - break; + g_assert_not_reached(); /* in decodetree */ case 0x6e: /* fdmulq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq); From patchwork Fri Oct 13 21:28:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733294 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679197wrv; Fri, 13 Oct 2023 14:34:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGFFBUMWaPsZqxP9iMH29r8j9ff64tlxAxIgVnYdMDU63W8WIK/rPuPq7l7bEm9elOGTf+N X-Received: by 2002:a1f:c541:0:b0:49e:2145:1654 with SMTP id v62-20020a1fc541000000b0049e21451654mr15208034vkf.7.1697232868035; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 72/85] target/sparc: Move FDMULQ to decodetree Date: Fri, 13 Oct 2023 14:28:33 -0700 Message-Id: <20231013212846.165724-73-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 41 +++++++++++++++++++++------------------ 2 files changed, 23 insertions(+), 19 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index a52fac9352..4063695cd9 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -255,6 +255,7 @@ FDIVs 10 ..... 110100 ..... 0 0100 1101 ..... @r_r_r FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r +FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 4b37a171ff..b0efcb4551 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1539,21 +1539,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, } #endif -static void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2, - void (*gen)(TCGv_ptr, TCGv_i64, TCGv_i64)) -{ - TCGv_i64 src1, src2; - - src1 = gen_load_fpr_D(dc, rs1); - src2 = gen_load_fpr_D(dc, rs2); - - gen(tcg_env, src1, src2); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - #ifdef TARGET_SPARC64 static void gen_fop_DF(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) @@ -4967,6 +4952,27 @@ TRANS(FSUBq, ALL, do_env_qqq, a, gen_helper_fsubq) TRANS(FMULq, ALL, do_env_qqq, a, gen_helper_fmulq) TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq) +static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a) +{ + TCGv_i64 src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src1 = gen_load_fpr_D(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + gen_helper_fdmulq(tcg_env, src1, src2); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5033,11 +5039,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x4b: /* fmulq */ case 0x4f: /* fdivq */ case 0x69: /* fsmuld */ - g_assert_not_reached(); /* in decodetree */ case 0x6e: /* fdmulq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QDD(dc, rd, rs1, rs2, gen_helper_fdmulq); - break; + g_assert_not_reached(); /* in decodetree */ case 0xc6: /* fdtos */ gen_fop_FD(dc, rd, rs2, gen_helper_fdtos); break; From patchwork Fri Oct 13 21:28:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733284 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1678945wrv; Fri, 13 Oct 2023 14:33:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE+FmtYcTeZY/BoHrE6NA0rEUcXeD/58kp0vw7lHcceOqtR13TdTo4aFV4Hj5CXRN/rlzax X-Received: by 2002:a81:5b82:0:b0:594:e97b:f6fa with SMTP id p124-20020a815b82000000b00594e97bf6famr33279402ywb.30.1697232815139; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 73/85] target/sparc: Move gen_fop_FD insns to decodetree Date: Fri, 13 Oct 2023 14:28:34 -0700 Message-Id: <20231013212846.165724-74-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::d2b; envelope-from=richard.henderson@linaro.org; helo=mail-io1-xd2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move FdTOs, FdTOi, FxTOs. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 +++ target/sparc/translate.c | 51 +++++++++++++++++++++------------------ 2 files changed, 30 insertions(+), 24 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 4063695cd9..6378dc5d07 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -257,9 +257,12 @@ FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 +FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 +FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 +FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 { [ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b0efcb4551..c1a82b4c9a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -57,6 +57,7 @@ #define gen_helper_fabsd ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fdtox ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fxtod ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_fxtos ({ qemu_build_not_reached(); NULL; }) #define gen_helper_done(E) qemu_build_not_reached() #define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() @@ -1570,21 +1571,6 @@ static void gen_ne_fop_DF(DisasContext *dc, int rd, int rs, gen_store_fpr_D(dc, rd, dst); } -static void gen_fop_FD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_ptr, TCGv_i64)) -{ - TCGv_i32 dst; - TCGv_i64 src; - - src = gen_load_fpr_D(dc, rs); - dst = gen_dest_fpr_F(dc); - - gen(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_FQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i32, TCGv_ptr)) { @@ -4700,6 +4686,29 @@ TRANS(FSQRTs, ALL, do_env_ff, a, gen_helper_fsqrts) TRANS(FiTOs, ALL, do_env_ff, a, gen_helper_fitos) TRANS(FsTOi, ALL, do_env_ff, a, gen_helper_fstoi) +static bool do_env_fd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_env, TCGv_i64)) +{ + TCGv_i32 dst; + TCGv_i64 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + dst = gen_dest_fpr_F(dc); + src = gen_load_fpr_D(dc, a->rs); + func(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_F(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FdTOs, ALL, do_env_fd, a, gen_helper_fdtos) +TRANS(FdTOi, ALL, do_env_fd, a, gen_helper_fdtoi) +TRANS(FxTOs, 64, do_env_fd, a, gen_helper_fxtos) + static bool do_dd(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_i64, TCGv_i64)) { @@ -5040,10 +5049,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x4f: /* fdivq */ case 0x69: /* fsmuld */ case 0x6e: /* fdmulq */ - g_assert_not_reached(); /* in decodetree */ case 0xc6: /* fdtos */ - gen_fop_FD(dc, rd, rs2, gen_helper_fdtos); - break; + case 0xd2: /* fdtoi */ + case 0x84: /* V9 fxtos */ + g_assert_not_reached(); /* in decodetree */ case 0xc7: /* fqtos */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos); @@ -5070,9 +5079,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); break; - case 0xd2: /* fdtoi */ - gen_fop_FD(dc, rd, rs2, gen_helper_fdtoi); - break; case 0xd3: /* fqtoi */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi); @@ -5097,9 +5103,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); break; - case 0x84: /* V9 fxtos */ - gen_fop_FD(dc, rd, rs2, gen_helper_fxtos); - break; case 0x8c: /* V9 fxtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); From patchwork Fri Oct 13 21:28:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733292 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679175wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 74/85] target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree Date: Fri, 13 Oct 2023 14:28:35 -0700 Message-Id: <20231013212846.165724-75-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Note that gen_ne_fop_DF was incorrectly named and does pass env. The two sets of helpers should have been unified. Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 ++ target/sparc/translate.c | 67 ++++++++++++++++----------------------- 2 files changed, 30 insertions(+), 40 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 6378dc5d07..4368ac25a9 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -256,11 +256,14 @@ FDIVd 10 ..... 110100 ..... 0 0100 1110 ..... @r_r_r FDIVq 10 ..... 110100 ..... 0 0100 1111 ..... @r_r_r FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r +FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2 FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 +FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2 +FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index c1a82b4c9a..1b1ac9b5f0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -56,6 +56,7 @@ #define gen_helper_fnegd ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fabsd ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fdtox ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_fstox ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fxtod ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fxtos ({ qemu_build_not_reached(); NULL; }) #define gen_helper_done(E) qemu_build_not_reached() @@ -1540,37 +1541,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, } #endif -#ifdef TARGET_SPARC64 -static void gen_fop_DF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) -{ - TCGv_i64 dst; - TCGv_i32 src; - - src = gen_load_fpr_F(dc, rs); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} -#endif - -static void gen_ne_fop_DF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i32)) -{ - TCGv_i64 dst; - TCGv_i32 src; - - src = gen_load_fpr_F(dc, rs); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_fop_FQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i32, TCGv_ptr)) { @@ -4753,6 +4723,29 @@ TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd) TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod) TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox) +static bool do_env_df(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i64, TCGv_env, TCGv_i32)) +{ + TCGv_i64 dst; + TCGv_i32 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + dst = gen_dest_fpr_D(dc, a->rd); + src = gen_load_fpr_F(dc, a->rs); + func(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FiTOd, ALL, do_env_df, a, gen_helper_fitod) +TRANS(FsTOd, ALL, do_env_df, a, gen_helper_fstod) +TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox) + static bool do_env_qq(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_env)) { @@ -5052,17 +5045,14 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0xc6: /* fdtos */ case 0xd2: /* fdtoi */ case 0x84: /* V9 fxtos */ + case 0xc8: /* fitod */ + case 0xc9: /* fstod */ + case 0x81: /* V9 fstox */ g_assert_not_reached(); /* in decodetree */ case 0xc7: /* fqtos */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos); break; - case 0xc8: /* fitod */ - gen_ne_fop_DF(dc, rd, rs2, gen_helper_fitod); - break; - case 0xc9: /* fstod */ - gen_ne_fop_DF(dc, rd, rs2, gen_helper_fstod); - break; case 0xcb: /* fqtod */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod); @@ -5096,9 +5086,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); break; - case 0x81: /* V9 fstox */ - gen_fop_DF(dc, rd, rs2, gen_helper_fstox); - break; case 0x83: /* V9 fqtox */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); From patchwork Fri Oct 13 21:28:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733305 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679649wrv; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 75/85] target/sparc: Move FqTOs, FqTOi to decodetree Date: Fri, 13 Oct 2023 14:28:36 -0700 Message-Id: <20231013212846.165724-76-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 48 +++++++++++++++++++++------------------ 2 files changed, 28 insertions(+), 22 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 4368ac25a9..f38ea9b343 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -262,10 +262,12 @@ FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 +FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2 FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2 FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 +FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 { [ diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1b1ac9b5f0..ee12a8b9b7 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1541,20 +1541,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, } #endif -static void gen_fop_FQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i32, TCGv_ptr)) -{ - TCGv_i32 dst; - - gen_op_load_fpr_QT1(QFPREG(rs)); - dst = gen_dest_fpr_F(dc); - - gen(dst, tcg_env); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_F(dc, rd, dst); -} - static void gen_fop_DQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_i64, TCGv_ptr)) { @@ -4767,6 +4753,30 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, TRANS(FSQRTq, ALL, do_env_qq, a, gen_helper_fsqrtq) +static bool do_env_fq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_env)) +{ + TCGv_i32 dst; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT1(QFPREG(a->rs)); + dst = gen_dest_fpr_F(dc); + func(dst, tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_F(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FqTOs, ALL, do_env_fq, a, gen_helper_fqtos) +TRANS(FqTOi, ALL, do_env_fq, a, gen_helper_fqtoi) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -5048,11 +5058,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0xc8: /* fitod */ case 0xc9: /* fstod */ case 0x81: /* V9 fstox */ - g_assert_not_reached(); /* in decodetree */ case 0xc7: /* fqtos */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_FQ(dc, rd, rs2, gen_helper_fqtos); - break; + case 0xd3: /* fqtoi */ + g_assert_not_reached(); /* in decodetree */ case 0xcb: /* fqtod */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod); @@ -5069,10 +5077,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); break; - case 0xd3: /* fqtoi */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi); - break; #ifdef TARGET_SPARC64 case 0x3: /* V9 fmovq */ CHECK_FPU_FEATURE(dc, FLOAT128); From patchwork Fri Oct 13 21:28:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733329 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680321wrv; Fri, 13 Oct 2023 14:38:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHvcyZA/WMITAmLREt//MMXNAItN50tiQbd0kcj+JC66Er8hUYrjDl27oUjvhA9oGBgGVrm X-Received: by 2002:ac8:5905:0:b0:412:24e6:a492 with SMTP id 5-20020ac85905000000b0041224e6a492mr33324921qty.60.1697233102121; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 76/85] target/sparc: Move FqTOd, FqTOx to decodetree Date: Fri, 13 Oct 2023 14:28:37 -0700 Message-Id: <20231013212846.165724-77-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 49 +++++++++++++++++++++------------------ 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f38ea9b343..f30f2bc800 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -258,6 +258,7 @@ FsMULd 10 ..... 110100 ..... 0 0110 1001 ..... @r_r_r FdMULq 10 ..... 110100 ..... 0 0110 1110 ..... @r_r_r FsTOx 10 ..... 110100 00000 0 1000 0001 ..... @r_r2 FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 +FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_r2 FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 @@ -265,6 +266,7 @@ FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2 FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2 FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 +FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ee12a8b9b7..4446bc2e48 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -57,6 +57,7 @@ #define gen_helper_fabsd ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fdtox ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fstox ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_fqtox ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fxtod ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fxtos ({ qemu_build_not_reached(); NULL; }) #define gen_helper_done(E) qemu_build_not_reached() @@ -1541,20 +1542,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, } #endif -static void gen_fop_DQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr)) -{ - TCGv_i64 dst; - - gen_op_load_fpr_QT1(QFPREG(rs)); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr, TCGv_i32)) { @@ -4777,6 +4764,30 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, TRANS(FqTOs, ALL, do_env_fq, a, gen_helper_fqtos) TRANS(FqTOi, ALL, do_env_fq, a, gen_helper_fqtoi) +static bool do_env_dq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i64, TCGv_env)) +{ + TCGv_i64 dst; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT1(QFPREG(a->rs)); + dst = gen_dest_fpr_D(dc, a->rd); + func(dst, tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FqTOd, ALL, do_env_dq, a, gen_helper_fqtod) +TRANS(FqTOx, 64, do_env_dq, a, gen_helper_fqtox) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -5060,11 +5071,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x81: /* V9 fstox */ case 0xc7: /* fqtos */ case 0xd3: /* fqtoi */ - g_assert_not_reached(); /* in decodetree */ case 0xcb: /* fqtod */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_DQ(dc, rd, rs2, gen_helper_fqtod); - break; + case 0x83: /* V9 fqtox */ + g_assert_not_reached(); /* in decodetree */ case 0xcc: /* fitoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq); @@ -5090,10 +5099,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); break; - case 0x83: /* V9 fqtox */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); - break; case 0x8c: /* V9 fxtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); From patchwork Fri Oct 13 21:28:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733330 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680329wrv; Fri, 13 Oct 2023 14:38:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFsJ+BJI+gWzJHf7j3FR809bGpZRmXbLtKm1IYBWVsggXmoauc5mTJurRaTAz+DyLqKRk2C X-Received: by 2002:a05:6214:1808:b0:66c:fbad:5026 with SMTP id o8-20020a056214180800b0066cfbad5026mr2232127qvw.29.1697233104051; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 77/85] target/sparc: Move FiTOq, FsTOq to decodetree Date: Fri, 13 Oct 2023 14:28:38 -0700 Message-Id: <20231013212846.165724-78-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 44 +++++++++++++++++++++------------------ 2 files changed, 26 insertions(+), 20 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f30f2bc800..f0a6abb170 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -267,6 +267,8 @@ FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2 FiTOd 10 ..... 110100 00000 0 1100 1000 ..... @r_r2 FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @r_r2 +FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @r_r2 +FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 4446bc2e48..d6ae4431dc 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -1542,19 +1542,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, } #endif -static void gen_ne_fop_QF(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr, TCGv_i32)) -{ - TCGv_i32 src; - - src = gen_load_fpr_F(dc, rs); - - gen(tcg_env, src); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - static void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr, TCGv_i64)) { @@ -4788,6 +4775,29 @@ static bool do_env_dq(DisasContext *dc, arg_r_r *a, TRANS(FqTOd, ALL, do_env_dq, a, gen_helper_fqtod) TRANS(FqTOx, 64, do_env_dq, a, gen_helper_fqtox) +static bool do_env_qf(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_env, TCGv_i32)) +{ + TCGv_i32 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src = gen_load_fpr_F(dc, a->rs); + func(tcg_env, src); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FiTOq, ALL, do_env_qf, a, gen_helper_fitoq) +TRANS(FsTOq, ALL, do_env_qf, a, gen_helper_fstoq) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -5073,15 +5083,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0xd3: /* fqtoi */ case 0xcb: /* fqtod */ case 0x83: /* V9 fqtox */ - g_assert_not_reached(); /* in decodetree */ case 0xcc: /* fitoq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QF(dc, rd, rs2, gen_helper_fitoq); - break; case 0xcd: /* fstoq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QF(dc, rd, rs2, gen_helper_fstoq); - break; + g_assert_not_reached(); /* in decodetree */ case 0xce: /* fdtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); From patchwork Fri Oct 13 21:28:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733301 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679426wrv; Fri, 13 Oct 2023 14:35:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGGk+tnZXp3NiVEll7P1kX+k0GbyXt8BEPe3cLkmNbzrfF5ydRbjgWRJq2wCw+RLFz8iDQ3 X-Received: by 2002:a0c:f40c:0:b0:66d:1d2:dd85 with SMTP id h12-20020a0cf40c000000b0066d01d2dd85mr11265153qvl.48.1697232914066; Fri, 13 Oct 2023 14:35:14 -0700 (PDT) ARC-Seal: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 78/85] target/sparc: Move FdTOq, FxTOq to decodetree Date: Fri, 13 Oct 2023 14:28:39 -0700 Message-Id: <20231013212846.165724-79-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 47 ++++++++++++++++++++++----------------- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f0a6abb170..f749e23ae6 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -261,6 +261,7 @@ FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FqTOx 10 ..... 110100 00000 0 1000 0011 ..... @r_r2 FxTOs 10 ..... 110100 00000 0 1000 0100 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 +FxTOq 10 ..... 110100 00000 0 1000 1100 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 FdTOs 10 ..... 110100 00000 0 1100 0110 ..... @r_r2 FqTOs 10 ..... 110100 00000 0 1100 0111 ..... @r_r2 @@ -269,6 +270,7 @@ FsTOd 10 ..... 110100 00000 0 1100 1001 ..... @r_r2 FqTOd 10 ..... 110100 00000 0 1100 1011 ..... @r_r2 FiTOq 10 ..... 110100 00000 0 1100 1100 ..... @r_r2 FsTOq 10 ..... 110100 00000 0 1100 1101 ..... @r_r2 +FdTOq 10 ..... 110100 00000 0 1100 1110 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index d6ae4431dc..22a1a13ef8 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -60,6 +60,7 @@ #define gen_helper_fqtox ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fxtod ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fxtos ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL; }) #define gen_helper_done(E) qemu_build_not_reached() #define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() @@ -1542,19 +1543,6 @@ static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, } #endif -static void gen_ne_fop_QD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr, TCGv_i64)) -{ - TCGv_i64 src; - - src = gen_load_fpr_D(dc, rs); - - gen(tcg_env, src); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - /* asi moves */ typedef enum { GET_ASI_HELPER, @@ -4798,6 +4786,29 @@ static bool do_env_qf(DisasContext *dc, arg_r_r *a, TRANS(FiTOq, ALL, do_env_qf, a, gen_helper_fitoq) TRANS(FsTOq, ALL, do_env_qf, a, gen_helper_fstoq) +static bool do_env_qd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_env, TCGv_i64)) +{ + TCGv_i64 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src = gen_load_fpr_D(dc, a->rs); + func(tcg_env, src); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FdTOq, ALL, do_env_qd, a, gen_helper_fdtoq) +TRANS(FxTOq, 64, do_env_qd, a, gen_helper_fxtoq) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -5085,11 +5096,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x83: /* V9 fqtox */ case 0xcc: /* fitoq */ case 0xcd: /* fstoq */ - g_assert_not_reached(); /* in decodetree */ case 0xce: /* fdtoq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QD(dc, rd, rs2, gen_helper_fdtoq); - break; + case 0x8c: /* V9 fxtoq */ + g_assert_not_reached(); /* in decodetree */ #ifdef TARGET_SPARC64 case 0x3: /* V9 fmovq */ CHECK_FPU_FEATURE(dc, FLOAT128); @@ -5103,10 +5112,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); break; - case 0x8c: /* V9 fxtoq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); - break; #endif default: goto illegal_insn; From patchwork Fri Oct 13 21:28:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733308 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679746wrv; Fri, 13 Oct 2023 14:36:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEpalH1yQCmYoXHbgj2Zp+JV9RLkAuwdvLrFn4RWOtWF07gSxG76lT8Ey5uXlf8HqHRC5Bp X-Received: by 2002:a0c:a892:0:b0:656:1cee:d1d with SMTP id x18-20020a0ca892000000b006561cee0d1dmr26120578qva.11.1697232981763; Fri, 13 Oct 2023 14:36:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697232981; cv=none; d=google.com; s=arc-20160816; b=eUzJ4JufMnTQFbUdAxBoOkTgduqWuOw8jbvQBVG/vuy7yiOCZNZV1dHI7zzjk9Vuzl 3w6+9JGJyAgjh/wyMlxA4ntA9wg1buY8XtZiv0egt4MwzIuzCV6GTsXm0WsBggP4FFdS jFWgURYMjbXOngu6elVK0qt+AzXRb7piggqwRBOEz/4KAL9SPDooL64omviqAYdA8Q8A p+eJEIQnqFkOhQY8WdVV6iT+DySHscL3jfNn4ha3x9GLD5fVj+Eh2QCb0WUlawcjtvfz USXKwOKEewWJ4j/UwDZcCXseeTKxpRcSDTipTOwN0QRHUCMYwaQiB7XpsAWiMizqJUgm R6Mg== ARC-Message-Signature: i=1; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id j5-20020aa78d05000000b0068842ebfd10sm13977191pfe.160.2023.10.13.14.32.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:32:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 79/85] target/sparc: Move FMOVq, FNEGq, FABSq to decodetree Date: Fri, 13 Oct 2023 14:28:40 -0700 Message-Id: <20231013212846.165724-80-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 3 + target/sparc/translate.c | 138 +++++++++++++------------------------- 2 files changed, 48 insertions(+), 93 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index f749e23ae6..8f953a6af6 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -235,10 +235,13 @@ RETRY 10 00001 111110 00000 0 0000000000000 FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2 FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2 +FMOVq 10 ..... 110100 00000 0 0000 0011 ..... @r_r2 FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2 FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 +FNEGq 10 ..... 110100 00000 0 0000 0111 ..... @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 +FABSq 10 ..... 110100 00000 0 0000 1011 ..... @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 22a1a13ef8..c16d572c88 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -54,7 +54,9 @@ #define gen_helper_saved ({ qemu_build_not_reached(); NULL; }) #define gen_helper_restored ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fnegd ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_fnegq ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fabsd ({ qemu_build_not_reached(); NULL; }) +#define gen_helper_fabsq ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fdtox ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fstox ({ qemu_build_not_reached(); NULL; }) #define gen_helper_fqtox ({ qemu_build_not_reached(); NULL; }) @@ -261,18 +263,6 @@ static void gen_op_store_QT0_fpr(unsigned int dst) offsetof(CPU_QuadU, ll.lower)); } -#ifdef TARGET_SPARC64 -static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs) -{ - rd = QFPREG(rd); - rs = QFPREG(rs); - - tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]); - tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]); - gen_update_fprs_dirty(dc, rd); -} -#endif - /* moves */ #ifdef CONFIG_USER_ONLY #define supervisor(dc) 0 @@ -1530,19 +1520,6 @@ static void gen_op_clear_ieee_excp_and_FTT(void) tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_CEXC_NMASK); } -#ifdef TARGET_SPARC64 -static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr)) -{ - gen_op_load_fpr_QT1(QFPREG(rs)); - - gen(tcg_env); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} -#endif - /* asi moves */ typedef enum { GET_ASI_HELPER, @@ -4694,6 +4671,48 @@ TRANS(FiTOd, ALL, do_env_df, a, gen_helper_fitod) TRANS(FsTOd, ALL, do_env_df, a, gen_helper_fstod) TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox) +static bool trans_FMOVq(DisasContext *dc, arg_FMOVq *a) +{ + int rd, rs; + + if (!avail_64(dc)) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + rd = QFPREG(a->rd); + rs = QFPREG(a->rs); + tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]); + tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]); + gen_update_fprs_dirty(dc, rd); + return advance_pc(dc); +} + +static bool do_qq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_env)) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_load_fpr_QT1(QFPREG(a->rs)); + func(tcg_env); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FNEGq, 64, do_qq, a, gen_helper_fnegq) +TRANS(FABSq, 64, do_qq, a, gen_helper_fabsq) + static bool do_env_qq(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_env)) { @@ -5048,74 +5067,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv cpu_dst __attribute__((unused)) = tcg_temp_new(); if (xop == 0x34) { /* FPU Operations */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_op_clear_ieee_excp_and_FTT(); - rs1 = GET_FIELD(insn, 13, 17); - rs2 = GET_FIELD(insn, 27, 31); - xop = GET_FIELD(insn, 18, 26); - - switch (xop) { - case 0x1: /* fmovs */ - case 0x5: /* fnegs */ - case 0x9: /* fabss */ - case 0x2: /* V9 fmovd */ - case 0x6: /* V9 fnegd */ - case 0xa: /* V9 fabsd */ - case 0x29: /* fsqrts */ - case 0xc4: /* fitos */ - case 0xd1: /* fstoi */ - case 0x2a: /* fsqrtd */ - case 0x82: /* V9 fdtox */ - case 0x88: /* V9 fxtod */ - case 0x2b: /* fsqrtq */ - case 0x41: /* fadds */ - case 0x45: /* fsubs */ - case 0x49: /* fmuls */ - case 0x4d: /* fdivs */ - case 0x42: /* faddd */ - case 0x46: /* fsubd */ - case 0x4a: /* fmuld */ - case 0x4e: /* fdivd */ - case 0x43: /* faddq */ - case 0x47: /* fsubq */ - case 0x4b: /* fmulq */ - case 0x4f: /* fdivq */ - case 0x69: /* fsmuld */ - case 0x6e: /* fdmulq */ - case 0xc6: /* fdtos */ - case 0xd2: /* fdtoi */ - case 0x84: /* V9 fxtos */ - case 0xc8: /* fitod */ - case 0xc9: /* fstod */ - case 0x81: /* V9 fstox */ - case 0xc7: /* fqtos */ - case 0xd3: /* fqtoi */ - case 0xcb: /* fqtod */ - case 0x83: /* V9 fqtox */ - case 0xcc: /* fitoq */ - case 0xcd: /* fstoq */ - case 0xce: /* fdtoq */ - case 0x8c: /* V9 fxtoq */ - g_assert_not_reached(); /* in decodetree */ -#ifdef TARGET_SPARC64 - case 0x3: /* V9 fmovq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_move_Q(dc, rd, rs2); - break; - case 0x7: /* V9 fnegq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq); - break; - case 0xb: /* V9 fabsq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq); - break; -#endif - default: - goto illegal_insn; - } + goto illegal_insn; /* in decodetree */ } else if (xop == 0x35) { /* FPU Operations */ #ifdef TARGET_SPARC64 int cond; From patchwork Fri Oct 13 21:28:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733307 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679741wrv; Fri, 13 Oct 2023 14:36:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGoIfQ1iFG4sFxzMd7zpu8qGMXbXYrQdn+Ac5+VtBQMIPGVGlfvxKGvMjY30DFVKX44e8Ut X-Received: by 2002:a05:622a:1994:b0:40c:21b2:40ab with SMTP id u20-20020a05622a199400b0040c21b240abmr2235305qtc.22.1697232980779; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id v127-20020a626185000000b0068790c41ca2sm1123984pfb.27.2023.10.13.14.36.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:36:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 80/85] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree Date: Fri, 13 Oct 2023 14:28:41 -0700 Message-Id: <20231013212846.165724-81-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 12 +++ target/sparc/translate.c | 189 +++++++++++++++----------------------- 2 files changed, 88 insertions(+), 113 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 8f953a6af6..5e8d456ab2 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -278,6 +278,18 @@ FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 FdTOi 10 ..... 110100 00000 0 1101 0010 ..... @r_r2 FqTOi 10 ..... 110100 00000 0 1101 0011 ..... @r_r2 +FMOVscc 10 rd:5 110101 0 cond:4 1 cc:1 0 000001 rs2:5 +FMOVdcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000010 rs2:5 +FMOVqcc 10 rd:5 110101 0 cond:4 1 cc:1 0 000011 rs2:5 + +FMOVsfcc 10 rd:5 110101 0 cond:4 0 cc:2 000001 rs2:5 +FMOVdfcc 10 rd:5 110101 0 cond:4 0 cc:2 000010 rs2:5 +FMOVqfcc 10 rd:5 110101 0 cond:4 0 cc:2 000011 rs2:5 + +FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5 +FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5 +FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5 + { [ EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index c16d572c88..2ecaa82de5 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2296,15 +2296,9 @@ static void gen_stda_asi(DisasContext *dc, DisasASI *da, TCGv addr, int rd) } } -#ifdef TARGET_SPARC64 -static TCGv get_src1(DisasContext *dc, unsigned int insn) -{ - unsigned int rs1 = GET_FIELD(insn, 13, 17); - return gen_load_gpr(dc, rs1); -} - static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { +#ifdef TARGET_SPARC64 TCGv_i32 c32, zero, dst, s1, s2; /* We have two choices here: extend the 32 bit data and use movcond_i64, @@ -2327,19 +2321,27 @@ static void gen_fmovs(DisasContext *dc, DisasCompare *cmp, int rd, int rs) tcg_gen_movcond_i32(TCG_COND_NE, dst, c32, zero, s1, s2); gen_store_fpr_F(dc, rd, dst); +#else + qemu_build_not_reached(); +#endif } static void gen_fmovd(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { +#ifdef TARGET_SPARC64 TCGv_i64 dst = gen_dest_fpr_D(dc, rd); tcg_gen_movcond_i64(cmp->cond, dst, cmp->c1, cmp->c2, gen_load_fpr_D(dc, rs), gen_load_fpr_D(dc, rd)); gen_store_fpr_D(dc, rd, dst); +#else + qemu_build_not_reached(); +#endif } static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) { +#ifdef TARGET_SPARC64 int qd = QFPREG(rd); int qs = QFPREG(rs); @@ -2349,8 +2351,12 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs) cpu_fpr[qs / 2 + 1], cpu_fpr[qd / 2 + 1]); gen_update_fprs_dirty(dc, qd); +#else + qemu_build_not_reached(); +#endif } +#ifdef TARGET_SPARC64 static void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr) { TCGv_i32 r_tl = tcg_temp_new_i32(); @@ -5036,6 +5042,69 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a) return advance_pc(dc); } +static bool do_fmovr(DisasContext *dc, arg_FMOVRs *a, bool is_128, + void (*func)(DisasContext *, DisasCompare *, int, int)) +{ + DisasCompare cmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (is_128 && gen_trap_float128(dc)) { + return true; + } + + gen_compare_reg(&cmp, a->cond, gen_load_gpr(dc, a->rs1)); + func(dc, &cmp, a->rd, a->rs2); + return advance_pc(dc); +} + +TRANS(FMOVRs, 64, do_fmovr, a, false, gen_fmovs) +TRANS(FMOVRd, 64, do_fmovr, a, false, gen_fmovd) +TRANS(FMOVRq, 64, do_fmovr, a, true, gen_fmovq) + +static bool do_fmovcc(DisasContext *dc, arg_FMOVscc *a, bool is_128, + void (*func)(DisasContext *, DisasCompare *, int, int)) +{ + DisasCompare cmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (is_128 && gen_trap_float128(dc)) { + return true; + } + + gen_compare(&cmp, a->cc, a->cond, dc); + func(dc, &cmp, a->rd, a->rs2); + return advance_pc(dc); +} + +TRANS(FMOVscc, 64, do_fmovcc, a, false, gen_fmovs) +TRANS(FMOVdcc, 64, do_fmovcc, a, false, gen_fmovd) +TRANS(FMOVqcc, 64, do_fmovcc, a, true, gen_fmovq) + +static bool do_fmovfcc(DisasContext *dc, arg_FMOVsfcc *a, bool is_128, + void (*func)(DisasContext *, DisasCompare *, int, int)) +{ + DisasCompare cmp; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (is_128 && gen_trap_float128(dc)) { + return true; + } + + gen_fcompare(&cmp, a->cc, a->cond); + func(dc, &cmp, a->rd, a->rs2); + return advance_pc(dc); +} + +TRANS(FMOVsfcc, 64, do_fmovfcc, a, false, gen_fmovs) +TRANS(FMOVdfcc, 64, do_fmovfcc, a, false, gen_fmovd) +TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5069,9 +5138,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) if (xop == 0x34) { /* FPU Operations */ goto illegal_insn; /* in decodetree */ } else if (xop == 0x35) { /* FPU Operations */ -#ifdef TARGET_SPARC64 - int cond; -#endif if (gen_trap_ifnofpu(dc)) { goto jmp_insn; } @@ -5080,110 +5146,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) rs2 = GET_FIELD(insn, 27, 31); xop = GET_FIELD(insn, 18, 26); -#ifdef TARGET_SPARC64 -#define FMOVR(sz) \ - do { \ - DisasCompare cmp; \ - cond = GET_FIELD_SP(insn, 10, 12); \ - cpu_src1 = get_src1(dc, insn); \ - gen_compare_reg(&cmp, cond, cpu_src1); \ - gen_fmov##sz(dc, &cmp, rd, rs2); \ - } while (0) - - if ((xop & 0x11f) == 0x005) { /* V9 fmovsr */ - FMOVR(s); - break; - } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr - FMOVR(d); - break; - } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVR(q); - break; - } -#undef FMOVR -#endif switch (xop) { -#ifdef TARGET_SPARC64 -#define FMOVCC(fcc, sz) \ - do { \ - DisasCompare cmp; \ - cond = GET_FIELD_SP(insn, 14, 17); \ - gen_fcompare(&cmp, fcc, cond); \ - gen_fmov##sz(dc, &cmp, rd, rs2); \ - } while (0) - - case 0x001: /* V9 fmovscc %fcc0 */ - FMOVCC(0, s); - break; - case 0x002: /* V9 fmovdcc %fcc0 */ - FMOVCC(0, d); - break; - case 0x003: /* V9 fmovqcc %fcc0 */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(0, q); - break; - case 0x041: /* V9 fmovscc %fcc1 */ - FMOVCC(1, s); - break; - case 0x042: /* V9 fmovdcc %fcc1 */ - FMOVCC(1, d); - break; - case 0x043: /* V9 fmovqcc %fcc1 */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(1, q); - break; - case 0x081: /* V9 fmovscc %fcc2 */ - FMOVCC(2, s); - break; - case 0x082: /* V9 fmovdcc %fcc2 */ - FMOVCC(2, d); - break; - case 0x083: /* V9 fmovqcc %fcc2 */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(2, q); - break; - case 0x0c1: /* V9 fmovscc %fcc3 */ - FMOVCC(3, s); - break; - case 0x0c2: /* V9 fmovdcc %fcc3 */ - FMOVCC(3, d); - break; - case 0x0c3: /* V9 fmovqcc %fcc3 */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(3, q); - break; -#undef FMOVCC -#define FMOVCC(xcc, sz) \ - do { \ - DisasCompare cmp; \ - cond = GET_FIELD_SP(insn, 14, 17); \ - gen_compare(&cmp, xcc, cond, dc); \ - gen_fmov##sz(dc, &cmp, rd, rs2); \ - } while (0) - - case 0x101: /* V9 fmovscc %icc */ - FMOVCC(0, s); - break; - case 0x102: /* V9 fmovdcc %icc */ - FMOVCC(0, d); - break; - case 0x103: /* V9 fmovqcc %icc */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(0, q); - break; - case 0x181: /* V9 fmovscc %xcc */ - FMOVCC(1, s); - break; - case 0x182: /* V9 fmovdcc %xcc */ - FMOVCC(1, d); - break; - case 0x183: /* V9 fmovqcc %xcc */ - CHECK_FPU_FEATURE(dc, FLOAT128); - FMOVCC(1, q); - break; -#undef FMOVCC -#endif case 0x51: /* fcmps, V9 %fcc */ cpu_src1_32 = gen_load_fpr_F(dc, rs1); cpu_src2_32 = gen_load_fpr_F(dc, rs2); From patchwork Fri Oct 13 21:28:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733306 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679740wrv; Fri, 13 Oct 2023 14:36:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHduRAqdvR8bN1/sybHYe0SX+LxAnxZhLpkoGRuzLsfupmDb0bWRLxHrySz4BkMMEPSudmq X-Received: by 2002:a05:620a:4481:b0:76f:10ab:7c64 with SMTP id x1-20020a05620a448100b0076f10ab7c64mr31016819qkp.28.1697232980727; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id v127-20020a626185000000b0068790c41ca2sm1123984pfb.27.2023.10.13.14.36.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:36:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 81/85] target/sparc: Convert FCMP, FCMPE to decodetree Date: Fri, 13 Oct 2023 14:28:42 -0700 Message-Id: <20231013212846.165724-82-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 7 ++ target/sparc/translate.c | 145 +++++++++++++++++++++++--------------- 2 files changed, 96 insertions(+), 56 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 5e8d456ab2..c5d6f46737 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -290,6 +290,13 @@ FMOVRs 10 rd:5 110101 rs1:5 0 cond:3 00101 rs2:5 FMOVRd 10 rd:5 110101 rs1:5 0 cond:3 00110 rs2:5 FMOVRq 10 rd:5 110101 rs1:5 0 cond:3 00111 rs2:5 +FCMPs 10 000 cc:2 110101 rs1:5 0 0101 0001 rs2:5 +FCMPd 10 000 cc:2 110101 rs1:5 0 0101 0010 rs2:5 +FCMPq 10 000 cc:2 110101 rs1:5 0 0101 0011 rs2:5 +FCMPEs 10 000 cc:2 110101 rs1:5 0 0101 0101 rs2:5 +FCMPEd 10 000 cc:2 110101 rs1:5 0 0101 0110 rs2:5 +FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 + { [ EDGE8cc 10 ..... 110110 ..... 0 0000 0000 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 2ecaa82de5..81d274448a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5105,6 +5105,82 @@ TRANS(FMOVsfcc, 64, do_fmovfcc, a, false, gen_fmovs) TRANS(FMOVdfcc, 64, do_fmovfcc, a, false, gen_fmovd) TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq) +static bool do_fcmps(DisasContext *dc, arg_FCMPs *a, bool e) +{ + TCGv_i32 src1, src2; + + if (avail_32(dc) && a->cc != 0) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src1 = gen_load_fpr_F(dc, a->rs1); + src2 = gen_load_fpr_F(dc, a->rs2); + if (e) { + gen_op_fcmpes(a->cc, src1, src2); + } else { + gen_op_fcmps(a->cc, src1, src2); + } + return advance_pc(dc); +} + +TRANS(FCMPs, ALL, do_fcmps, a, false) +TRANS(FCMPEs, ALL, do_fcmps, a, true) + +static bool do_fcmpd(DisasContext *dc, arg_FCMPq *a, bool e) +{ + TCGv_i64 src1, src2; + + if (avail_32(dc) && a->cc != 0) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + src1 = gen_load_fpr_D(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + if (e) { + gen_op_fcmped(a->cc, src1, src2); + } else { + gen_op_fcmpd(a->cc, src1, src2); + } + return advance_pc(dc); +} + +TRANS(FCMPd, ALL, do_fcmpd, a, false) +TRANS(FCMPEd, ALL, do_fcmpd, a, true) + +static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e) +{ + if (avail_32(dc) && a->cc != 0) { + return false; + } + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT0(QFPREG(a->rs1)); + gen_op_load_fpr_QT1(QFPREG(a->rs2)); + if (e) { + gen_op_fcmpeq(a->cc); + } else { + gen_op_fcmpq(a->cc); + } + return advance_pc(dc); +} + +TRANS(FCMPq, ALL, do_fcmpq, a, false) +TRANS(FCMPEq, ALL, do_fcmpq, a, true) + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -5115,15 +5191,7 @@ TRANS(FMOVqfcc, 64, do_fmovfcc, a, true, gen_fmovq) /* before an instruction, dc->pc must be static */ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) { - unsigned int opc, rs1, rs2, rd; - TCGv cpu_src1 __attribute__((unused)); - TCGv_i32 cpu_src1_32, cpu_src2_32; - TCGv_i64 cpu_src1_64, cpu_src2_64; - TCGv_i32 cpu_dst_32 __attribute__((unused)); - TCGv_i64 cpu_dst_64 __attribute__((unused)); - - opc = GET_FIELD(insn, 0, 1); - rd = GET_FIELD(insn, 2, 6); + unsigned int opc = GET_FIELD(insn, 0, 1); switch (opc) { case 0: @@ -5133,61 +5201,22 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 2: /* FPU & Logical Operations */ { unsigned int xop = GET_FIELD(insn, 7, 12); - TCGv cpu_dst __attribute__((unused)) = tcg_temp_new(); if (xop == 0x34) { /* FPU Operations */ goto illegal_insn; /* in decodetree */ } else if (xop == 0x35) { /* FPU Operations */ - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - gen_op_clear_ieee_excp_and_FTT(); - rs1 = GET_FIELD(insn, 13, 17); - rs2 = GET_FIELD(insn, 27, 31); - xop = GET_FIELD(insn, 18, 26); - - switch (xop) { - case 0x51: /* fcmps, V9 %fcc */ - cpu_src1_32 = gen_load_fpr_F(dc, rs1); - cpu_src2_32 = gen_load_fpr_F(dc, rs2); - gen_op_fcmps(rd & 3, cpu_src1_32, cpu_src2_32); - break; - case 0x52: /* fcmpd, V9 %fcc */ - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_op_fcmpd(rd & 3, cpu_src1_64, cpu_src2_64); - break; - case 0x53: /* fcmpq, V9 %fcc */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_op_load_fpr_QT0(QFPREG(rs1)); - gen_op_load_fpr_QT1(QFPREG(rs2)); - gen_op_fcmpq(rd & 3); - break; - case 0x55: /* fcmpes, V9 %fcc */ - cpu_src1_32 = gen_load_fpr_F(dc, rs1); - cpu_src2_32 = gen_load_fpr_F(dc, rs2); - gen_op_fcmpes(rd & 3, cpu_src1_32, cpu_src2_32); - break; - case 0x56: /* fcmped, V9 %fcc */ - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_op_fcmped(rd & 3, cpu_src1_64, cpu_src2_64); - break; - case 0x57: /* fcmpeq, V9 %fcc */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_op_load_fpr_QT0(QFPREG(rs1)); - gen_op_load_fpr_QT1(QFPREG(rs2)); - gen_op_fcmpeq(rd & 3); - break; - default: - goto illegal_insn; - } + goto illegal_insn; /* in decodetree */ } else if (xop == 0x36) { #ifdef TARGET_SPARC64 /* VIS */ + TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; + TCGv_i32 cpu_dst_32; + TCGv cpu_dst = tcg_temp_new(); int opf = GET_FIELD_SP(insn, 5, 13); - rs1 = GET_FIELD(insn, 13, 17); - rs2 = GET_FIELD(insn, 27, 31); + int rs1 = GET_FIELD(insn, 13, 17); + int rs2 = GET_FIELD(insn, 27, 31); + int rd = GET_FIELD(insn, 2, 6); + if (gen_trap_ifnofpu(dc)) { goto jmp_insn; } @@ -5372,14 +5401,18 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) goto illegal_insn; /* in decodetree */ } advance_pc(dc); +#ifdef TARGET_SPARC64 jmp_insn: +#endif return; illegal_insn: gen_exception(dc, TT_ILL_INSN); return; +#ifdef TARGET_SPARC64 nfpu_insn: gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); return; +#endif } static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) From patchwork Fri Oct 13 21:28:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733321 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680119wrv; Fri, 13 Oct 2023 14:37:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IETUilLB2G/kavpAeGos7kOuAABhPRaJXphay6oom+iRbJkjUmhtNV3mfwQHWv4Zr147h3X X-Received: by 2002:a05:6830:1050:b0:6c0:7bab:3457 with SMTP id b16-20020a056830105000b006c07bab3457mr28576979otp.20.1697233055681; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id v127-20020a626185000000b0068790c41ca2sm1123984pfb.27.2023.10.13.14.36.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:36:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 82/85] target/sparc: Move FPCMP* to decodetree Date: Fri, 13 Oct 2023 14:28:43 -0700 Message-Id: <20231013212846.165724-83-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 9 ++++ target/sparc/translate.c | 94 +++++++++++++++++---------------------- 2 files changed, 50 insertions(+), 53 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index c5d6f46737..9333c8ba3b 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -321,6 +321,15 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r + FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_r_r + FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_r_r + FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_r_r + FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_r_r + FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_r_r + FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_r_r + FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_r_r + FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_r_r + FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 81d274448a..1a9fa18d64 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -77,7 +77,14 @@ #define gen_helper_fpmerge ({ g_assert_not_reached(); NULL; }) #define gen_helper_fexpand ({ g_assert_not_reached(); NULL; }) #define gen_helper_pdist ({ g_assert_not_reached(); NULL; }) -#define gen_helper_fsqrtq ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpeq16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpne16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmple16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpgt16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpeq32 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpne32 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmple32 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpgt32 ({ g_assert_not_reached(); NULL; }) #define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; }) #define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; }) # ifdef CONFIG_USER_ONLY @@ -4930,6 +4937,37 @@ TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32) TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata) TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle) +static bool do_rdd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ +#ifdef TARGET_SPARC64 + TCGv_i64 dst, src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = gen_dest_gpr(dc, a->rd); + src1 = gen_load_fpr_D(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + func(dst, src1, src2); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +#else + g_assert_not_reached(); +#endif +} + +TRANS(FPCMPLE16, VIS1, do_rdd, a, gen_helper_fcmple16) +TRANS(FPCMPNE16, VIS1, do_rdd, a, gen_helper_fcmpne16) +TRANS(FPCMPGT16, VIS1, do_rdd, a, gen_helper_fcmpgt16) +TRANS(FPCMPEQ16, VIS1, do_rdd, a, gen_helper_fcmpeq16) + +TRANS(FPCMPLE32, VIS1, do_rdd, a, gen_helper_fcmple32) +TRANS(FPCMPNE32, VIS1, do_rdd, a, gen_helper_fcmpne32) +TRANS(FPCMPGT32, VIS1, do_rdd, a, gen_helper_fcmpgt32) +TRANS(FPCMPEQ32, VIS1, do_rdd, a, gen_helper_fcmpeq32) + static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) { @@ -5209,11 +5247,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } else if (xop == 0x36) { #ifdef TARGET_SPARC64 /* VIS */ - TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; + TCGv_i64 cpu_src1_64, cpu_dst_64; TCGv_i32 cpu_dst_32; - TCGv cpu_dst = tcg_temp_new(); int opf = GET_FIELD_SP(insn, 5, 13); - int rs1 = GET_FIELD(insn, 13, 17); int rs2 = GET_FIELD(insn, 27, 31); int rd = GET_FIELD(insn, 2, 6); @@ -5289,63 +5325,15 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x03a: /* VIS I fpack32 */ case 0x048: /* VIS I faligndata */ case 0x04c: /* VIS II bshuffle */ - g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x022: /* VIS I fcmpne16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x024: /* VIS I fcmple32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x026: /* VIS I fcmpne32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x028: /* VIS I fcmpgt16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x02a: /* VIS I fcmpeq16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x02c: /* VIS I fcmpgt32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x02e: /* VIS I fcmpeq32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x03b: /* VIS I fpack16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 = gen_load_fpr_D(dc, rs2); From patchwork Fri Oct 13 21:28:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733322 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680161wrv; Fri, 13 Oct 2023 14:37:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEkMIYbRyvnoGleDLhpood2Hnv/vRnARiujtfWVqyobMAFfWJnMmGumVfO7Dt7lWYNjLa5a X-Received: by 2002:aca:1a04:0:b0:3a7:af4c:2406 with SMTP id a4-20020aca1a04000000b003a7af4c2406mr28519352oia.44.1697233064859; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id v127-20020a626185000000b0068790c41ca2sm1123984pfb.27.2023.10.13.14.36.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:36:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 83/85] target/sparc: Move FPACK16, FPACKFIX to decodetree Date: Fri, 13 Oct 2023 14:28:44 -0700 Message-Id: <20231013212846.165724-84-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 55 ++++++++++++++++++++++++++++----------- 2 files changed, 42 insertions(+), 15 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 9333c8ba3b..14daaa4a92 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -338,6 +338,8 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 FMULD8SUx16 10 ..... 110110 ..... 0 0011 1000 ..... @r_r_r FMULD8ULx16 10 ..... 110110 ..... 0 0011 1001 ..... @r_r_r FPACK32 10 ..... 110110 ..... 0 0011 1010 ..... @r_r_r + FPACK16 10 ..... 110110 00000 0 0011 1011 ..... @r_r2 + FPACKFIX 10 ..... 110110 00000 0 0011 1101 ..... @r_r2 PDIST 10 ..... 110110 ..... 0 0011 1110 ..... @r_r_r FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1a9fa18d64..a7e2bcfb53 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -690,6 +690,24 @@ static void gen_op_array32(TCGv dst, TCGv src1, TCGv src2) tcg_gen_shli_tl(dst, dst, 2); } +static void gen_op_fpack16(TCGv_i32 dst, TCGv_i64 src) +{ +#ifdef TARGET_SPARC64 + gen_helper_fpack16(dst, cpu_gsr, src); +#else + g_assert_not_reached(); +#endif +} + +static void gen_op_fpackfix(TCGv_i32 dst, TCGv_i64 src) +{ +#ifdef TARGET_SPARC64 + gen_helper_fpackfix(dst, cpu_gsr, src); +#else + g_assert_not_reached(); +#endif +} + static void gen_op_fpack32(TCGv_i64 dst, TCGv_i64 src1, TCGv_i64 src2) { #ifdef TARGET_SPARC64 @@ -4573,6 +4591,26 @@ TRANS(FABSs, ALL, do_ff, a, gen_helper_fabss) TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32) TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32) +static bool do_fd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i32, TCGv_i64)) +{ + TCGv_i32 dst; + TCGv_i64 src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = gen_dest_fpr_F(dc); + src = gen_load_fpr_D(dc, a->rs); + func(dst, src); + gen_store_fpr_F(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FPACK16, VIS1, do_fd, a, gen_op_fpack16) +TRANS(FPACKFIX, VIS1, do_fd, a, gen_op_fpackfix) + static bool do_env_ff(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_i32, TCGv_env, TCGv_i32)) { @@ -5247,10 +5285,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } else if (xop == 0x36) { #ifdef TARGET_SPARC64 /* VIS */ - TCGv_i64 cpu_src1_64, cpu_dst_64; + TCGv_i64 cpu_dst_64; TCGv_i32 cpu_dst_32; int opf = GET_FIELD_SP(insn, 5, 13); - int rs2 = GET_FIELD(insn, 27, 31); int rd = GET_FIELD(insn, 2, 6); if (gen_trap_ifnofpu(dc)) { @@ -5333,21 +5370,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x02a: /* VIS I fcmpeq16 */ case 0x02c: /* VIS I fcmpgt32 */ case 0x02e: /* VIS I fcmpeq32 */ - g_assert_not_reached(); /* in decodetree */ case 0x03b: /* VIS I fpack16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs2); - cpu_dst_32 = gen_dest_fpr_F(dc); - gen_helper_fpack16(cpu_dst_32, cpu_gsr, cpu_src1_64); - gen_store_fpr_F(dc, rd, cpu_dst_32); - break; case 0x03d: /* VIS I fpackfix */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs2); - cpu_dst_32 = gen_dest_fpr_F(dc); - gen_helper_fpackfix(cpu_dst_32, cpu_gsr, cpu_src1_64); - gen_store_fpr_F(dc, rd, cpu_dst_32); - break; + g_assert_not_reached(); /* in decodetree */ case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id v127-20020a626185000000b0068790c41ca2sm1123984pfb.27.2023.10.13.14.36.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:36:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 84/85] target/sparc: Convert FZERO, FONE to decodetree Date: Fri, 13 Oct 2023 14:28:45 -0700 Message-Id: <20231013212846.165724-85-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++ target/sparc/translate.c | 69 +++++++++++++++++++++++---------------- 2 files changed, 45 insertions(+), 29 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 14daaa4a92..0c3d6071ff 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -385,6 +385,11 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 FORNOTs 10 ..... 110110 ..... 0 0111 1011 ..... @r_r_r_swap # ... 1s FORd 10 ..... 110110 ..... 0 0111 1100 ..... @r_r_r FORs 10 ..... 110110 ..... 0 0111 1101 ..... @r_r_r + + FZEROd 10 rd:5 110110 00000 0 0110 0000 00000 + FZEROs 10 rd:5 110110 00000 0 0110 0001 00000 + FONEd 10 rd:5 110110 00000 0 0111 1110 00000 + FONEs 10 rd:5 110110 00000 0 0111 1111 00000 ] NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1 } diff --git a/target/sparc/translate.c b/target/sparc/translate.c index a7e2bcfb53..ffdd600353 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4570,6 +4570,45 @@ static bool do_stfsr(DisasContext *dc, arg_r_r_ri *a, MemOp mop) TRANS(STFSR, ALL, do_stfsr, a, MO_TEUL) TRANS(STXFSR, 64, do_stfsr, a, MO_TEUQ) +static bool do_fc(DisasContext *dc, int rd, bool c) +{ + uint64_t mask; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + if (rd & 1) { + mask = MAKE_64BIT_MASK(0, 32); + } else { + mask = MAKE_64BIT_MASK(32, 32); + } + if (c) { + tcg_gen_ori_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], mask); + } else { + tcg_gen_andi_i64(cpu_fpr[rd / 2], cpu_fpr[rd / 2], ~mask); + } + gen_update_fprs_dirty(dc, rd); + return advance_pc(dc); +} + +TRANS(FZEROs, VIS1, do_fc, a->rd, 0) +TRANS(FONEs, VIS1, do_fc, a->rd, 1) + +static bool do_dc(DisasContext *dc, int rd, int64_t c) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + + tcg_gen_movi_i64(cpu_fpr[rd / 2], c); + gen_update_fprs_dirty(dc, rd); + return advance_pc(dc); +} + +TRANS(FZEROd, VIS1, do_dc, a->rd, 0) +TRANS(FONEd, VIS1, do_dc, a->rd, -1) + static bool do_ff(DisasContext *dc, arg_r_r *a, void (*func)(TCGv_i32, TCGv_i32)) { @@ -5285,10 +5324,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } else if (xop == 0x36) { #ifdef TARGET_SPARC64 /* VIS */ - TCGv_i64 cpu_dst_64; - TCGv_i32 cpu_dst_32; int opf = GET_FIELD_SP(insn, 5, 13); - int rd = GET_FIELD(insn, 2, 6); if (gen_trap_ifnofpu(dc)) { goto jmp_insn; @@ -5372,31 +5408,11 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x02e: /* VIS I fcmpeq32 */ case 0x03b: /* VIS I fpack16 */ case 0x03d: /* VIS I fpackfix */ - g_assert_not_reached(); /* in decodetree */ case 0x060: /* VIS I fzero */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_dst_64 = gen_dest_fpr_D(dc, rd); - tcg_gen_movi_i64(cpu_dst_64, 0); - gen_store_fpr_D(dc, rd, cpu_dst_64); - break; case 0x061: /* VIS I fzeros */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_dst_32 = gen_dest_fpr_F(dc); - tcg_gen_movi_i32(cpu_dst_32, 0); - gen_store_fpr_F(dc, rd, cpu_dst_32); - break; case 0x07e: /* VIS I fone */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_dst_64 = gen_dest_fpr_D(dc, rd); - tcg_gen_movi_i64(cpu_dst_64, -1); - gen_store_fpr_D(dc, rd, cpu_dst_64); - break; case 0x07f: /* VIS I fones */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_dst_32 = gen_dest_fpr_F(dc); - tcg_gen_movi_i32(cpu_dst_32, -1); - gen_store_fpr_F(dc, rd, cpu_dst_32); - break; + g_assert_not_reached(); /* in decodetree */ case 0x080: /* VIS I shutdown */ case 0x081: /* VIS II siam */ // XXX @@ -5421,11 +5437,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) illegal_insn: gen_exception(dc, TT_ILL_INSN); return; -#ifdef TARGET_SPARC64 - nfpu_insn: - gen_op_fpexception_im(dc, FSR_FTT_UNIMPFPOP); - return; -#endif } static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) From patchwork Fri Oct 13 21:28:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733310 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1679796wrv; Fri, 13 Oct 2023 14:36:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFQl+IW1JXdCQBftf/MfLiutSwuj1uA3hNblUKc4BlNDpahUagRwaOEGtTMPn5UJzzG0kfB X-Received: by 2002:a05:620a:2996:b0:775:ed1e:2b14 with SMTP id r22-20020a05620a299600b00775ed1e2b14mr28823892qkp.54.1697232990832; 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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id v127-20020a626185000000b0068790c41ca2sm1123984pfb.27.2023.10.13.14.36.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:36:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 85/85] target/sparc: Remove disas_sparc_legacy Date: Fri, 13 Oct 2023 14:28:46 -0700 Message-Id: <20231013212846.165724-86-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All instructions are now converted. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 145 +-------------------------------------- 1 file changed, 1 insertion(+), 144 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ffdd600353..b7f98c7e18 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5296,149 +5296,6 @@ static bool do_fcmpq(DisasContext *dc, arg_FCMPq *a, bool e) TRANS(FCMPq, ALL, do_fcmpq, a, false) TRANS(FCMPEq, ALL, do_fcmpq, a, true) -#define CHECK_IU_FEATURE(dc, FEATURE) \ - if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ - goto illegal_insn; -#define CHECK_FPU_FEATURE(dc, FEATURE) \ - if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ - goto nfpu_insn; - -/* before an instruction, dc->pc must be static */ -static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) -{ - unsigned int opc = GET_FIELD(insn, 0, 1); - - switch (opc) { - case 0: - goto illegal_insn; /* in decodetree */ - case 1: - g_assert_not_reached(); /* in decodetree */ - case 2: /* FPU & Logical Operations */ - { - unsigned int xop = GET_FIELD(insn, 7, 12); - - if (xop == 0x34) { /* FPU Operations */ - goto illegal_insn; /* in decodetree */ - } else if (xop == 0x35) { /* FPU Operations */ - goto illegal_insn; /* in decodetree */ - } else if (xop == 0x36) { -#ifdef TARGET_SPARC64 - /* VIS */ - int opf = GET_FIELD_SP(insn, 5, 13); - - if (gen_trap_ifnofpu(dc)) { - goto jmp_insn; - } - - switch (opf) { - case 0x000: /* VIS I edge8cc */ - case 0x001: /* VIS II edge8n */ - case 0x002: /* VIS I edge8lcc */ - case 0x003: /* VIS II edge8ln */ - case 0x004: /* VIS I edge16cc */ - case 0x005: /* VIS II edge16n */ - case 0x006: /* VIS I edge16lcc */ - case 0x007: /* VIS II edge16ln */ - case 0x008: /* VIS I edge32cc */ - case 0x009: /* VIS II edge32n */ - case 0x00a: /* VIS I edge32lcc */ - case 0x00b: /* VIS II edge32ln */ - case 0x010: /* VIS I array8 */ - case 0x012: /* VIS I array16 */ - case 0x014: /* VIS I array32 */ - case 0x018: /* VIS I alignaddr */ - case 0x01a: /* VIS I alignaddrl */ - case 0x019: /* VIS II bmask */ - case 0x067: /* VIS I fnot2s */ - case 0x06b: /* VIS I fnot1s */ - case 0x075: /* VIS I fsrc1s */ - case 0x079: /* VIS I fsrc2s */ - case 0x066: /* VIS I fnot2 */ - case 0x06a: /* VIS I fnot1 */ - case 0x074: /* VIS I fsrc1 */ - case 0x078: /* VIS I fsrc2 */ - case 0x051: /* VIS I fpadd16s */ - case 0x053: /* VIS I fpadd32s */ - case 0x055: /* VIS I fpsub16s */ - case 0x057: /* VIS I fpsub32s */ - case 0x063: /* VIS I fnors */ - case 0x065: /* VIS I fandnot2s */ - case 0x069: /* VIS I fandnot1s */ - case 0x06d: /* VIS I fxors */ - case 0x06f: /* VIS I fnands */ - case 0x071: /* VIS I fands */ - case 0x073: /* VIS I fxnors */ - case 0x077: /* VIS I fornot2s */ - case 0x07b: /* VIS I fornot1s */ - case 0x07d: /* VIS I fors */ - case 0x050: /* VIS I fpadd16 */ - case 0x052: /* VIS I fpadd32 */ - case 0x054: /* VIS I fpsub16 */ - case 0x056: /* VIS I fpsub32 */ - case 0x062: /* VIS I fnor */ - case 0x064: /* VIS I fandnot2 */ - case 0x068: /* VIS I fandnot1 */ - case 0x06c: /* VIS I fxor */ - case 0x06e: /* VIS I fnand */ - case 0x070: /* VIS I fand */ - case 0x072: /* VIS I fxnor */ - case 0x076: /* VIS I fornot2 */ - case 0x07a: /* VIS I fornot1 */ - case 0x07c: /* VIS I for */ - case 0x031: /* VIS I fmul8x16 */ - case 0x033: /* VIS I fmul8x16au */ - case 0x035: /* VIS I fmul8x16al */ - case 0x036: /* VIS I fmul8sux16 */ - case 0x037: /* VIS I fmul8ulx16 */ - case 0x038: /* VIS I fmuld8sux16 */ - case 0x039: /* VIS I fmuld8ulx16 */ - case 0x04b: /* VIS I fpmerge */ - case 0x04d: /* VIS I fexpand */ - case 0x03e: /* VIS I pdist */ - case 0x03a: /* VIS I fpack32 */ - case 0x048: /* VIS I faligndata */ - case 0x04c: /* VIS II bshuffle */ - case 0x020: /* VIS I fcmple16 */ - case 0x022: /* VIS I fcmpne16 */ - case 0x024: /* VIS I fcmple32 */ - case 0x026: /* VIS I fcmpne32 */ - case 0x028: /* VIS I fcmpgt16 */ - case 0x02a: /* VIS I fcmpeq16 */ - case 0x02c: /* VIS I fcmpgt32 */ - case 0x02e: /* VIS I fcmpeq32 */ - case 0x03b: /* VIS I fpack16 */ - case 0x03d: /* VIS I fpackfix */ - case 0x060: /* VIS I fzero */ - case 0x061: /* VIS I fzeros */ - case 0x07e: /* VIS I fone */ - case 0x07f: /* VIS I fones */ - g_assert_not_reached(); /* in decodetree */ - case 0x080: /* VIS I shutdown */ - case 0x081: /* VIS II siam */ - // XXX - goto illegal_insn; - default: - goto illegal_insn; - } -#endif - } else { - goto illegal_insn; /* in decodetree */ - } - } - break; - case 3: /* load/store instructions */ - goto illegal_insn; /* in decodetree */ - } - advance_pc(dc); -#ifdef TARGET_SPARC64 - jmp_insn: -#endif - return; - illegal_insn: - gen_exception(dc, TT_ILL_INSN); - return; -} - static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); @@ -5506,7 +5363,7 @@ static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) dc->base.pc_next += 4; if (!decode(dc, insn)) { - disas_sparc_legacy(dc, insn); + gen_exception(dc, TT_ILL_INSN); } if (dc->base.is_jmp == DISAS_NORETURN) {