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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id i16-20020a1709064ed000b0099bd0b5a2bcsm11065610ejv.101.2023.10.12.05.19.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 1/8] hw/pci-host/designware: Declare CPU QOM types using DEFINE_TYPES() macro Date: Thu, 12 Oct 2023 14:18:49 +0200 Message-ID: <20231012121857.31873-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. Remove a pointless structure declaration in "designware.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- include/hw/pci-host/designware.h | 2 -- hw/pci-host/designware.c | 39 ++++++++++++++------------------ 2 files changed, 17 insertions(+), 24 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h index 908f3d946b..c484e377a8 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -31,8 +31,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST) #define TYPE_DESIGNWARE_PCIE_ROOT "designware-pcie-root" OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT) -struct DesignwarePCIERoot; - typedef struct DesignwarePCIEViewport { DesignwarePCIERoot *root; diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 6f5442f108..304eca1b5c 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -746,28 +746,23 @@ static void designware_pcie_host_init(Object *obj) qdev_prop_set_bit(DEVICE(root), "multifunction", false); } -static const TypeInfo designware_pcie_root_info = { - .name = TYPE_DESIGNWARE_PCIE_ROOT, - .parent = TYPE_PCI_BRIDGE, - .instance_size = sizeof(DesignwarePCIERoot), - .class_init = designware_pcie_root_class_init, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_PCIE_DEVICE }, - { } +static const TypeInfo designware_pcie_types[] = { + { + .name = TYPE_DESIGNWARE_PCIE_HOST, + .parent = TYPE_PCI_HOST_BRIDGE, + .instance_size = sizeof(DesignwarePCIEHost), + .instance_init = designware_pcie_host_init, + .class_init = designware_pcie_host_class_init, + }, { + .name = TYPE_DESIGNWARE_PCIE_ROOT, + .parent = TYPE_PCI_BRIDGE, + .instance_size = sizeof(DesignwarePCIERoot), + .class_init = designware_pcie_root_class_init, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_PCIE_DEVICE }, + { } + }, }, }; -static const TypeInfo designware_pcie_host_info = { - .name = TYPE_DESIGNWARE_PCIE_HOST, - .parent = TYPE_PCI_HOST_BRIDGE, - .instance_size = sizeof(DesignwarePCIEHost), - .instance_init = designware_pcie_host_init, - .class_init = designware_pcie_host_class_init, -}; - -static void designware_pcie_register(void) -{ - type_register_static(&designware_pcie_root_info); - type_register_static(&designware_pcie_host_info); -} -type_init(designware_pcie_register) +DEFINE_TYPES(designware_pcie_types) From patchwork Thu Oct 12 12:18:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 732475 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp917782wrv; Thu, 12 Oct 2023 05:22:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEGKu0loVokQZ9folL7d0Xaw37lnUw0Df/zYkRiIc2CPfpyketoQNBr9vt/TCJLZnQRkKOv X-Received: by 2002:a05:6102:5709:b0:457:a913:e89d with SMTP id dg9-20020a056102570900b00457a913e89dmr3309742vsb.12.1697113342120; Thu, 12 Oct 2023 05:22:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697113342; cv=none; d=google.com; s=arc-20160816; b=nl+/8D/TcJVeas4WK6sYuLmYy4LMh3xSieROTV3rM4M/mx8Aj5t0yl/Zp8jKvsvyVY 40sUQhvFJrOEybaKP9/bavYjATXzotvWHj4u0idZf1yIOXTnZdXlfh0ZovIQHvlHw8iB 9yiy843riL8aajlE/OOmS3vj3dNdR9zkkdP592tntxiN9db1o9xP/38fh/Db7zGaG3h2 4lNBBjFbOJoEt22ioJS3zT4BVHAFCxec96UDKRdI9kpXi89IuHbiUsgHMxZbY5thsKaB mHcQ+0muNGjKHisSNyZ+grjnraXBbl079w4BZ4tZ809lO0qjlEwVNJAnpONQhgOB7Kn4 Q4kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Fa15t5TAOGLEwbp/XmPMZ/3+NPt1m11OvXKqtHI65yw=; fh=uMYo3jOuXUsDthaXCE4/M6n3+voY5rtHQA7Grzg1cYU=; b=I4GhKohQ3qoYxaOa4XJSu242I+c3YBUrdU36dCxiQzaZ1TPwPBHseFAfwPgcaaSP+c 0FWmSbvFTIJNT6pGxco/KZmiiFbV9iL86ZamI53hB1TvoVu95kMWLlftDF5vm7I/b2u7 elY3KhGfzGz2EKc0mpoikW8wH1oY20Zxzc2E2KGHBK5GQeO+J4JhkRuR/yJaKOgyzl0L ar5bhmlXRnZR1VNuwDz3MuEr79jCRzX3tr32jBcEiyHBxhlO59inssG2xbk35fXV9v5r lGMnmQT1jTOMNbZoDv2GqU9n5ez7z0YBNMYtjEsr6caFaxaRY8OLlfXs8gl2a1gHNXVT ecMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XnsZHgGN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id x20-20020a170906299400b00997c1d125fasm11157488eje.170.2023.10.12.05.19.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/8] hw/pci-host/designware: Initialize root function in host bridge realize Date: Thu, 12 Oct 2023 14:18:50 +0200 Message-ID: <20231012121857.31873-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org There are no root function properties exposed by the host bridge, so using a 2-step QOM creation isn't really useful. Simplify by creating the root function when the host bridge is realized. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/designware.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 304eca1b5c..692e0731cd 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -707,6 +707,10 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp) "pcie-bus-address-space"); pci_setup_iommu(pci->bus, designware_pcie_host_set_iommu, s); + object_initialize_child(OBJECT(dev), "root", &s->root, + TYPE_DESIGNWARE_PCIE_ROOT); + qdev_prop_set_int32(DEVICE(&s->root), "addr", PCI_DEVFN(0, 0)); + qdev_prop_set_bit(DEVICE(&s->root), "multifunction", false); qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal); } @@ -736,22 +740,11 @@ static void designware_pcie_host_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_designware_pcie_host; } -static void designware_pcie_host_init(Object *obj) -{ - DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(obj); - DesignwarePCIERoot *root = &s->root; - - object_initialize_child(obj, "root", root, TYPE_DESIGNWARE_PCIE_ROOT); - qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); - qdev_prop_set_bit(DEVICE(root), "multifunction", false); -} - static const TypeInfo designware_pcie_types[] = { { .name = TYPE_DESIGNWARE_PCIE_HOST, .parent = TYPE_PCI_HOST_BRIDGE, .instance_size = sizeof(DesignwarePCIEHost), - .instance_init = designware_pcie_host_init, .class_init = designware_pcie_host_class_init, }, { .name = TYPE_DESIGNWARE_PCIE_ROOT, From patchwork Thu Oct 12 12:18:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 732474 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp917693wrv; Thu, 12 Oct 2023 05:22:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGGf5SzmRQU71MJ3ThlnTkZsWkarvzHtY9uxdKekqtDhvrz0Dv2N4veRwdxErmcw3H4y5qJ X-Received: by 2002:a81:6e88:0:b0:5a2:15bc:b32c with SMTP id j130-20020a816e88000000b005a215bcb32cmr26174677ywc.42.1697113330217; Thu, 12 Oct 2023 05:22:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697113330; cv=none; d=google.com; s=arc-20160816; b=cxY9lBXR348lveq5zb504+MlrMYHd5GqfUCCV843UM5RNBGEo2lk1X66LXHKKsea5k w1cd0tDFH5+UEPq407/6apWjg48un6TXo6SZhNjhtjduz0RGToNwIIt1gv5YPObzNSDU cFUUZPxsL7+S5hkqSk2f0L2gbGuwb13xwQqORqPqohkiteHFaUigcgyEWbUQ0K/dafxS gB77h8hiElbBEmxqT4otqtjcnLE058uAzvfio3zUJyP46RBwv0s14lNDewxbcsNWbkzg DG30ysMflmti21p/hqYPrXlF99C0TzzsGPFc5+bEGkzcGadMVnqE52lQFpxwkg0sgU3+ h49Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=x9j0wB4sagFap8UlCk3DGG3Emv5eeF0Xy9DDluHlDSM=; fh=uMYo3jOuXUsDthaXCE4/M6n3+voY5rtHQA7Grzg1cYU=; b=cyvhPEij1gYD2Qa98gMw5ELTXvobO5rrLUJWXDRNM56Ap6dxrsCsYlCmd7fvRojyFg qCqtjnu0KHAQqg2V2NrsPTU+7H3BrQA71kWoVo01/6IR0X7s7fnYrI1ylO22TbRDf6uV L/n9VDdV9lONOO6kEStvHHjFibYUznPKIj/9mFS/y9L9i59kBOEDThMWUKfwoKl/0ESJ 4zyWcQpq/HfRYBnL9n4wadS/9B5wUB5DZhdgjQtt/MHGRcdTj37mYse9fQwv9IG/Ob2a 6eM2vOYeJKLx2ALLLzKzsn3fOMRhwhtKLag0XttZrDm9RG/U2FFcoN33a/Dj+rwwL4nM K1ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Op3YQS6i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id f23-20020a170906139700b0098f99048053sm11226132ejc.148.2023.10.12.05.19.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:19 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 3/8] hw/pci-host/designware: Add 'host_mem' variable for clarity Date: Thu, 12 Oct 2023 14:18:51 +0200 Message-ID: <20231012121857.31873-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org designware_pcie_root_realize() uses get_system_memory() as the "host side memory region", as opposed to the "PCI side" one. Introduce the 'host_mem' variable for clarity. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/pci-host/designware.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 692e0731cd..bacb2bdb2d 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -393,6 +393,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) { DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev); DesignwarePCIEHost *host = designware_pcie_root_to_host(root); + MemoryRegion *host_mem = get_system_memory(); MemoryRegion *address_space = &host->pci.memory; PCIBridge *br = PCI_BRIDGE(dev); DesignwarePCIEViewport *viewport; @@ -433,7 +434,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; source = &host->pci.address_space_root; - destination = get_system_memory(); + destination = host_mem; direction = "Inbound"; /* @@ -458,7 +459,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) destination = &host->pci.memory; direction = "Outbound"; - source = get_system_memory(); + source = host_mem; /* * Configure MemoryRegion implementing CPU -> PCI memory From patchwork Thu Oct 12 12:18:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 732472 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp917617wrv; Thu, 12 Oct 2023 05:21:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFuScAmb8RDO7VZsLFHpTYz3yFVPApVImMAr0YNbwC7M1cvfV+NcW3MeXau5VHgrHQabD8l X-Received: by 2002:a05:6808:18:b0:3a8:ccf0:103f with SMTP id u24-20020a056808001800b003a8ccf0103fmr24513216oic.3.1697113319537; Thu, 12 Oct 2023 05:21:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697113319; cv=none; d=google.com; s=arc-20160816; b=Gip9w9JfaE1dvhFjW5uslkyv2+Kd5oqQwVPxTyX2eWlhm8OhdYvLWymAUWmSl9cbEf D/HYjhygmFSXvqXAUMVlqB/WBIXbamwlMFPOq06VztoLARbFAHKukeiP6sO+zJwJabFz bvrpqal1cZYy3LRXtlBRRmRrONlc+zyZ1LSJVjCXsovKN/4oHkgBWodV39JuNq0N7gR6 TH9P+pMhNldIovJl/yOd+9a9TnWFcVYZrQ0C4cOcTuPWAjK7Qcj87i+TsAchObZWpM3f 8kevJeTbfcjBJyqe7bYF+VTRKPBh9uC/DehauflFy52++u6BLmtsm97YWWvh/fTzdZpH 47+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xa2WXsDwKflmWK2k8quohK6TTrUH1twZfhC/r4NA1UE=; fh=uMYo3jOuXUsDthaXCE4/M6n3+voY5rtHQA7Grzg1cYU=; b=cYOKM+fvUQ90GV28WNkPYWmwjF1ezM6sIzKPVx+H+jU+z7qAQX1RF/07dpuHQrsufb KCtOri1erGwfTQj7/enEhaJCC9KbO8hGu+BMik1XProFOphZ7MSyH3lGRpvYo5f0yhAb AGqhmwh/HlvWCKRFJtEWIKEYwwixayChbtlpT/xqCTtsIaytq8qa+4BrUiXCCvEFjQX+ hSacsE45ZOY6fo1oBZxeQvfkP0J18Dc04fAhq1UaWlUEJ8qCL9bHv8BhCt+VZ7gyqGGi satt5SS9k0mkWwKAfK/Ukli9DXlUPXHxPvyPDk2JZV/LgFx5gJwx/lu4Ys3Yhpj3dyqM xo1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nLvXAOTh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id a23-20020a50ff17000000b005342fa19070sm10081874edu.89.2023.10.12.05.19.25 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 4/8] hw/pci-host/designware: Hoist host controller in root function #0 Date: Thu, 12 Oct 2023 14:18:52 +0200 Message-ID: <20231012121857.31873-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org There is always an unique root function for the host bridge controller. We create this function when the controller is realized, in designware_pcie_host_realize(). No need to call qdev_get_parent_bus() each time the root function want to resolve its host part. Hoist a pointer in its state. Set the pointer once when the function is realized. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci-host/designware.h | 1 + hw/pci-host/designware.c | 15 +++++---------- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h index c484e377a8..9e2caa04e9 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -71,6 +71,7 @@ struct DesignwarePCIERoot { DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS]; DesignwarePCIEMSI msi; + DesignwarePCIEHost *host; }; struct DesignwarePCIEHost { diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index bacb2bdb2d..fb46493a05 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -57,13 +57,6 @@ #define DESIGNWARE_PCIE_IRQ_MSI 3 -static DesignwarePCIEHost * -designware_pcie_root_to_host(DesignwarePCIERoot *root) -{ - BusState *bus = qdev_get_parent_bus(DEVICE(root)); - return DESIGNWARE_PCIE_HOST(bus->parent); -} - static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, unsigned size) { @@ -85,7 +78,7 @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque); - DesignwarePCIEHost *host = designware_pcie_root_to_host(root); + DesignwarePCIEHost *host = root->host; root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; @@ -300,7 +293,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, uint32_t val, int len) { DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); - DesignwarePCIEHost *host = designware_pcie_root_to_host(root); + DesignwarePCIEHost *host = root->host; DesignwarePCIEViewport *viewport = designware_pcie_root_get_current_viewport(root); @@ -392,7 +385,8 @@ static char *designware_pcie_viewport_name(const char *direction, static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) { DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev); - DesignwarePCIEHost *host = designware_pcie_root_to_host(root); + DesignwarePCIEHost *host = DESIGNWARE_PCIE_HOST( + qdev_get_parent_bus(DEVICE(dev))->parent); MemoryRegion *host_mem = get_system_memory(); MemoryRegion *address_space = &host->pci.memory; PCIBridge *br = PCI_BRIDGE(dev); @@ -406,6 +400,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) size_t i; br->bus_name = "dw-pcie"; + root->host = host; pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); From patchwork Thu Oct 12 12:18:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 732467 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp916572wrv; Thu, 12 Oct 2023 05:19:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFqaMsssQzmqunhBpEAW5IRa4L1w9nQdtlCNE7127CUUf70LpeHwRxsM1UxsfRgGUEgzi9C X-Received: by 2002:a25:5143:0:b0:d81:89e9:9f4c with SMTP id f64-20020a255143000000b00d8189e99f4cmr19545371ybb.39.1697113191658; Thu, 12 Oct 2023 05:19:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697113191; cv=none; d=google.com; s=arc-20160816; b=GwuSqcsJFcHotxQNiGAysXrbvoEn/W4URFLILVXesABZcNNvVhLNm50fE/xPwGGdjq m6DAbKEG4Dmlnq71DQ3SfiaZFpQODrcW4u4hxmPyyFEkVIuLVh/64N+lMJ1imgXv2QKn JesOG4mfU3g4HZx+1QaHr584+M39mDeNYyRBEqkS4+8553Ud5PbJczQV5apv8uqZSZ7y hXiC7B+uW7zAQtStVdyatZa6VQ+q707fu3HHiTIoErNPbkVc+0igztfNPu3/nu4EBxe7 bawCfKUhDGkb6kLRysIVg5ilW6/LAJlXKMgN2pGXi19HFdL20HUXNgUGX+jTYbWhdLPm kupQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=R+a0EyKEUxgm0lXUaYS7q8xxVvw9rO8rB+Ai3q4Lewo=; fh=uMYo3jOuXUsDthaXCE4/M6n3+voY5rtHQA7Grzg1cYU=; b=huBZI308GdrNWNHFXp63ZoWHkVTV8ncrZOXjCjw7r1VBovJByK7mJIyHDTFovsX1YM uyulzEU1uVwrvhT2CJXX75mMdA/cxMr638NfUjFuu0qQE9GUgSzc9yXvixYoKfClsdhu H031ZMEizp7N775NncxOmfV8Mlt8nyQ+jc5D8cff+kor2nyBUNAF8iIML1kqQxDrJKI/ 3FTlg7r97oR8Y0J1el6UdpSJ5pAe4a6qUhHEon3P8Kubrys9HnHml9ddEiQEeVOkzTlV D5Frz4577CVyp7p7xsKtB1LKnpMYeao9I3OVqyrckIMy+kSv1XqnAAaQmEs6dx32ffNo hqPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HRYzUdju; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id a6-20020a170906190600b009ad89697c86sm11081226eje.144.2023.10.12.05.19.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 5/8] hw/pci-host/designware: Keep host reference in DesignwarePCIEViewport Date: Thu, 12 Oct 2023 14:18:53 +0200 Message-ID: <20231012121857.31873-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The PCI root function is irrelevant for the ViewPort; only a reference to the host bridge is required. Since we can directly access the PCI bus, remove the pci_get_bus() call. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci-host/designware.h | 2 +- hw/pci-host/designware.c | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h index 9e2caa04e9..e1952ad324 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -32,7 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIEHost, DESIGNWARE_PCIE_HOST) OBJECT_DECLARE_SIMPLE_TYPE(DesignwarePCIERoot, DESIGNWARE_PCIE_ROOT) typedef struct DesignwarePCIEViewport { - DesignwarePCIERoot *root; + DesignwarePCIEHost *host; MemoryRegion cfg; MemoryRegion mem; diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index fb46493a05..d12a36b628 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -211,12 +211,11 @@ static uint64_t designware_pcie_root_data_access(void *opaque, hwaddr addr, uint64_t *val, unsigned len) { DesignwarePCIEViewport *viewport = opaque; - DesignwarePCIERoot *root = viewport->root; + PCIHostState *pci = PCI_HOST_BRIDGE(viewport->host); const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target); const uint8_t devfn = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target); - PCIBus *pcibus = pci_get_bus(PCI_DEVICE(root)); - PCIDevice *pcidev = pci_find_device(pcibus, busnum, devfn); + PCIDevice *pcidev = pci_find_device(pci->bus, busnum, devfn); if (pcidev) { addr &= pci_config_size(pcidev) - 1; @@ -445,7 +444,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) g_free(name); viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i]; - viewport->root = root; + viewport->host = host; viewport->inbound = false; viewport->base = 0x0000000000000000ULL; viewport->target = 0x0000000000000000ULL; From patchwork Thu Oct 12 12:18:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 732468 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp916614wrv; Thu, 12 Oct 2023 05:19:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFJRF9lYSznlYozwbUunic84xUtCI1wo3MyISPHGSSfK8i0uOfjq6hgKbBEaob75UQkxhYB X-Received: by 2002:a05:620a:f0d:b0:76c:a9a1:a318 with SMTP id v13-20020a05620a0f0d00b0076ca9a1a318mr27933226qkl.6.1697113197528; Thu, 12 Oct 2023 05:19:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697113197; cv=none; d=google.com; s=arc-20160816; b=qFIsAK8u9pPL1oNPc2/UbRXKQJDA8vJI5tXt4uAUS7Yn+2Vj7pmHCg8RkPW8kZqXyE 3fdfuZ/4CzMRKY7QBoXT3xtKm+FNYIcxfLylnhiOVHkepJJWGTOo7jp9FkDZ9MhfkgaL 2XMBxTf00UYtEFhrcefQ083XtVqfkzOlWX6MGSsart+poTic5fFg6GtRafSVe3vba03R OeR0tTdUj8qJyqwpRs1K3/sTZbm+5nk/Sk+bIbDijHQaaWYkb80z/A8ZyB1iVOS5/M2Y 6aJ2KfP2n8aYNeXxSIGh/X5mrIAFfM7a3h+aPJ5ENyO//WlyxI4+JewGGUsQp8zrsRjy qNUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4YRr81WGc0jZpkwI738+aZ2Qnn+FlQH2u0zMxI+6iKE=; fh=uMYo3jOuXUsDthaXCE4/M6n3+voY5rtHQA7Grzg1cYU=; b=M/Ol27D/zFkpCzlFFzVeVGn9aWxXAvkfxttNlsfgFM09HHRns8rVDzMw7lf2SzENzJ PlDRobM3cKf57FReEfPZ8C0rkdeSFBc1M6ZSKZ97NtlIlPhGVL5rTwaHV7+0VsauRQ0H ceFZvg/8dpIEeHRSP6GeH3xmyZMPYug5OmbbyDoOFEqqJEA0Tmw72AOTLzX3gkKWzfVJ /jKdbL4TRjIzFLUi1TsD6T0XunBAODpKebP1N2sKRV8cSF+AgTsyse3ojPCCveXF2om/ 7DwY0QCYkvXWbTm23XQnzsj0o8PF/rdhlgk5BGW+9Ac2Qzmy1xM2XqxBm2WauAQiqQcb 7PdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NlTVkg3M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id gh18-20020a170906e09200b009786c8249d6sm11146880ejb.175.2023.10.12.05.19.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 6/8] hw/pci-host/designware: Move viewports from root func to host bridge Date: Thu, 12 Oct 2023 14:18:54 +0200 Message-ID: <20231012121857.31873-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org As mentioned in previous commit, the PCI root function is irrelevant for the ViewPorts. Move the fields to the host bridge state. This is a migration compatibility break for the machines using the i.MX7 SoC (currently the mcimx7d-sabre machine). Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci-host/designware.h | 13 ++++----- hw/pci-host/designware.c | 47 ++++++++++++++++---------------- 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h index e1952ad324..702777ab17 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -63,13 +63,6 @@ typedef struct DesignwarePCIEMSI { struct DesignwarePCIERoot { PCIBridge parent_obj; - uint32_t atu_viewport; - -#define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND 0 -#define DESIGNWARE_PCIE_VIEWPORT_INBOUND 1 -#define DESIGNWARE_PCIE_NUM_VIEWPORTS 4 - - DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS]; DesignwarePCIEMSI msi; DesignwarePCIEHost *host; }; @@ -79,6 +72,12 @@ struct DesignwarePCIEHost { DesignwarePCIERoot root; + uint32_t atu_viewport; +#define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND 0 +#define DESIGNWARE_PCIE_VIEWPORT_INBOUND 1 +#define DESIGNWARE_PCIE_NUM_VIEWPORTS 4 + DesignwarePCIEViewport viewports[2][DESIGNWARE_PCIE_NUM_VIEWPORTS]; + struct { AddressSpace address_space; MemoryRegion address_space_root; diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index d12a36b628..2ef17137e2 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -109,20 +109,21 @@ static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root) } static DesignwarePCIEViewport * -designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root) +designware_pcie_host_get_current_viewport(DesignwarePCIEHost *host) { - const unsigned int idx = root->atu_viewport & 0xF; + const unsigned int idx = host->atu_viewport & 0xF; const unsigned int dir = - !!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND); - return &root->viewports[dir][idx]; + !!(host->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND); + return &host->viewports[dir][idx]; } static uint32_t designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len) { DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); + DesignwarePCIEHost *host = root->host; DesignwarePCIEViewport *viewport = - designware_pcie_root_get_current_viewport(root); + designware_pcie_host_get_current_viewport(host); uint32_t val; @@ -170,7 +171,7 @@ designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len) break; case DESIGNWARE_PCIE_ATU_VIEWPORT: - val = root->atu_viewport; + val = host->atu_viewport; break; case DESIGNWARE_PCIE_ATU_LOWER_BASE: @@ -294,7 +295,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); DesignwarePCIEHost *host = root->host; DesignwarePCIEViewport *viewport = - designware_pcie_root_get_current_viewport(root); + designware_pcie_host_get_current_viewport(host); switch (address) { case DESIGNWARE_PCIE_PORT_LINK_CONTROL: @@ -332,7 +333,7 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, break; case DESIGNWARE_PCIE_ATU_VIEWPORT: - root->atu_viewport = val; + host->atu_viewport = val; break; case DESIGNWARE_PCIE_ATU_LOWER_BASE: @@ -420,7 +421,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) const char *direction; char *name; - viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i]; + viewport = &host->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i]; viewport->inbound = true; viewport->base = 0x0000000000000000ULL; viewport->target = 0x0000000000000000ULL; @@ -443,7 +444,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) memory_region_set_enabled(mem, false); g_free(name); - viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i]; + viewport = &host->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i]; viewport->host = host; viewport->inbound = false; viewport->base = 0x0000000000000000ULL; @@ -490,7 +491,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) * NOTE: This will not work correctly for the case when first * configured inbound window is window 0 */ - viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0]; + viewport = &host->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0]; viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE; designware_pcie_update_viewport(root, viewport); @@ -563,18 +564,10 @@ static const VMStateDescription vmstate_designware_pcie_viewport = { static const VMStateDescription vmstate_designware_pcie_root = { .name = "designware-pcie-root", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), - VMSTATE_UINT32(atu_viewport, DesignwarePCIERoot), - VMSTATE_STRUCT_2DARRAY(viewports, - DesignwarePCIERoot, - 2, - DESIGNWARE_PCIE_NUM_VIEWPORTS, - 1, - vmstate_designware_pcie_viewport, - DesignwarePCIEViewport), VMSTATE_STRUCT(msi, DesignwarePCIERoot, 1, @@ -711,14 +704,22 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp) static const VMStateDescription vmstate_designware_pcie_host = { .name = "designware-pcie-host", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { VMSTATE_STRUCT(root, DesignwarePCIEHost, 1, vmstate_designware_pcie_root, DesignwarePCIERoot), + VMSTATE_UINT32(atu_viewport, DesignwarePCIEHost), + VMSTATE_STRUCT_2DARRAY(viewports, + DesignwarePCIEHost, + 2, + DESIGNWARE_PCIE_NUM_VIEWPORTS, + 1, + vmstate_designware_pcie_viewport, + DesignwarePCIEViewport), VMSTATE_END_OF_LIST() } }; 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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id a6-20020a170906190600b009ad89697c86sm11081434eje.144.2023.10.12.05.19.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:44 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 7/8] hw/pci-host/designware: Move MSI registers from root func to host bridge Date: Thu, 12 Oct 2023 14:18:55 +0200 Message-ID: <20231012121857.31873-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philmd@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The MSI registers belong the the host bridge. Move the DesignwarePCIEMSI field to the host bridge state. This is a migration compatibility break for the machines using the i.MX7 SoC (currently the mcimx7d-sabre machine). Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci-host/designware.h | 2 +- hw/pci-host/designware.c | 79 ++++++++++++++++---------------- 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designware.h index 702777ab17..fe8e8a9f24 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -63,7 +63,6 @@ typedef struct DesignwarePCIEMSI { struct DesignwarePCIERoot { PCIBridge parent_obj; - DesignwarePCIEMSI msi; DesignwarePCIEHost *host; }; @@ -71,6 +70,7 @@ struct DesignwarePCIEHost { PCIHostState parent_obj; DesignwarePCIERoot root; + DesignwarePCIEMSI msi; uint32_t atu_viewport; #define DESIGNWARE_PCIE_VIEWPORT_OUTBOUND 0 diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 2ef17137e2..6cb8655a75 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -57,7 +57,7 @@ #define DESIGNWARE_PCIE_IRQ_MSI 3 -static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, +static uint64_t designware_pcie_host_msi_read(void *opaque, hwaddr addr, unsigned size) { /* @@ -74,22 +74,21 @@ static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, return 0; } -static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, +static void designware_pcie_host_msi_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { - DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque); - DesignwarePCIEHost *host = root->host; + DesignwarePCIEHost *host = opaque; - root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; + host->msi.intr[0].status |= BIT(val) & host->msi.intr[0].enable; - if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { + if (host->msi.intr[0].status & ~host->msi.intr[0].mask) { qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1); } } static const MemoryRegionOps designware_pci_host_msi_ops = { - .read = designware_pcie_root_msi_read, - .write = designware_pcie_root_msi_write, + .read = designware_pcie_host_msi_read, + .write = designware_pcie_host_msi_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 4, @@ -97,12 +96,12 @@ static const MemoryRegionOps designware_pci_host_msi_ops = { }, }; -static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root) +static void designware_pcie_host_update_msi_mapping(DesignwarePCIEHost *host) { - MemoryRegion *mem = &root->msi.iomem; - const uint64_t base = root->msi.base; - const bool enable = root->msi.intr[0].enable; + MemoryRegion *mem = &host->msi.iomem; + const uint64_t base = host->msi.base; + const bool enable = host->msi.intr[0].enable; memory_region_set_address(mem, base); memory_region_set_enabled(mem, enable); @@ -147,23 +146,23 @@ designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len) break; case DESIGNWARE_PCIE_MSI_ADDR_LO: - val = root->msi.base; + val = host->msi.base; break; case DESIGNWARE_PCIE_MSI_ADDR_HI: - val = root->msi.base >> 32; + val = host->msi.base >> 32; break; case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: - val = root->msi.intr[0].enable; + val = host->msi.intr[0].enable; break; case DESIGNWARE_PCIE_MSI_INTR0_MASK: - val = root->msi.intr[0].mask; + val = host->msi.intr[0].mask; break; case DESIGNWARE_PCIE_MSI_INTR0_STATUS: - val = root->msi.intr[0].status; + val = host->msi.intr[0].status; break; case DESIGNWARE_PCIE_PHY_DEBUG_R1: @@ -305,29 +304,29 @@ static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, break; case DESIGNWARE_PCIE_MSI_ADDR_LO: - root->msi.base &= 0xFFFFFFFF00000000ULL; - root->msi.base |= val; - designware_pcie_root_update_msi_mapping(root); + host->msi.base &= 0xFFFFFFFF00000000ULL; + host->msi.base |= val; + designware_pcie_host_update_msi_mapping(host); break; case DESIGNWARE_PCIE_MSI_ADDR_HI: - root->msi.base &= 0x00000000FFFFFFFFULL; - root->msi.base |= (uint64_t)val << 32; - designware_pcie_root_update_msi_mapping(root); + host->msi.base &= 0x00000000FFFFFFFFULL; + host->msi.base |= (uint64_t)val << 32; + designware_pcie_host_update_msi_mapping(host); break; case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: - root->msi.intr[0].enable = val; - designware_pcie_root_update_msi_mapping(root); + host->msi.intr[0].enable = val; + designware_pcie_host_update_msi_mapping(host); break; case DESIGNWARE_PCIE_MSI_INTR0_MASK: - root->msi.intr[0].mask = val; + host->msi.intr[0].mask = val; break; case DESIGNWARE_PCIE_MSI_INTR0_STATUS: - root->msi.intr[0].status ^= val; - if (!root->msi.intr[0].status) { + host->msi.intr[0].status ^= val; + if (!host->msi.intr[0].status) { qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0); } break; @@ -495,7 +494,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE; designware_pcie_update_viewport(root, viewport); - memory_region_init_io(&root->msi.iomem, OBJECT(root), + memory_region_init_io(&host->msi.iomem, OBJECT(root), &designware_pci_host_msi_ops, root, "pcie-msi", 0x4); /* @@ -504,8 +503,8 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) * in designware_pcie_root_update_msi_mapping() as a part of * initialization done by guest OS */ - memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem); - memory_region_set_enabled(&root->msi.iomem, false); + memory_region_add_subregion(address_space, dummy_offset, &host->msi.iomem); + memory_region_set_enabled(&host->msi.iomem, false); } static void designware_pcie_set_irq(void *opaque, int irq_num, int level) @@ -564,15 +563,10 @@ static const VMStateDescription vmstate_designware_pcie_viewport = { static const VMStateDescription vmstate_designware_pcie_root = { .name = "designware-pcie-root", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), - VMSTATE_STRUCT(msi, - DesignwarePCIERoot, - 1, - vmstate_designware_pcie_msi, - DesignwarePCIEMSI), VMSTATE_END_OF_LIST() } }; @@ -704,8 +698,8 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp) static const VMStateDescription vmstate_designware_pcie_host = { .name = "designware-pcie-host", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (VMStateField[]) { VMSTATE_STRUCT(root, DesignwarePCIEHost, @@ -720,6 +714,11 @@ static const VMStateDescription vmstate_designware_pcie_host = { 1, vmstate_designware_pcie_viewport, DesignwarePCIEViewport), + VMSTATE_STRUCT(msi, + DesignwarePCIEHost, + 1, + vmstate_designware_pcie_msi, + DesignwarePCIEMSI), VMSTATE_END_OF_LIST() } }; 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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id c25-20020aa7d619000000b0053622a35665sm9929836edr.66.2023.10.12.05.19.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 8/8] hw/pci-host/designware: Create ViewPorts during host bridge realization Date: Thu, 12 Oct 2023 14:18:56 +0200 Message-ID: <20231012121857.31873-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=philmd@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ViewPorts are managed by the host bridge part, so create them when the host bridge is realized. The host bridge become the owner of the memory regions. The PCI root function realize() method now only contains PCI specific code. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/designware.c | 207 +++++++++++++++++++-------------------- 1 file changed, 102 insertions(+), 105 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 6cb8655a75..e5dc9b4b8d 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -384,22 +384,10 @@ static char *designware_pcie_viewport_name(const char *direction, static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) { DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev); - DesignwarePCIEHost *host = DESIGNWARE_PCIE_HOST( - qdev_get_parent_bus(DEVICE(dev))->parent); - MemoryRegion *host_mem = get_system_memory(); - MemoryRegion *address_space = &host->pci.memory; PCIBridge *br = PCI_BRIDGE(dev); - DesignwarePCIEViewport *viewport; - /* - * Dummy values used for initial configuration of MemoryRegions - * that belong to a given viewport - */ - const hwaddr dummy_offset = 0; - const uint64_t dummy_size = 4; - size_t i; br->bus_name = "dw-pcie"; - root->host = host; + root->host = DESIGNWARE_PCIE_HOST(qdev_get_parent_bus(DEVICE(dev))->parent); pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); @@ -414,97 +402,6 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) msi_nonbroken = true; msi_init(dev, 0x50, 32, true, true, &error_fatal); - - for (i = 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) { - MemoryRegion *source, *destination, *mem; - const char *direction; - char *name; - - viewport = &host->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i]; - viewport->inbound = true; - viewport->base = 0x0000000000000000ULL; - viewport->target = 0x0000000000000000ULL; - viewport->limit = UINT32_MAX; - viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; - - source = &host->pci.address_space_root; - destination = host_mem; - direction = "Inbound"; - - /* - * Configure MemoryRegion implementing PCI -> CPU memory - * access - */ - mem = &viewport->mem; - name = designware_pcie_viewport_name(direction, i, "MEM"); - memory_region_init_alias(mem, OBJECT(root), name, destination, - dummy_offset, dummy_size); - memory_region_add_subregion_overlap(source, dummy_offset, mem, -1); - memory_region_set_enabled(mem, false); - g_free(name); - - viewport = &host->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i]; - viewport->host = host; - viewport->inbound = false; - viewport->base = 0x0000000000000000ULL; - viewport->target = 0x0000000000000000ULL; - viewport->limit = UINT32_MAX; - viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; - - destination = &host->pci.memory; - direction = "Outbound"; - source = host_mem; - - /* - * Configure MemoryRegion implementing CPU -> PCI memory - * access - */ - mem = &viewport->mem; - name = designware_pcie_viewport_name(direction, i, "MEM"); - memory_region_init_alias(mem, OBJECT(root), name, destination, - dummy_offset, dummy_size); - memory_region_add_subregion(source, dummy_offset, mem); - memory_region_set_enabled(mem, false); - g_free(name); - - /* - * Configure MemoryRegion implementing access to configuration - * space - */ - mem = &viewport->cfg; - name = designware_pcie_viewport_name(direction, i, "CFG"); - memory_region_init_io(&viewport->cfg, OBJECT(root), - &designware_pci_host_conf_ops, - viewport, name, dummy_size); - memory_region_add_subregion(source, dummy_offset, mem); - memory_region_set_enabled(mem, false); - g_free(name); - } - - /* - * If no inbound iATU windows are configured, HW defaults to - * letting inbound TLPs to pass in. We emulate that by explicitly - * configuring first inbound window to cover all of target's - * address space. - * - * NOTE: This will not work correctly for the case when first - * configured inbound window is window 0 - */ - viewport = &host->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0]; - viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE; - designware_pcie_update_viewport(root, viewport); - - memory_region_init_io(&host->msi.iomem, OBJECT(root), - &designware_pci_host_msi_ops, - root, "pcie-msi", 0x4); - /* - * We initially place MSI interrupt I/O region at address 0 and - * disable it. It'll be later moved to correct offset and enabled - * in designware_pcie_root_update_msi_mapping() as a part of - * initialization done by guest OS - */ - memory_region_add_subregion(address_space, dummy_offset, &host->msi.iomem); - memory_region_set_enabled(&host->msi.iomem, false); } static void designware_pcie_set_irq(void *opaque, int irq_num, int level) @@ -590,7 +487,7 @@ static void designware_pcie_root_class_init(ObjectClass *klass, void *data) dc->reset = pci_bridge_reset; /* * PCI-facing part of the host bridge, not usable without the - * host-facing part, which can't be device_add'ed, yet. + * host-facing part. */ dc->user_creatable = false; dc->vmsd = &vmstate_designware_pcie_root; @@ -650,8 +547,17 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp) PCIHostState *pci = PCI_HOST_BRIDGE(dev); DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + MemoryRegion *host_mem = get_system_memory(); + DesignwarePCIEViewport *viewport; size_t i; + /* + * Dummy values used for initial configuration of MemoryRegions + * that belong to a given viewport + */ + const hwaddr dummy_offset = 0; + const uint64_t dummy_size = 4; + for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) { sysbus_init_irq(sbd, &s->pci.irqs[i]); } @@ -694,6 +600,97 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp) qdev_prop_set_int32(DEVICE(&s->root), "addr", PCI_DEVFN(0, 0)); qdev_prop_set_bit(DEVICE(&s->root), "multifunction", false); qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal); + + memory_region_init_io(&s->msi.iomem, OBJECT(s), + &designware_pci_host_msi_ops, + s, "pcie-msi", 0x4); + /* + * We initially place MSI interrupt I/O region at address 0 and + * disable it. It'll be later moved to correct offset and enabled + * in designware_pcie_host_update_msi_mapping() as a part of + * initialization done by guest OS + */ + memory_region_add_subregion(&s->pci.memory, dummy_offset, &s->msi.iomem); + memory_region_set_enabled(&s->msi.iomem, false); + + for (i = 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) { + MemoryRegion *source, *destination, *mem; + const char *direction; + char *name; + + viewport = &s->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i]; + viewport->inbound = true; + viewport->base = 0x0000000000000000ULL; + viewport->target = 0x0000000000000000ULL; + viewport->limit = UINT32_MAX; + viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; + + source = &s->pci.address_space_root; + destination = host_mem; + direction = "Inbound"; + + /* + * Configure MemoryRegion implementing PCI -> CPU memory + * access + */ + mem = &viewport->mem; + name = designware_pcie_viewport_name(direction, i, "MEM"); + memory_region_init_alias(mem, OBJECT(s), name, destination, + dummy_offset, dummy_size); + memory_region_add_subregion_overlap(source, dummy_offset, mem, -1); + memory_region_set_enabled(mem, false); + g_free(name); + + viewport = &s->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i]; + viewport->host = s; + viewport->inbound = false; + viewport->base = 0x0000000000000000ULL; + viewport->target = 0x0000000000000000ULL; + viewport->limit = UINT32_MAX; + viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; + + destination = &s->pci.memory; + direction = "Outbound"; + source = host_mem; + + /* + * Configure MemoryRegion implementing CPU -> PCI memory + * access + */ + mem = &viewport->mem; + name = designware_pcie_viewport_name(direction, i, "MEM"); + memory_region_init_alias(mem, OBJECT(s), name, destination, + dummy_offset, dummy_size); + memory_region_add_subregion(source, dummy_offset, mem); + memory_region_set_enabled(mem, false); + g_free(name); + + /* + * Configure MemoryRegion implementing access to configuration + * space + */ + mem = &viewport->cfg; + name = designware_pcie_viewport_name(direction, i, "CFG"); + memory_region_init_io(&viewport->cfg, OBJECT(s), + &designware_pci_host_conf_ops, + viewport, name, dummy_size); + memory_region_add_subregion(source, dummy_offset, mem); + memory_region_set_enabled(mem, false); + g_free(name); + } + + /* + * If no inbound iATU windows are configured, HW defaults to + * letting inbound TLPs to pass in. We emulate that by explicitly + * configuring first inbound window to cover all of target's + * address space. + * + * NOTE: This will not work correctly for the case when first + * configured inbound window is window 0 + */ + viewport = &s->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0]; + viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE; + designware_pcie_update_viewport(&s->root, viewport); } static const VMStateDescription vmstate_designware_pcie_host = {