From patchwork Tue Oct 10 08:59:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 731835 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B7A8CD690A for ; Tue, 10 Oct 2023 08:59:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229533AbjJJI7o (ORCPT ); Tue, 10 Oct 2023 04:59:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229539AbjJJI7n (ORCPT ); Tue, 10 Oct 2023 04:59:43 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7252CA4; Tue, 10 Oct 2023 01:59:38 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-58916df84c8so3414075a12.3; Tue, 10 Oct 2023 01:59:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696928377; x=1697533177; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nJQrTaJjPi0Je/kfhPU0DQ5oya5Qf9MZSqPuDbE0Nms=; b=ahQYp+b+SNyVKnOGaEF2d3hq7fuYdVWGQHAS7MjB19zTF75UCa+UYJBVb3EH2Cu2+4 lqAXijhW9dmZvBs8bnasx43/nqQ2oIbMb4Rnu019BvxPKLAa3uEezxRJA1fMtrtsZguf aJqENAPnoTh0KkG2Z1RZ41pyNkvH5Zlc4LIXWIm4tgVbJivI7BhMoqn3tswLExWugqst W0Mcy/OKtlAdLlzjB8QvB9bIobBe/0FO46qYasn7Xnw0AaIreldQLRW6GZqmPk82LqXK 2h8XXrPEeDxjVvDqhsiWPLSO5mIOBJCdVS9Ob/H7wZYLaVT/cMHwU/sSpEKEj5bCruyX 6B0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696928377; x=1697533177; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nJQrTaJjPi0Je/kfhPU0DQ5oya5Qf9MZSqPuDbE0Nms=; b=Jqkk7d+JfpGNfbJU3oJGes3FknhpSvahY8CG2d4JMv5THeI4bkMvus4ynwykPhencm h0K/7KbX/iXSjlNc0em8OQfPBdskasRvJC99GB+sa5YmSQ+Z4DjKL+uXUZlO6UKZCbCx 4ht2gQEI+ih3STIPK1E6GMGj4qe5rt9zI13lr0TJltYWPPaxBc+kXKTsseOLrwsushkt sf/66bfLBtAUuijDUgNICbi4IWCsOq9ygtqcG+K1qRMRSGnww0Y3v7uONEXi9WAgagVu Epgmrvq4DchrQ1r9ILOw4c7XOE2q/FnwmQdn+txrg9p+5cazQpQQqlXy/Cmohlm6sns/ 0p0Q== X-Gm-Message-State: AOJu0YwT0A/qArtKQNz8jUq7J7AF8fEhM3C9xWlTkXvOpqhRySFbfB6M TQW3yfYNIK1sWW/pXftgnq8Rs+wnchQ= X-Google-Smtp-Source: AGHT+IHiDzgTslln6QB9BjU5V4YxjCpd8q1lMFq/5OF/t2L4x4RwUoLdTLB8v/D8FsZ4ezkuvTZhdQ== X-Received: by 2002:a17:90b:4b86:b0:279:e5e:ea1b with SMTP id lr6-20020a17090b4b8600b002790e5eea1bmr15363646pjb.5.1696928377627; Tue, 10 Oct 2023 01:59:37 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:646:a201:19d0:f462:7ab2:1aaa:db73]) by smtp.gmail.com with ESMTPSA id o12-20020a17090a3d4c00b0027782f611d1sm12542731pjf.36.2023.10.10.01.59.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 01:59:37 -0700 (PDT) From: Max Filippov To: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org Cc: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Max Filippov Subject: [PATCH v5 1/5] serial: core: tidy invalid baudrate handling in uart_get_baud_rate Date: Tue, 10 Oct 2023 01:59:22 -0700 Message-Id: <20231010085926.1021667-2-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20231010085926.1021667-1-jcmvbkbc@gmail.com> References: <20231010085926.1021667-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org uart_get_baud_rate has input parameters 'min' and 'max' limiting the range of acceptable baud rates from the caller's perspective. If neither current or old termios structures have acceptable baud rate setting and 9600 is not in the min/max range either the function returns 0 and issues a warning. However for a UART that does not support speed of 9600 baud this is expected behavior. Clarify that 0 can be (and always could be) returned from the uart_get_baud_rate. Don't issue a warning in that case. Signed-off-by: Max Filippov --- Changes v4->v5: - fix commit message Changes v3->v4: - drop WARN_ON from uart_get_divisor() drivers/tty/serial/serial_core.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c index 7bdc21d5e13b..3f130fe9f1a0 100644 --- a/drivers/tty/serial/serial_core.c +++ b/drivers/tty/serial/serial_core.c @@ -431,7 +431,7 @@ EXPORT_SYMBOL(uart_update_timeout); * baud. * * If the new baud rate is invalid, try the @old termios setting. If it's still - * invalid, we try 9600 baud. + * invalid, we try 9600 baud. If that is also invalid 0 is returned. * * The @termios structure is updated to reflect the baud rate we're actually * going to be using. Don't do this for the case where B0 is requested ("hang @@ -515,8 +515,6 @@ uart_get_baud_rate(struct uart_port *port, struct ktermios *termios, max - 1, max - 1); } } - /* Should never happen */ - WARN_ON(1); return 0; } EXPORT_SYMBOL(uart_get_baud_rate); From patchwork Tue Oct 10 08:59:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Max Filippov X-Patchwork-Id: 731833 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 374DFCD6911 for ; Tue, 10 Oct 2023 08:59:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229797AbjJJI7r (ORCPT ); Tue, 10 Oct 2023 04:59:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51174 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229609AbjJJI7o (ORCPT ); Tue, 10 Oct 2023 04:59:44 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC28EB0; Tue, 10 Oct 2023 01:59:40 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id 41be03b00d2f7-564af0ac494so3578424a12.0; Tue, 10 Oct 2023 01:59:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696928380; x=1697533180; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gw8iqjyrBtgTVh/NK/8WnPkyoN5gU6XxnEm9Y4H4sTU=; b=Aety5nryhyEMWUUiSYDx5AIt6mhuE+hSeKsya19eYMEi5+OqswRkWK/7lbBsSwUBfn 7CMns7e2uk1OitbcBiSqDAIANah7ZHk1KS4Pc25Yuu4hPI7my9HGWamoNS5zP3oGZ42T k2rX6EpJhbawT3r6CXHlxWQzrMuoOLnreVo1dYFrSFltNQ2iEKURD9v0Pr8M3ZWH1aht 4vq+XVULTDY8o+44R9W6hVZecE9IbMQP8ZdaU6B6aAz2dN6yXuIYGNNMU59wi/buwZU/ n5YKeYK6ufyjc1uvYnSo3O9K27bHeQzejdkTli8vNcJUfeDaa2r4xNry1clCXRQmweMQ EvrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696928380; x=1697533180; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gw8iqjyrBtgTVh/NK/8WnPkyoN5gU6XxnEm9Y4H4sTU=; b=T3A7riwE7zQY+IfLTNpa8r1SMSUqlVpBWqHJGhLwtuArWyMCuWG452BPj/QV9Wt9LE wrvYKBsTlBOzCFfsAIgW0JlgatR/XpTRxv8nBEVdFYXov7AzNmTF5jj3A7fJQdJl5zGX uYkDiYmAMFEfWTCamu+ku1v5fEgkKvnwnipMarZaWAWxakSfhP9V3ZY030s/bk6TXEMN kHA0TuyJByl6EgiBSAsD2tJmSuHoeeRS/DMWwL3dTaHlZjzDB2Y1JCYsmLRhVO0omaXF xSgGRLoIOfzZXQak86hJJe+gy4/Ij3UYMG0VmWsA6HYeBJiOM/Ipu/uZT5Q/vRJXV+Zu 6Z1Q== X-Gm-Message-State: AOJu0YxCW8elv7X3PsMcDV7ay193+t9wVJtnrZn5iRMLWEVavOkIKCO+ mmh+ux/mhJIjxKm8dO9OsmWTP8YMujo= X-Google-Smtp-Source: AGHT+IGlfE/JvR60sIAzWysB1ZllZzpDLXzeCJMWPX/a8kwy5Xingh1B/1HfvYnhXSONPZWlP6Pdug== X-Received: by 2002:a17:90b:30cb:b0:279:cea:cfa9 with SMTP id hi11-20020a17090b30cb00b002790ceacfa9mr14293170pjb.21.1696928379874; Tue, 10 Oct 2023 01:59:39 -0700 (PDT) Received: from octofox.hsd1.ca.comcast.net ([2601:646:a201:19d0:f462:7ab2:1aaa:db73]) by smtp.gmail.com with ESMTPSA id o12-20020a17090a3d4c00b0027782f611d1sm12542731pjf.36.2023.10.10.01.59.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 01:59:39 -0700 (PDT) From: Max Filippov To: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org Cc: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Max Filippov Subject: [PATCH v5 3/5] drivers/tty/serial: add driver for the ESP32 UART Date: Tue, 10 Oct 2023 01:59:24 -0700 Message-Id: <20231010085926.1021667-4-jcmvbkbc@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20231010085926.1021667-1-jcmvbkbc@gmail.com> References: <20231010085926.1021667-1-jcmvbkbc@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add driver for the UART controllers of the Espressif ESP32 and ESP32S3 SoCs. Hardware specification is available at the following URLs: https://www.espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf (Chapter 13 UART Controller) https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf (Chapter 26 UART Controller) Signed-off-by: Max Filippov --- Changes v4->v5: - use PORT_GENERIC instead of unique PORT_ESP32UART Changes v2->v3: - rework brk handling in esp32_uart_rxint - only increment port->icount.rx in case insert_flip_char() is called - use HZ instead of msecs_to_jiffies(1000) in esp32_uart_put_char_sync - add early return to esp32_uart_transmit_buffer - use request_irq/free_irq instead of devm_* versions - add blank lines before certain return statements Changes v1->v2: - redefine register fields using BIT and GENMASK - drop _MASK suffix from register field definitions - drop *_SHIFT definitions where possible - drop unused rxfifo_full_thrhd_mask and txfifo_empty_thrhd_mask - split register reads/writes and bitwise operations into multiple lines - use u8 instead of unsigned char in internal functions - add timeout to esp32_uart_put_char_sync - use uart_port_tx_limited in esp32_uart_transmit_buffer - use IRQ_RETVAL in esp32_uart_int - disable clock in esp32_uart_startup in case devm_request_irq fails - rearrange devm_request_irq with enabling IRQs in the UART registers - drop empty esp32_uart_release_port and esp32_uart_request_port - simplify esp32_uart_tx_empty - mask out unsupported CMSPAR flag in termios->c_cflag in esp32_uart_set_termios - invoke uart_update_timeout in esp32_uart_set_termios - drop MODULE_DESCRIPTION - rearrange esp32_uart_set_baud: return bool indicating whether baud rate was set or not, use it in the esp32_uart_set_termios to set the default 115200 - turn 'locked' into bool in esp32_uart_console_write - turn num_read into unsigned int in esp32_uart_earlycon_read drivers/tty/serial/Kconfig | 13 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/esp32_uart.c | 741 ++++++++++++++++++++++++++++++++ 3 files changed, 755 insertions(+) create mode 100644 drivers/tty/serial/esp32_uart.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index bdc568a4ab66..d9ca6b268f01 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -1578,6 +1578,19 @@ config SERIAL_NUVOTON_MA35D1_CONSOLE but you can alter that using a kernel command line option such as "console=ttyNVTx". +config SERIAL_ESP32 + tristate "Espressif ESP32 UART support" + depends on XTENSA_PLATFORM_ESP32 || (COMPILE_TEST && OF) + select SERIAL_CORE + select SERIAL_CORE_CONSOLE + select SERIAL_EARLYCON + help + Driver for the UART controllers of the Espressif ESP32xx SoCs. + When earlycon option is enabled the following kernel command line + snippets may be used: + earlycon=esp32s3uart,mmio32,0x60000000,115200n8,40000000 + earlycon=esp32uart,mmio32,0x3ff40000,115200n8 + endmenu config SERIAL_MCTRL_GPIO diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 138abbc89738..7b73137df7f3 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -88,6 +88,7 @@ obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o obj-$(CONFIG_SERIAL_SIFIVE) += sifive.o obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o obj-$(CONFIG_SERIAL_SUNPLUS) += sunplus-uart.o +obj-$(CONFIG_SERIAL_ESP32) += esp32_uart.o # GPIOLIB helpers for modem control lines obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o diff --git a/drivers/tty/serial/esp32_uart.c b/drivers/tty/serial/esp32_uart.c new file mode 100644 index 000000000000..82033470db44 --- /dev/null +++ b/drivers/tty/serial/esp32_uart.c @@ -0,0 +1,741 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_NAME "esp32-uart" +#define DEV_NAME "ttyS" +#define UART_NR 3 + +#define ESP32_UART_TX_FIFO_SIZE 127 +#define ESP32_UART_RX_FIFO_SIZE 127 + +#define UART_FIFO_REG 0x00 +#define UART_INT_RAW_REG 0x04 +#define UART_INT_ST_REG 0x08 +#define UART_INT_ENA_REG 0x0c +#define UART_INT_CLR_REG 0x10 +#define UART_RXFIFO_FULL_INT BIT(0) +#define UART_TXFIFO_EMPTY_INT BIT(1) +#define UART_BRK_DET_INT BIT(7) +#define UART_CLKDIV_REG 0x14 +#define ESP32_UART_CLKDIV GENMASK(19, 0) +#define ESP32S3_UART_CLKDIV GENMASK(11, 0) +#define UART_CLKDIV_SHIFT 0 +#define UART_CLKDIV_FRAG GENMASK(23, 20) +#define UART_STATUS_REG 0x1c +#define ESP32_UART_RXFIFO_CNT GENMASK(7, 0) +#define ESP32S3_UART_RXFIFO_CNT GENMASK(9, 0) +#define UART_RXFIFO_CNT_SHIFT 0 +#define UART_DSRN BIT(13) +#define UART_CTSN BIT(14) +#define ESP32_UART_TXFIFO_CNT GENMASK(23, 16) +#define ESP32S3_UART_TXFIFO_CNT GENMASK(25, 16) +#define UART_TXFIFO_CNT_SHIFT 16 +#define UART_CONF0_REG 0x20 +#define UART_PARITY BIT(0) +#define UART_PARITY_EN BIT(1) +#define UART_BIT_NUM GENMASK(3, 2) +#define UART_BIT_NUM_5 0 +#define UART_BIT_NUM_6 1 +#define UART_BIT_NUM_7 2 +#define UART_BIT_NUM_8 3 +#define UART_STOP_BIT_NUM GENMASK(5, 4) +#define UART_STOP_BIT_NUM_1 1 +#define UART_STOP_BIT_NUM_2 3 +#define UART_SW_RTS BIT(6) +#define UART_SW_DTR BIT(7) +#define UART_LOOPBACK BIT(14) +#define UART_TX_FLOW_EN BIT(15) +#define UART_RTS_INV BIT(23) +#define UART_DTR_INV BIT(24) +#define UART_CONF1_REG 0x24 +#define UART_RXFIFO_FULL_THRHD_SHIFT 0 +#define ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT 8 +#define ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT 10 +#define ESP32_UART_RX_FLOW_EN BIT(23) +#define ESP32S3_UART_RX_FLOW_EN BIT(22) + +struct esp32_port { + struct uart_port port; + struct clk *clk; +}; + +struct esp32_uart_variant { + u32 clkdiv_mask; + u32 rxfifo_cnt_mask; + u32 txfifo_cnt_mask; + u32 txfifo_empty_thrhd_shift; + u32 rx_flow_en; + const char *type; +}; + +static const struct esp32_uart_variant esp32_variant = { + .clkdiv_mask = ESP32_UART_CLKDIV, + .rxfifo_cnt_mask = ESP32_UART_RXFIFO_CNT, + .txfifo_cnt_mask = ESP32_UART_TXFIFO_CNT, + .txfifo_empty_thrhd_shift = ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT, + .rx_flow_en = ESP32_UART_RX_FLOW_EN, + .type = "ESP32 UART", +}; + +static const struct esp32_uart_variant esp32s3_variant = { + .clkdiv_mask = ESP32S3_UART_CLKDIV, + .rxfifo_cnt_mask = ESP32S3_UART_RXFIFO_CNT, + .txfifo_cnt_mask = ESP32S3_UART_TXFIFO_CNT, + .txfifo_empty_thrhd_shift = ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT, + .rx_flow_en = ESP32S3_UART_RX_FLOW_EN, + .type = "ESP32S3 UART", +}; + +static const struct of_device_id esp32_uart_dt_ids[] = { + { + .compatible = "esp,esp32-uart", + .data = &esp32_variant, + }, { + .compatible = "esp,esp32s3-uart", + .data = &esp32s3_variant, + }, { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, esp32_uart_dt_ids); + +static struct esp32_port *esp32_uart_ports[UART_NR]; + +static const struct esp32_uart_variant *port_variant(struct uart_port *port) +{ + return port->private_data; +} + +static void esp32_uart_write(struct uart_port *port, unsigned long reg, u32 v) +{ + writel(v, port->membase + reg); +} + +static u32 esp32_uart_read(struct uart_port *port, unsigned long reg) +{ + return readl(port->membase + reg); +} + +static u32 esp32_uart_tx_fifo_cnt(struct uart_port *port) +{ + u32 status = esp32_uart_read(port, UART_STATUS_REG); + + return (status & port_variant(port)->txfifo_cnt_mask) >> UART_TXFIFO_CNT_SHIFT; +} + +static u32 esp32_uart_rx_fifo_cnt(struct uart_port *port) +{ + u32 status = esp32_uart_read(port, UART_STATUS_REG); + + return (status & port_variant(port)->rxfifo_cnt_mask) >> UART_RXFIFO_CNT_SHIFT; +} + +/* return TIOCSER_TEMT when transmitter is not busy */ +static unsigned int esp32_uart_tx_empty(struct uart_port *port) +{ + return esp32_uart_tx_fifo_cnt(port) ? 0 : TIOCSER_TEMT; +} + +static void esp32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + u32 conf0 = esp32_uart_read(port, UART_CONF0_REG); + + conf0 &= ~(UART_LOOPBACK | + UART_SW_RTS | UART_RTS_INV | + UART_SW_DTR | UART_DTR_INV); + + if (mctrl & TIOCM_RTS) + conf0 |= UART_SW_RTS; + if (mctrl & TIOCM_DTR) + conf0 |= UART_SW_DTR; + if (mctrl & TIOCM_LOOP) + conf0 |= UART_LOOPBACK; + + esp32_uart_write(port, UART_CONF0_REG, conf0); +} + +static unsigned int esp32_uart_get_mctrl(struct uart_port *port) +{ + u32 status = esp32_uart_read(port, UART_STATUS_REG); + unsigned int ret = TIOCM_CAR; + + if (status & UART_DSRN) + ret |= TIOCM_DSR; + if (status & UART_CTSN) + ret |= TIOCM_CTS; + + return ret; +} + +static void esp32_uart_stop_tx(struct uart_port *port) +{ + u32 int_ena; + + int_ena = esp32_uart_read(port, UART_INT_ENA_REG); + int_ena &= ~UART_TXFIFO_EMPTY_INT; + esp32_uart_write(port, UART_INT_ENA_REG, int_ena); +} + +static void esp32_uart_rxint(struct uart_port *port) +{ + struct tty_port *tty_port = &port->state->port; + u32 rx_fifo_cnt = esp32_uart_rx_fifo_cnt(port); + unsigned long flags; + u32 i; + + if (!rx_fifo_cnt) + return; + + spin_lock_irqsave(&port->lock, flags); + + for (i = 0; i < rx_fifo_cnt; ++i) { + u32 rx = esp32_uart_read(port, UART_FIFO_REG); + + if (!rx && + (esp32_uart_read(port, UART_INT_ST_REG) & UART_BRK_DET_INT)) { + esp32_uart_write(port, UART_INT_CLR_REG, UART_BRK_DET_INT); + ++port->icount.brk; + uart_handle_break(port); + } else { + if (uart_handle_sysrq_char(port, (unsigned char)rx)) + continue; + tty_insert_flip_char(tty_port, rx, TTY_NORMAL); + ++port->icount.rx; + } + } + spin_unlock_irqrestore(&port->lock, flags); + + tty_flip_buffer_push(tty_port); +} + +static void esp32_uart_put_char(struct uart_port *port, u8 c) +{ + esp32_uart_write(port, UART_FIFO_REG, c); +} + +static void esp32_uart_put_char_sync(struct uart_port *port, u8 c) +{ + unsigned long timeout = jiffies + HZ; + + while (esp32_uart_tx_fifo_cnt(port) >= ESP32_UART_TX_FIFO_SIZE) { + if (time_after(jiffies, timeout)) { + dev_warn(port->dev, "timeout waiting for TX FIFO\n"); + return; + } + cpu_relax(); + } + esp32_uart_put_char(port, c); +} + +static void esp32_uart_transmit_buffer(struct uart_port *port) +{ + u32 tx_fifo_used = esp32_uart_tx_fifo_cnt(port); + unsigned int pending; + u8 ch; + + if (tx_fifo_used >= ESP32_UART_TX_FIFO_SIZE) + return; + + pending = uart_port_tx_limited(port, ch, + ESP32_UART_TX_FIFO_SIZE - tx_fifo_used, + true, esp32_uart_put_char(port, ch), + ({})); + if (pending) { + u32 int_ena; + + int_ena = esp32_uart_read(port, UART_INT_ENA_REG); + int_ena |= UART_TXFIFO_EMPTY_INT; + esp32_uart_write(port, UART_INT_ENA_REG, int_ena); + } +} + +static void esp32_uart_txint(struct uart_port *port) +{ + esp32_uart_transmit_buffer(port); +} + +static irqreturn_t esp32_uart_int(int irq, void *dev_id) +{ + struct uart_port *port = dev_id; + u32 status; + + status = esp32_uart_read(port, UART_INT_ST_REG); + + if (status & (UART_RXFIFO_FULL_INT | UART_BRK_DET_INT)) + esp32_uart_rxint(port); + if (status & UART_TXFIFO_EMPTY_INT) + esp32_uart_txint(port); + + esp32_uart_write(port, UART_INT_CLR_REG, status); + + return IRQ_RETVAL(status); +} + +static void esp32_uart_start_tx(struct uart_port *port) +{ + esp32_uart_transmit_buffer(port); +} + +static void esp32_uart_stop_rx(struct uart_port *port) +{ + u32 int_ena; + + int_ena = esp32_uart_read(port, UART_INT_ENA_REG); + int_ena &= ~UART_RXFIFO_FULL_INT; + esp32_uart_write(port, UART_INT_ENA_REG, int_ena); +} + +static int esp32_uart_startup(struct uart_port *port) +{ + int ret = 0; + unsigned long flags; + struct esp32_port *sport = container_of(port, struct esp32_port, port); + + ret = clk_prepare_enable(sport->clk); + if (ret) + return ret; + + ret = request_irq(port->irq, esp32_uart_int, 0, DRIVER_NAME, port); + if (ret) { + clk_disable_unprepare(sport->clk); + return ret; + } + + spin_lock_irqsave(&port->lock, flags); + esp32_uart_write(port, UART_CONF1_REG, + (1 << UART_RXFIFO_FULL_THRHD_SHIFT) | + (1 << port_variant(port)->txfifo_empty_thrhd_shift)); + esp32_uart_write(port, UART_INT_CLR_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT); + esp32_uart_write(port, UART_INT_ENA_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT); + spin_unlock_irqrestore(&port->lock, flags); + + return ret; +} + +static void esp32_uart_shutdown(struct uart_port *port) +{ + struct esp32_port *sport = container_of(port, struct esp32_port, port); + + esp32_uart_write(port, UART_INT_ENA_REG, 0); + free_irq(port->irq, port); + clk_disable_unprepare(sport->clk); +} + +static bool esp32_uart_set_baud(struct uart_port *port, u32 baud) +{ + u32 div = port->uartclk / baud; + u32 frag = (port->uartclk * 16) / baud - div * 16; + + if (div <= port_variant(port)->clkdiv_mask) { + esp32_uart_write(port, UART_CLKDIV_REG, + div | FIELD_PREP(UART_CLKDIV_FRAG, frag)); + return true; + } + + return false; +} + +static void esp32_uart_set_termios(struct uart_port *port, + struct ktermios *termios, + const struct ktermios *old) +{ + unsigned long flags; + u32 conf0, conf1; + u32 baud; + const u32 rx_flow_en = port_variant(port)->rx_flow_en; + + termios->c_cflag &= ~CMSPAR; + + baud = uart_get_baud_rate(port, termios, old, + port->uartclk / port_variant(port)->clkdiv_mask, + port->uartclk / 16); + + spin_lock_irqsave(&port->lock, flags); + + conf0 = esp32_uart_read(port, UART_CONF0_REG); + conf0 &= ~(UART_PARITY_EN | UART_PARITY | UART_BIT_NUM | UART_STOP_BIT_NUM); + + conf1 = esp32_uart_read(port, UART_CONF1_REG); + conf1 &= ~rx_flow_en; + + if (termios->c_cflag & PARENB) { + conf0 |= UART_PARITY_EN; + if (termios->c_cflag & PARODD) + conf0 |= UART_PARITY; + } + + switch (termios->c_cflag & CSIZE) { + case CS5: + conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_5); + break; + case CS6: + conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_6); + break; + case CS7: + conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_7); + break; + case CS8: + conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_8); + break; + } + + if (termios->c_cflag & CSTOPB) + conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_2); + else + conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_1); + + if (termios->c_cflag & CRTSCTS) + conf1 |= rx_flow_en; + + esp32_uart_write(port, UART_CONF0_REG, conf0); + esp32_uart_write(port, UART_CONF1_REG, conf1); + + if (baud) { + esp32_uart_set_baud(port, baud); + uart_update_timeout(port, termios->c_cflag, baud); + } else { + if (esp32_uart_set_baud(port, 115200)) { + baud = 115200; + tty_termios_encode_baud_rate(termios, baud, baud); + uart_update_timeout(port, termios->c_cflag, baud); + } else { + dev_warn(port->dev, + "unable to set speed to %d baud or the default 115200\n", + baud); + } + } + spin_unlock_irqrestore(&port->lock, flags); +} + +static const char *esp32_uart_type(struct uart_port *port) +{ + return port_variant(port)->type; +} + +/* configure/auto-configure the port */ +static void esp32_uart_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) + port->type = PORT_GENERIC; +} + +#ifdef CONFIG_CONSOLE_POLL +static int esp32_uart_poll_init(struct uart_port *port) +{ + struct esp32_port *sport = container_of(port, struct esp32_port, port); + + return clk_prepare_enable(sport->clk); +} + +static void esp32_uart_poll_put_char(struct uart_port *port, unsigned char c) +{ + esp32_uart_put_char_sync(port, c); +} + +static int esp32_uart_poll_get_char(struct uart_port *port) +{ + if (esp32_uart_rx_fifo_cnt(port)) + return esp32_uart_read(port, UART_FIFO_REG); + else + return NO_POLL_CHAR; + +} +#endif + +static const struct uart_ops esp32_uart_pops = { + .tx_empty = esp32_uart_tx_empty, + .set_mctrl = esp32_uart_set_mctrl, + .get_mctrl = esp32_uart_get_mctrl, + .stop_tx = esp32_uart_stop_tx, + .start_tx = esp32_uart_start_tx, + .stop_rx = esp32_uart_stop_rx, + .startup = esp32_uart_startup, + .shutdown = esp32_uart_shutdown, + .set_termios = esp32_uart_set_termios, + .type = esp32_uart_type, + .config_port = esp32_uart_config_port, +#ifdef CONFIG_CONSOLE_POLL + .poll_init = esp32_uart_poll_init, + .poll_put_char = esp32_uart_poll_put_char, + .poll_get_char = esp32_uart_poll_get_char, +#endif +}; + +static void esp32_uart_console_putchar(struct uart_port *port, u8 c) +{ + esp32_uart_put_char_sync(port, c); +} + +static void esp32_uart_string_write(struct uart_port *port, const char *s, + unsigned int count) +{ + uart_console_write(port, s, count, esp32_uart_console_putchar); +} + +static void +esp32_uart_console_write(struct console *co, const char *s, unsigned int count) +{ + struct esp32_port *sport = esp32_uart_ports[co->index]; + struct uart_port *port = &sport->port; + unsigned long flags; + bool locked = true; + + if (port->sysrq) + locked = false; + else if (oops_in_progress) + locked = spin_trylock_irqsave(&port->lock, flags); + else + spin_lock_irqsave(&port->lock, flags); + + esp32_uart_string_write(port, s, count); + + if (locked) + spin_unlock_irqrestore(&port->lock, flags); +} + +static int __init esp32_uart_console_setup(struct console *co, char *options) +{ + struct esp32_port *sport; + int baud = 115200; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + int ret; + + /* + * check whether an invalid uart number has been specified, and + * if so, search for the first available port that does have + * console support. + */ + if (co->index == -1 || co->index >= ARRAY_SIZE(esp32_uart_ports)) + co->index = 0; + + sport = esp32_uart_ports[co->index]; + if (!sport) + return -ENODEV; + + ret = clk_prepare_enable(sport->clk); + if (ret) + return ret; + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(&sport->port, co, baud, parity, bits, flow); +} + +static int esp32_uart_console_exit(struct console *co) +{ + struct esp32_port *sport = esp32_uart_ports[co->index]; + + clk_disable_unprepare(sport->clk); + return 0; +} + +static struct uart_driver esp32_uart_reg; +static struct console esp32_uart_console = { + .name = DEV_NAME, + .write = esp32_uart_console_write, + .device = uart_console_device, + .setup = esp32_uart_console_setup, + .exit = esp32_uart_console_exit, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &esp32_uart_reg, +}; + +static void esp32_uart_earlycon_putchar(struct uart_port *port, u8 c) +{ + esp32_uart_put_char_sync(port, c); +} + +static void esp32_uart_earlycon_write(struct console *con, const char *s, + unsigned int n) +{ + struct earlycon_device *dev = con->data; + + uart_console_write(&dev->port, s, n, esp32_uart_earlycon_putchar); +} + +#ifdef CONFIG_CONSOLE_POLL +static int esp32_uart_earlycon_read(struct console *con, char *s, unsigned int n) +{ + struct earlycon_device *dev = con->data; + unsigned int num_read = 0; + + while (num_read < n) { + int c = esp32_uart_poll_get_char(&dev->port); + + if (c == NO_POLL_CHAR) + break; + s[num_read++] = c; + } + return num_read; +} +#endif + +static int __init esp32xx_uart_early_console_setup(struct earlycon_device *device, + const char *options) +{ + if (!device->port.membase) + return -ENODEV; + + device->con->write = esp32_uart_earlycon_write; +#ifdef CONFIG_CONSOLE_POLL + device->con->read = esp32_uart_earlycon_read; +#endif + if (device->port.uartclk != BASE_BAUD * 16) + esp32_uart_set_baud(&device->port, device->baud); + + return 0; +} + +static int __init esp32_uart_early_console_setup(struct earlycon_device *device, + const char *options) +{ + device->port.private_data = (void *)&esp32_variant; + + return esp32xx_uart_early_console_setup(device, options); +} + +OF_EARLYCON_DECLARE(esp32uart, "esp,esp32-uart", + esp32_uart_early_console_setup); + +static int __init esp32s3_uart_early_console_setup(struct earlycon_device *device, + const char *options) +{ + device->port.private_data = (void *)&esp32s3_variant; + + return esp32xx_uart_early_console_setup(device, options); +} + +OF_EARLYCON_DECLARE(esp32s3uart, "esp,esp32s3-uart", + esp32s3_uart_early_console_setup); + +static struct uart_driver esp32_uart_reg = { + .owner = THIS_MODULE, + .driver_name = DRIVER_NAME, + .dev_name = DEV_NAME, + .nr = ARRAY_SIZE(esp32_uart_ports), + .cons = &esp32_uart_console, +}; + +static int esp32_uart_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + static const struct of_device_id *match; + struct uart_port *port; + struct esp32_port *sport; + struct resource *res; + int ret; + + match = of_match_device(esp32_uart_dt_ids, &pdev->dev); + if (!match) + return -ENODEV; + + sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); + if (!sport) + return -ENOMEM; + + port = &sport->port; + + ret = of_alias_get_id(np, "serial"); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); + return ret; + } + if (ret >= UART_NR) { + dev_err(&pdev->dev, "driver limited to %d serial ports\n", UART_NR); + return -ENOMEM; + } + + port->line = ret; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + port->mapbase = res->start; + port->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(port->membase)) + return PTR_ERR(port->membase); + + sport->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(sport->clk)) + return PTR_ERR(sport->clk); + + port->uartclk = clk_get_rate(sport->clk); + port->dev = &pdev->dev; + port->type = PORT_GENERIC; + port->iotype = UPIO_MEM; + port->irq = platform_get_irq(pdev, 0); + port->ops = &esp32_uart_pops; + port->flags = UPF_BOOT_AUTOCONF; + port->has_sysrq = 1; + port->fifosize = ESP32_UART_TX_FIFO_SIZE; + port->private_data = (void *)match->data; + + esp32_uart_ports[port->line] = sport; + + platform_set_drvdata(pdev, port); + + return uart_add_one_port(&esp32_uart_reg, port); +} + +static int esp32_uart_remove(struct platform_device *pdev) +{ + struct uart_port *port = platform_get_drvdata(pdev); + + uart_remove_one_port(&esp32_uart_reg, port); + + return 0; +} + + +static struct platform_driver esp32_uart_driver = { + .probe = esp32_uart_probe, + .remove = esp32_uart_remove, + .driver = { + .name = DRIVER_NAME, + .of_match_table = esp32_uart_dt_ids, + }, +}; + +static int __init esp32_uart_init(void) +{ + int ret; + + ret = uart_register_driver(&esp32_uart_reg); + if (ret) + return ret; + + ret = platform_driver_register(&esp32_uart_driver); + if (ret) + uart_unregister_driver(&esp32_uart_reg); + + return ret; +} + +static void __exit esp32_uart_exit(void) +{ + platform_driver_unregister(&esp32_uart_driver); + uart_unregister_driver(&esp32_uart_reg); +} + +module_init(esp32_uart_init); +module_exit(esp32_uart_exit); + +MODULE_AUTHOR("Max Filippov "); +MODULE_LICENSE("GPL");