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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id c12-20020a170906694c00b009b8a4f9f20esm8131582ejs.102.2023.10.10.02.29.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:29:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 01/18] target: Mention 'cpu-qom.h' is target agnostic Date: Tue, 10 Oct 2023 11:28:43 +0200 Message-ID: <20231010092901.99189-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philmd@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu-qom.h | 2 +- target/hppa/cpu-qom.h | 2 +- target/microblaze/cpu-qom.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 514c22ced9..064317a245 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU ARM CPU + * QEMU ARM CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index b96e0318c7..a89a4f3a0a 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU HPPA CPU + * QEMU HPPA CPU QOM header (target agnostic) * * Copyright (c) 2016 Richard Henderson * diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h index cda9220fa9..0e3ebaddb1 100644 --- a/target/microblaze/cpu-qom.h +++ b/target/microblaze/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU MicroBlaze CPU + * QEMU MicroBlaze CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * From patchwork Tue Oct 10 09:28:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731439 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641508wrw; Tue, 10 Oct 2023 02:32:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IERy4StaCnxXA8UD2WyXCyY7cJklnbvtnF76dokqHVkjXf7DLVKZrLNpUA8MgfTZi5/IQBl X-Received: by 2002:a0c:f5cd:0:b0:658:50c1:b1d6 with SMTP id q13-20020a0cf5cd000000b0065850c1b1d6mr17011455qvm.1.1696930376452; Tue, 10 Oct 2023 02:32:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930376; cv=none; d=google.com; s=arc-20160816; b=RgLaDl+2KgxI9dvqEW9WrDsCjq8XeZljw5eqPPZzMRLcjUsxYRBmY7EP1c0ra9m8H/ qNDO0CfeVaX0JlcUT4/xCNHX0Bap74PKUPSTee6e+ntwo/yf1hFjqSg3KXtn3IYwDo6M 7Zt3o6XfGiI4wbUs/hpUfmZkUMllczpvSnHaLOH+g6abRL9vwNJEEG5Wf11lJUf7yh15 sHmRfB4RTnhNgbGVfy4YMUZbjPHOuBhvV6IPhlTfxdhbyn/V0phcm8sGwgcfreiwl801 0H0ATGRKlWu7yR+n37KJbKO7X+BiNRk5XTpJ3OF2Kb6x8LlkS0Wql9TZrQPviAwYZBUp HYNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=z/h9w6SijQxndRm+za3Ly8qK6pPEviCCn5/tSqn0iYo=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=dMpWPrgFG8iSXzAD+3iGvisB5YlwFNI/fWSMgvnSNjWJP+t+A1rGk4C1QeJ8o8/hVA AgAhRlB1/nCwHCKsgXy6ClBN8JcQdIo0wkPc+kn7v03g8KaP1pBurJFM0m7F8FpTxmXD iwPRN7WkoS/PZRQ61dToxJVbNLSs4UmxWus+QA9Vh1hGusjps6Hov+nNRcVpBFyIRSbd dce3tRXKS6aomIT7PMC7ZiXlYC/FiX2jcd3F9Q1YOlhEFV9xN6Oe37gGV1tk01GC+olC c2XvuAYqXSd7OdkGHCL9tk4r+/ed+nbqsxhf0zvmj9E8ksRZQPDhozZFs+HUqZwFSVyd CCCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tJz8Q6I0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id n19-20020a056402515300b0053495596f42sm7389833edd.30.2023.10.10.02.29.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:29:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 02/18] target/ppc: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' Date: Tue, 10 Oct 2023 11:28:44 +0200 Message-ID: <20231010092901.99189-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPU_RESOLVING_TYPE is a per-target definition, and is irrelevant for other targets. Move it to "cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/cpu-qom.h | 3 +-- target/ppc/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index be33786bd8..41df51269b 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU PowerPC CPU + * QEMU PowerPC CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -33,7 +33,6 @@ OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX -#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 30392ebeee..492fdecaf3 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -27,6 +27,8 @@ #include "qom/object.h" #include "hw/registerfields.h" +#define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU + #define TCG_GUEST_DEFAULT_MO 0 #define TARGET_PAGE_BITS_64K 16 From patchwork Tue Oct 10 09:28:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731433 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1640935wrw; Tue, 10 Oct 2023 02:31:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH3kpxx3G+UbHXB0XVnl7dBCmAqmj65D8USUOGwXyy4merF+nCIiLwdEvYmdf2gvqnd75/t X-Received: by 2002:a05:622a:1913:b0:417:8f2e:4e2d with SMTP id w19-20020a05622a191300b004178f2e4e2dmr24943825qtc.31.1696930293510; Tue, 10 Oct 2023 02:31:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930293; cv=none; d=google.com; s=arc-20160816; b=Zv9jg+2T9MAXjxNrgYlnvAsLf/HPPkKRvbgNBNGZHmzYJl7bHhP2HU7mdVzaxxoQpR xDke1ZLAHNUwj2WXQSjbpVd4pyOgzYSIjSO8W3vIWVgyeimFEr10aTntjY4W7FmYdAVX 1i/e5pZkO7EZonQvWg4Qsb+LQ+wvhIcKIO776OsLbF+ZJQHPH2A5N9D76fWcmfJ/1swE +zdGtn5/bsCpUuOcf7eEHEBOpIbNmQR5g4felMJMVmCuEQM7ggkEiXTBCbazSO4/92MA q3l8D3bz3G3Ry4mvhkDWDDTifar3FeS3Cxh23bkODe0ySHuCHVGQ1ISoGIx2t5YGro5/ eWiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1P+KsNPR279ILK4eCnAbqPNl6Wjvg7v5l/+zhWQrkdI=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=DI7L34qYCAByEL0ej0XxRc+dptb1Hh9NbOlD6KKkNDhFDto/IlfD7oomVeHCcGGXTN +cvh7wd0Ns1fSfBDtS5jSJxlPCDtcZHtcOHmc8k2TulYu3ybrBP4bk2J8bamgKoNgS/+ AsXIT9i7O5gmbWrVrWdJZUJvHrbuF0ChiXhZMXoaBFWqHQ2x5C1/UYAPOdBNDHRs/Jma WlWS6Fw+GZp4kNo+rzCTbPpZ6L/mjznv+FWpKkpkGf+uJlaldxOjwkoQZJ2VM68i1knJ k2Ynhu21pH2YjgpT05kzStOI4Qc5jFTYPSMfxnd4wqCcdurJhcjdCzMsOd857vl5vnTm omiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=POVjFEG8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id s10-20020a170906354a00b0099bd1ce18fesm8321907eja.10.2023.10.10.02.29.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:29:29 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 03/18] target/riscv: Remove CPU_RESOLVING_TYPE from 'cpu-qom.h' Date: Tue, 10 Oct 2023 11:28:45 +0200 Message-ID: <20231010092901.99189-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPU_RESOLVING_TYPE is a per-target definition, and is irrelevant for other targets. Move it to "cpu.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/cpu-qom.h | 1 - target/riscv/cpu.h | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 04af50983e..8cb67b84a4 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -27,7 +27,6 @@ #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) -#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ef9cf21c0c..374b813f20 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -31,6 +31,8 @@ #include "qapi/qapi-types-common.h" #include "cpu-qom.h" +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU + #define TCG_GUEST_DEFAULT_MO 0 /* From patchwork Tue Oct 10 09:28:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731436 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641184wrw; Tue, 10 Oct 2023 02:32:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG3BlMoSHft06sBAtBS+ubF0Pe7zsq9j2jeRGI/kpBwk8KlWsYAQTPXDuIA5SdN7coPgfFk X-Received: by 2002:ac8:5914:0:b0:417:99ea:5058 with SMTP id 20-20020ac85914000000b0041799ea5058mr20719526qty.38.1696930326765; Tue, 10 Oct 2023 02:32:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930326; cv=none; d=google.com; s=arc-20160816; b=FFkVSTF24LGEt9KLur5jwuUscjYqUKOIRhzll83KT/lEqluTBHvrZ5m/lnlpZxLG1T yL13fkKWeJOtRaXQChb72M7ER7gyLcWIprqBjnDtwMh2iWrrruSLM34vX1GBzTfbDqT3 2nJFlLACtM2JG8ewGXmxlywbOJIZAQi69h9Ozk1O2zjrHf43fyB4/Nkjka8Ni6MMdxZi F0cHIJKHdBumRGxBg08rdAeDyTZMcaAi12fXtYOTPKQSczBljt2XBSwgkfXDiNTJyn8b qvhZh/a3Gqw49oQRlIFtRE2se8o6PmLPJr/QIgn/8wJP3pvqbadap7k5f3FmzmOyEbE7 2eNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/bS8yw5KHUhKLWpYvWXGMLDFfCa1VRkPc6GuV5vAqFg=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=g65XebDmELB7wdq19ZCeKlF22TyIb0ptCUqPzvgDrs7U6UPgLLFaNzclNTWSz4M2yv BZnHMbjkBJWD8aE0e1mSF6LS04S7efBwtc0xHMdsj0RJd5LTKF2kpF+IQjZVgXq/wq3G lWt0NrMt91fx651XzPaHLgqFbVUBlkPcSLHvCZwf0J825JHd0BFC8/It5DxYBH3qBhs5 VgHlyQCQhVSwhfRqOhGC9X32BO0+8WLQxsajXM4GDm6XkNiOXaBIDBOU3UVQ9+QZnG/L L6vBJCncwhvRXV33Slyp4pweoUANKRiJUsHkUb2Gx4Bf9WpxD1Tb95C2ASzQ8RvAXwuz vntQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N5lSIo8l; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id t24-20020a1709066bd800b0099ddc81903asm8183501ejs.221.2023.10.10.02.29.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:29:38 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 04/18] target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' Date: Tue, 10 Oct 2023 11:28:46 +0200 Message-ID: <20231010092901.99189-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philmd@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME() macro to resolve target CPU types. Move the declaration (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Acked-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/alpha/cpu-qom.h | 5 ++++- target/alpha/cpu.h | 2 -- target/avr/cpu-qom.h | 5 ++++- target/avr/cpu.h | 2 -- target/cris/cpu-qom.h | 5 ++++- target/cris/cpu.h | 2 -- target/i386/cpu-qom.h | 3 +++ target/i386/cpu.h | 2 -- target/m68k/cpu-qom.h | 5 ++++- target/m68k/cpu.h | 2 -- target/mips/cpu-qom.h | 3 +++ target/mips/cpu.h | 2 -- target/rx/cpu-qom.h | 5 ++++- target/rx/cpu.h | 2 -- target/s390x/cpu-qom.h | 5 ++++- target/s390x/cpu.h | 2 -- target/sh4/cpu-qom.h | 5 ++++- target/sh4/cpu.h | 2 -- target/sparc/cpu-qom.h | 5 ++++- target/sparc/cpu.h | 2 -- target/tricore/cpu-qom.h | 5 +++++ target/tricore/cpu.h | 2 -- target/xtensa/cpu-qom.h | 5 ++++- target/xtensa/cpu.h | 2 -- 24 files changed, 47 insertions(+), 33 deletions(-) diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h index 1f200724b6..d596d1b69f 100644 --- a/target/alpha/cpu-qom.h +++ b/target/alpha/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU Alpha CPU + * QEMU Alpha CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU) +#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU +#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX + /** * AlphaCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e2a467ec17..ba0d9e3468 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -428,8 +428,6 @@ enum { void alpha_translate_init(void); -#define ALPHA_CPU_TYPE_SUFFIX "-" TYPE_ALPHA_CPU -#define ALPHA_CPU_TYPE_NAME(model) model ALPHA_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_ALPHA_CPU void alpha_cpu_list(void); diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h index 01ea5f160b..a810d6dc09 100644 --- a/target/avr/cpu-qom.h +++ b/target/avr/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU AVR CPU + * QEMU AVR CPU QOM header (target agnostic) * * Copyright (c) 2016-2020 Michael Rolnik * @@ -28,6 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU) +#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU +#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX) + /** * AVRCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 4ce22d8e4f..d3f0cc65d4 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -28,8 +28,6 @@ #error "AVR 8-bit does not support user mode" #endif -#define AVR_CPU_TYPE_SUFFIX "-" TYPE_AVR_CPU -#define AVR_CPU_TYPE_NAME(name) (name AVR_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_AVR_CPU #define TCG_GUEST_DEFAULT_MO 0 diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index 431a1d536a..02a5b589b8 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU CRIS CPU + * QEMU CRIS CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) +#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU +#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) + /** * CRISCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 676b8e93ca..1af7ae5ef9 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -242,8 +242,6 @@ enum { /* CRIS uses 8k pages. */ #define MMAP_SHIFT TARGET_PAGE_BITS -#define CRIS_CPU_TYPE_SUFFIX "-" TYPE_CRIS_CPU -#define CRIS_CPU_TYPE_NAME(name) (name CRIS_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_CRIS_CPU /* MMU modes definitions */ diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index 2350f4ae60..78207c0a7c 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -32,6 +32,9 @@ OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU) +#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU +#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) + typedef struct X86CPUModel X86CPUModel; /** diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e1875466b9..862e4f1ff5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2241,8 +2241,6 @@ void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7); /* hw/pc.c */ uint64_t cpu_get_tsc(CPUX86State *env); -#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU -#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_X86_CPU #ifdef TARGET_X86_64 diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h index 0ec7750a92..7192ecd71f 100644 --- a/target/m68k/cpu-qom.h +++ b/target/m68k/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU Motorola 68k CPU + * QEMU Motorola 68k CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU) +#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU +#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX + /* * M68kCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 20afb0c94d..ae144ebc2f 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -563,8 +563,6 @@ enum { ACCESS_DATA = 0x20, /* Data load/store access */ }; -#define M68K_CPU_TYPE_SUFFIX "-" TYPE_M68K_CPU -#define M68K_CPU_TYPE_NAME(model) model M68K_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_M68K_CPU #define cpu_list m68k_cpu_list diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 0dffab453b..9c98ca1956 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -31,6 +31,9 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) +#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU +#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX + /** * MIPSCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 5fddceff3a..6b026e6bcf 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1303,8 +1303,6 @@ enum { */ #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 -#define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU -#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU bool cpu_type_supports_cps_smp(const char *cpu_type); diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index 1c8466a187..99fe771534 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -1,5 +1,5 @@ /* - * RX CPU + * QEMU RX CPU QOM header (target agnostic) * * Copyright (c) 2019 Yoshinori Sato * @@ -28,6 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU) +#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU +#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX + /* * RXCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/rx/cpu.h b/target/rx/cpu.h index f66754eb8a..f89d88a37f 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -114,8 +114,6 @@ struct ArchCPU { CPURXState env; }; -#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU -#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_RX_CPU const char *rx_crname(uint8_t cr); diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index 00cae2b131..463fe16386 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU S/390 CPU + * QEMU S/390 CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -27,6 +27,9 @@ OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU) +#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU +#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) + typedef struct S390CPUModel S390CPUModel; typedef struct S390CPUDef S390CPUDef; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 7bea7075e1..3e161862e5 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -810,8 +810,6 @@ void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, /* helper.c */ -#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU -#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_S390_CPU /* interrupt.c */ diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 89785a90f0..ed2de98949 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU SuperH CPU + * QEMU SuperH CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -31,6 +31,9 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU) +#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU +#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX + /** * SuperHCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index f75a235973..f44b3e5b25 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -252,8 +252,6 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); void cpu_load_tlb(CPUSH4State * env); -#define SUPERH_CPU_TYPE_SUFFIX "-" TYPE_SUPERH_CPU -#define SUPERH_CPU_TYPE_NAME(model) model SUPERH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SUPERH_CPU #define cpu_list sh4_cpu_list diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index 78bf00b9a2..86b24a254a 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU SPARC CPU + * QEMU SPARC CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -31,6 +31,9 @@ OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) +#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU +#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX + typedef struct sparc_def_t sparc_def_t; /** * SPARCCPUClass: diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index b3a98f1d74..924e83b9ce 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -650,8 +650,6 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, #endif #endif -#define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU -#define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_SPARC_CPU #define cpu_list sparc_cpu_list diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h index 612731daa0..5368689bd9 100644 --- a/target/tricore/cpu-qom.h +++ b/target/tricore/cpu-qom.h @@ -1,4 +1,6 @@ /* + * QEMU TriCore CPU QOM header (target agnostic) + * * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn * * This library is free software; you can redistribute it and/or @@ -26,6 +28,9 @@ OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU) +#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU +#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX + struct TriCoreCPUClass { /*< private >*/ CPUClass parent_class; diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index a357b573f2..fc09590a4f 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -270,8 +270,6 @@ static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, *flags = new_flags; } -#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU -#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU /* helpers.c */ diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h index 419c7d8e4a..710ffa0403 100644 --- a/target/xtensa/cpu-qom.h +++ b/target/xtensa/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU Xtensa CPU + * QEMU Xtensa CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * All rights reserved. @@ -36,6 +36,9 @@ OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU) +#define XTENSA_CPU_TYPE_SUFFIX "-" TYPE_XTENSA_CPU +#define XTENSA_CPU_TYPE_NAME(model) model XTENSA_CPU_TYPE_SUFFIX + typedef struct XtensaConfig XtensaConfig; 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id n10-20020aa7c78a000000b00535204ffdb4sm7430597eds.72.2023.10.10.02.29.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:29:45 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 05/18] target/hexagon: Declare QOM definitions in 'cpu-qom.h' Date: Tue, 10 Oct 2023 11:28:47 +0200 Message-ID: <20231010092901.99189-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philmd@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé --- target/hexagon/cpu-qom.h | 35 +++++++++++++++++++++++++++++++++++ target/hexagon/cpu.h | 23 +---------------------- 2 files changed, 36 insertions(+), 22 deletions(-) create mode 100644 target/hexagon/cpu-qom.h diff --git a/target/hexagon/cpu-qom.h b/target/hexagon/cpu-qom.h new file mode 100644 index 0000000000..cd45850c64 --- /dev/null +++ b/target/hexagon/cpu-qom.h @@ -0,0 +1,35 @@ +/* + * QEMU Hexagon CPU QOM header (target agnostic) + * + * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef QEMU_HEXAGON_CPU_QOM_H +#define QEMU_HEXAGON_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_HEXAGON_CPU "hexagon-cpu" + +#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU +#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) + +#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") +#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") +#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") +#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") +#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") + +OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) + +typedef struct HexagonCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +} HexagonCPUClass; + +#endif diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 10cd1efd57..7c3b993035 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -20,11 +20,10 @@ #include "fpu/softfloat-types.h" +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "hex_regs.h" #include "mmvec/mmvec.h" -#include "qom/object.h" -#include "hw/core/cpu.h" #include "hw/registerfields.h" #define NUM_PREGS 4 @@ -36,18 +35,8 @@ #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ #define VSTORES_MAX 2 -#define TYPE_HEXAGON_CPU "hexagon-cpu" - -#define HEXAGON_CPU_TYPE_SUFFIX "-" TYPE_HEXAGON_CPU -#define HEXAGON_CPU_TYPE_NAME(name) (name HEXAGON_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU -#define TYPE_HEXAGON_CPU_V67 HEXAGON_CPU_TYPE_NAME("v67") -#define TYPE_HEXAGON_CPU_V68 HEXAGON_CPU_TYPE_NAME("v68") -#define TYPE_HEXAGON_CPU_V69 HEXAGON_CPU_TYPE_NAME("v69") -#define TYPE_HEXAGON_CPU_V71 HEXAGON_CPU_TYPE_NAME("v71") -#define TYPE_HEXAGON_CPU_V73 HEXAGON_CPU_TYPE_NAME("v73") - void hexagon_cpu_list(void); #define cpu_list hexagon_cpu_list @@ -127,16 +116,6 @@ typedef struct CPUArchState { VTCMStoreLog vtcm_log; } CPUHexagonState; -OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) - -typedef struct HexagonCPUClass { - /*< private >*/ - CPUClass parent_class; - /*< public >*/ - DeviceRealize parent_realize; - ResettablePhases parent_phases; -} HexagonCPUClass; - struct ArchCPU { /*< private >*/ CPUState parent_obj; From patchwork Tue Oct 10 09:28:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731447 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641998wrw; Tue, 10 Oct 2023 02:34:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFeTqbAxK41oE+IyWdHkHzei/2eQMyNgd9x68IEG7HP6lVvi8g+LKPX4PoZSu7DYS1BlMbC X-Received: by 2002:a0c:a809:0:b0:65d:343:8e50 with SMTP id w9-20020a0ca809000000b0065d03438e50mr15852250qva.3.1696930453761; Tue, 10 Oct 2023 02:34:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930453; cv=none; d=google.com; s=arc-20160816; b=hf09oOTQOVj7GsvCwSMq2zNcxc2Dk7sg64gSl+InCq5fMVSLhdymk1M9i+ElROyLa9 d9xzHyEbzDUQydd4FVCITmOV4a4BKWvOTUt/DacO+0aEnkv8wAyvgT6RskiHk/Z0Il/H b4VRjeci+ta5FYDI+DWa7XxdtTW5/Iam2XzN2GHhe2SdZ9K8VCFav7HkWaSYKr8hGfKL ySco8vT1vgV51aBzSI3CY+e46TAkBwWUOOW2Gdv0YThwKB2bc9Vbx6+jkVfbjPxRl52U YAPHde8gn00bWfCFQpTgQZWuv9lgizvFqwxCi8MbrRi0JJXv0ItVz7WAazA1RHSeVlDA VKxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NKemy3mrOQvsycwsAw7RG7OOitRzhA3E8db/8fyu+SQ=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=kw7dR242tsERNwKNCmX8XG8I1J85Gr0cuZy1MuiB9fGprk9tTK1A9+aCse/iFu/1rl IEsNrqJ+QIU3G9AW+9qdyzrvbl7fxu9+NV/2Rb+D35j2pmfcY+YAjZrg3U2XjVzBAV0I XUeEX+vgo63IZPKovQGc4yOJkiniIPHyWuJMVM/XFcXIGo3aYvNNq1oaaxG5wWlDjdM2 txCPzipbvJAysQ3xapK0huYo4pI8Z/kJ6JdA69+mb6C1RGQFGAPs7gypxV+/EUF20Mx7 RfT5T437pnG4su24I/+mkYkpQzd4aBm5IauzHWJnFWqJfzNJkK3YtCPKYDBWGqlgsirz bCMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dwBEbjyr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id w13-20020a170906480d00b0098d2d219649sm8226101ejq.174.2023.10.10.02.29.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:29:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 06/18] target/loongarch: Declare QOM definitions in 'cpu-qom.h' Date: Tue, 10 Oct 2023 11:28:48 +0200 Message-ID: <20231010092901.99189-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Song Gao --- target/loongarch/cpu-qom.h | 38 ++++++++++++++++++++++++++++++++++++++ target/loongarch/cpu.h | 26 +------------------------- 2 files changed, 39 insertions(+), 25 deletions(-) create mode 100644 target/loongarch/cpu-qom.h diff --git a/target/loongarch/cpu-qom.h b/target/loongarch/cpu-qom.h new file mode 100644 index 0000000000..d577af9f6e --- /dev/null +++ b/target/loongarch/cpu-qom.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * QEMU LoongArch CPU QOM header (target agnostic) + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + */ + +#ifndef LOONGARCH_CPU_QOM_H +#define LOONGARCH_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_LOONGARCH_CPU "loongarch-cpu" +#define TYPE_LOONGARCH32_CPU "loongarch32-cpu" +#define TYPE_LOONGARCH64_CPU "loongarch64-cpu" + +OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, + LOONGARCH_CPU) + +#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU +#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX + +/** + * LoongArchCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A LoongArch CPU model. + */ +struct LoongArchCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#endif diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 40e70a8119..22cebc6280 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -17,6 +17,7 @@ #include "exec/memory.h" #endif #include "cpu-csr.h" +#include "cpu-qom.h" #define IOCSRF_TEMP 0 #define IOCSRF_NODECNT 1 @@ -383,29 +384,6 @@ struct ArchCPU { const char *dtb_compatible; }; -#define TYPE_LOONGARCH_CPU "loongarch-cpu" -#define TYPE_LOONGARCH32_CPU "loongarch32-cpu" -#define TYPE_LOONGARCH64_CPU "loongarch64-cpu" - -OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, - LOONGARCH_CPU) - -/** - * LoongArchCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A LoongArch CPU model. - */ -struct LoongArchCPUClass { - /*< private >*/ - CPUClass parent_class; - /*< public >*/ - - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - /* * LoongArch CPUs has 4 privilege levels. * 0 for kernel mode, 3 for user mode. @@ -482,8 +460,6 @@ void loongarch_cpu_list(void); #include "exec/cpu-all.h" -#define LOONGARCH_CPU_TYPE_SUFFIX "-" TYPE_LOONGARCH_CPU -#define LOONGARCH_CPU_TYPE_NAME(model) model LOONGARCH_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU #endif /* LOONGARCH_CPU_H */ From patchwork Tue Oct 10 09:28:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731432 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1640793wrw; Tue, 10 Oct 2023 02:31:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG1tljGDP/Nke3OFdwjbG47xzmvlXYyYG/p2aRFarEndH40KYtvGtnL9vHmLMvv0xzWNLEF X-Received: by 2002:a05:620a:244b:b0:774:2113:743a with SMTP id h11-20020a05620a244b00b007742113743amr21792842qkn.19.1696930273696; Tue, 10 Oct 2023 02:31:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930273; cv=none; d=google.com; s=arc-20160816; b=Mho0j3ztvItjd4y/I4WFRsvXmIOD2ngCydah7xU93gD0xsS8RUrhJr3CCLCA+sVe5m nKp3bcIB9i8M5IjrKbKTgySJDPjeUIrPFJY+SqrI8jPhZoD90t1aJIvzfohNmaSnRk4R 5boF8MYAFQnsgPMZhjfzX1tPzwTyFDsP2iaiNW25+vFf6K+LmNVVXWniyLjJGwRb/WJL tN/FVIXms+XR+8fDizKvEHHk3j1eIwUOnXkGmG7NyOuhMS+rtyf2DFMkwip2cl1hsHOY DLhjt/WvWTKSrc/fWNVG71cvzZpvURz3Xi9zphQT35SPffh0NadPkPQ+n5oMdTf4qKFG Z8og== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nwvgJq8V3A4EcSBga8/aE9oI0VJyJynq/QeqcrvxjMA=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=wa3EZ6q0w7SE+YYtli0nwM2U9MEAdgsRQms+OiOVKZ2GXyPCe5nL0lZekpiY1h2K8I Af9fH7qKd0Y6Q5YihjvhkespdgUBpFQkGQSDUNp38qtRAlhXokcMaKn1mN6cH//s60wH 6ZIhZ2exQycQpN2YYIlZE2swyAUoyjT/e8429kA/hi83oPs5k5KxlY1BIgr/4B0vkEfI pOrYQdAiti+ANrz6Q1gTGLabuBZhNuTwIYlXpbesZdvUIiG7zv2QwLC0Z+ZoEs1B5JG9 93Omx0q+pvfwvWohKgZAhqDyGmjhK3piPED9evl5a/ZP6pDUsKCC3LmSyLE1RO3WqA/1 VWKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="M/FBDsV3"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id v19-20020a1709064e9300b00988e953a586sm8108187eju.61.2023.10.10.02.29.58 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:30:02 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 07/18] target/nios2: Declare QOM definitions in 'cpu-qom.h' Date: Tue, 10 Oct 2023 11:28:49 +0200 Message-ID: <20231010092901.99189-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé --- target/nios2/cpu-qom.h | 32 ++++++++++++++++++++++++++++++++ target/nios2/cpu.h | 22 +--------------------- 2 files changed, 33 insertions(+), 21 deletions(-) create mode 100644 target/nios2/cpu-qom.h diff --git a/target/nios2/cpu-qom.h b/target/nios2/cpu-qom.h new file mode 100644 index 0000000000..0bcf2c724f --- /dev/null +++ b/target/nios2/cpu-qom.h @@ -0,0 +1,32 @@ +/* + * QEMU Nios II CPU QOM header (target agnostic) + * + * Copyright (c) 2012 Chris Wulff + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef QEMU_NIOS2_CPU_QOM_H +#define QEMU_NIOS2_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_NIOS2_CPU "nios2-cpu" + +OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU) + +/** + * Nios2CPUClass: + * @parent_phases: The parent class' reset phase handlers. + * + * A Nios2 CPU model. + */ +struct Nios2CPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#endif diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 70b6377a4f..e19e12b2a6 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -21,35 +21,15 @@ #ifndef NIOS2_CPU_H #define NIOS2_CPU_H +#include "cpu-qom.h" #include "exec/cpu-defs.h" -#include "hw/core/cpu.h" #include "hw/registerfields.h" -#include "qom/object.h" typedef struct CPUArchState CPUNios2State; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" #endif -#define TYPE_NIOS2_CPU "nios2-cpu" - -OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU) - -/** - * Nios2CPUClass: - * @parent_phases: The parent class' reset phase handlers. - * - * A Nios2 CPU model. - */ -struct Nios2CPUClass { - /*< private >*/ - CPUClass parent_class; - /*< public >*/ - - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - #define TARGET_HAS_ICE 1 /* Configuration options for Nios II */ From patchwork Tue Oct 10 09:28:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731445 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641786wrw; Tue, 10 Oct 2023 02:33:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF7nUQotcfky0J2MQq5RKEz5SgrIWjPGvTALzhyhtM5xf7ZqE8NMn31B8VHYZpZbSGMflC9 X-Received: by 2002:a0c:dd90:0:b0:65b:177b:a430 with SMTP id v16-20020a0cdd90000000b0065b177ba430mr17563029qvk.47.1696930421367; Tue, 10 Oct 2023 02:33:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930421; cv=none; d=google.com; s=arc-20160816; b=GFypxojjLDABo4vFSp/B/3VuzGLTQwx5f8+B6JXeCVYDPfmCFgX7uERPRLd2PpDhbW CDu4MBThfq75lcVue2v1RJ+JTb6yGSbC5h5QveCQQKJWWxPHVSstl3ZCsegmtG0xMpz2 wC9xUyP0mJL76ypcFqVp+nN+qzS0mKxiKKGK+Rjc/ElcpWq1VaYUod5Kkm1aivhgyOiP YA2PvJumvV28YpeXcEsRJqbUuC0mkG//exccmiEPjbmXyULOG66j0V+rN2vdZqzTUW+3 nhC3XVxMGqCZEDROD8dZg4av1wlDhL54QXcu0uxkft2TQorWLlSPjrAwILg08T5hLSFB pv8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7/Dazi2VzLCUVkcADynMQnmNFinEpKaq76+gzFIU2vQ=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=P2aBuyixx2kHvKhm0im8Sh4rQU+9sUvvTBoeBw9800TDAQf3FLHEpRcrC3t5aj9rhK NmL1g6rmq/0Hc/J8cnpU7psrooxe4pWG3qmc9Bo2Lbvh3qVAqHhv4V1ffvaYPFcjlUe+ ZQ+4+6pDqOye46bPs533V0KeTbD9uNIE0QRG2V2C5PA/0F6Osfv2XaLviVTSuQzfiBv9 jQ8481HFutHXJIOCRtj3UsB9W1KDCik0PjpxuhheLR4P8/GMNSBDyc6eQsLZuxPRcHPL j96ya2pNx7vtoQSwfZEPWuY3oRKR3N7dHSQZzCBlJli6x1mIQwmMHtcg34oORIFQ1omC 4Bvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="dFh3/cNe"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id n12-20020a170906378c00b009ade1a4f795sm8142642ejc.168.2023.10.10.02.30.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:30:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 08/18] target/openrisc: Declare QOM definitions in 'cpu-qom.h' Date: Tue, 10 Oct 2023 11:28:50 +0200 Message-ID: <20231010092901.99189-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé --- target/openrisc/cpu-qom.h | 36 ++++++++++++++++++++++++++++++++++++ target/openrisc/cpu.h | 26 +------------------------- 2 files changed, 37 insertions(+), 25 deletions(-) create mode 100644 target/openrisc/cpu-qom.h diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h new file mode 100644 index 0000000000..d1930acb74 --- /dev/null +++ b/target/openrisc/cpu-qom.h @@ -0,0 +1,36 @@ +/* + * QEMU OpenRISC CPU QOM header (target agnostic) + * + * Copyright (c) 2011-2012 Jia Liu + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef QEMU_OPENRISC_CPU_QOM_H +#define QEMU_OPENRISC_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_OPENRISC_CPU "or1k-cpu" + +OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) + +#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU +#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX + +/** + * OpenRISCCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A OpenRISC CPU model. + */ +struct OpenRISCCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 334997e9a1..2dccd67378 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -20,33 +20,12 @@ #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -#include "hw/core/cpu.h" -#include "qom/object.h" #define TCG_GUEST_DEFAULT_MO (0) -#define TYPE_OPENRISC_CPU "or1k-cpu" - -OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) - -/** - * OpenRISCCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A OpenRISC CPU model. - */ -struct OpenRISCCPUClass { - /*< private >*/ - CPUClass parent_class; - /*< public >*/ - - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - #define TARGET_INSN_START_EXTRA_WORDS 1 enum { @@ -308,7 +287,6 @@ struct ArchCPU { CPUOpenRISCState env; }; - void cpu_openrisc_list(void); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -343,8 +321,6 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu); void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #endif -#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU -#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU #include "exec/cpu-all.h" From patchwork Tue Oct 10 09:28:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731440 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641522wrw; Tue, 10 Oct 2023 02:32:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IElpNs7DZ1ygi1m1Uk+6/c22BVgT1s3kWk+uKRZw7PB2TIkoUUegGjmBSKcrezwdXogHiU/ X-Received: by 2002:a05:6214:1907:b0:65b:1ad4:ca7e with SMTP id er7-20020a056214190700b0065b1ad4ca7emr16639999qvb.56.1696930379104; Tue, 10 Oct 2023 02:32:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930379; cv=none; d=google.com; s=arc-20160816; b=JPByUmw1Dt5W4HQx1S3+fcnfJlbQbZ8LGA467xr/tdiH74TF543YPFVDQL5GmoEH8R QTZRJ8WUGRyH7L0ZjjU9tS4cFzqLtQjuXfsXeH7TiSho0PLi7euifS89AkwCtbY0PdNM Nb6PlTtkhUQ+rmu+zwG0Md+V59VUvbl9SNqFLoKUOnIX2c2GmZMyz+wre69TUs37QzH6 fgjnzM61un4/dVj8zvivTdNVx2Dxphx8YP5QEQvjL+dsIMXtF2NMDMPa4F6BQ0Nby1F3 9oK+sMnYd3pqJLb4iNx1c6z9u8K7ZsC1ZPjXlFlcOp35ieNis6cXyPHEV4RtNbjzvSF7 YSHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FCZsPKk2jjgL5uslZNHqLJ2r1o7NzsXUetagm0hbuBc=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=Y3TwJcxxdS/N95hSP3qwGREj5uRDRDep/0eF60QHZz7RySKXcCDBMh14HhMPE5F6t+ WFl58bvtyX+bhhX7J7FddjJUYRlvL9JYr5L2C4Q+AYu5MaYNmLmr05qiEB6o4LOxNfBu GJbis7ISMeq01tN0SItBi/ALL9Dh3q2K5VqTHIJVChbfOrWdJpES9hCytD5d3DYhSl29 rF85l/LF7QQu0mrEdOasbNbPG4hlwaRY8vGFHYK7tDLscL3KAXNKDclpmChHEpLkiumm SU2ZY2xlmPQCtE3Ir5BXzzM7YS3+3ZcNo3tUL4RI4YhJNAaQxED6jDT4x80/enSGGwcn Reow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Ilr/f8eY"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id u25-20020aa7db99000000b0053116e45317sm7298755edt.44.2023.10.10.02.30.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:30:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 09/18] target/i386: Inline target specific TARGET_DEFAULT_CPU_TYPE definition Date: Tue, 10 Oct 2023 11:28:51 +0200 Message-ID: <20231010092901.99189-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=philmd@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org TARGET_DEFAULT_CPU_TYPE depends on the TARGET_X86_64 definition which is target specific. Such target specific definition taint "cpu-qom.h". Since "cpu-qom.h" must be target agnostic, remove this target specific definition uses by inlining TARGET_DEFAULT_CPU_TYPE in the two machines using it. "target/i386/cpu-qom.h" is now fully target agnostic. Signed-off-by: Philippe Mathieu-Daudé --- target/i386/cpu.h | 6 ------ hw/i386/microvm.c | 6 +++++- hw/i386/pc.c | 6 +++++- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 862e4f1ff5..7c976971c7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2243,12 +2243,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define CPU_RESOLVING_TYPE TYPE_X86_CPU -#ifdef TARGET_X86_64 -#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu64") -#else -#define TARGET_DEFAULT_CPU_TYPE X86_CPU_TYPE_NAME("qemu32") -#endif - #define cpu_list x86_cpu_list /* MMU modes definitions */ diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index b9c93039e2..281bf0c364 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -650,7 +650,11 @@ static void microvm_class_init(ObjectClass *oc, void *data) mc->has_hotpluggable_cpus = false; mc->auto_enable_numa_with_memhp = false; mc->auto_enable_numa_with_memdev = false; - mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; +#ifdef TARGET_X86_64 + mc->default_cpu_type = X86_CPU_TYPE_NAME("qemu64"); +#else + mc->default_cpu_type = X86_CPU_TYPE_NAME("qemu32"); +#endif mc->nvdimm_supported = false; mc->default_ram_id = "microvm.ram"; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index aad7e8ccd1..2f7c0c1bdb 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1818,7 +1818,11 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) hc->plug = pc_machine_device_plug_cb; hc->unplug_request = pc_machine_device_unplug_request_cb; hc->unplug = pc_machine_device_unplug_cb; - mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; +#ifdef TARGET_X86_64 + mc->default_cpu_type = X86_CPU_TYPE_NAME("qemu64"); +#else + mc->default_cpu_type = X86_CPU_TYPE_NAME("qemu32"); +#endif mc->nvdimm_supported = true; mc->smp_props.dies_supported = true; mc->default_ram_id = "pc.ram"; From patchwork Tue Oct 10 09:28:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731443 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641646wrw; Tue, 10 Oct 2023 02:33:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHAuZpT8/Jxdi5HUzowJEHmWWooOEE/y9XCd+wBlKEmJkCGxXXyenf7J4rrvK10qysXmFpH X-Received: by 2002:a81:ae1c:0:b0:5a7:b53f:c304 with SMTP id m28-20020a81ae1c000000b005a7b53fc304mr2483735ywh.37.1696930398619; Tue, 10 Oct 2023 02:33:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930398; cv=none; d=google.com; s=arc-20160816; b=AfNtXZh6AcJcN40rF8qNIZDKwMvNR9NlSXgZ/Z8+3NxNDkciiGc8o1Yf5Ux1nhXdAM V7i1WE00ZZvFgTbX/nv7gsBUZvzubXMTH37fGfKyja9WZ2r0ZCTADmlRzVOPIiqMQzAk qyV1xa2dON44IcAR2XsWDS5Pxmd+or8c1VCPRDzA3+VDJFucV70pqBb0h9AtF/6Vvgy8 xcvqucRlutsBcvqVwh+Mr8Qr227K0g39hgbAP9jpq9jFg1ttsYT0G0ShOaZA6MIpAzjg 4jSF9N39wJ4Xw5v3Q4k6o8nNd0DRyFvLyeoN2mQU9BdW7eGY+1n/YW6Z13JonZ0Nce6r X1+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ty5A8kcVGZ5VAZ2hfMU3PH9M5Fs6Xopxrwnt8GKnicA=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=IelBjeNDqSAnBI1OhUXzldDCbwUFxTQ2rFYYSHnSeFXS5zuziOcmsL8PObXzFpdzGT V+pkdK9AzUhraE1QOMdBmbjqHcZRJbusRBhc9BEAqvSdI4MBIB6FO075UjFmsiQQBg9a BVUMRwYoUihR7xI31zGWqMTEAi6mT6w4OCCEsGKZ1BXx3RPsTUkZKlEIelLz2U9uFM4W tYanEfxPRvHSk96ExzLpPyu1SX0g0QGTF11NFQ1h6/A47dVxLxaq99Au4b3Pj8+DrRCW yd/6AaZhylfg/JWNnU7QFYoCrrRytmykcnhWlTYxs5rlYpRz/4NWIDz+2ng1GtQwWdoj I7GQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zniWLfBA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id g26-20020aa7c59a000000b00530ccd180a3sm7276170edq.97.2023.10.10.02.30.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:30:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 10/18] target/riscv: Inline target specific TYPE_RISCV_CPU_BASE definition Date: Tue, 10 Oct 2023 11:28:52 +0200 Message-ID: <20231010092901.99189-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org TYPE_RISCV_CPU_BASE depends on the TARGET_RISCV32/TARGET_RISCV64 definitions which are target specific. Such target specific definition taints "cpu-qom.h". Since "cpu-qom.h" must be target agnostic, remove its target specific definition uses by inlining TYPE_RISCV_CPU_BASE in the two machines using it. "target/riscv/cpu-qom.h" is now fully target agnostic. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis --- target/riscv/cpu-qom.h | 8 +------- hw/riscv/spike.c | 8 +++++++- hw/riscv/virt.c | 8 +++++++- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 8cb67b84a4..f607687384 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU RISC-V CPU QOM header + * QEMU RISC-V CPU QOM header (target agnostic) * * Copyright (c) 2023 Ventana Micro Systems Inc. * @@ -43,12 +43,6 @@ #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") -#if defined(TARGET_RISCV32) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 -#elif defined(TARGET_RISCV64) -# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 -#endif - typedef struct CPUArchState CPURISCVState; OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 81f7e53aed..eae49da6d6 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -349,7 +349,13 @@ static void spike_machine_class_init(ObjectClass *oc, void *data) mc->init = spike_board_init; mc->max_cpus = SPIKE_CPUS_MAX; mc->is_default = true; - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; +#if defined(TARGET_RISCV32) + mc->default_cpu_type = TYPE_RISCV_CPU_BASE32; +#elif defined(TARGET_RISCV64) + mc->default_cpu_type = TYPE_RISCV_CPU_BASE64; +#else +#error unsupported target +#endif mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5edc1d98d2..620a4e5f07 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1685,7 +1685,13 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) mc->desc = "RISC-V VirtIO board"; mc->init = virt_machine_init; mc->max_cpus = VIRT_CPUS_MAX; - mc->default_cpu_type = TYPE_RISCV_CPU_BASE; +#if defined(TARGET_RISCV32) + mc->default_cpu_type = TYPE_RISCV_CPU_BASE32; +#elif defined(TARGET_RISCV64) + mc->default_cpu_type = TYPE_RISCV_CPU_BASE64; +#else +#error unsupported target +#endif mc->pci_allow_0_address = true; mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; From patchwork Tue Oct 10 09:28:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731434 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641034wrw; Tue, 10 Oct 2023 02:31:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHn2nGhEQiSNXExWf5YI/RQCR6ONFsa/uk5UqNM0gB7QzqADtjBImHTi8TMK0hdlwyaiiPx X-Received: by 2002:a05:620a:4248:b0:774:193c:94bd with SMTP id w8-20020a05620a424800b00774193c94bdmr20091057qko.4.1696930304843; Tue, 10 Oct 2023 02:31:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930304; cv=none; d=google.com; s=arc-20160816; b=0FZpSqngGm4H754U6ktex/vTKUfAjrdf/fDPG7zWsqMdUBLrVmHnopHN7w2AQ3EWz/ qGpwfgJ/wZL0kRXqzQ17hiZvzGOSdaze8OWNEvyES8yoxWtB9sJt4bkUoioly/3md8ph HrpE1m1r3XfT4mnxdBYnQIMPyZ4LFaRI6TYg0idhCwe8j5yuyX2XU3tHjg+Aj0Vrb2ZS KYfACKzNd57/IHaU6wlf+Taxv/LNlKVpWZums8wNY50YUJFZ7JviTxA0fSBDeAVFFejW n/hEvEZBB5q/EdKXuRs2lPN8crpXghFcOOYd+zSJ7YMXdBrHHIF3VTXNtdBwmH8cWIcq 6B3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1MyuGXLiWN8UopdjDzgIKzA4UsMWUE83156ltUpzRtA=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=eK3ONGrKOQfgSthRz2pZZgyRkF8kI0xWLOR6MOCSWiDe9GZ8V2HVLGWxmgqJGjGowU VcnLncb8rAyIpTA1F+SwqRk4pUi4LByQZRhr69T63fe0x/YygTk5hHvnkDaEUN7lHhT2 pwO+Qu2JnvLoiXHlw098nVgl8GeWpEjxevLam+updVi+5wtXvdgcDVmAr3yzYLHvlb8W woLhRoZNbEsIEKC12wxh7pNnuw/xXNd6kVhPlAUGztpP+om7mOU/ZSusG0VRj0U5ywe+ x9BGUxejDPI6QhnRSPIOFjNHpYj1H5JJQGKzkh1lQ5ZD1/+i6+iYd2+xzYnhQIxA3bht YsZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BT9Xud44; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id u2-20020a17090617c200b009ad8084e08asm8033134eje.0.2023.10.10.02.30.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:30:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 11/18] target/i386: Declare CPU QOM types using DEFINE_TYPES() macro Date: Tue, 10 Oct 2023 11:28:53 +0200 Message-ID: <20231010092901.99189-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. In few commits we are going to add more types, so replace the type_register_static() to ease further reviews. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/i386/cpu.c | 50 ++++++++++++++++++++++------------------------- 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9fad31b8db..8f1fd5f304 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4989,13 +4989,6 @@ static void max_x86_cpu_initfn(Object *obj) &error_abort); } -static const TypeInfo max_x86_cpu_type_info = { - .name = X86_CPU_TYPE_NAME("max"), - .parent = TYPE_X86_CPU, - .instance_init = max_x86_cpu_initfn, - .class_init = max_x86_cpu_class_init, -}; - static char *feature_word_description(FeatureWordInfo *f, uint32_t bit) { assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD); @@ -8017,19 +8010,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) } } -static const TypeInfo x86_cpu_type_info = { - .name = TYPE_X86_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(X86CPU), - .instance_align = __alignof(X86CPU), - .instance_init = x86_cpu_initfn, - .instance_post_init = x86_cpu_post_initfn, - - .abstract = true, - .class_size = sizeof(X86CPUClass), - .class_init = x86_cpu_common_class_init, -}; - /* "base" CPU model, used by query-cpu-model-expansion */ static void x86_cpu_base_class_init(ObjectClass *oc, void *data) { @@ -8041,22 +8021,38 @@ static void x86_cpu_base_class_init(ObjectClass *oc, void *data) xcc->ordering = 8; } -static const TypeInfo x86_base_cpu_type_info = { - .name = X86_CPU_TYPE_NAME("base"), - .parent = TYPE_X86_CPU, - .class_init = x86_cpu_base_class_init, +static const TypeInfo x86_cpu_types[] = { + { + .name = TYPE_X86_CPU, + .parent = TYPE_CPU, + .abstract = true, + .instance_size = sizeof(X86CPU), + .instance_align = __alignof(X86CPU), + .instance_init = x86_cpu_initfn, + .instance_post_init = x86_cpu_post_initfn, + .class_size = sizeof(X86CPUClass), + .class_init = x86_cpu_common_class_init, + }, { + .name = X86_CPU_TYPE_NAME("base"), + .parent = TYPE_X86_CPU, + .class_init = x86_cpu_base_class_init, + }, { + .name = X86_CPU_TYPE_NAME("max"), + .parent = TYPE_X86_CPU, + .instance_init = max_x86_cpu_initfn, + .class_init = max_x86_cpu_class_init, + } }; +DEFINE_TYPES(x86_cpu_types) + static void x86_cpu_register_types(void) { int i; - type_register_static(&x86_cpu_type_info); for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { x86_register_cpudef_types(&builtin_x86_defs[i]); } - type_register_static(&max_x86_cpu_type_info); - type_register_static(&x86_base_cpu_type_info); } type_init(x86_cpu_register_types) From patchwork Tue Oct 10 09:28:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731441 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641582wrw; Tue, 10 Oct 2023 02:33:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE3vQG3hjDT7wuFbpoFoo5h64k1LyyA0wFQIxql/cY1JNGOOkEI08pVYMaZPueCi5SudgCH X-Received: by 2002:a1f:c6c7:0:b0:49a:3538:18e3 with SMTP id w190-20020a1fc6c7000000b0049a353818e3mr12599276vkf.6.1696930387907; Tue, 10 Oct 2023 02:33:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930387; cv=none; d=google.com; s=arc-20160816; b=HteHgyMtIgI6j2MQaF/vQJVC0Sry5S3f7QUZhGQqGAX2YgjvvJo/i//hTXQs2BM3z5 QHvVYLuLeo4mbuNJJAHEAkMJwQqJx+48r1HDSS8/0N6DPjkf5QiU41p0C0sp8HWdlPE8 iXBhqRnm9VlcfQkmJRd+AOgRp7Xgqoh70ywOuqTBWn6XJxZ6ebpNQKu/p2uKYfa844N2 1W3RmrYCMWCrZBbU9SQ5WFcAcP+8vkkejpSeheKiZoTxMFP6VhddNKoaRtlOIMeXzfV8 esJQK0/Eqx9efC7F502Iog1cLDTp5nItIva9/ENxWRPglZbO33tZQ4bwDqAGz2LRcR06 63vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tGDIRmDFCC3SzHQp/xiOV97Tov37+momJ53r+jvT974=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=Mr3CVDkasnrvArn4ppzhHv6jOc3RrHXSqRjB384fD2LlSLE0qtfnJuVcl4LW+5OdYp MnUtPH12OzZGWokJZala1KgEm1XNMwac2rJrElSQsOkU2uktW+3smbjhukHCD9kxQs8i 9ATiJmiZpSv4SuuEufi7F1887rOhq1AQe6lVC3jRyUdjYIVtR7Tn3S9KbwQMKPm/aAyB APNlkVdPWu26VrGc41qc5qrR+2+joUbTK3wm5rumjm1Yw3wMW1mecz+JkIvfckXJq4B0 wLE2oSPAGmWzGYBJm/gciwMiQb5pMsm7bXNwp/dkznBeNmWgL3yNXCKx0fSScKu5/fb9 m5IA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xQd8MQoD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id st12-20020a170907c08c00b009b9f87b34b6sm6753332ejc.189.2023.10.10.02.30.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:30:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 12/18] target/mips: Declare CPU QOM types using DEFINE_TYPES() macro Date: Tue, 10 Oct 2023 11:28:54 +0200 Message-ID: <20231010092901.99189-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. In few commits we are going to add more types, so replace the type_register_static() to ease further reviews. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a0023edd43..83ee54f766 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -595,17 +595,21 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) #endif /* CONFIG_TCG */ } -static const TypeInfo mips_cpu_type_info = { - .name = TYPE_MIPS_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(MIPSCPU), - .instance_align = __alignof(MIPSCPU), - .instance_init = mips_cpu_initfn, - .abstract = true, - .class_size = sizeof(MIPSCPUClass), - .class_init = mips_cpu_class_init, +static const TypeInfo mips_cpu_types[] = { + { + .name = TYPE_MIPS_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(MIPSCPU), + .instance_align = __alignof(MIPSCPU), + .instance_init = mips_cpu_initfn, + .abstract = true, + .class_size = sizeof(MIPSCPUClass), + .class_init = mips_cpu_class_init, + } }; +DEFINE_TYPES(mips_cpu_types) + static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) { MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); @@ -630,7 +634,6 @@ static void mips_cpu_register_types(void) { int i; - type_register_static(&mips_cpu_type_info); for (i = 0; i < mips_defs_number; i++) { mips_register_cpudef_type(&mips_defs[i]); } From patchwork Tue Oct 10 09:28:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731442 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641640wrw; Tue, 10 Oct 2023 02:33:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH72q/GwljA28feiPKE3AX6Sbbu902ejmgjGe6RoXCorJIEF/zF2xDVZUi6SYqSlpDkLAmR X-Received: by 2002:a05:620a:1210:b0:775:7909:ece8 with SMTP id u16-20020a05620a121000b007757909ece8mr17264368qkj.43.1696930398103; Tue, 10 Oct 2023 02:33:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930398; cv=none; d=google.com; s=arc-20160816; b=ia7a8HKrtJFfIdNYYWSrm8fUAnEl97VmYIiglY7pljTarXFA26FRm9CcUuYVkhmsvx QLvovuDFAG47U96xFDGsRAF/4y2nsEZ7hiruEV+qKtPkegfma5oQsEYRx9U4F7BA8hbb Flt7X/APpnnwzErhkcUPCyWYouh8szlvVx6ZQ+vD1at9s+FshmwmYtoXoGHV75OSXRvn RnGf1xx7WoNzTwTyGLPBSYyapJtHLwA2euUwMP5i2tTSfElRD8nncFpV2jcqnriF6XPo rBLX32Tso4CO2RlgBb8+AdvCSbckQUQlxijW9K93TWmrY4I9MHUBG/cSIPjoFhKgCLVv dr1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BMy5FMNiGQxFcppEwI4sVWirnEfoYMzZHwDGKyKUC/Q=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=K5m6+sXytMPQ9rav7YL97sJ8Djq0HKubdePax0b3qi1MoTz6Y5USM2FUK+ds6VuuWt yWp0KODUrDnl/CaM1SdoxyXLBz2cfkzVG0QJl8ngEMJz1HvkwEff6m5C7KvppD8r29yA POjuz5bEgPY5ux33+ghGADe6/nFZ3SdnpmdC7Cwma4XytbLezF6fJWodcTZpIhL6eZzg MYMl9U/UFe++pvk87GWJZ9HfDh29cLLDz7GQ9qXePHp9yR09RlHV5TTX2+tWWAs+BlN9 gtEssOLTcqVEiGiOrP0lwL1SByoasrghBX5Mny31LjrbO19lXz3jyqOfqBN7chRNjUDv /e0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vQAeosbc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id op13-20020a170906bced00b009a13fdc139fsm8181867ejb.183.2023.10.10.02.30.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:30:52 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 13/18] target/ppc: Declare CPU QOM types using DEFINE_TYPES() macro Date: Tue, 10 Oct 2023 11:28:55 +0200 Message-ID: <20231010092901.99189-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. In few commits we are going to add more types, so replace the type_register_static() to ease further reviews. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/ppc/cpu_init.c | 52 +++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 29 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 40fe14a6c2..055436c141 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7408,39 +7408,34 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) #endif /* CONFIG_TCG */ } -static const TypeInfo ppc_cpu_type_info = { - .name = TYPE_POWERPC_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(PowerPCCPU), - .instance_align = __alignof__(PowerPCCPU), - .instance_init = ppc_cpu_instance_init, - .instance_finalize = ppc_cpu_instance_finalize, - .abstract = true, - .class_size = sizeof(PowerPCCPUClass), - .class_init = ppc_cpu_class_init, +static const TypeInfo ppc_cpu_types[] = { + { + .name = TYPE_POWERPC_CPU, + .parent = TYPE_CPU, + .abstract = true, + .instance_size = sizeof(PowerPCCPU), + .instance_align = __alignof__(PowerPCCPU), + .instance_init = ppc_cpu_instance_init, + .instance_finalize = ppc_cpu_instance_finalize, + .class_size = sizeof(PowerPCCPUClass), + .class_init = ppc_cpu_class_init, #ifndef CONFIG_USER_ONLY - .interfaces = (InterfaceInfo[]) { - { TYPE_INTERRUPT_STATS_PROVIDER }, - { } + .interfaces = (InterfaceInfo[]) { + { TYPE_INTERRUPT_STATS_PROVIDER }, + { } + }, +#endif + }, +#ifndef CONFIG_USER_ONLY + { + .name = TYPE_PPC_VIRTUAL_HYPERVISOR, + .parent = TYPE_INTERFACE, + .class_size = sizeof(PPCVirtualHypervisorClass), }, #endif }; -#ifndef CONFIG_USER_ONLY -static const TypeInfo ppc_vhyp_type_info = { - .name = TYPE_PPC_VIRTUAL_HYPERVISOR, - .parent = TYPE_INTERFACE, - .class_size = sizeof(PPCVirtualHypervisorClass), -}; -#endif - -static void ppc_cpu_register_types(void) -{ - type_register_static(&ppc_cpu_type_info); -#ifndef CONFIG_USER_ONLY - type_register_static(&ppc_vhyp_type_info); -#endif -} +DEFINE_TYPES(ppc_cpu_types) void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) { @@ -7635,4 +7630,3 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) #undef RGPL #undef RFPL } -type_init(ppc_cpu_register_types) From patchwork Tue Oct 10 09:28:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731448 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641992wrw; Tue, 10 Oct 2023 02:34:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE9UqDCDPI/K556yIP/VPnzv58Vmg4M55jN656Axervr9z0I7dGPdKwqf/I1KDtahidzDOY X-Received: by 2002:a05:620a:2584:b0:774:1012:8220 with SMTP id x4-20020a05620a258400b0077410128220mr22012241qko.23.1696930452776; Tue, 10 Oct 2023 02:34:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930452; cv=none; d=google.com; s=arc-20160816; b=g1DEezYeWo12jMAZgv6ettNQ26kEH/Wz0Dv4/qzLH10uQZ9iZ5e9nfsRZ3O7yNSkMw LKyUiRgALt4GActidMhj56I5ngZBdSFozkWBGmamDm1wpRr/cqFH/r9nDqC3RA5v68P5 C37B+FJxiR/9jUl0DBD6ylemr6R8+BV4D36rK7bWNl4MCkCrw63dDcOxr9lvir/rBqjS PJCoZyK6a4AO56+rr4gQThTanEQLu7a9mBXth+xcCU9ecxLmlCxCzEcQUnYkMCeUiW89 PAS8oz6u5oVuYpnHZrXqtI7AD5Jti49ZhJ3v0fr0iZf7J0Q4g58S+fRbVIiZmROppyiT AW6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=g9ac00GoAEt719cFFz9dDP5blE56OLyiS+6SiHpN8FY=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=fRiyEEMflqj+k6Pr6yrxd77K5zYnRJIpUUZLlHsem0jOCargcnPR3wlGbYE9Nb+a/J JF3YNnFHo3hsG+EiVLwi76U6xRzLxwZn0U0CGvFmIdqXFnYfAE05Fj4ly0b6U9j8l48s S+/mMJ9CUfj23tAyy85lCIxYzF9OilSc6WOwI3PLY6wxYmHkd301LYgcIRphNUbeWUaR XbuVny2QE1Y7dvh5e/p08aIKeH1+Mvmwplou6vFVmEH24A9ttXMXhzQxltdDppt+/Opg d6pze2QcArH2+gNZBAcf6wUkjKv5slCP45drVmc95E7oRXRDfIy+3XIZgo/KIU7+vcR3 fgAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VeZUhIXa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id n12-20020a170906378c00b0099d45ed589csm8100822ejc.125.2023.10.10.02.30.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:31:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 14/18] target/sparc: Declare CPU QOM types using DEFINE_TYPES() macro Date: Tue, 10 Oct 2023 11:28:56 +0200 Message-ID: <20231010092901.99189-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. In particular because type array declared with such macro are easier to review. In few commits we are going to add more types, so replace the type_register_static() to ease further reviews. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Mark Cave-Ayland --- target/sparc/cpu.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 8ba96ae225..1e66413e94 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -924,17 +924,21 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->tcg_ops = &sparc_tcg_ops; } -static const TypeInfo sparc_cpu_type_info = { - .name = TYPE_SPARC_CPU, - .parent = TYPE_CPU, - .instance_size = sizeof(SPARCCPU), - .instance_align = __alignof(SPARCCPU), - .instance_init = sparc_cpu_initfn, - .abstract = true, - .class_size = sizeof(SPARCCPUClass), - .class_init = sparc_cpu_class_init, +static const TypeInfo sparc_cpu_types[] = { + { + .name = TYPE_SPARC_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(SPARCCPU), + .instance_align = __alignof(SPARCCPU), + .instance_init = sparc_cpu_initfn, + .abstract = true, + .class_size = sizeof(SPARCCPUClass), + .class_init = sparc_cpu_class_init, + } }; +DEFINE_TYPES(sparc_cpu_types) + static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data) { SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); @@ -959,7 +963,6 @@ static void sparc_cpu_register_types(void) { int i; - type_register_static(&sparc_cpu_type_info); for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { sparc_register_cpudef_type(&sparc_defs[i]); } From patchwork Tue Oct 10 09:28:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731446 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641854wrw; Tue, 10 Oct 2023 02:33:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG7XNpQRpRhMG9F7WlTBghuQ2qe4U5NoSRoig53s3ufGxCDhQpMHaAS1D2OuqMxG0jJMvI1 X-Received: by 2002:a37:ac01:0:b0:774:1641:d60f with SMTP id e1-20020a37ac01000000b007741641d60fmr18915515qkm.41.1696930431946; Tue, 10 Oct 2023 02:33:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930431; cv=none; d=google.com; s=arc-20160816; b=ypZ78hTYuXOPnHh0S3DeWXew3B9ZZLi21KLhTREvoPcVuOqMlR8uA0CpEq1th1a5Nf IeA7JM92jeY2NGrUX/WF8AMB8PHTAKP/6iDMKGJjVjCS8Vt0emcORbP2D1lSApmjmoAv NFs3fOUluO/whjyVCw5SVIdYIxbn9RrW8rCvvZDSN3ojUdrMN43I+dMuKVqB3bUYX8a+ LiRF6XpFIxGu1rFKNqSmNqcOcLKMftjliDnCEZzKsp3R5Hj23w9rDUxG/kGwftqicbYm KkyAbJhbFqKYEZNgm0i28EhKqXuuzp0pgtFMGoAKxzhdLU2m8ENxNx3eZL2l2pP1lE2K aU/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7WiHkuSW70dwreiTW00ZFUbfeyH/7vFgJnStNjqec/s=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=ddPx0NbMomhIKOu9K/1mp66PN2uF/D14x4YnnPobGIt/XtgVOOL3IwYcYdiDM30cum mHFBnVrdTrbM9fyDNRl8mg7yhuI0l+xo19N8bL1HwR2q5s8EPibPQE0eDX8sq9JlGnAL 3OegMF0IEfmlCVwWkeME74Hb8q92tyHHan0dvK1zq5tKaGHYDYxJjiX1FgDCavKAFK21 h8UTh5XcepClkVoeCb/q1DqP9d3jE8W91uz8Ac7RarHlRmVXT5nEqOMBvOSAs69BQmTK jwLk5Nh+QNWHQ7NVgve7SHuJSnSPUR9nHVmBYPtwMCNgNY+9EIII6HOMaWuDVmAGTbiM YSnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qr7H9Mw2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id b11-20020aa7c90b000000b00536246d1eadsm7353953edt.41.2023.10.10.02.31.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:31:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 15/18] cpus: Open code OBJECT_DECLARE_TYPE() in OBJECT_DECLARE_CPU_TYPE() Date: Tue, 10 Oct 2023 11:28:57 +0200 Message-ID: <20231010092901.99189-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=philmd@linaro.org; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since the OBJECT_DECLARE_CPU_TYPE() macro uses the abstract ArchCPU type, when declaring multiple CPUs of the same ArchCPU type we get an error related to the indirect G_DEFINE_AUTOPTR_CLEANUP_FUNC() use within OBJECT_DECLARE_TYPE(): target/mips/cpu-qom.h:31:1: error: redefinition of 'glib_autoptr_clear_ArchCPU' OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU) ^ include/hw/core/cpu.h:82:5: note: expanded from macro 'OBJECT_DECLARE_CPU_TYPE' OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); ^ include/qom/object.h:237:5: note: expanded from macro 'OBJECT_DECLARE_TYPE' G_DEFINE_AUTOPTR_CLEANUP_FUNC(InstanceType, object_unref) \ ^ /usr/include/glib-2.0/glib/gmacros.h:1371:3: note: expanded from macro 'G_DEFINE_AUTOPTR_CLEANUP_FUNC' _GLIB_DEFINE_AUTOPTR_CLEANUP_FUNCS(TypeName, TypeName, func) ^ /usr/include/glib-2.0/glib/gmacros.h:1354:36: note: expanded from macro '_GLIB_DEFINE_AUTOPTR_CLEANUP_FUNCS' static G_GNUC_UNUSED inline void _GLIB_AUTOPTR_CLEAR_FUNC_NAME(TypeName) (TypeName *_ptr) \ ^ /usr/include/glib-2.0/glib/gmacros.h:1338:49: note: expanded from macro '_GLIB_AUTOPTR_CLEAR_FUNC_NAME' #define _GLIB_AUTOPTR_CLEAR_FUNC_NAME(TypeName) glib_autoptr_clear_##TypeName ^ :54:1: note: expanded from here glib_autoptr_clear_ArchCPU ^ target/mips/cpu-qom.h:30:1: note: previous definition is here OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU) ^ Avoid that problem by expanding the OBJECT_DECLARE_TYPE() macro within OBJECT_DECLARE_CPU_TYPE(). Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson --- include/hw/core/cpu.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index e02bc5980f..ab724fab3a 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -79,7 +79,12 @@ DECLARE_CLASS_CHECKERS(CPUClass, CPU, */ #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \ typedef struct ArchCPU CpuInstanceType; \ - OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); + typedef struct CpuClassType CpuClassType; \ + \ + G_DEFINE_AUTOPTR_CLEANUP_FUNC(CpuInstanceType, object_unref) \ + \ + DECLARE_OBJ_CHECKERS(CpuInstanceType, CpuClassType, \ + CPU_MODULE_OBJ_NAME, TYPE_##CPU_MODULE_OBJ_NAME) typedef enum MMUAccessType { MMU_DATA_LOAD = 0, From patchwork Tue Oct 10 09:28:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731437 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641467wrw; Tue, 10 Oct 2023 02:32:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGAAlp3Ki/N/Gva2w04VtjsjXxZHhX0FlbSLCxVy9lSD56Tw35TUwfz0tDdhWaaXDQTEsaj X-Received: by 2002:a05:6214:3bc4:b0:65c:fd5b:d74e with SMTP id ng4-20020a0562143bc400b0065cfd5bd74emr17714064qvb.26.1696930373035; Tue, 10 Oct 2023 02:32:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930373; cv=none; d=google.com; s=arc-20160816; b=k3kqXBg0ffJq35/vDBruMUt4fekxDk/SCDRp/lqggV8KwrFlOeYw5PQm2/9nKAwKvc wRNWx+X5l2Bcd+c3NjlWpIn97EZDBzHhVL1PwQsnAS+C5AA2XI+8yqejHxKYO8a9ToRt AK2wgcFdmqDuOWMvSDLDZzGTv74csKM3aybIR05Ovuxt1wXWdhMtLFagMwL5Jtbajj75 0oIYlyMhuS0KfdIIHBq7qeHJBY0bAMyVJA1LtS5uQ/KdZkUwacUGRDt3kSRXgsnf12iP z6Ajlc8XZRYshTr57DD2y1oeptSFReEdHBhZENT6ox15Xft4cg6ZAduM9JneKvRunlqr byWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=igxlAzxucraozvyYxr1AoU5+SPegRZLZXUAG6vlLMuM=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=sUHADf1NS31/RA2sEc3+tOgh508bBe2+Zvry8LM8EsIWe7YsZFIw1UWAKwiDGBhZ9m V70qrMpeMUOt7xof2vwj5KHHf2p6oyLNF8ihBoMbjRddI5XmjW+j2LJ0ONJG283uL718 HEL0vKtJ6eMYNg3iUnloNG2MlVBtdcGsp9obL5hjBT7ZzCMYGSZG3Nf7XsrrgocBvLa8 SgsCj8up4ZzGWw5Eo3q4nJTeuS7lB4StksHH4qW/knEYKb6O1AS9O7/lKNRF4O8BJCNB BT34LAXD7jmmh7pV8a4uQlN83IpK28bXdtalENz+Tm2C9lVzmzTgrV5EPjuuHF0L2rWF bMxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ugshjq8+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id ev5-20020a056402540500b0053b67aba57bsm4579372edb.17.2023.10.10.02.31.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:31:16 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 16/18] target/i386: Make X86_CPU common to new I386_CPU / X86_64_CPU types Date: Tue, 10 Oct 2023 11:28:58 +0200 Message-ID: <20231010092901.99189-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philmd@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu-qom.h" can not use any target specific definitions. Currently "target/i386/cpu-qom.h" defines TYPE_X86_CPU depending on the i386/x86_64 build type. This doesn't scale in a heterogeneous context where we need to access both types concurrently. In order to do that, introduce the new I386_CPU / X86_64_CPU types, both inheriting a common TYPE_X86_CPU base type. Keep the current "base" and "max" CPU types as 32 or 64-bit, depending on the binary built. Adapt the cpu-plug-test, since the 'base' architecture is now common to both 32/64-bit x86 targets. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson --- target/i386/cpu-qom.h | 16 +++++++++------- target/i386/cpu.h | 3 +++ target/i386/cpu.c | 20 ++++++++++++++++++-- tests/qtest/cpu-plug-test.c | 2 +- 4 files changed, 31 insertions(+), 10 deletions(-) diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index 78207c0a7c..81f40bf91e 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU x86 CPU + * QEMU x86 CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -24,13 +24,15 @@ #include "qemu/notify.h" #include "qom/object.h" -#ifdef TARGET_X86_64 -#define TYPE_X86_CPU "x86_64-cpu" -#else -#define TYPE_X86_CPU "i386-cpu" -#endif +#define TYPE_X86_CPU "x86-cpu" +#define TYPE_I386_CPU "i386-cpu" +#define TYPE_X86_64_CPU "x86_64-cpu" -OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU) +OBJECT_DECLARE_CPU_TYPE(I386CPU, X86CPUClass, I386_CPU) +OBJECT_DECLARE_CPU_TYPE(X86_64CPU, X86CPUClass, X86_64_CPU) + +#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU +#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7c976971c7..5deb39a380 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -28,6 +28,9 @@ #include "qemu/cpu-float.h" #include "qemu/timer.h" +/* Abstract QOM X86 CPU, not exposed to other targets */ +OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU) + #define XEN_NR_VIRQS 24 /* The x86 has a strong memory model with some store-after-load re-ordering */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8f1fd5f304..1b1dae92c6 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8033,12 +8033,28 @@ static const TypeInfo x86_cpu_types[] = { .class_size = sizeof(X86CPUClass), .class_init = x86_cpu_common_class_init, }, { - .name = X86_CPU_TYPE_NAME("base"), + .name = TYPE_I386_CPU, .parent = TYPE_X86_CPU, + .abstract = true, + }, { + .name = TYPE_X86_64_CPU, + .parent = TYPE_X86_CPU, + .abstract = true, + }, { + .name = X86_CPU_TYPE_NAME("base"), +#ifdef TARGET_X86_64 + .parent = TYPE_X86_64_CPU, +#else + .parent = TYPE_I386_CPU, +#endif .class_init = x86_cpu_base_class_init, }, { .name = X86_CPU_TYPE_NAME("max"), - .parent = TYPE_X86_CPU, +#ifdef TARGET_X86_64 + .parent = TYPE_X86_64_CPU, +#else + .parent = TYPE_I386_CPU, +#endif .instance_init = max_x86_cpu_initfn, .class_init = max_x86_cpu_class_init, } diff --git a/tests/qtest/cpu-plug-test.c b/tests/qtest/cpu-plug-test.c index 7f5dd5f85a..97316d131f 100644 --- a/tests/qtest/cpu-plug-test.c +++ b/tests/qtest/cpu-plug-test.c @@ -90,7 +90,7 @@ static void add_pc_test_case(const char *mname) data->machine = g_strdup(mname); data->cpu_model = "Haswell"; /* 1.3+ theoretically */ data->device_model = g_strdup_printf("%s-%s-cpu", data->cpu_model, - qtest_get_arch()); + qtest_get_base_arch()); data->sockets = 1; data->cores = 3; data->threads = 2; From patchwork Tue Oct 10 09:28:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731438 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641503wrw; Tue, 10 Oct 2023 02:32:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IENdF4SMwtlFJ0pLIgo7WGVdyUn0ZQ67IpLxVS0clWWC7HApjgvkEJKJo7HvELvGE+hTBWm X-Received: by 2002:a05:622a:1749:b0:418:1a99:3918 with SMTP id l9-20020a05622a174900b004181a993918mr17980879qtk.6.1696930376165; Tue, 10 Oct 2023 02:32:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930376; cv=none; d=google.com; s=arc-20160816; b=ohxY/1YDNHcgsyruacnDehCVvgpGE1dl/yDTzkh/kpomaY+Zh81Fvlo0jh2rBwIpSh ICeHuCfS7N/j2gmYNjgzOanK9XhKtG05nYOPmeM9KITOosLWfSFX3rhxpNzAhjf3Q6zx Y8JjTaLw0hY/0DsvbXjiOWTt9oI0p+ubLco2S/faLj0Ka1WJfXA3IWPfz9J9YUg2Eccf hUlmwgLSNkZVr5QbCldd/wVN0oFgtKK5Q6eGdK8sjoV3anK4xsNTJBa1oIkUpaLE07cr 9Xr/nsJj7CwImNE+qvJPcjlU8jD38oNjteaNXRaj9hFCTgvVzyi8n9v7w24kmuFxPOkr exzQ== ARC-Message-Signature: i=1; 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id fi10-20020a170906da0a00b009ad8796a6aesm8106883ejb.56.2023.10.10.02.31.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:31:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 17/18] target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types Date: Tue, 10 Oct 2023 11:28:59 +0200 Message-ID: <20231010092901.99189-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu-qom.h" can not use any target specific definitions. Currently "target/mips/cpu-qom.h" defines TYPE_MIPS_CPU depending on the mips(32)/mips64 build type. This doesn't scale in a heterogeneous context where we need to access both types concurrently. In order to do that, introduce the new MIPS32_CPU / MIPS64_CPU types, both inheriting a common TYPE_MIPS_CPU base type. Keep the current CPU types registered in mips_register_cpudef_type() as 32 or 64-bit, but instead of depending on the binary built being targeting 32/64-bit, check whether the CPU is 64-bit by looking at the CPU_MIPS64 bit. Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu-qom.h | 13 ++++++------- target/mips/cpu.h | 3 +++ target/mips/cpu.c | 11 ++++++++++- 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 9c98ca1956..1a71509b5e 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -1,5 +1,5 @@ /* - * QEMU MIPS CPU + * QEMU MIPS CPU QOM header (target agnostic) * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -23,13 +23,12 @@ #include "hw/core/cpu.h" #include "qom/object.h" -#ifdef TARGET_MIPS64 -#define TYPE_MIPS_CPU "mips64-cpu" -#else -#define TYPE_MIPS_CPU "mips-cpu" -#endif +#define TYPE_MIPS_CPU "mips-cpu" +#define TYPE_MIPS32_CPU "mips32-cpu" +#define TYPE_MIPS64_CPU "mips64-cpu" -OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) +OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU) +OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU) #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 6b026e6bcf..3b6d0a7a8a 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -10,6 +10,9 @@ #include "hw/clock.h" #include "mips-defs.h" +/* Abstract QOM MIPS CPU, not exposed to other targets */ +OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) + #define TCG_GUEST_DEFAULT_MO (0) typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 83ee54f766..f43300dd5e 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -605,6 +605,14 @@ static const TypeInfo mips_cpu_types[] = { .abstract = true, .class_size = sizeof(MIPSCPUClass), .class_init = mips_cpu_class_init, + }, { + .name = TYPE_MIPS32_CPU, + .parent = TYPE_MIPS_CPU, + .abstract = true, + }, { + .name = TYPE_MIPS64_CPU, + .parent = TYPE_MIPS_CPU, + .abstract = true, } }; @@ -621,7 +629,8 @@ static void mips_register_cpudef_type(const struct mips_def_t *def) char *typename = mips_cpu_type_name(def->name); TypeInfo ti = { .name = typename, - .parent = TYPE_MIPS_CPU, + .parent = def->insn_flags & CPU_MIPS64 + ? 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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id e5-20020a17090681c500b00993a37aebc5sm8090599ejx.50.2023.10.10.02.31.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:31:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 18/18] target/sparc: Make SPARC_CPU common to new SPARC32_CPU/SPARC64_CPU types Date: Tue, 10 Oct 2023 11:29:00 +0200 Message-ID: <20231010092901.99189-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu-qom.h" can not use any target specific definitions. Currently "target/sparc/cpu-qom.h" defines TYPE_SPARC_CPU depending on the sparc(32)/sparc64 build type. This doesn't scale in a heterogeneous context where we need to access both types concurrently. In order to do that, introduce the new SPARC32_CPU / SPARC64_CPU types, both inheriting a common TYPE_SPARC_CPU base type. Keep the current CPU types registered in sparc_register_cpudef_type() as 32 or 64-bit, depending on the binary built. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland --- target/sparc/cpu-qom.h | 9 ++++----- target/sparc/cpu.h | 3 +++ target/sparc/cpu.c | 12 +++++++++++- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index 86b24a254a..d08fbd4ddc 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -23,13 +23,12 @@ #include "hw/core/cpu.h" #include "qom/object.h" -#ifdef TARGET_SPARC64 -#define TYPE_SPARC_CPU "sparc64-cpu" -#else #define TYPE_SPARC_CPU "sparc-cpu" -#endif +#define TYPE_SPARC32_CPU "sparc32-cpu" +#define TYPE_SPARC64_CPU "sparc64-cpu" -OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) +OBJECT_DECLARE_CPU_TYPE(SPARC32CPU, SPARCCPUClass, SPARC32_CPU) +OBJECT_DECLARE_CPU_TYPE(SPARC64CPU, SPARCCPUClass, SPARC64_CPU) #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 924e83b9ce..0f94e5a442 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -12,6 +12,9 @@ #define TARGET_DPREGS 32 #endif +/* Abstract QOM SPARC CPU, not exposed to other targets */ +OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) + /*#define EXCP_INTERRUPT 0x100*/ /* Windowed register indexes. */ diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 1e66413e94..7d060ba488 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -934,6 +934,12 @@ static const TypeInfo sparc_cpu_types[] = { .abstract = true, .class_size = sizeof(SPARCCPUClass), .class_init = sparc_cpu_class_init, + }, { + .name = TYPE_SPARC32_CPU, + .parent = TYPE_SPARC_CPU, + }, { + .name = TYPE_SPARC64_CPU, + .parent = TYPE_SPARC_CPU, } }; @@ -950,7 +956,11 @@ static void sparc_register_cpudef_type(const struct sparc_def_t *def) char *typename = sparc_cpu_type_name(def->name); TypeInfo ti = { .name = typename, - .parent = TYPE_SPARC_CPU, +#ifdef TARGET_SPARC64 + .parent = TYPE_SPARC64_CPU, +#else + .parent = TYPE_SPARC32_CPU, +#endif .class_init = sparc_cpu_cpudef_class_init, .class_data = (void *)def, };