From patchwork Mon Oct 9 02:49:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li \(Jassmine\)" X-Patchwork-Id: 731272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70DB5E95A8F for ; Mon, 9 Oct 2023 02:50:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233425AbjJICuE (ORCPT ); Sun, 8 Oct 2023 22:50:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231542AbjJICuD (ORCPT ); Sun, 8 Oct 2023 22:50:03 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2064.outbound.protection.outlook.com [40.107.220.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1207BAC; Sun, 8 Oct 2023 19:50:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Et0oDnMQy7rmgaLvZgrSHTXGUNwJlV8fb1ZfYO6FnHN5Fp/t8Zk9bYCUDVt3vY4qZQkTvco6oBJixq+iDygggAnCS9QFvTu0qPGTapsIMZePQ2DNXaoOxls98EzfQ78K1GDbTjZlDw8sjWXZRTJNBygoIEGDI3AijJJBZx8QEYp6R/LVGxYzs2TgfJ4OO3sPWxMQ9c8i8zUmrACSlFwAMOn/8f3DyITF55PFhE/rbH/ZVnQSHAmi5RuzsIAirS7x7KMQ/lPWXik5IMZ9I12tP1KUQ2IkYP0ArLQpu+P2QcU4Kj+es2LRgvagArwD6m51k06Y9Brz1mLiQh95EKywiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hjcQ49bg8CAFre4NUkzFDvQ8GWwZ8FmEd7dO3NaTlE8=; b=PeW98c//99W7Zx6ZaFzBFKRKSUWxfQSQiIMY4abmK/+ZaRcAIQLz7ec26BUgt/lbTrG6oXTuxTTSqY7tv/weEZqpuzKeO1r/mpbaLHcrLvzktaV+hfuDZ+6WKIleeLhzdm2Vq+9VUI5lG+fMqBpos+dd5ocK2fL8cWHtBRGi5pwdgrTyJ/NenQDQ2VHj/vqJTBseyUe+Vh51nTfOTQKInR6lKrxjrlLDSdpeqlP6Pvxagvpo5eJYWMYKKXES7v39okeFpqNNNzgCnKSLBxw7UesfquocrKBkv39caVlLW8vfsWLB55dG5Hh5IVfjuBHz9dlu3wCW2ENGekkdLXKMpQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hjcQ49bg8CAFre4NUkzFDvQ8GWwZ8FmEd7dO3NaTlE8=; b=ld29TM/q6oLxheWCOj2X4t87Zwv1dmwlK+2++j0TvQDAOWhisxPIG994s+sNo85OkWkAEhivAqvF2c1KmPUIsGyhWtFEMHXn7toyD+eEH6+k+8G3A9mTg2yqYfCzFwXaleBjph8NKT1ucexh94VB5yTj39qH0aS0DlaLaXeJAT4= Received: from PH0PR07CA0099.namprd07.prod.outlook.com (2603:10b6:510:4::14) by SN7PR12MB8003.namprd12.prod.outlook.com (2603:10b6:806:32a::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.33; Mon, 9 Oct 2023 02:49:58 +0000 Received: from SN1PEPF0002529D.namprd05.prod.outlook.com (2603:10b6:510:4:cafe::aa) by PH0PR07CA0099.outlook.office365.com (2603:10b6:510:4::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.36 via Frontend Transport; Mon, 9 Oct 2023 02:49:58 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF0002529D.mail.protection.outlook.com (10.167.242.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.21 via Frontend Transport; Mon, 9 Oct 2023 02:49:57 +0000 Received: from jasmine-meng.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Sun, 8 Oct 2023 21:49:53 -0500 From: Meng Li To: "Rafael J . Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V8 1/7] x86: Drop CPU_SUP_INTEL from SCHED_MC_PRIO for the expansion. Date: Mon, 9 Oct 2023 10:49:26 +0800 Message-ID: <20231009024932.2563622-2-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231009024932.2563622-1-li.meng@amd.com> References: <20231009024932.2563622-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002529D:EE_|SN7PR12MB8003:EE_ X-MS-Office365-Filtering-Correlation-Id: b02c98c0-9344-4a96-6961-08dbc8726ccc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: kchJsCtkhH8gnux0MqD+aofDU57h+pJq94qpca4IKHGu1D3bbw3c9LQdRH660AyVpe9sfWZcyiNo7/Xs+MuLHuHTY476LMiVENSpYEpxNXmgu5VEvOGYHiKGJ6velPPY3Ba1cQS8Qm1Sj0N17iF5rsbQYA1vp28hWKze8nh3TRgEdufLlE28klVQR5Eupc9qgrGmN4Sczf/k7lQLHrSJk4j6kymeas7+/dfAvxB8ZJ9z0hgVgAHbju3C5seinZXxsl78dcWo3FN6Qk1oLNHV2/lxJ2KUfRXaChTY9BViqjKSxF01tolzwsFZcW/Ns6latOm9wp0/OcNdRR2Cs4EZayNVbGPLpt9N0d5/3wK6a7e30aPpBv9SHz7gLbRPvlCx7kOnsj5HWWAblvPnslui997rV1OCRAJ/k1ADerBRfIhIjgU7vJ4jnbcWZbUHY9LH5DSsA34jp7cwo2ewddvFmfkROU+AhbK+pIbvbd/BZxsTvMwE5hrTOMUtg16ghCSVdNRCoenC2Hd0o7EeQ6vbJ+aRUCzyrFqGdLHSgTwtiy5cHD1VVaIhiax4XZX5EzUxRvvVITq2Ce5wA7Gbwm45OPorhw61mMZjB1e9VTFT1YNj3nYoesxpFelY94XxNENCe3UrN/Hsip9zHUsHMlX8UxuQ+Lxva3dv0hG7d7DNizMNFjye35pXgvZiDbqUalPsT5OItiLOF0CUCQd3JIDo1KugVBsLmOhAf6qK0ZpICCZOcfGRGOGzqE8TsvCyNSDJePbRCesFK55PGdN6KiJp8g== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(376002)(396003)(346002)(136003)(39860400002)(230922051799003)(186009)(82310400011)(451199024)(1800799009)(64100799003)(40470700004)(36840700001)(46966006)(7696005)(40460700003)(70206006)(54906003)(6636002)(478600001)(426003)(36860700001)(356005)(82740400003)(47076005)(70586007)(83380400001)(36756003)(8676002)(40480700001)(16526019)(110136005)(6666004)(2616005)(1076003)(81166007)(336012)(86362001)(4744005)(8936002)(4326008)(2906002)(316002)(5660300002)(26005)(41300700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 02:49:57.9594 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b02c98c0-9344-4a96-6961-08dbc8726ccc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8003 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org amd-pstate driver also uses SCHED_MC_PRIO, so decouple the requirement of CPU_SUP_INTEL from the dependencies to allow compilation in kernels without Intel CPU support. Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li --- arch/x86/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 66bfabae8814..a2e163acf623 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1054,8 +1054,9 @@ config SCHED_MC config SCHED_MC_PRIO bool "CPU core priorities scheduler support" - depends on SCHED_MC && CPU_SUP_INTEL - select X86_INTEL_PSTATE + depends on SCHED_MC + select X86_INTEL_PSTATE if CPU_SUP_INTEL + select X86_AMD_PSTATE if CPU_SUP_AMD && ACPI select CPU_FREQ default y help From patchwork Mon Oct 9 02:49:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li \(Jassmine\)" X-Patchwork-Id: 731271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60B25E95A8E for ; Mon, 9 Oct 2023 02:50:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345027AbjJICus (ORCPT ); Sun, 8 Oct 2023 22:50:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34958 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231542AbjJICur (ORCPT ); Sun, 8 Oct 2023 22:50:47 -0400 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2046.outbound.protection.outlook.com [40.107.96.46]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 877D0A6; Sun, 8 Oct 2023 19:50:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=f1YpHNBvFHmm/t/eZgXUNG6JvtVYJKKhf2yX9sco6xvMSjFnedBjAwOvEJxSoqsSloNH61vnyXlt/XQ7H7tcmZvweZhILTwdFwLqsEheugf1lNqEkw1r7vdjlCtkkba5JwFpMKHjOVZnSG34pwJUTkxFVoYgeb9lTj0kB7XmhzVl1cZ7ZWAR1PAIrre1Gp79wxNAuW3IIZELdJYrj0IJROP9+qM9BqXQrGuyVJ6FNjAn3joC8/rzpkcTSFfr6ilQtxUk0jjemofUQD8P2RZVwQ9yeXgA0j5W+NIJUoQtpFeDS/6CqcggrR/6As2NOjnvILq70488kX8W27yOrqP8Eg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RJYvjMJKHJ8ceESTBOKOhrQihm4T6VwTm0HICO7uIBk=; b=BG57K2ABVsHWj4nTnBVcRQk+KsiziC7c06B3xW9ksJS6ddJSZQfcAnHhjStzzF9j5B1CWTKimEff6k0aLTFiS/O9tJgaxKzjpNwsVsvZdN2H7beNQZmTCplQ+sWh4fink5gTdeSFE9ndD6nbMl+n8CWc7fLEFcVea/oyIUS2sSabiGMUn1rpTDGZ7lTTYk62lSwalpGyUuVLhkaSOktK0HUYyP+UEsvRqWsxgwX1taOid489UkO9ucWxEgT1Wk3P4fB7HGtkKmirCReSiSnkH+NW9lGSAH+61AmvZCXEvr5gsgJYmSbU5/xNWZdgQIFm6j5sCTt5WNNj0+Lr42i8Aw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RJYvjMJKHJ8ceESTBOKOhrQihm4T6VwTm0HICO7uIBk=; b=KexvDRW0qtII5RSsTL34r2feoYAEoh1oPb0fwVXPKmBUwu6AZVRr1OudCE3XniP2XGCG/tRIfltj8J977n/IMQ9BxD79u2ehOmfK1Vbr1IlpiOaDlha6gNYd38Shdqn3oQrpZ2IJ87oLDNmhPuPXs1CrelKzOLgwzzH0koTzE5I= Received: from SA9PR11CA0018.namprd11.prod.outlook.com (2603:10b6:806:6e::23) by SA1PR12MB6774.namprd12.prod.outlook.com (2603:10b6:806:259::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.41; Mon, 9 Oct 2023 02:50:42 +0000 Received: from SA2PEPF00001509.namprd04.prod.outlook.com (2603:10b6:806:6e:cafe::1b) by SA9PR11CA0018.outlook.office365.com (2603:10b6:806:6e::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.36 via Frontend Transport; Mon, 9 Oct 2023 02:50:42 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00001509.mail.protection.outlook.com (10.167.242.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6838.14 via Frontend Transport; Mon, 9 Oct 2023 02:50:42 +0000 Received: from jasmine-meng.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Sun, 8 Oct 2023 21:50:02 -0500 From: Meng Li To: "Rafael J . Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V8 3/7] cpufreq: amd-pstate: Enable amd-pstate preferred core supporting. Date: Mon, 9 Oct 2023 10:49:28 +0800 Message-ID: <20231009024932.2563622-4-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231009024932.2563622-1-li.meng@amd.com> References: <20231009024932.2563622-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001509:EE_|SA1PR12MB6774:EE_ X-MS-Office365-Filtering-Correlation-Id: 4bcd9b09-bb8a-4a7e-d833-08dbc8728739 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VUI4rnqkE+7iwRr2Vm1txAoesp5+OcuYs9twpLUUjpVJHW4pnRl/XaAS18GEY05wBl55okzRR2s9WV0eD0wRtzwKjX2TtQ5P1Z0ba0u+O0UtVurhnlU9T2e+ti0m5oO64LnYuw5ykwumy+tGr6HSVa8RSmLfBLTrp7EBBvaXYzzHrqnn7EYodCbDkIFt852suJ/bxqSo3GpqkV/bYrzAUl3qhcdqMqjiU2uARYBUgtTx02Q6iJEqB0WIXmFwTMv04xA18ibYTVgGtYq17n1qlE9cFJqyHgLaAzStSHwVjTC9FnzIKw6ILkTyBfs1crtbvVA4J1BeDtXriN+IBILgs/R1YAMTmHHVrpbvhBASFRUsU2TdfLV9R+KvzVa3jIXuB6AowlvJfLISDuWlU987EqroiVuCpfDG4EsP+rRs2/2YBjMSlBLsq1H34oVLCtvcKRG0PNr25AfYk57i04rNJBKef8ZYN0ucZvbwwuQEz1bSt93OZFbuVhAki24NgLTQ8am+Mp4gQKEKbWxrR9f+KQdJc43qnPJKrmjphev6IQEAaj5nt+MAhV3cAVlu4QMa3dOavv/mpJT23q2/zuL/oLsNtsmceNHAx4OWsz/Zyrot5lx8NyhehAHCeN4xofdkQr/BT0vQtLEpFVuTpqpZaDfS6LTnzG1gTVVSAenT+updss9N1VjoscUIzwvvkSe7bfwY4rS0nfLfibdsWt+dZxH4pp5G/AtFpuf681rGkF7SysYMdmnd4Oz8coTGE1F1yBHyLm9rQ6qqAZqovwmOgw== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(376002)(136003)(346002)(39860400002)(396003)(230922051799003)(1800799009)(451199024)(186009)(64100799003)(82310400011)(36840700001)(40470700004)(46966006)(70586007)(54906003)(6636002)(70206006)(316002)(30864003)(41300700001)(110136005)(336012)(426003)(16526019)(1076003)(2616005)(26005)(47076005)(2906002)(8936002)(8676002)(6666004)(7696005)(4326008)(5660300002)(83380400001)(356005)(478600001)(36860700001)(81166007)(36756003)(86362001)(82740400003)(40460700003)(40480700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 02:50:42.3130 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4bcd9b09-bb8a-4a7e-d833-08dbc8728739 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001509.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6774 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org amd-pstate driver utilizes the functions and data structures provided by the ITMT architecture to enable the scheduler to favor scheduling on cores which can be get a higher frequency with lower voltage. We call it amd-pstate preferrred core. Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. amd-pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority. The initial core rankings are set up by amd-pstate when the system boots. Add a variable hw_prefcore in cpudata structure. It will check if the processor and power firmware support preferred core feature. Add one new early parameter `disable` to allow user to disable the preferred core. Only when hardware supports preferred core and user set `enabled` in early parameter, amd pstate driver supports preferred core featue. Reviewed-by: Mario Limonciello Co-developed-by: Perry Yuan Signed-off-by: Perry Yuan Signed-off-by: Meng Li --- drivers/cpufreq/amd-pstate.c | 152 +++++++++++++++++++++++++++++++---- include/linux/amd-pstate.h | 4 + 2 files changed, 140 insertions(+), 16 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..6ac8939fce5a 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,8 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 +#define AMD_PSTATE_MAX_CPPC_PERF 255 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -64,6 +67,7 @@ static struct cpufreq_driver amd_pstate_driver; static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; +static bool amd_pstate_prefcore = true; /* * AMD Energy Preference Performance (EPP) @@ -290,23 +294,21 @@ static inline int amd_pstate_enable(bool enable) static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; - u32 highest_perf; int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; - /* - * TODO: Introduce AMD specific power feature. - * - * CPPC entry doesn't indicate the highest performance in some ASICs. + /* For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as + * the default max perf. */ - highest_perf = amd_get_highest_perf(); - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (cpudata->hw_prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +320,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) static int cppc_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; - u32 highest_perf; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - highest_perf = amd_get_highest_perf(); - if (highest_perf > cppc_perf.highest_perf) - highest_perf = cppc_perf.highest_perf; - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (cpudata->hw_prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); WRITE_ONCE(cpudata->lowest_nonlinear_perf, @@ -676,6 +676,90 @@ static void amd_perf_ctl_reset(unsigned int cpu) wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } +/* + * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks + * due to locking, so queue the work for later. + */ +static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); + +/* + * Get the highest performance register value. + * @cpu: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) +{ + int ret; + u64 cppc_highest_perf; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 cap1; + + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + } else { + ret = cppc_get_highest_perf(cpu, &cppc_highest_perf); + *highest_perf = (u32)(cppc_highest_perf & 0xFFFF); + } + + return (ret); +} + +static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) +{ + int ret; + u32 highest_perf; + static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; + + ret = amd_pstate_get_highest_perf(cpudata->cpu, &highest_perf); + if (ret) + return; + + cpudata->hw_prefcore = true; + /* check if CPPC preferred core feature is enabled*/ + if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) { + pr_debug("AMD CPPC preferred core is unsupported!\n"); + cpudata->hw_prefcore = false; + return; + } + + if (!amd_pstate_prefcore) + return; + + /* + * The priorities can be set regardless of whether or not + * sched_set_itmt_support(true) has been called and it is valid to + * update them at any time after it has been called. + */ + sched_set_itmt_core_prio(highest_perf, cpudata->cpu); + + if (max_highest_perf <= min_highest_perf) { + if (highest_perf > max_highest_perf) + max_highest_perf = highest_perf; + + if (highest_perf < min_highest_perf) + min_highest_perf = highest_perf; + + if (max_highest_perf > min_highest_perf) { + /* + * This code can be run during CPU online under the + * CPU hotplug locks, so sched_set_itmt_support() + * cannot be called from here. Queue up a work item + * to invoke it. + */ + schedule_work(&sched_prefcore_work); + } + } +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -697,6 +781,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; + amd_pstate_init_prefcore(cpudata); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -845,6 +931,17 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sysfs_emit(buf, "%u\n", perf); } +static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy, + char *buf) +{ + bool hw_prefcore; + struct amd_cpudata *cpudata = policy->driver_data; + + hw_prefcore = READ_ONCE(cpudata->hw_prefcore); + + return sysfs_emit(buf, "%s\n", hw_prefcore ? "supported" : "unsupported"); +} + static ssize_t show_energy_performance_available_preferences( struct cpufreq_policy *policy, char *buf) { @@ -1037,18 +1134,27 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, return ret < 0 ? ret : count; } +static ssize_t prefcore_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%s\n", amd_pstate_prefcore ? "enabled" : "disabled"); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); +static DEVICE_ATTR_RO(prefcore); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_hw_prefcore, NULL, }; @@ -1056,6 +1162,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_hw_prefcore, &energy_performance_preference, &energy_performance_available_preferences, NULL, @@ -1063,6 +1170,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, + &dev_attr_prefcore.attr, NULL }; @@ -1114,6 +1222,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; cpudata->epp_policy = 0; + amd_pstate_init_prefcore(cpudata); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1527,7 +1637,17 @@ static int __init amd_pstate_param(char *str) return amd_pstate_set_driver(mode_idx); } + +static int __init amd_prefcore_param(char *str) +{ + if (!strcmp(str, "disable")) + amd_pstate_prefcore = false; + + return 0; +} + early_param("amd_pstate", amd_pstate_param); +early_param("amd_prefcore", amd_prefcore_param); MODULE_AUTHOR("Huang Rui "); MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 446394f84606..87e140e9e6db 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -52,6 +52,9 @@ struct amd_aperf_mperf { * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value * @boost_supported: check whether the Processor or SBIOS supports boost mode + * @hw_prefcore: check whether HW supports preferred core featue. + * Only when hw_prefcore and early prefcore param are true, + * AMD P-State driver supports preferred core featue. * @epp_policy: Last saved policy used to set energy-performance preference * @epp_cached: Cached CPPC energy-performance preference value * @policy: Cpufreq policy value @@ -81,6 +84,7 @@ struct amd_cpudata { u64 freq; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li , Wyes Karny Subject: [PATCH V8 5/7] cpufreq: amd-pstate: Update amd-pstate preferred core ranking dynamically Date: Mon, 9 Oct 2023 10:49:30 +0800 Message-ID: <20231009024932.2563622-6-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231009024932.2563622-1-li.meng@amd.com> References: <20231009024932.2563622-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4D:EE_|MW4PR12MB5666:EE_ X-MS-Office365-Filtering-Correlation-Id: 8aabc7bd-f99d-4aef-96a6-08dbc8728bde X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: A52HU1fduQjBgxTPKCVRceY9qMxYINvoe6OAlYcieKo9GGFm/jUPez16mrA2kXO/2c+UbRzgeWURVCQsHXsprGdjHm1CzVdrz9eBCYctKs1K0WNELMKO08a09KWQLj6QviDrG9GEqhU1jPbNd5MVP1II/kBXeS6aCL7UPRhRnxajvp4aB3zmiBRPhmgUF9odmBrz3qp3tO3/fjg6S9zwMV68MfFlKUwH4RnGkKdOu4zCgXpV3CplUtFXS+v2rhTMdT0uNKKtVt14AI/ZmvtdclG3SV6VE8V2bWAwQYrWKAiztPrb6mF8weCi1Ab7Aw40JAUa2ghCieOsr48QiaH0g5Ig5vF5rAONQhljDXP7MkA83jeGbVlzswTeEeKrMcpmVib4IkqZr1JhIW2njr3KPdHoxQpC8RL4rB0V1ID8FYh2TQ/lOkuVrD9CkAxBtVn9CtLhKVIVco7cSBQ9HWGNHyqZOo1qVHCPaBwyEiz61AE+d16ZzfEw+rvoNqI37kLjvksSxYC/MKk2u6dbbqdnKrFYm14+7Z9/hJnatsRyYhrOvrYwZZwpL2L5dj4H3iW2sEcOuSLhNIIG3i699Cne+SjCLvo41A8dBAtw3IqOMBmzMioseG+bYY04kCuQmrY3wVqEGUcvYv94DQGXnw7FCM6GkeaDHrbnB0AIjSjzBdLh7GsY2US9cmylY7hMide+WScPeBxsJhBI31Z2pMM/VcY21qRiwjV0I/GgejOoZYl2MhtpDdcPuM7+tXR0wwxDHtMDelfeJROjn8nJ2pxzvQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(136003)(396003)(346002)(376002)(230922051799003)(451199024)(82310400011)(64100799003)(186009)(1800799009)(46966006)(40470700004)(36840700001)(40480700001)(66899024)(40460700003)(83380400001)(1076003)(2616005)(336012)(426003)(26005)(16526019)(47076005)(36860700001)(54906003)(70206006)(70586007)(110136005)(316002)(6636002)(8936002)(8676002)(4326008)(5660300002)(41300700001)(7696005)(6666004)(2906002)(15650500001)(82740400003)(478600001)(36756003)(356005)(81166007)(86362001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 02:50:50.1035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8aabc7bd-f99d-4aef-96a6-08dbc8728bde X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5666 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Preferred core rankings can be changed dynamically by the platform based on the workload and platform conditions and accounting for thermals and aging. When this occurs, cpu priority need to be set. Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Reviewed-by: Huang Rui Signed-off-by: Meng Li --- drivers/cpufreq/amd-pstate.c | 34 ++++++++++++++++++++++++++++++++-- include/linux/amd-pstate.h | 6 ++++++ 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6ac8939fce5a..d3369247c6c9 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -313,6 +313,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); + WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1)); return 0; } @@ -334,6 +335,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->lowest_nonlinear_perf, cppc_perf.lowest_nonlinear_perf); WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); + WRITE_ONCE(cpudata->prefcore_ranking, cppc_perf.highest_perf); if (cppc_state == AMD_PSTATE_ACTIVE) return 0; @@ -540,7 +542,7 @@ static void amd_pstate_adjust_perf(unsigned int cpu, if (target_perf < capacity) des_perf = DIV_ROUND_UP(cap_perf * target_perf, capacity); - min_perf = READ_ONCE(cpudata->highest_perf); + min_perf = READ_ONCE(cpudata->lowest_perf); if (_min_perf < capacity) min_perf = DIV_ROUND_UP(cap_perf * _min_perf, capacity); @@ -760,6 +762,32 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) } } +static void amd_pstate_update_highest_perf(unsigned int cpu) +{ + struct cpufreq_policy *policy; + struct amd_cpudata *cpudata; + u32 prev_high = 0, cur_high = 0; + int ret; + + if ((!amd_pstate_prefcore) || (!cpudata->hw_prefcore)) + return; + + ret = amd_pstate_get_highest_perf(cpu, &cur_high); + if (ret) + return; + + policy = cpufreq_cpu_get(cpu); + cpudata = policy->driver_data; + prev_high = READ_ONCE(cpudata->prefcore_ranking); + + if (prev_high != cur_high) { + WRITE_ONCE(cpudata->prefcore_ranking, cur_high); + sched_set_itmt_core_prio(cur_high, cpu); + } + + cpufreq_cpu_put(policy); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -926,7 +954,7 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, u32 perf; struct amd_cpudata *cpudata = policy->driver_data; - perf = READ_ONCE(cpudata->highest_perf); + perf = READ_ONCE(cpudata->prefcore_ranking); return sysfs_emit(buf, "%u\n", perf); } @@ -1502,6 +1530,7 @@ static struct cpufreq_driver amd_pstate_driver = { .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, .set_boost = amd_pstate_set_boost, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate", .attr = amd_pstate_attr, }; @@ -1516,6 +1545,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .online = amd_pstate_epp_cpu_online, .suspend = amd_pstate_epp_suspend, .resume = amd_pstate_epp_resume, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 87e140e9e6db..426822612373 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -39,11 +39,16 @@ struct amd_aperf_mperf { * @cppc_req_cached: cached performance request hints * @highest_perf: the maximum performance an individual processor may reach, * assuming ideal conditions + * For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the fixed value as the highest_perf. * @nominal_perf: the maximum sustained performance level of the processor, * assuming ideal operating conditions * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power * savings are achieved * @lowest_perf: the absolute lowest performance level of the processor + * @prefcore_ranking: the preferred core ranking, the higher value indicates a higher + * priority. * @max_freq: the frequency that mapped to highest_perf * @min_freq: the frequency that mapped to lowest_perf * @nominal_freq: the frequency that mapped to nominal_perf @@ -73,6 +78,7 @@ struct amd_cpudata { u32 nominal_perf; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li , Wyes Karny Subject: [PATCH V8 7/7] Documentation: introduce amd-pstate preferrd core mode kernel command line options Date: Mon, 9 Oct 2023 10:49:32 +0800 Message-ID: <20231009024932.2563622-8-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231009024932.2563622-1-li.meng@amd.com> References: <20231009024932.2563622-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4E:EE_|CH3PR12MB8483:EE_ X-MS-Office365-Filtering-Correlation-Id: fb4bae77-f719-4c60-2102-08dbc8729148 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: dPs+KhFcmpizslPneYl4k62+j3RQm0cPBB9/t5cTRrWHRlTpwbOnq6aY91cXXsYAcKT0sHpF++zrrDuhs2FZnB2Ct6QG33SIIX2sWY7IQV3+XVVSXqHK015/O+2pmu77s+rqtcMIkVFHj3vSyrUN6gt8rJSOLky7242Xhcc7tUvbexI+jRxwFwDE7H86Y/6sQX2HxYZ4iJ7/GIBjU4QYA4W4ujIFdgvR4r27HPbxmDoHCEgvPGRdfQgkdSmPL0LMp+4k9ml8sUQ1G+PrKYn1beANMIh5yvK5hqeNYcSnaZcDQc2+SbSt1pIShmK+VBkDTf5/Q04I6/xufCYjSAWBBdda8djtibIWqHA+WfGs7g0sQ0UuS6IU/9nwFfDg5SdSlAcKbpQZZsPInT0+y1pcOgw4YSzUIHigR3bdF3IP2OGSdm0rorPY2eeL4+DPiSybVvcL7rSK3D0newKXe46cSTAjBmY81ZnS7v35rrxjsYtGlra+bTMRYhvIolhkLYUR+PnLn4LayCgtHKD4QIOydFckWwyjJJyJ/79ytCcnspnUAyqPCvw3Qt+ZrVOp+xFIN+GnLYwvHO5Rd/GfP2ZldW4XqyDvoKbWGEoa2mxQfJDdBtapTOGgFUaVMEt4GEr1OfbkIBXe6OmH37WnA6j0+orR76Uxq6Y6EoFLnusAA9hto3ofwHZq2c2V0QLiMGZuRYRS4vYU7qSpkt4YsG7/L4YlEU5RmLFgo7ThE4e8/TbFnZnRf+//YQrr+wUx4Slh23EhCn7yPHofBQTaRjhDFX0sTRBu+KZXYSJQABDk+cYepjrsz0z4oj0e6Kx9B9LJ X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(396003)(376002)(136003)(346002)(39860400002)(230922051799003)(82310400011)(451199024)(186009)(1800799009)(64100799003)(40470700004)(36840700001)(46966006)(336012)(1076003)(40460700003)(7696005)(478600001)(6666004)(26005)(86362001)(82740400003)(2906002)(356005)(16526019)(81166007)(36860700001)(316002)(110136005)(6636002)(83380400001)(2616005)(426003)(41300700001)(36756003)(8676002)(40480700001)(70586007)(70206006)(8936002)(47076005)(4326008)(5660300002)(54906003)(36900700001)(14943795004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2023 02:50:59.1838 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb4bae77-f719-4c60-2102-08dbc8729148 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8483 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org amd-pstate driver support enable/disable preferred core. Default enabled on platforms supporting amd-pstate preferred core. Disable amd-pstate preferred core with "amd_prefcore=disable" added to the kernel command line. Signed-off-by: Meng Li Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Reviewed-by: Huang Rui --- Documentation/admin-guide/kernel-parameters.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 0a1731a0f0ef..e35b795aa8aa 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -363,6 +363,11 @@ selects a performance level in this range and appropriate to the current workload. + amd_prefcore= + [X86] + disable + Disable amd-pstate preferred core. + amijoy.map= [HW,JOY] Amiga joystick support Map of devices attached to JOY0DAT and JOY1DAT Format: ,