From patchwork Mon Oct 9 09:37:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 731177 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4722D16421 for ; Mon, 9 Oct 2023 09:39:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="ytNFsULQ" Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ECBD94; Mon, 9 Oct 2023 02:39:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1696844389; x=1728380389; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IFHxvV76DQ6UmIeCUgXcZ1c22Kaa/5MKcYvW0mJV6W4=; b=ytNFsULQkAtxILLizPjB0iH8+1ZLeYWGnituqPePK+vObDUPPNnmx/Fo 1OoP9chQkrNd4nJBtHd0jxQ4ILF8G2KkaBL5G8Z2y4SIcN0eVnPJYlGYr 4GR/u9NLE1a6LFLT4oe8RyK7Ls2VtnE1tSZFqyGxssu5fFoLbS42w3qZh /TQbPRB8puYrOGYYmSPooy5BhvqjiN2EOs83bvEPQbT0cG/QO650yhU7u 6Xhh6VraQs0TQ+0nAATfOs9SWYShcSy1gBWXBZP3038JtK+DG5jr/wkGj m9HQVSYZGpsF4hbkUttX9H4JeMrXraUxCiRMKwQ+Q5mRr6cvGIFGj+cS0 w==; X-CSE-ConnectionGUID: ss/kXsifRKO4Oj8Q887AdA== X-CSE-MsgGUID: Npy1MPcYTa+Nx9vgamJKCQ== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="9216030" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Oct 2023 02:39:48 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 9 Oct 2023 02:39:47 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 9 Oct 2023 02:39:43 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , "Jernej Skrabec" , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , "Emil Renner Berthing" , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , , , , Subject: [PATCH v3 1/6] riscv: dts: microchip: convert isa detection to new properties Date: Mon, 9 Oct 2023 10:37:45 +0100 Message-ID: <20231009-rockfish-wistful-3e0106be968c@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231009-approve-verbalize-ce9324858e76@wendy> References: <20231009-approve-verbalize-ce9324858e76@wendy> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2237; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=IFHxvV76DQ6UmIeCUgXcZ1c22Kaa/5MKcYvW0mJV6W4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnKJ1/udH4lYKXuf7K3PXt9hU+nK5Ps4f+8GzyeMSVuuFD5 ePK6jlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExEyZaRYfZrtus/Es92XF/zJnGLa/ mU1NMNFeGn9/adOlukJx/bNJ2RYY1cNOfG6T/efnnT8dxvfnjXQmevbBnXI0mGN0yC7nt+4AAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Convert the PolarFire SoC devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 104504352e99..a6faf24f1dba 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -22,6 +22,9 @@ cpu0: cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; @@ -48,6 +51,9 @@ cpu1: cpu@1 { mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -76,6 +82,9 @@ cpu2: cpu@2 { mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -104,6 +113,9 @@ cpu3: cpu@3 { mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -132,6 +144,9 @@ cpu4: cpu@4 { mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; From patchwork Mon Oct 9 09:37:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 731626 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 285DBB669 for ; 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a=openpgp-sha256; l=4405; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=JeWUK0ufN5IjWUK8JaRe4S+wcrQNicrtckqH96ZSDM8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnKJ1+2XVrdyCb1IPr755MXis9tyH9tzsdUVzqlLbZzS8wU f9sLHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjIlzRGhgar4j2as46vONFQ0Faq1T BR/tmhtRI/bE88/TMputTGs46R4Y7GokdKzh0yFTc2X4ze9HPxsgnixcfn1H3Qn7OPdYtaExMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Convert the fu540 and fu740 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Reviewed-by: Samuel Holland Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++ arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 15 +++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi index 24bba83bec77..156330a9bbf3 100644 --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi @@ -30,6 +30,9 @@ cpu0: cpu@0 { i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -53,6 +56,9 @@ cpu1: cpu@1 { mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { @@ -77,6 +83,9 @@ cpu2: cpu@2 { mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { @@ -101,6 +110,9 @@ cpu3: cpu@3 { mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { @@ -125,6 +137,9 @@ cpu4: cpu@4 { mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index 5235fd1c9cb6..6150f3397bff 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -31,6 +31,9 @@ cpu0: cpu@0 { next-level-cache = <&ccache>; reg = <0x0>; riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -55,6 +58,9 @@ cpu1: cpu@1 { next-level-cache = <&ccache>; reg = <0x1>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; @@ -79,6 +85,9 @@ cpu2: cpu@2 { next-level-cache = <&ccache>; reg = <0x2>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; @@ -103,6 +112,9 @@ cpu3: cpu@3 { next-level-cache = <&ccache>; reg = <0x3>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; @@ -127,6 +139,9 @@ cpu4: cpu@4 { next-level-cache = <&ccache>; reg = <0x4>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; From patchwork Mon Oct 9 09:37:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 731625 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CBD21642B for ; Mon, 9 Oct 2023 09:44:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="T4FAYotp" Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C6A7C6; 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09 Oct 2023 02:40:04 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 9 Oct 2023 02:39:57 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 9 Oct 2023 02:39:52 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , "Jernej Skrabec" , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , "Emil Renner Berthing" , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , , , , Subject: [PATCH v3 3/6] riscv: dts: starfive: convert isa detection to new properties Date: Mon, 9 Oct 2023 10:37:47 +0100 Message-ID: <20231009-unloader-april-e613cf388354@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231009-approve-verbalize-ce9324858e76@wendy> References: <20231009-approve-verbalize-ce9324858e76@wendy> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3464; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=ZtQo0AOZyII3HHuuFcu57y2laopGel6BHtBnxFpkQGE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnKJ19Gmmcu9DRV5c/f9mdBn9mzNwKr+AXltulnM124mtn5 WC28o5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABMJaWVk2NKv/eHelw8y/q+8WD2qct fai2+YtGP1h/m6XSE2UfIaTxgZvouU8wXJz9q1PcLy9mKdv9nv1p3sPf+i9Yl1qGNH2/kMFgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Convert the jh7100 and jh7110 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 6 ++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 35ab54fb235f..e68cafe7545f 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -33,6 +33,9 @@ U74_0: cpu@0 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu0_intc: interrupt-controller { @@ -58,6 +61,9 @@ U74_1: cpu@1 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; cpu1_intc: interrupt-controller { diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 9f31dec57c0d..45213cdf50dc 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -28,6 +28,9 @@ S7_0: cpu@0 { i-cache-size = <16384>; next-level-cache = <&ccache>; riscv,isa = "rv64imac_zba_zbb"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr", + "zifencei", "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { @@ -54,6 +57,9 @@ U74_1: cpu@1 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -84,6 +90,9 @@ U74_2: cpu@2 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -114,6 +123,9 @@ U74_3: cpu@3 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; @@ -144,6 +156,9 @@ U74_4: cpu@4 { mmu-type = "riscv,sv39"; next-level-cache = <&ccache>; riscv,isa = "rv64imafdc_zba_zbb"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr", + "zicsr", "zifencei", "zihpm"; tlb-split; operating-points-v2 = <&cpu_opp>; clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; From patchwork Mon Oct 9 09:37:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 731624 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ED72168DA for ; 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For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley Acked-by: Geert Uytterhoeven --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index b0796015e36b..eb301d8eb2b0 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -24,6 +24,9 @@ cpu0: cpu@0 { reg = <0x0>; status = "okay"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; mmu-type = "riscv,sv39"; i-cache-size = <0x8000>; i-cache-line-size = <0x40>; From patchwork Mon Oct 9 09:37:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 731175 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 554EB1642B for ; Mon, 9 Oct 2023 09:44:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="tVMJtwta" Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85A0994; Mon, 9 Oct 2023 02:44:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1696844677; x=1728380677; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7kiFiWXf0X7YTKnlUryjTPWfXBjavhZEL7/N/C8FSjM=; b=tVMJtwtaoq89RZhvFrNaHMjrTwfNRvNH5zZAR2iBbEBimuPF3K8J+9Dl cqhtYukySKkYXkVKhBlFiYcBwd5a1/PH+/u1EEAogQIYhtRGn2uaeFqHs Apa+ouFTbRU4BQ9lPaRZ1+Q70TVXiCm6eR1maQEy8HczyYyuY1fHW6hms XAjxKoJkJt43deh0C/6sh9Nb8JoOxKSSZje8dMVIXcEzOvJWQP9jHsKlw eNyuTGTWuHRGgorhDYI2fNcrod1ac/GOCTo4ONf6k+PE5nXRurAJrG+Rn /8FJOhbt3fI7gn8DRuqLmar1lsxSZg84hkVw9FiiVxlRbpxLI+LF1s03c A==; X-CSE-ConnectionGUID: ExFLQ79KS3SJV7MWrGq2IQ== X-CSE-MsgGUID: my6VmZ1KS9WOwm6ckdPIdw== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="239927170" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Oct 2023 02:40:06 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 9 Oct 2023 02:40:06 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 9 Oct 2023 02:40:02 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , "Jernej Skrabec" , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , "Emil Renner Berthing" , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , , , , Subject: [PATCH v3 5/6] riscv: dts: allwinner: convert isa detection to new properties Date: Mon, 9 Oct 2023 10:37:49 +0100 Message-ID: <20231009-moonlight-gray-92debdc89f30@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231009-approve-verbalize-ce9324858e76@wendy> References: <20231009-approve-verbalize-ce9324858e76@wendy> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=988; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=7kiFiWXf0X7YTKnlUryjTPWfXBjavhZEL7/N/C8FSjM=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnKJ1/Fr8/WfiFqvXtltb7OSo9vh1wvG72dcC1uScmSyFn7 7O+FdpSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAi1amMDAf5Zr48puEkVbn3lW7x9X MGX5d2nFg9x1tXOE/SueR9uAbD/6TXfJuN37w8UlCSuUPsYuqJXAdDxk9vj7+/9H+jCYfucnYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Convert the D1 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Acked-by: Jernej Skrabec Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 0856f18dc3cf..64c3c2e6cbe0 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -25,6 +25,9 @@ cpu0: cpu@0 { mmu-type = "riscv,sv39"; operating-points-v2 = <&opp_table_cpu>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; #cooling-cells = <2>; cpu0_intc: interrupt-controller { From patchwork Mon Oct 9 09:37:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 731176 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81C5915AEA for ; Mon, 9 Oct 2023 09:40:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="OZuKNfZZ" Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C3A2694; Mon, 9 Oct 2023 02:40:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1696844420; x=1728380420; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VMvqdOH2bfvF8b1Y4FhIf8IeIgyZ5ZAtbeMPwdNyDAA=; b=OZuKNfZZo1TXdLtbMmQz0OOb0U1COmS1Zq1v6g/GkYvtRnuLFgloaf3w kaf+YVoo8bzD8Svs/dxo1OPI6ZPxLTWzODN8zC+ddlQGLasVdizb3CpUD G1YOPDF5CePlzMPFAqtpMKkykesfPruCEuZg1mnUaBqASSqPcQChfz84D fcqkk+NeInpX/zGdKqwGYhRoyaqrxX9vfS9pdp38Pf9YBx5dfnkYIOc99 l5+7OlcvG2UHvlcxvBHlp1yZzW3tUn1h1LYnH8ypTwXmO2Yh0WqeWtHy/ WDa5q5CvwvRVMEf95Ep0saddiAVc0kbuCGD05UZYA9lbjjsNn3LVZ2eiI w==; X-CSE-ConnectionGUID: hHeZTK8qRb+XNP3M4wjW+Q== X-CSE-MsgGUID: 9qRUDNU3T6WKGVKRrO2f/g== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,210,1694761200"; d="scan'208";a="176379099" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 09 Oct 2023 02:40:19 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 9 Oct 2023 02:40:10 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 9 Oct 2023 02:40:06 -0700 From: Conor Dooley To: CC: , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Paul Walmsley" , Palmer Dabbelt , Albert Ou , Chen-Yu Tsai , "Jernej Skrabec" , Samuel Holland , Daire McNamara , Geert Uytterhoeven , Magnus Damm , "Emil Renner Berthing" , Jisheng Zhang , Guo Ren , Fu Wei , Chen Wang , , , , Subject: [PATCH v3 6/6] riscv: dts: thead: convert isa detection to new properties Date: Mon, 9 Oct 2023 10:37:50 +0100 Message-ID: <20231009-observant-placate-0e2097996244@wendy> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231009-approve-verbalize-ce9324858e76@wendy> References: <20231009-approve-verbalize-ce9324858e76@wendy> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2059; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=VMvqdOH2bfvF8b1Y4FhIf8IeIgyZ5ZAtbeMPwdNyDAA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnKJ19fr9UT0lzruPzEuz93I5VqVxaGfN5XFxCzJeLdi0LR PWKZHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiIdRfD/8q3zYe13YNLNjzWaeSecn /f9suhq/2PLzsU/PGoc56V7zJGhs91atHX3xpMWLTQqXxOXI9sntI90R29c3p/GdwvXB2Vxw4A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Reviewed-by: Jisheng Zhang Acked-by: Guo Ren Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ce708183b6f6..723f65487246 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -20,6 +20,9 @@ c910_0: cpu@0 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -41,6 +44,9 @@ c910_1: cpu@1 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -62,6 +68,9 @@ c910_2: cpu@2 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -83,6 +92,9 @@ c910_3: cpu@3 { compatible = "thead,c910", "riscv"; device_type = "cpu"; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>;