From patchwork Fri Oct 6 12:14:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 730753 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 041901CF9A for ; Fri, 6 Oct 2023 12:27:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KtJmRO1C" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DBCAC433CC; Fri, 6 Oct 2023 12:26:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696595220; bh=SnqqmnuywOhmCW0NrWgiJLL8C+SD9HabtHjqFfDXRA0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KtJmRO1Cou5EiBgcTPgxHF4yWrW5dQsCuOzc3NBJ/sytY3coZjSlqnwJaYftSR8c7 2RbcSXoDWtBH/JU/0Vv+1XBJS/XocLczha3d5kPnnzAKQjdDMhkmE08ejeAW/fNTer B+7zdTmj/wISBxpDgLLSmQW30RcjirkDhk5DV+0eQ668kmQWp6bP5OImaXA9OCu5x7 elML0q+1TQ6DSXYEsM5eb1Iq9lPpSTNfbFrYt9Kfkr5A1g0Nr0wqxmsBCduLzspe76 fNOu9O2z/0AsoSH/m0DQCuxk7Teh7Uvg6CHROcN8NPvmvRJpKT8rnJ/jC65Yxbdl+C 12L9Y4fspI3Ew== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Inochi Amaoto , Conor Dooley Subject: [PATCH v2 1/5] dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic Date: Fri, 6 Oct 2023 20:14:45 +0800 Message-Id: <20231006121449.721-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231006121449.721-1-jszhang@kernel.org> References: <20231006121449.721-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add compatible string for SOPHGO CV1800B plic. Signed-off-by: Jisheng Zhang Acked-by: Conor Dooley --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 16f9c4760c0f..0c07e8dda445 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -65,6 +65,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-plic + - sophgo,cv1800b-plic - sophgo,sg2042-plic - thead,th1520-plic - const: thead,c900-plic From patchwork Fri Oct 6 12:14:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 730078 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AEC91CF9A for ; Fri, 6 Oct 2023 12:27:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IMgFKe86" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3643BC43397; Fri, 6 Oct 2023 12:27:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696595224; bh=aIfy+YMFnPIuOo+znZOJ9L0lx1fBT20WZxlMNK06oX8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IMgFKe86ZFLLLFU0LQEjPKfDWW4nirs7rURYXhO8AHquYNbENHIa15tooFlH3TxTA FI9pk2mToKN150eFZmLtherHr1GheN87w/PjoVm7Hrj+kMmzhHEjd7suFCor797gkW 7nkEt8hHR/lhVSlDHsTAnKLi0KnH1EMf7L8No3uFssv8/8IwxEYK7tYreYHzs/8seC EPAzmkAxd1vQNvhdOohN+EgT2cQVGTl3s5igxLxrNuA2VeCKiIqbHuGC/7Xzx1Ixoa dwdLDytVPS760OTw3fgA+8Xg9AZwvzimjJfiNm87g8S1T3Mhz7FogbDUKLhJ/CdwT6 I+qEBZl/Vm4Pg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Inochi Amaoto , Conor Dooley Subject: [PATCH v2 2/5] dt-bindings: timer: Add SOPHGO CV1800B clint Date: Fri, 6 Oct 2023 20:14:46 +0800 Message-Id: <20231006121449.721-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231006121449.721-1-jszhang@kernel.org> References: <20231006121449.721-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add compatible string for the SOPHGO CV1800B clint. Signed-off-by: Jisheng Zhang Acked-by: Conor Dooley --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index a0185e15a42f..e8be6c470364 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -37,6 +37,7 @@ properties: - items: - enum: - allwinner,sun20i-d1-clint + - sophgo,cv1800b-clint - thead,th1520-clint - const: thead,c900-clint - items: From patchwork Fri Oct 6 12:14:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 730752 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 639601CFB5 for ; Fri, 6 Oct 2023 12:27:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Dxk2dDWL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5A0ECC4166B; Fri, 6 Oct 2023 12:27:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696595226; bh=vK2e3eQyu+2RwwEcd/fM4Ck3i9PQ2DpagYXnMZgMMks=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dxk2dDWLVPcQeveUPSAdTFi42lTUudLuJqloZTONbgWb7SQLlQqEhAEuzFHDZsEVm /vjayuxdfMKJkf/QCedhgEPmRyhcf2bfjpEg1/l1OmVOKtvdP1QjA+havuZd0LDMwJ iFHK+7KKBsg0jM7Pv5rX5ZQTuckPPP3HlJlkX5U0lB0kIbAg7tn0pO2Sm7ABBMxIOR NyT+1hItlAyHRR9+jg6rKmaRip1cUVw9s8RZkLWl1Yl2G6+HpdBl+poX7UDEE24Dvq JYHFIv1aWKjR0+hUy/3Jr1WFvmPr6q9qoQtAPmoA84k5OSor4ai5CXKnRkIudgXNe3 T4BWv7tVVaMhg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Inochi Amaoto , Conor Dooley , Chen Wang Subject: [PATCH v2 3/5] dt-bindings: riscv: Add Milk-V Duo board compatibles Date: Fri, 6 Oct 2023 20:14:47 +0800 Message-Id: <20231006121449.721-4-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231006121449.721-1-jszhang@kernel.org> References: <20231006121449.721-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document the compatible strings for the Milk-V Duo board[1] which uses the SOPHGO CV1800B SoC[2]. Link: https://milkv.io/duo [1] Link: https://en.sophgo.com/product/introduce/cv180xB.html [2] Signed-off-by: Jisheng Zhang Acked-by: Conor Dooley Acked-by: Chen Wang --- Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml index 8adb5f39ca53..86748c5390be 100644 --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml @@ -18,6 +18,10 @@ properties: const: '/' compatible: oneOf: + - items: + - enum: + - milkv,duo + - const: sophgo,cv1800b - items: - enum: - milkv,pioneer From patchwork Fri Oct 6 12:14:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 730077 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00B671CFB5 for ; Fri, 6 Oct 2023 12:27:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NP80/FAH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 41D96C433AD; Fri, 6 Oct 2023 12:27:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696595229; bh=bOf8w7XnCc16OPMA+e95RqpCtIBPs/nM95W8FKx64k0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NP80/FAHyJhx3j01yWIu134p/m29xD1K3Ijk8Or65OIPy+/vZg3qqkLuqI06ZtSa3 siQewwfwxXxIUr7ls+Z3ldqvWMoknqNIx/FWvcKpvh9MhN2eD3khDwWpi1o307/zyk JhQx9m3LJN2HRuxoxQqPyiUCu5UEes+e3K+dMPGxLESsclqnPeKvvPoV5XpZ2RI2Ni Ntw9A7qIFcvlL/0tfQw+3PCQg7eBrYZTnyS/7uUK8vSvP9Ht9t8lsa9GsN0Gyd4TMz 1r2VnN+YKlOIkzQ8MpwyuGpKdzKwWbi7dCPctPJGtcMteKfR7TOvH2FT466OQ3YmZn lr3nvfYLaEPTg== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Inochi Amaoto Subject: [PATCH v2 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree Date: Fri, 6 Oct 2023 20:14:48 +0800 Message-Id: <20231006121449.721-5-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231006121449.721-1-jszhang@kernel.org> References: <20231006121449.721-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. Signed-off-by: Jisheng Zhang Acked-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 123 ++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b.dtsi diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi new file mode 100644 index 000000000000..df40e87ee063 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + compatible = "sophgo,cv1800b"; + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <1>; + #size-cells = <1>; + dma-noncoherent; + ranges; + + uart0: serial@4140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@4150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@4160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@4170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@41c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@70000000 { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + + clint: timer@74000000 { + compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; + reg = <0x74000000 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; + }; + }; +}; From patchwork Fri Oct 6 12:14:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 730751 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0250A1CF8F for ; Fri, 6 Oct 2023 12:27:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l9Zm4Xpq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3600EC116A7; Fri, 6 Oct 2023 12:27:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696595233; bh=RtdMEoqo8nayEQ4k8BfxK/6NPIxdjeCli2iRVgA15Qk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l9Zm4XpqcRXxtoKBJ04/OP2WV4jBlgdVOmS+pJWo0bE4lEilHOgidYWUHIXLM6bHS IzwlrGHDYYQg4jsC7LSgmgWQ/WnB4i62BF9L8muVDrWTRqsURMvOM2oJvCnWRXJ18j T/ukWIQtJ/2wYXWptjfh1DluHgU7a51xfTo6oyEbnLnE/zEYEi6MRcDtKKK3NU6Pmf Smm4b938sKDqReI6BKx5sOe+bwcR6RHz30msy9DW9c0slSSSq1qgmYnBnqUT7Nk8SC MLIr3hBjTtrQb3W8HSoLrwcKKDQIsYQoy7HzmeArK3UUxC5lKEeUuC7UVOky8jqkC7 /eCzsLbTMzZAA== From: Jisheng Zhang To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Inochi Amaoto Subject: [PATCH v2 5/5] riscv: dts: sophgo: add Milk-V Duo board device tree Date: Fri, 6 Oct 2023 20:14:49 +0800 Message-Id: <20231006121449.721-6-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231006121449.721-1-jszhang@kernel.org> References: <20231006121449.721-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Milk-V Duo[1] board is an embedded development platform based on the CV1800B chip. Add minimal device tree files for the development board. Support basic uart drivers, so supports booting to a basic shell. Link: https://milkv.io/duo [1] Signed-off-by: Jisheng Zhang --- arch/riscv/boot/dts/sophgo/Makefile | 2 +- .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 38 +++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile index 5a471b19df22..3fb65512c631 100644 --- a/arch/riscv/boot/dts/sophgo/Makefile +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb - diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts new file mode 100644 index 000000000000..3af9e34b3bc7 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +/dts-v1/; + +#include "cv1800b.dtsi" + +/ { + model = "Milk-V Duo"; + compatible = "milkv,duo", "sophgo,cv1800b"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x3f40000>; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +};