From patchwork Thu Oct 5 02:58:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AKASHI Takahiro X-Patchwork-Id: 729828 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F1D67E for ; Thu, 5 Oct 2023 02:59:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="P8CD0Huk" Received: from mail-ot1-x331.google.com (mail-ot1-x331.google.com [IPv6:2607:f8b0:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20718192 for ; Wed, 4 Oct 2023 19:59:24 -0700 (PDT) Received: by mail-ot1-x331.google.com with SMTP id 46e09a7af769-6c61dd1c229so94830a34.0 for ; Wed, 04 Oct 2023 19:59:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696474763; x=1697079563; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C71OcQAzBT261vJLaVS0ZLT3a6uuXRpHLmHkJwsnefw=; b=P8CD0HukQ+P5Uo9B8X121NvvGG8A+1PT8xI9Ob5+8tDdJ1mW69fs375RdP0e3MlFzu p8H2kuzDbPhyhcIgBO6wsL8SCE/1Bu9HFZexj6nv9jIxBqALBcSu+57SnSVPNBo4z6AR QnxJwhsQwl8zIV0dn6aZ/aYtU5lU/73VhWm2+RIFEgsKqWKtFbaeOzamvCHUNyytPamo MqWZCAqOC/NtP6wSTm81Eiakp73JcqO2F7br4dCJlZk7t/XO2fpBj5S55ZzDWo7BZlRE PwQK1TXWlArdbfCAmQa5AR07wwNq5UeQ4sV2etlQQ3UNpOeQpF15B0Uyg7QPbNhagzn1 r3Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696474763; x=1697079563; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C71OcQAzBT261vJLaVS0ZLT3a6uuXRpHLmHkJwsnefw=; b=RWhizCuYkFfTDcN8YfxjkvDFgvVRuPwnUpQ5Vj5QhV7s8R0iMCSwrPI0XHyHhFR31B moEMJb0LSFyUCoKPkeJNjn1neuiQ93zxt1BtJXI31pxV+8gnEzyAFVUMquykHPfP1XTF WRfnH+0gIay/eQBvMwthag+z1kVmNeDFiQJuZaGbSxCqjBDt12WzETn44D33sIKDGwbe ZoFoivuPP9wGVkeE9PFJNY+odl1V1q4y3syQW8YW6HAbm90M4LhMxgFriMbVmPrQW+H3 m4bRSTdYb4lEU/pOHQPzZ2pyenqulonzvjGzsQ+HD61YxeEzeFGEHTGvFAJaH2E6YGS9 g83A== X-Gm-Message-State: AOJu0Yx6CUWhSbnlnj/G7+JU0dlFztdNJ4VKC5JgWUqjMwobLy/iULYk TIIZfDTUnpmrqIzBtdoUKplk9g== X-Google-Smtp-Source: AGHT+IFLE3a+7Vp/OvWCFi9446MZ5SR2US5WlY9g/kRa6BRPFqm4JfQA8hECuQL2KLgO1V/YM25PiQ== X-Received: by 2002:a05:6830:4867:b0:6bf:500f:b570 with SMTP id dx7-20020a056830486700b006bf500fb570mr3559438otb.3.1696474763244; Wed, 04 Oct 2023 19:59:23 -0700 (PDT) Received: from octopus.. ([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:22 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro Subject: [RFC v2 1/5] pinctrl: define PIN_CONFIG_INPUT Date: Thu, 5 Oct 2023 11:58:39 +0900 Message-Id: <20231005025843.508689-2-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net This configuration is intended to be used to allow a pin controller based GPIO driver to obtain a value at a gpio input pin. Signed-off-by: AKASHI Takahiro Reviewed-by: Linus Walleij --- RFC v2 (Oct 5, 2023) * improve a comment against @PIN_CONFIG_INPUT as per Linus RFC(Oct 2, 2023) --- include/linux/pinctrl/pinconf-generic.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index d74b7a4ea154..da0d80aa532d 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -67,6 +67,10 @@ struct pinctrl_map; * passed as argument. The argument is in mA. * @PIN_CONFIG_DRIVE_STRENGTH_UA: the pin will sink or source at most the current * passed as argument. The argument is in uA. + * @PIN_CONFIG_INPUT: This will obtain a value on an input pin. To put a line + * into input mode, @PIN_CONFIG_INPUT_ENABLE must be used. Otherwise, + * an error will be returned. The returned argument is 1 for logic high + * and 0 for logic low. * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode, * which means it will wait for signals to settle when reading inputs. The * argument gives the debounce time in usecs. Setting the @@ -128,6 +132,7 @@ enum pin_config_param { PIN_CONFIG_DRIVE_PUSH_PULL, PIN_CONFIG_DRIVE_STRENGTH, PIN_CONFIG_DRIVE_STRENGTH_UA, + PIN_CONFIG_INPUT, PIN_CONFIG_INPUT_DEBOUNCE, PIN_CONFIG_INPUT_ENABLE, PIN_CONFIG_INPUT_SCHMITT, From patchwork Thu Oct 5 02:58:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AKASHI Takahiro X-Patchwork-Id: 730859 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 118861106 for ; Thu, 5 Oct 2023 02:59:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="XueE8YDI" Received: from mail-oi1-x229.google.com (mail-oi1-x229.google.com [IPv6:2607:f8b0:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 939F5194 for ; Wed, 4 Oct 2023 19:59:27 -0700 (PDT) Received: by mail-oi1-x229.google.com with SMTP id 5614622812f47-3ae473c0bd6so76146b6e.0 for ; Wed, 04 Oct 2023 19:59:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696474767; x=1697079567; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TSbRKsYb8q8GitmB/U1RL+XJyPpceXOp7I/10Xz1sb8=; b=XueE8YDI+5wUzH/Y/c1ekq0JHsfG0iDJZ0DZKAYcl8g1xl0cXcnsOXRfnBYI5z+5Sp uF0woHMq1a2m8jg1QEBPTkidp0l3V1+YLRG2+beaqk85481HjmHmdleil1b1Lv9CB5yk YsuvkOClIFGfkf1921MjtShKipa4prN2W2nG+GHHnyDn/7TkB6trSsIL5iq70+GweTJC Qvu/yMW1TvG0Oe2qsAXjcPw/T8Yjx/sKhLJuGHrvsRXxDClu2FjNL65wzgb/7jknu+P+ aXE0i4n55uHxxZ0p4BgDhenLVIowkX0VJphrfNg8z8rLfG0RW6GE9FmtviA1tQ4ttg4X UJAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696474767; x=1697079567; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TSbRKsYb8q8GitmB/U1RL+XJyPpceXOp7I/10Xz1sb8=; b=lbaevan4tIyi/0ahUez5+idHjXToBSUg+6k3Zhr4tfwGpCmUCBU1Deu6ZzfPfWYSpe 6LMrTzAvvnbv0PF8PZpEuOpPUHCiLt5xljHmtNJS0v5qB55CicER7mxbDj7120rkWtKA kxl4TToDza84vMSFROy4maE4T8V8IdbxQk67sjejnJ1BLyjJXLf7VOFfSEgVr19JAE8F 5NZjb3zoBH8J44EVtZb4ozOVh1ukgjJhuKopjwKcNw1n9O0qfVvmgUECUuapf4nNQMYF i18vNi9I6iFYN/M0OEpRv+BSgp7TGwMhl9Qw0cszv6MsWnmJcfVEFlODUllKwUQhsj41 JzGQ== X-Gm-Message-State: AOJu0Yww5PWJ/NYbUNujG9Zw/zTlfbOmbsbk9AxqG8gF7DpBy/Ou3t8X 4D/KW1MxHM3SQDjROQNcUmA5xg== X-Google-Smtp-Source: AGHT+IEvgr4xZLoO3AM+An1x16yJUdYmGeTqCDtyfPw8q8eOIK+ezaH2/Gf3R2hl6ENX1z8p9dBrGw== X-Received: by 2002:a05:6808:1a27:b0:3ae:5e6a:5693 with SMTP id bk39-20020a0568081a2700b003ae5e6a5693mr4930128oib.0.1696474766819; Wed, 04 Oct 2023 19:59:26 -0700 (PDT) Received: from octopus.. ([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:26 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro , kernel test robot Subject: [RFC v2 2/5] pinctrl: always export pin_config_get_for_pin() Date: Thu, 5 Oct 2023 11:58:40 +0900 Message-Id: <20231005025843.508689-3-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net This function will be used to implement a new pinctrl_gpio_get_config() outside pinconf.c in a succeeding commit. So make it always visible to avoid a kernel test bot error. Signed-off-by: AKASHI Takahiro Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202310021320.gYfm1nLQ-lkp@intel.com/ Reviewed-by: Linus Walleij --- RFC v2 (Oct 5, 2023) * new --- drivers/pinctrl/pinconf.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index 694bfc9961fa..068089b199e4 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -31,13 +31,13 @@ int pinconf_apply_setting(const struct pinctrl_setting *setting); int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, size_t nconfigs); +int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config); /* * You will only be interested in these if you're using PINCONF * so don't supply any stubs for these. */ -int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *config); int pin_config_group_get(const char *dev_name, const char *pin_group, unsigned long *config); @@ -74,6 +74,12 @@ static inline int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin, return -ENOTSUPP; } +static inline int pin_config_get_for_pin(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *config) +{ + return -ENOTSUPP; +} + #endif #if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS) From patchwork Thu Oct 5 02:58:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AKASHI Takahiro X-Patchwork-Id: 729827 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8174317FE for ; Thu, 5 Oct 2023 02:59:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VKUQsTLh" Received: from mail-ot1-x334.google.com (mail-ot1-x334.google.com [IPv6:2607:f8b0:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40F87193 for ; Wed, 4 Oct 2023 19:59:31 -0700 (PDT) Received: by mail-ot1-x334.google.com with SMTP id 46e09a7af769-6c7a4735a30so92742a34.1 for ; Wed, 04 Oct 2023 19:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696474770; x=1697079570; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=10JswCDtKjfsgUgjTt05ZkVWjMO4ZebDQWE8d7lo6tc=; b=VKUQsTLhCArnRioaPv2u3UlcoY7e8nqdOs9Fb8algbw+e/Qb7F1MxBH78hSGbgQeN1 TwlbgeZPvk3tZQ7Lq8E6ic5XwdO/8VtzCHs1nfuxFf+Sw7/p8277olzuPDWtgoIFuGNn qHw0a1+iIxDAu2HGCyUgI4HJ8wQkn8ADY4recjFsosL/9dYBfb14a2x3Gk115QhSo2z7 DE9EzsnfoW6uLCk6ubnPJ4tilrCnrOPxFYiD6zYXGZ+kF/Y1eX2AAHjoaQhsnxF0bg3i Sazzd3ecdU00wp6MoWT9BsqGzcmwqGrT+wb5AO1OPrrQPxBu8AyFISFRW2OzSSoc25yl vUuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696474770; x=1697079570; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=10JswCDtKjfsgUgjTt05ZkVWjMO4ZebDQWE8d7lo6tc=; b=LtQirzeYVb054q/z44F2S+KzldCDhkYWq8t8NPszo7BY08TMNkjyBLB8DKqz8TUqew dQKBhvCRXK7cAW5F1rfozKZlmgHEfmKuyPm65FxvDgtRfTt08xMMh6yL/htO9GFBOx6R um06a2OoghGrT0mDurLn+zN1MWVhBvpJ5K0/SdVvG+aVe9feOd1aHB+VJLSgxGkHtDHw 8N5DPtHTWvJ6C1VIk/JxH9+nctakm6qEI0SuBDrgrw1Rd8hfpHGHR55OgrGFgShZ5RSh 106CtreFJRNW9RdoeDQuJoo6lEZw54eqQXPpqRzobx03wz0m7G8QcX+9R8O+fsgj1Zzc Vp6w== X-Gm-Message-State: AOJu0Yz6TubGheAFF9LK/zv4ADllaAoN3dfg7DGuSMYuRqkDV/vrSJjR SCm7yz+GUm1tjgFkWmrClcygMA== X-Google-Smtp-Source: AGHT+IFVHEUYGWZTaKBOTIg0Zt8j6bgzzj5zfngX59+MW1xuz8QaG4UOkQ4Qt1xPSuv/ln7C4yvMeg== X-Received: by 2002:a05:6808:15a8:b0:3ad:f3c0:5da3 with SMTP id t40-20020a05680815a800b003adf3c05da3mr4643158oiw.3.1696474770489; Wed, 04 Oct 2023 19:59:30 -0700 (PDT) Received: from octopus.. ([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:30 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro Subject: [RFC v2 3/5] pinctrl: add pinctrl_gpio_get_config() Date: Thu, 5 Oct 2023 11:58:41 +0900 Message-Id: <20231005025843.508689-4-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net This is a counterpart of pinctrl_gpio_set_config() which will be used, at least initially, to implement gpio_get interface in pin controller based generic gpio driver. Signed-off-by: AKASHI Takahiro Reviewed-by: Linus Walleij --- RFC (Oct 2, 2023) --- drivers/pinctrl/core.c | 19 +++++++++++++++++++ include/linux/pinctrl/consumer.h | 8 ++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index e9dc9638120a..2f9c2efdfe0e 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -926,6 +926,25 @@ int pinctrl_gpio_set_config(unsigned gpio, unsigned long config) } EXPORT_SYMBOL_GPL(pinctrl_gpio_set_config); +int pinctrl_gpio_get_config(unsigned int gpio, unsigned long *config) +{ + struct pinctrl_gpio_range *range; + struct pinctrl_dev *pctldev; + int ret, pin; + + ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); + if (ret) + return ret; + + mutex_lock(&pctldev->mutex); + pin = gpio_to_pin(range, gpio); + ret = pin_config_get_for_pin(pctldev, pin, config); + mutex_unlock(&pctldev->mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(pinctrl_gpio_get_config); + static struct pinctrl_state *find_state(struct pinctrl *p, const char *name) { diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h index 4729d54e8995..852fac97a79b 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -31,6 +31,8 @@ extern void pinctrl_gpio_free(unsigned gpio); extern int pinctrl_gpio_direction_input(unsigned gpio); extern int pinctrl_gpio_direction_output(unsigned gpio); extern int pinctrl_gpio_set_config(unsigned gpio, unsigned long config); +extern int pinctrl_gpio_get_config(unsigned int gpio, + unsigned long *config); extern struct pinctrl * __must_check pinctrl_get(struct device *dev); extern void pinctrl_put(struct pinctrl *p); @@ -92,6 +94,12 @@ static inline int pinctrl_gpio_set_config(unsigned gpio, unsigned long config) return 0; } +static inline int pinctrl_gpio_get_config(unsigned int gpio, + unsigned long *config) +{ + return 0; +} + static inline struct pinctrl * __must_check pinctrl_get(struct device *dev) { return NULL; From patchwork Thu Oct 5 02:58:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AKASHI Takahiro X-Patchwork-Id: 730858 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28BD21847 for ; Thu, 5 Oct 2023 02:59:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="K+IK+vyD" Received: from mail-io1-xd2b.google.com (mail-io1-xd2b.google.com [IPv6:2607:f8b0:4864:20::d2b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C800619A for ; Wed, 4 Oct 2023 19:59:34 -0700 (PDT) Received: by mail-io1-xd2b.google.com with SMTP id ca18e2360f4ac-7a24c86aae3so8587739f.0 for ; Wed, 04 Oct 2023 19:59:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696474774; x=1697079574; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o8UbiRXeWQbu5CCxehWCFCKEGYBPmnXfSamsU23VNAk=; b=K+IK+vyDrEfWzOT5JIT48hmKzhKKMLZFDbPaFEtMSfNdxRbnFRUwpxKPZgx6WNCIPa Q/tfeX4dF60zzaRc6qGDxu8TS/XpLaDxVtd0OOZTWBau3G7OlfTRlLCZh3R6PP3edKi1 Ru+ZdOHqAcEBNBNxR1zDzPlJWQI5K/On1Ee8GwIBthfLrMJoWpbTx0XV3dEsJ83X8XUf uac99DhOkV1AeYnDnh9VUTtL2sPKvd+W+BgD8revfnQm7RIkR5ahDK1FNFSA6zFQM/vX zNknROnZxuuEl6bUgTOeTksuxH9kBvRzTTa/Bt30fdPVuFBQhLOBOvzPf9jZaXwDqgM0 rsQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696474774; x=1697079574; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o8UbiRXeWQbu5CCxehWCFCKEGYBPmnXfSamsU23VNAk=; b=xFYOCwQ01ahrzUQvQZDW1Tfdn2lfmIhV1JTDHS1q+S50J8IDmhdjk8wHw7hVfShLRL gMjOnUqq1jlacc8Aaiv0zDiZpp8V9lVHWYRlhHmoBiXq3hxP/ikm8Mw7pygPwIZyVZH9 thbu03bAkZyYcFJpLYTPjJCFfR+dMNYt7UiHN0hqvPArps/16jlkOJFfzQP1n/0nUCzd PphS8J1SqVWXI9TF1S1SUQy8IPLbWAT1aPsUuMaSE/3DwWWIruTBO3L9av6OGJPdWMcc t+PA80ALHVdPLzl1gIUA/8wYzoBefjbw81zxOigTZY7FMtC/q/YkA2STdkn3/3zteecG yVAQ== X-Gm-Message-State: AOJu0YxY4xxbhLB8VY23K+nM7KlSSvJyUnv8MA/QyDZkJg1woM8S2c2W CX34f1ap7Iya6sPHYz48uOFL8A== X-Google-Smtp-Source: AGHT+IEIo4FgrkyprKPEFogjQ8fMf3lI1H/+E2BdJpeZVdJkotQfybd+YwiLDuLtUjYGfdM29DxTOg== X-Received: by 2002:a92:dacd:0:b0:351:1ed0:5c6b with SMTP id o13-20020a92dacd000000b003511ed05c6bmr3933124ilq.3.1696474774015; Wed, 04 Oct 2023 19:59:34 -0700 (PDT) Received: from octopus.. ([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:33 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro Subject: [RFC v2 4/5] gpio: add pinctrl based generic gpio driver Date: Thu, 5 Oct 2023 11:58:42 +0900 Message-Id: <20231005025843.508689-5-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Some pin controllers provide not only a method to set up lines but also gpio function. With this commit, a new generic gpio driver will be provided. It is implemented purely by using pinctrl interfaces. One of such pin controllers is Arm's SCMI. Signed-off-by: AKASHI Takahiro --- RFC v2 (Oct 5, 2023) * rename the driver to pin-control-gpio (CONFIG_GPIO_BY_PINCTRL) * return meaningful error codes instead of -1 * remove the masking at PIN_CONFIG_PACKED * handle emulated OPEN_DRAIN configuration at get_direction() * define config_set in gpio_chip * drop remove hook RFC (Oct 2, 2023) --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-by-pinctrl.c | 165 +++++++++++++++++++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 drivers/gpio/gpio-by-pinctrl.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 673bafb8be58..a60972be114c 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -216,6 +216,13 @@ config GPIO_BRCMSTB help Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs. +config GPIO_BY_PINCTRL + tristate "GPIO support based on a pure pin control backend" + depends on GPIOLIB + help + Select this option to support GPIO devices based solely on pin + control, specifically pin configuration, such as SCMI. + config GPIO_CADENCE tristate "Cadence GPIO support" depends on OF_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index eb73b5d633eb..71458d81e16a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o +obj-$(CONFIG_GPIO_BY_PINCTRL) += gpio-by-pinctrl.o obj-$(CONFIG_GPIO_CADENCE) += gpio-cadence.o obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o obj-$(CONFIG_GPIO_SNPS_CREG) += gpio-creg-snps.o diff --git a/drivers/gpio/gpio-by-pinctrl.c b/drivers/gpio/gpio-by-pinctrl.c new file mode 100644 index 000000000000..c297a9633e03 --- /dev/null +++ b/drivers/gpio/gpio-by-pinctrl.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2023 Linaro Inc. +// Author: AKASHI takahiro + +#include +#include +#include +#include +#include +#include +#include "gpiolib.h" + +struct pin_control_gpio_priv { + struct gpio_chip chip; +}; + +static int pin_control_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + unsigned long config; + bool out_en, in_en; + int ret; + + config = PIN_CONFIG_OUTPUT_ENABLE; + ret = pinctrl_gpio_get_config(chip->gpiodev->base + offset, &config); + if (!ret) + out_en = !!config; + else if (ret == -EINVAL) + out_en = false; + else + return ret; + + config = PIN_CONFIG_INPUT_ENABLE; + ret = pinctrl_gpio_get_config(chip->gpiodev->base + offset, &config); + if (!ret) + in_en = !!config; + else if (ret == -EINVAL) + in_en = false; + else + return ret; + + if (in_en && !out_en) + return GPIO_LINE_DIRECTION_IN; + + if (!in_en && out_en) + return GPIO_LINE_DIRECTION_OUT; + + if (in_en && out_en) { + /* This may be an emulation for output with open drain */ + config = PIN_CONFIG_DRIVE_OPEN_DRAIN; + ret = pinctrl_gpio_get_config(chip->gpiodev->base + offset, + &config); + if (!ret && config) + return GPIO_LINE_DIRECTION_OUT; + } + + return -EINVAL; +} + +static int pin_control_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + return pinctrl_gpio_direction_input(chip->gpiodev->base + offset); +} + +static int pin_control_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int val) +{ + return pinctrl_gpio_direction_output(chip->gpiodev->base + offset); +} + +static int pin_control_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + unsigned long config; + int ret; + + config = PIN_CONFIG_INPUT; + ret = pinctrl_gpio_get_config(chip->gpiodev->base + offset, &config); + if (ret) + return ret; + + if (config >> 8) + return 1; + + return 0; +} + +static void pin_control_gpio_set(struct gpio_chip *chip, unsigned int offset, + int val) +{ + unsigned long config; + + config = PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, val); + + pinctrl_gpio_set_config(chip->gpiodev->base + offset, config); +} + +static u16 sum_up_ngpios(struct gpio_chip *chip) +{ + struct gpio_pin_range *range; + struct gpio_device *gdev = chip->gpiodev; + u16 ngpios = 0; + + list_for_each_entry(range, &gdev->pin_ranges, node) { + ngpios += range->range.npins; + } + + return ngpios; +} + +static int pin_control_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pin_control_gpio_priv *priv; + struct gpio_chip *chip; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + chip = &priv->chip; + chip->label = dev_name(dev); + chip->parent = dev; + chip->base = -1; + + chip->request = gpiochip_generic_request; + chip->free = gpiochip_generic_free; + chip->get_direction = pin_control_gpio_get_direction; + chip->direction_input = pin_control_gpio_direction_input; + chip->direction_output = pin_control_gpio_direction_output; + chip->get = pin_control_gpio_get; + chip->set = pin_control_gpio_set; + chip->set_config = gpiochip_generic_config; + + ret = devm_gpiochip_add_data(dev, chip, priv); + if (ret) + return ret; + + chip->ngpio = sum_up_ngpios(chip); + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static const struct of_device_id pin_control_gpio_match[] = { + { .compatible = "pin-control-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, pin_control_gpio_match); + +static struct platform_driver pin_control_gpio_driver = { + .probe = pin_control_gpio_probe, + .driver = { + .name = "pin-control-gpio", + .of_match_table = pin_control_gpio_match, + }, +}; +module_platform_driver(pin_control_gpio_driver); + +MODULE_AUTHOR("AKASHI Takahiro "); +MODULE_DESCRIPTION("Pinctrl based GPIO driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Oct 5 02:58:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AKASHI Takahiro X-Patchwork-Id: 729826 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41E9C1847 for ; Thu, 5 Oct 2023 02:59:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="F0nD+MhF" Received: from mail-ot1-x336.google.com (mail-ot1-x336.google.com [IPv6:2607:f8b0:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A28B61A1 for ; Wed, 4 Oct 2023 19:59:37 -0700 (PDT) Received: by mail-ot1-x336.google.com with SMTP id 46e09a7af769-6c61dd1c229so94873a34.0 for ; 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([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:36 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro Subject: [RFC v2 5/5] dt-bindings: gpio: Add bindings for pinctrl based generic gpio driver Date: Thu, 5 Oct 2023 11:58:43 +0900 Message-Id: <20231005025843.508689-6-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net A dt binding for pin controller based generic gpio driver is defined in this commit. One usable device is Arm's SCMI. Signed-off-by: AKASHI Takahiro --- RFC v2 (Oct 5, 2023) * rename the binding to pin-control-gpio * add the "description" * remove nodename, hog properties, and a consumer example RFC (Oct 2, 2023) --- .../bindings/gpio/pin-control-gpio.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml b/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml new file mode 100644 index 000000000000..bc935dbd7edb --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/pin-control-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pin control based generic GPIO controller + +description: + The pin control-based GPIO will facilitate a pin controller's ability + to drive electric lines high/low and other generic properties of a + pin controller to perform general-purpose one-bit binary I/O. + +maintainers: + - AKASHI Takahiro + +properties: + compatible: + const: pin-control-gpio + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: true + + gpio-ranges-group-names: true + +patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + + required: + - gpio-hog + +required: + - compatible + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + gpio0: gpio@0 { + compatible = "pin-control-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&scmi_pinctrl 0 10 5>, + <&scmi_pinctrl 5 0 0>; + gpio-ranges-group-names = "", + "pinmux_gpio"; + };