From patchwork Wed Jul 31 22:41:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 170275 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp4576498ile; Wed, 31 Jul 2019 15:43:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqwqwNPP7CwZiEr5IWouj4dH8jc+eqaCM4eajnCkiyFQwoMJwAdJM9EpBLjU2zYF/BtwaXvD X-Received: by 2002:a65:6552:: with SMTP id a18mr107486865pgw.208.1564613031724; Wed, 31 Jul 2019 15:43:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564613031; cv=none; d=google.com; s=arc-20160816; b=NccRAOBCKy2A1ec/nFCd0susVrpp8TY5MHKSRU0pal2cBPwfyJs2lg+63S88Fvg48O xRK09+QGJeOVqnp2dBbsARJtv5lXqsK9fOC3cU/f6GRGnELEZHVqTZ9FrdO07sAaae6g jVjPs2IdESEoxZiOF1SFTZpcryCeZvTEIan1LcDRxO8VJRWdumvcTaMmOBjMOV3GC0wR jSaCGE+PuuhfJE/EvDOeJnlRfNQo4VYfFLc2f9eNrFrbMcX42oHGSALBGoYd4/8XB9ob +HN4ile9h0gXMZ0i86WOgReR3+DcIOr7cKbQ9YO/vw+rBA8AIKNgxYrYK2AWwBGN6Ove Qx4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9K/J0BXXkg1V7+TopOSDu0/Aqdt/mMj4ZSjiFenqJH4=; b=BZnZJn3a+maTHuWTbg2rPFvk/Y8uqCAU0155RZRPsvYABPNoJ1YBJCtLhbtFkRQAzX 7atOyjZIvPvg6Sl+tobbGOJcIM5noqd8ffvDrJyr6/DBkjVQu/sNExf8XPx3NhpFbxjJ 7mmAEMwi2odYTBtAbaid68yvqK3OuR00NuS+H6yApc5SJD4+IRYUDKAxTiGyYprf7njo y794HWd5zUUD+2ixG1tJIDMLDr9kcLwaKh++qjm+kpX9TQJjban5ifTYN/SccGxdvE/S AdHwp3/cH6edDXvYJdax1jlOFbkYcbeFLLx9Z6kM/ziDOUof5aRPHxfMCfC343lfaUao /Tbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=XkRz1vAW; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j191si34746458pgd.88.2019.07.31.15.43.51; Wed, 31 Jul 2019 15:43:51 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=XkRz1vAW; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730086AbfGaWnu (ORCPT + 5 others); Wed, 31 Jul 2019 18:43:50 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:49258 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730038AbfGaWnu (ORCPT ); Wed, 31 Jul 2019 18:43:50 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x6VMgfeH026871; Wed, 31 Jul 2019 17:42:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1564612961; bh=9K/J0BXXkg1V7+TopOSDu0/Aqdt/mMj4ZSjiFenqJH4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XkRz1vAWQLHKKSJe/tZLpTEEwx6B7dBcPNNBunjhkK12rY9tPmW1BeaD6upeAmzt/ kBMzRjpemMTmnjlDdhMmzbs7JLoJNY+NlLumCWUwAsmEN2I9Sq+0ElgKUANU0bB/XI ZaNeV7Gouyu4JuyWppthhUObCi0l/2fjflqicvvs= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x6VMgfoN072378 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2019 17:42:41 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 31 Jul 2019 17:42:40 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 31 Jul 2019 17:42:40 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6VMgeVh072677; Wed, 31 Jul 2019 17:42:40 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6VMgeZ25759; Wed, 31 Jul 2019 17:42:40 -0500 (CDT) From: Suman Anna To: Marc Zyngier , Thomas Gleixner , Jason Cooper CC: Rob Herring , David Lechner , Tony Lindgren , "Andrew F. Davis" , Roger Quadros , Lokesh Vutla , Grygorii Strashko , Sekhar Nori , Murali Karicheri , , , , , Suman Anna , Rob Herring Subject: [PATCH v2 1/6] dt-bindings: irqchip: Add PRUSS interrupt controller bindings Date: Wed, 31 Jul 2019 17:41:44 -0500 Message-ID: <20190731224149.11153-2-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731224149.11153-1-s-anna@ti.com> References: <20190731224149.11153-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The Programmable Real-Time Unit Subsystem (PRUSS) contains an interrupt controller (INTC) that can handle various system input events and post interrupts back to the device-level initiators. The INTC can support upto 64 input events on most SoCs with individual control configuration and hardware prioritization. These events are mapped onto 10 output interrupt lines through two levels of many-to-one mapping support. Different interrupt lines are routed to the individual PRU cores or to the host CPU or to other PRUSS instances. The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The ICSSG interrupt controller on K3 SoCs provide a higher number of host interrupts (20 vs 10) and can handle an increased number of input events (160 vs 64) from various SoC interrupt sources. Add the bindings document for these interrupt controllers on all the applicable SoCs. It covers the OMAP architecture SoCs - AM33xx, AM437x and AM57xx; the Keystone 2 architecture based 66AK2G SoC; the Davinci architecture based OMAPL138 SoCs, and the K3 architecture based AM65x and J721E SoCs. Signed-off-by: Suman Anna Signed-off-by: Andrew F. Davis Signed-off-by: Roger Quadros Reviewed-by: Rob Herring --- v2: - Updated the interrupt-names from "hostX" to "host_intrX" and updated example accordingly - Updated the description for interrupts property - Used generic interrupt controller in descriptions rather than GIC - Added some clarifications about interrupt names to PRUSS INTC output interrupts - Picked up Rob's reviewed-by v1: https://patchwork.kernel.org/patch/11034567/ .../interrupt-controller/ti,pruss-intc.txt | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt -- 2.22.0 diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt new file mode 100644 index 000000000000..17c7b49a7f2e --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.txt @@ -0,0 +1,98 @@ +PRU ICSS INTC on TI SoCs +======================== + +Each PRUSS has a single interrupt controller instance that is common to both +the PRU cores. Most interrupt controllers can route 64 input events which are +then mapped to 10 possible output interrupts through two levels of mapping. +The input events can be triggered by either the PRUs and/or various other PRUSS +internal and external peripherals. The first 2 output interrupts (0 & 1) are +fed exclusively to the internal PRU cores, with the remaining 8 (2 through 9) +connected to external interrupt controllers including the MPU and/or other +PRUSS instances, DSPs or devices. + +The K3 family of SoCs can handle 160 input events that can be mapped to 20 +different possible output interrupts. The additional output interrupts (10 +through 19) are connected to new sub-modules within the ICSSG instances. + +This interrupt-controller node should be defined as a child node of the +corresponding PRUSS node. The node should be named "interrupt-controller". +Please see the overall PRUSS bindings document for additional details +including a complete example, + Documentation/devicetree/bindings/soc/ti/ti,pruss.txt + +Required Properties: +-------------------- +- compatible : should be one of the following, + "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs, + AM335x family of SoCs, + AM437x family of SoCs, + AM57xx family of SoCs + 66AK2G family of SoCs + "ti,icssg-intc" for K3 AM65x & J721E family of SoCs +- reg : base address and size for the PRUSS INTC sub-module +- interrupts : all the interrupts generated towards the main host + processor in the SoC. The format depends on the + interrupt specifier for the particular SoC's Arm + parent interrupt controller. A shared interrupt can + be skipped if the desired destination and usage is by + a different processor/device. +- interrupt-names : should use one of the following names for each valid + host event interrupt connected to Arm interrupt + controller, the name should match the corresponding + host event interrupt number, + "host_intr0", "host_intr1", "host_intr2", + "host_intr3", "host_intr4", "host_intr5", + "host_intr6" or "host_intr7" +- interrupt-controller : mark this node as an interrupt controller +- #interrupt-cells : should be 1. Client users shall use the PRU System + event number (the interrupt source that the client + is interested in) as the value of the interrupts + property in their node + +Optional Properties: +-------------------- +The following properties are _required_ only for some SoCs. If none of the below +properties are defined, it implies that all the PRUSS INTC output interrupts 2 +through 9 (host_intr0 through host_intr7) are connected exclusively to the +Arm interrupt controller. + +- ti,irqs-reserved : an array of 8-bit elements of host interrupts between + 0 and 7 (corresponding to PRUSS INTC output interrupts + 2 through 9) that are not connected to the Arm + interrupt controller. + Eg: AM437x and 66AK2G SoCs do not have "host_intr5" + interrupt connected to MPU +- ti,irqs-shared : an array of 8-bit elements of host interrupts between + 0 and 7 (corresponding to PRUSS INTC output interrupts + 2 through 9) that are also connected to other devices + or processors in the SoC. + Eg: AM65x and J721E SoCs have "host_intr5", + "host_intr6" and "host_intr7" interrupts + connected to MPU, and other ICSSG instances + + +Example: +-------- + +1. /* AM33xx PRU-ICSS */ + pruss: pruss@0 { + compatible = "ti,am3356-pruss"; + reg = <0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ... + + pruss_intc: interrupt-controller@20000 { + compatible = "ti,pruss-intc"; + reg = <0x20000 0x2000>; + interrupts = <20 21 22 23 24 25 26 27>; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + interrupt-controller; + #interrupt-cells = <1>; + ti,irqs-shared = /bits/ 8 <0 6 7>; + }; + }; From patchwork Wed Jul 31 22:41:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 170277 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp4576569ile; Wed, 31 Jul 2019 15:43:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqyG4sF9tH/cwh96CJ8+55iHuhPfAa01fQEqZSuYzlO40SqR7jsRA4caexDMR4ACrpbvGG+/ X-Received: by 2002:a65:6552:: with SMTP id a18mr107487063pgw.208.1564613035910; Wed, 31 Jul 2019 15:43:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564613035; cv=none; d=google.com; s=arc-20160816; b=LGQ68eH+QtRzQx3A6Oa4YgLqo3kQ5zH004Xye9p9xETYJEXicFjGxm7RGIwGMJqwSu n3ofMr5qls927zzYZXFvjE5LCPpHywsGkxa/Fkj0acCuGho0G5LEjIN8el/semoeaEmS jgTgmUBKKUauKXyk+htOfj5M9PYllRL/Apri2Y7TkLtfG4Y0WpRI2ypggnEtlTGEczYB qLbG8BK5zJyIaISNf12E70CNpmYaW5qXTxtH33Casa4MP6+DJv1FvumcrLj+cp5p62Rc TPdBreB4MyrrgOllZnan41XHfyNMfB7TXVbSWwYbqHnkm3Q046mHCKf9nxy9mWIZz0Pa h3Hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/9Ma6uSBzOyvNJSA6eCHG0NmCUFeMZ7i4htZ2o0Tc5U=; b=pohK+6O+clWt8pUyart910dujX5X3HXZeZd6fOnBjNr8dYBq1zfz7HS4CE8PU8jo8Y iAYrGzGLDU0dB1G9PUC4DOq2EqAP7EWfK/gme5LZS9zUL4xMR5WFIbh2iBf4rN5GIIWc sJRfgyngQi8LKnQrOQ4nckx/rGBqhcEgSIUalX8ghAXwLr1A437+9dRUtrgrXTzTOkr/ n5EBuKwDhkX2MucJqONvs+G8SM9rWzJPtuumkGT30zhF1pNMc2MicsUrMUnoNCZ2lfcp GKAAe72DXKyXJBAzY0p4EHBYu3dOGtz5xEiq8NrbpFZ4H1f6IxwcOZSI8MHUkTJbHhSc AURg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eGdUMgII; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j191si34746458pgd.88.2019.07.31.15.43.55; Wed, 31 Jul 2019 15:43:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=eGdUMgII; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730273AbfGaWnz (ORCPT + 5 others); Wed, 31 Jul 2019 18:43:55 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:48384 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730184AbfGaWnx (ORCPT ); Wed, 31 Jul 2019 18:43:53 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x6VMgg15095981; Wed, 31 Jul 2019 17:42:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1564612962; bh=/9Ma6uSBzOyvNJSA6eCHG0NmCUFeMZ7i4htZ2o0Tc5U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eGdUMgIIVllgtzVuG8zAhy9naFmGzBa9Tsqg1e/2KX/NhwiOlzCXIFq9rDY4IgQ/E 7kVCdswVnryyDIMoD9sZcaE4PocfuscuQ8oykCbXi48avvMa9ZoRNCx+A50PC9H+nB HoydzHEOOg0y7KyNptpSgqNzXHvRhRvP/Zo0BRaQ= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x6VMggHk001890 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 31 Jul 2019 17:42:42 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 31 Jul 2019 17:42:41 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 31 Jul 2019 17:42:41 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6VMgfoB104327; Wed, 31 Jul 2019 17:42:41 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6VMgfZ25779; Wed, 31 Jul 2019 17:42:41 -0500 (CDT) From: Suman Anna To: Marc Zyngier , Thomas Gleixner , Jason Cooper CC: Rob Herring , David Lechner , Tony Lindgren , "Andrew F. Davis" , Roger Quadros , Lokesh Vutla , Grygorii Strashko , Sekhar Nori , Murali Karicheri , , , , , Suman Anna Subject: [PATCH v2 2/6] irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts Date: Wed, 31 Jul 2019 17:41:45 -0500 Message-ID: <20190731224149.11153-3-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731224149.11153-1-s-anna@ti.com> References: <20190731224149.11153-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org From: "Andrew F. Davis" The Programmable Real-Time Unit Subsystem (PRUSS) contains a local interrupt controller (INTC) that can handle various system input events and post interrupts back to the device-level initiators. The INTC can support upto 64 input events with individual control configuration and hardware prioritization. These events are mapped onto 10 output interrupt lines through two levels of many-to-one mapping support. Different interrupt lines are routed to the individual PRU cores or to the host CPU, or to other devices on the SoC. Some of these events are sourced from peripherals or other sub-modules within that PRUSS, while a few others are sourced from SoC-level peripherals/devices. The PRUSS INTC platform driver manages this PRUSS interrupt controller and implements an irqchip driver to provide a Linux standard way for the PRU client users to enable/disable/ack/re-trigger a PRUSS system event. The system events to interrupt channels and output interrupts relies on the mapping configuration provided either through the PRU firmware blob or via the PRU application's device tree node. The mappings will be programmed during the boot/shutdown of a PRU core. The PRUSS INTC module is reference counted during the interrupt setup phase through the irqchip's irq_request_resources() and irq_release_resources() ops. This restricts the module from being removed as long as there are active interrupt users. The driver currently supports and can be built for OMAP architecture based AM335x, AM437x and AM57xx SoCs; Keystone2 architecture based 66AK2G SoCs and Davinci architecture based OMAP-L13x/AM18x/DA850 SoCs. All of these SoCs support 64 system events, 10 interrupt channels and 10 output interrupt lines per PRUSS INTC with a few SoC integration differences. NOTE: Each PRU-ICSS's INTC on AM57xx SoCs is preceded by a Crossbar that enables multiple external events to be routed to a specific number of input interrupt events. Any non-default external interrupt event directed towards PRUSS needs this crossbar to be setup properly. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Signed-off-by: Roger Quadros --- v2: - Addressed all of David Lechner's comments - Dropped irq_retrigger callback - Updated interrupt names from "hostX" to "host_intrX" - Moved host_mask variable to patch 4 v1: https://patchwork.kernel.org/patch/11034545/ v0: https://patchwork.kernel.org/patch/10795761/ drivers/irqchip/Kconfig | 10 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-pruss-intc.c | 338 +++++++++++++++++++++++++++++++ 3 files changed, 349 insertions(+) create mode 100644 drivers/irqchip/irq-pruss-intc.c -- 2.22.0 diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 80e10f4e213a..dc6b5aa77a5d 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -471,6 +471,16 @@ config TI_SCI_INTA_IRQCHIP If you wish to use interrupt aggregator irq resources managed by the TI System Controller, say Y here. Otherwise, say N. +config TI_PRUSS_INTC + tristate "TI PRU-ICSS Interrupt Controller" + depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE + select IRQ_DOMAIN + help + This enables support for the PRU-ICSS Local Interrupt Controller + present within a PRU-ICSS subsystem present on various TI SoCs. + The PRUSS INTC enables various interrupts to be routed to multiple + different processors within the SoC. + endmenu config SIFIVE_PLIC diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 8d0fcec6ab23..a02e652ca805 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -102,3 +102,4 @@ obj-$(CONFIG_MADERA_IRQ) += irq-madera.o obj-$(CONFIG_LS1X_IRQ) += irq-ls1x.o obj-$(CONFIG_TI_SCI_INTR_IRQCHIP) += irq-ti-sci-intr.o obj-$(CONFIG_TI_SCI_INTA_IRQCHIP) += irq-ti-sci-inta.o +obj-$(CONFIG_TI_PRUSS_INTC) += irq-pruss-intc.o diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c new file mode 100644 index 000000000000..4a9456544fd0 --- /dev/null +++ b/drivers/irqchip/irq-pruss-intc.c @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PRU-ICSS INTC IRQChip driver for various TI SoCs + * + * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Andrew F. Davis + * Suman Anna + */ + +#include +#include +#include +#include +#include +#include + +/* + * Number of host interrupts reaching the main MPU sub-system. Note that this + * is not the same as the total number of host interrupts supported by the PRUSS + * INTC instance + */ +#define MAX_NUM_HOST_IRQS 8 + +/* minimum starting host interrupt number for MPU */ +#define MIN_PRU_HOST_INT 2 + +/* maximum number of system events */ +#define MAX_PRU_SYS_EVENTS 64 + +/* PRU_ICSS_INTC registers */ +#define PRU_INTC_REVID 0x0000 +#define PRU_INTC_CR 0x0004 +#define PRU_INTC_GER 0x0010 +#define PRU_INTC_GNLR 0x001c +#define PRU_INTC_SISR 0x0020 +#define PRU_INTC_SICR 0x0024 +#define PRU_INTC_EISR 0x0028 +#define PRU_INTC_EICR 0x002c +#define PRU_INTC_HIEISR 0x0034 +#define PRU_INTC_HIDISR 0x0038 +#define PRU_INTC_GPIR 0x0080 +#define PRU_INTC_SRSR0 0x0200 +#define PRU_INTC_SRSR1 0x0204 +#define PRU_INTC_SECR0 0x0280 +#define PRU_INTC_SECR1 0x0284 +#define PRU_INTC_ESR0 0x0300 +#define PRU_INTC_ESR1 0x0304 +#define PRU_INTC_ECR0 0x0380 +#define PRU_INTC_ECR1 0x0384 +#define PRU_INTC_CMR(x) (0x0400 + (x) * 4) +#define PRU_INTC_HMR(x) (0x0800 + (x) * 4) +#define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4) +#define PRU_INTC_SIPR0 0x0d00 +#define PRU_INTC_SIPR1 0x0d04 +#define PRU_INTC_SITR0 0x0d80 +#define PRU_INTC_SITR1 0x0d84 +#define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) +#define PRU_INTC_HIER 0x1500 + +/* HIPIR register bit-fields */ +#define INTC_HIPIR_NONE_HINT 0x80000000 + +/** + * struct pruss_intc - PRUSS interrupt controller structure + * @irqs: kernel irq numbers corresponding to PRUSS host interrupts + * @base: base virtual address of INTC register space + * @irqchip: irq chip for this interrupt controller + * @domain: irq domain for this interrupt controller + * @lock: mutex to serialize access to INTC + */ +struct pruss_intc { + unsigned int irqs[MAX_NUM_HOST_IRQS]; + void __iomem *base; + struct irq_chip *irqchip; + struct irq_domain *domain; + struct mutex lock; /* PRUSS INTC lock */ +}; + +static inline u32 pruss_intc_read_reg(struct pruss_intc *intc, unsigned int reg) +{ + return readl_relaxed(intc->base + reg); +} + +static inline void pruss_intc_write_reg(struct pruss_intc *intc, + unsigned int reg, u32 val) +{ + writel_relaxed(val, intc->base + reg); +} + +static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg, + unsigned int sysevent) +{ + if (!intc) + return -EINVAL; + + if (sysevent >= MAX_PRU_SYS_EVENTS) + return -EINVAL; + + pruss_intc_write_reg(intc, reg, sysevent); + + return 0; +} + +static void pruss_intc_init(struct pruss_intc *intc) +{ + int i; + + /* configure polarity to active high for all system interrupts */ + pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff); + pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff); + + /* configure type to pulse interrupt for all system interrupts */ + pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0); + pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0); + + /* clear all 16 interrupt channel map registers */ + for (i = 0; i < 16; i++) + pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0); + + /* clear all 3 host interrupt map registers */ + for (i = 0; i < 3; i++) + pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0); +} + +static void pruss_intc_irq_ack(struct irq_data *data) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + unsigned int hwirq = data->hwirq; + + pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq); +} + +static void pruss_intc_irq_mask(struct irq_data *data) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + unsigned int hwirq = data->hwirq; + + pruss_intc_check_write(intc, PRU_INTC_EICR, hwirq); +} + +static void pruss_intc_irq_unmask(struct irq_data *data) +{ + struct pruss_intc *intc = irq_data_get_irq_chip_data(data); + unsigned int hwirq = data->hwirq; + + pruss_intc_check_write(intc, PRU_INTC_EISR, hwirq); +} + +static int pruss_intc_irq_reqres(struct irq_data *data) +{ + if (!try_module_get(THIS_MODULE)) + return -ENODEV; + + return 0; +} + +static void pruss_intc_irq_relres(struct irq_data *data) +{ + module_put(THIS_MODULE); +} + +static int pruss_intc_irq_domain_map(struct irq_domain *d, unsigned int virq, + irq_hw_number_t hw) +{ + struct pruss_intc *intc = d->host_data; + + irq_set_chip_data(virq, intc); + irq_set_chip_and_handler(virq, intc->irqchip, handle_level_irq); + + return 0; +} + +static void pruss_intc_irq_domain_unmap(struct irq_domain *d, unsigned int virq) +{ + irq_set_chip_and_handler(virq, NULL, NULL); + irq_set_chip_data(virq, NULL); +} + +static const struct irq_domain_ops pruss_intc_irq_domain_ops = { + .xlate = irq_domain_xlate_onecell, + .map = pruss_intc_irq_domain_map, + .unmap = pruss_intc_irq_domain_unmap, +}; + +static void pruss_intc_irq_handler(struct irq_desc *desc) +{ + unsigned int irq = irq_desc_get_irq(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + struct pruss_intc *intc = irq_get_handler_data(irq); + u32 hipir; + unsigned int virq; + int i, hwirq; + + chained_irq_enter(chip, desc); + + /* find our host irq number */ + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) + if (intc->irqs[i] == irq) + break; + if (i == MAX_NUM_HOST_IRQS) + goto err; + + i += MIN_PRU_HOST_INT; + + /* get highest priority pending PRUSS system event */ + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); + while (!(hipir & INTC_HIPIR_NONE_HINT)) { + hwirq = hipir & GENMASK(9, 0); + virq = irq_linear_revmap(intc->domain, hwirq); + + /* + * NOTE: manually ACK any system events that do not have a + * handler mapped yet + */ + if (unlikely(!virq)) + pruss_intc_check_write(intc, PRU_INTC_SICR, hwirq); + else + generic_handle_irq(virq); + + /* get next system event */ + hipir = pruss_intc_read_reg(intc, PRU_INTC_HIPIR(i)); + } +err: + chained_irq_exit(chip, desc); +} + +static int pruss_intc_probe(struct platform_device *pdev) +{ + static const char * const irq_names[] = { + "host_intr0", "host_intr1", "host_intr2", "host_intr3", + "host_intr4", "host_intr5", "host_intr6", "host_intr7", }; + struct device *dev = &pdev->dev; + struct pruss_intc *intc; + struct resource *res; + struct irq_chip *irqchip; + int i, irq; + + intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); + if (!intc) + return -ENOMEM; + platform_set_drvdata(pdev, intc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + intc->base = devm_ioremap_resource(dev, res); + if (IS_ERR(intc->base)) { + dev_err(dev, "failed to parse and map intc memory resource\n"); + return PTR_ERR(intc->base); + } + + dev_dbg(dev, "intc memory: pa %pa size 0x%zx va %pK\n", &res->start, + (size_t)resource_size(res), intc->base); + + mutex_init(&intc->lock); + + pruss_intc_init(intc); + + irqchip = devm_kzalloc(dev, sizeof(*irqchip), GFP_KERNEL); + if (!irqchip) + return -ENOMEM; + + irqchip->irq_ack = pruss_intc_irq_ack; + irqchip->irq_mask = pruss_intc_irq_mask; + irqchip->irq_unmask = pruss_intc_irq_unmask; + irqchip->irq_request_resources = pruss_intc_irq_reqres; + irqchip->irq_release_resources = pruss_intc_irq_relres; + irqchip->name = dev_name(dev); + intc->irqchip = irqchip; + + /* always 64 events */ + intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS, + &pruss_intc_irq_domain_ops, intc); + if (!intc->domain) + return -ENOMEM; + + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { + irq = platform_get_irq_byname(pdev, irq_names[i]); + if (irq < 0) { + dev_err(dev, "platform_get_irq_byname failed for %s : %d\n", + irq_names[i], irq); + goto fail_irq; + } + + intc->irqs[i] = irq; + irq_set_handler_data(irq, intc); + irq_set_chained_handler(irq, pruss_intc_irq_handler); + } + + return 0; + +fail_irq: + while (--i >= 0) { + if (intc->irqs[i]) + irq_set_chained_handler_and_data(intc->irqs[i], NULL, + NULL); + } + irq_domain_remove(intc->domain); + return irq; +} + +static int pruss_intc_remove(struct platform_device *pdev) +{ + struct pruss_intc *intc = platform_get_drvdata(pdev); + unsigned int hwirq; + int i; + + for (i = 0; i < MAX_NUM_HOST_IRQS; i++) { + if (intc->irqs[i]) + irq_set_chained_handler_and_data(intc->irqs[i], NULL, + NULL); + } + + for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) + irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq)); + irq_domain_remove(intc->domain); + + return 0; +} + +static const struct of_device_id pruss_intc_of_match[] = { + { .compatible = "ti,pruss-intc", }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, pruss_intc_of_match); + +static struct platform_driver pruss_intc_driver = { + .driver = { + .name = "pruss-intc", + .of_match_table = pruss_intc_of_match, + }, + .probe = pruss_intc_probe, + .remove = pruss_intc_remove, +}; +module_platform_driver(pruss_intc_driver); + +MODULE_AUTHOR("Andrew F. Davis "); +MODULE_AUTHOR("Suman Anna "); +MODULE_DESCRIPTION("TI PRU-ICSS INTC Driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Jul 31 22:41:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 170278 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp4576676ile; Wed, 31 Jul 2019 15:44:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqw6BeNW5AQEyCtGEbYnfnIkTdVR+wXTuEkOWT2kk7mUREW9G7jyAs98j+653eb84oNxPSlr X-Received: by 2002:a17:90a:8688:: with SMTP id p8mr5235152pjn.57.1564613042286; Wed, 31 Jul 2019 15:44:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564613042; cv=none; d=google.com; s=arc-20160816; b=Bes3OfA9qx8M2H1TJw/c/oH/CNlJRQQu1KDJFixiAz65rBk1pN4UdcP73pPNW1YrUg 2v+GbzGnAd8PK0sB83ogq4PeJqej0YeH+1g+OE8sPHmBVBpWQbuYniQiigtUyA2Tgi5L T1WT9m8pt+u0tkRpKkTTlJQzf9dLz6SqTp7AbqQgWtALl5Usag0/Sdqh0h32yyh+1EJ/ LfxS+7244um1OOXIJ0VguHU8lExI7ns9hf5DfnnMLXkZtqGwiSVf7m0p/3MPJI++ByjN s9jaTXC9Q27SyaIYk/MCFxJXoewp9DKOqnj3MJzPPvScgZvon4frNho0vOra6GoxQmWA Pw2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Bhsdx4U0VO7X8x31n3G9Tta7yCxO4I1Lew0AJtA66mU=; b=XFId+FyPQj87MXLP2ZrvZ1452ff8UlJY7U4ZX2JmKzhwSZOeMuDf3KIPpkHza+1zuT vNsDNnJCfVEgrtFLYv4vSa6gfqMlkERY8DVvf1D3ZFxAOCjcVKmbtc9ZtnKqmtIhHgQD 0d1R4WszUdgi8L4S4ESf0NhYkCf68O7ZKTJYpGSSALODB4moD81PLVBDUhkX0SeAfKdz Dg9Zq/vy4HUBf4jp61RQ5jUuCWkpLXFuD+aH/IwRIoZLXagYd/lPdvkqL7E8yxr/12ZW WI7S70JZs5LjdXP4HTOrNb0G1au4B+c+J80Oj080JbBB8MOJ/dPjcFLLOMx/ewg2apev dXdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=asMoq1XP; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Davis" , Roger Quadros , Lokesh Vutla , Grygorii Strashko , Sekhar Nori , Murali Karicheri , , , , , Suman Anna Subject: [PATCH v2 6/6] irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs Date: Wed, 31 Jul 2019 17:41:49 -0500 Message-ID: <20190731224149.11153-7-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731224149.11153-1-s-anna@ti.com> References: <20190731224149.11153-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org The K3 AM65x and J721E SoCs have the next generation of the PRU-ICSS IP, commonly called ICSSG. The PRUSS INTC present within the ICSSG supports more System Events (160 vs 64), more Interrupt Channels and Host Interrupts (20 vs 10) compared to the previous generation PRUSS INTC instances. The first 2 and the last 10 of these host interrupt lines are used by the PRU and other auxiliary cores and sub-modules within the ICSSG, with 8 host interrupts connected to MPU. The host interrupts 5, 6, 7 are also connected to the other ICSSG instances within the SoC and can be partitioned as per system integration through the board dts files. Enhance the PRUSS INTC driver to add support for this ICSSG INTC instance. This support is added using specific compatible and match data and updating the code to use this data instead of the current hard-coded macros. The INTC config structure is updated to use the higher events and channels on all SoCs, while limiting the actual processing to only the relevant number of events/channels/interrupts. Signed-off-by: Suman Anna --- v2: - Rebased patch with indexed macros like ESRx, ECRx where x = 0,1 dropped v1: https://patchwork.kernel.org/patch/11034543/ drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-pruss-intc.c | 181 +++++++++++++++++-------- include/linux/irqchip/irq-pruss-intc.h | 4 +- 3 files changed, 126 insertions(+), 61 deletions(-) -- 2.22.0 diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index dc6b5aa77a5d..a98bfec6b364 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -473,7 +473,7 @@ config TI_SCI_INTA_IRQCHIP config TI_PRUSS_INTC tristate "TI PRU-ICSS Interrupt Controller" - depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE + depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM437X || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3 select IRQ_DOMAIN help This enables support for the PRU-ICSS Local Interrupt Controller diff --git a/drivers/irqchip/irq-pruss-intc.c b/drivers/irqchip/irq-pruss-intc.c index 59e26dfbb179..891a14b6c399 100644 --- a/drivers/irqchip/irq-pruss-intc.c +++ b/drivers/irqchip/irq-pruss-intc.c @@ -7,6 +7,7 @@ * Suman Anna */ +#include #include #include #include @@ -26,9 +27,6 @@ /* minimum starting host interrupt number for MPU */ #define MIN_PRU_HOST_INT 2 -/* maximum number of host interrupts */ -#define MAX_PRU_HOST_INT 10 - /* PRU_ICSS_INTC registers */ #define PRU_INTC_REVID 0x0000 #define PRU_INTC_CR 0x0004 @@ -42,19 +40,14 @@ #define PRU_INTC_HIDISR 0x0038 #define PRU_INTC_GPIR 0x0080 #define PRU_INTC_SRSR(x) (0x0200 + (x) * 4) -#define PRU_INTC_SECR0 0x0280 -#define PRU_INTC_SECR1 0x0284 -#define PRU_INTC_ESR0 0x0300 -#define PRU_INTC_ESR1 0x0304 -#define PRU_INTC_ECR0 0x0380 -#define PRU_INTC_ECR1 0x0384 +#define PRU_INTC_SECR(x) (0x0280 + (x) * 4) +#define PRU_INTC_ESR(x) (0x0300 + (x) * 4) +#define PRU_INTC_ECR(x) (0x0380 + (x) * 4) #define PRU_INTC_CMR(x) (0x0400 + (x) * 4) #define PRU_INTC_HMR(x) (0x0800 + (x) * 4) #define PRU_INTC_HIPIR(x) (0x0900 + (x) * 4) -#define PRU_INTC_SIPR0 0x0d00 -#define PRU_INTC_SIPR1 0x0d04 -#define PRU_INTC_SITR0 0x0d80 -#define PRU_INTC_SITR1 0x0d84 +#define PRU_INTC_SIPR(x) (0x0d00 + (x) * 4) +#define PRU_INTC_SITR(x) (0x0d80 + (x) * 4) #define PRU_INTC_HINLR(x) (0x1100 + (x) * 4) #define PRU_INTC_HIER 0x1500 @@ -71,12 +64,23 @@ /* HIPIR register bit-fields */ #define INTC_HIPIR_NONE_HINT 0x80000000 +/** + * struct pruss_intc_match_data - match data to handle SoC variations + * @num_system_events: number of input system events handled by the PRUSS INTC + * @num_host_intrs: number of host interrupts supported by the PRUSS INTC + */ +struct pruss_intc_match_data { + u8 num_system_events; + u8 num_host_intrs; +}; + /** * struct pruss_intc - PRUSS interrupt controller structure * @irqs: kernel irq numbers corresponding to PRUSS host interrupts * @base: base virtual address of INTC register space * @irqchip: irq chip for this interrupt controller * @domain: irq domain for this interrupt controller + * @data: cached PRUSS INTC IP configuration data * @config_map: stored INTC configuration mapping data * @lock: mutex to serialize access to INTC * @host_mask: indicate which HOST IRQs are enabled @@ -88,6 +92,7 @@ struct pruss_intc { void __iomem *base; struct irq_chip *irqchip; struct irq_domain *domain; + const struct pruss_intc_match_data *data; struct pruss_intc_config config_map; struct mutex lock; /* PRUSS INTC lock */ u32 host_mask; @@ -112,7 +117,7 @@ static int pruss_intc_check_write(struct pruss_intc *intc, unsigned int reg, if (!intc) return -EINVAL; - if (sysevent >= MAX_PRU_SYS_EVENTS) + if (sysevent >= intc->data->num_system_events) return -EINVAL; pruss_intc_write_reg(intc, reg, sysevent); @@ -191,16 +196,28 @@ int pruss_intc_configure(struct device *dev, struct pruss_intc_config *intc_config) { struct pruss_intc *intc; - int i, idx, ret; + int i, idx; s8 ch, host; - u64 sysevt_mask = 0; + u32 num_events, num_intrs, num_regs; + unsigned long *sysevt_bitmap; + u32 *sysevts; u32 ch_mask = 0; u32 host_mask = 0; + int ret = 0; intc = to_pruss_intc(dev); if (IS_ERR(intc)) return PTR_ERR(intc); + num_events = intc->data->num_system_events; + num_intrs = intc->data->num_host_intrs; + num_regs = DIV_ROUND_UP(num_events, 32); + + sysevt_bitmap = bitmap_zalloc(num_events, GFP_KERNEL); + if (!sysevt_bitmap) + return -ENOMEM; + sysevts = (u32 *)sysevt_bitmap; + mutex_lock(&intc->lock); /* @@ -208,7 +225,7 @@ int pruss_intc_configure(struct device *dev, * for 4 events, with each event occupying the lower nibble in * a register byte address in little-endian fashion */ - for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { + for (i = 0; i < num_events; i++) { ch = intc_config->sysev_to_ch[i]; if (ch < 0) continue; @@ -223,7 +240,7 @@ int pruss_intc_configure(struct device *dev, intc->config_map.sysev_to_ch[i] = ch; pruss_intc_update_cmr(intc, i, ch); - sysevt_mask |= BIT_ULL(i); + bitmap_set(sysevt_bitmap, i, 1); ch_mask |= BIT(ch); idx = i / CMR_EVT_PER_REG; @@ -236,7 +253,7 @@ int pruss_intc_configure(struct device *dev, * 4 channels, with each channel occupying the lower nibble in * a register byte address in little-endian fashion */ - for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { + for (i = 0; i < num_intrs; i++) { host = intc_config->ch_to_host[i]; if (host < 0) continue; @@ -267,17 +284,19 @@ int pruss_intc_configure(struct device *dev, pruss_intc_read_reg(intc, PRU_INTC_HMR(idx))); } - dev_info(dev, "configured system_events = 0x%016llx intr_channels = 0x%08x host_intr = 0x%08x\n", - sysevt_mask, ch_mask, host_mask); + dev_info(dev, "configured system_events[%d-0] = %*pb\n", + num_events - 1, num_events, sysevt_bitmap); + dev_info(dev, "configured intr_channels = 0x%08x host_intr = 0x%08x\n", + ch_mask, host_mask); /* enable system events, writing 0 has no-effect */ - pruss_intc_write_reg(intc, PRU_INTC_ESR0, lower_32_bits(sysevt_mask)); - pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask)); - pruss_intc_write_reg(intc, PRU_INTC_ESR1, upper_32_bits(sysevt_mask)); - pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask)); + for (i = 0; i < num_regs; i++) { + pruss_intc_write_reg(intc, PRU_INTC_ESR(i), sysevts[i]); + pruss_intc_write_reg(intc, PRU_INTC_SECR(i), sysevts[i]); + } /* enable host interrupts */ - for (i = 0; i < MAX_PRU_HOST_INT; i++) { + for (i = 0; i < num_intrs; i++) { if (host_mask & BIT(i)) pruss_intc_write_reg(intc, PRU_INTC_HIEISR, i); } @@ -286,9 +305,7 @@ int pruss_intc_configure(struct device *dev, pruss_intc_write_reg(intc, PRU_INTC_GER, 1); intc->host_mask |= host_mask; - - mutex_unlock(&intc->lock); - return 0; + goto out; fail_ch: while (--i >= 0) { @@ -297,7 +314,7 @@ int pruss_intc_configure(struct device *dev, pruss_intc_update_hmr(intc, i, 0); } } - i = ARRAY_SIZE(intc_config->sysev_to_ch); + i = num_events; fail_evt: while (--i >= 0) { if (intc_config->sysev_to_ch[i] >= 0) { @@ -305,7 +322,9 @@ int pruss_intc_configure(struct device *dev, pruss_intc_update_cmr(intc, i, 0); } } +out: mutex_unlock(&intc->lock); + bitmap_free(sysevt_bitmap); return ret; } EXPORT_SYMBOL_GPL(pruss_intc_configure); @@ -325,28 +344,39 @@ int pruss_intc_unconfigure(struct device *dev, struct pruss_intc *intc; int i; s8 ch, host; - u64 sysevt_mask = 0; + u32 num_events, num_intrs, num_regs; + unsigned long *sysevt_bitmap; + u32 *sysevts; u32 host_mask = 0; intc = to_pruss_intc(dev); if (IS_ERR(intc)) return PTR_ERR(intc); + num_events = intc->data->num_system_events; + num_intrs = intc->data->num_host_intrs; + num_regs = DIV_ROUND_UP(num_events, 32); + + sysevt_bitmap = bitmap_zalloc(num_events, GFP_KERNEL); + if (!sysevt_bitmap) + return -ENOMEM; + sysevts = (u32 *)sysevt_bitmap; + mutex_lock(&intc->lock); - for (i = 0; i < ARRAY_SIZE(intc_config->sysev_to_ch); i++) { + for (i = 0; i < num_events; i++) { ch = intc_config->sysev_to_ch[i]; if (ch < 0) continue; /* mark sysevent free in global map */ intc->config_map.sysev_to_ch[i] = PRU_INTC_FREE; - sysevt_mask |= BIT_ULL(i); + bitmap_set(sysevt_bitmap, i, 1); /* clear the map using reset value 0 */ pruss_intc_update_cmr(intc, i, 0); } - for (i = 0; i < ARRAY_SIZE(intc_config->ch_to_host); i++) { + for (i = 0; i < num_intrs; i++) { host = intc_config->ch_to_host[i]; if (host < 0) continue; @@ -358,24 +388,26 @@ int pruss_intc_unconfigure(struct device *dev, pruss_intc_update_hmr(intc, i, 0); } - dev_info(dev, "unconfigured system_events = 0x%016llx host_intr = 0x%08x\n", - sysevt_mask, host_mask); + dev_info(dev, "unconfigured system_events[%d-0] = %*pb\n", + num_events - 1, num_events, sysevt_bitmap); + dev_info(dev, "unconfigured host_intr = 0x%08x\n", host_mask); - /* disable system events, writing 0 has no-effect */ - pruss_intc_write_reg(intc, PRU_INTC_ECR0, lower_32_bits(sysevt_mask)); - pruss_intc_write_reg(intc, PRU_INTC_ECR1, upper_32_bits(sysevt_mask)); - /* clear any pending status */ - pruss_intc_write_reg(intc, PRU_INTC_SECR0, lower_32_bits(sysevt_mask)); - pruss_intc_write_reg(intc, PRU_INTC_SECR1, upper_32_bits(sysevt_mask)); + for (i = 0; i < num_regs; i++) { + /* disable system events, writing 0 has no-effect */ + pruss_intc_write_reg(intc, PRU_INTC_ECR(i), sysevts[i]); + /* clear any pending status */ + pruss_intc_write_reg(intc, PRU_INTC_SECR(i), sysevts[i]); + } /* disable host interrupts */ - for (i = 0; i < MAX_PRU_HOST_INT; i++) { + for (i = 0; i < num_intrs; i++) { if (host_mask & BIT(i)) pruss_intc_write_reg(intc, PRU_INTC_HIDISR, i); } intc->host_mask &= ~host_mask; mutex_unlock(&intc->lock); + bitmap_free(sysevt_bitmap); return 0; } @@ -384,21 +416,28 @@ EXPORT_SYMBOL_GPL(pruss_intc_unconfigure); static void pruss_intc_init(struct pruss_intc *intc) { int i; + int num_chnl_map_regs = DIV_ROUND_UP(intc->data->num_system_events, + CMR_EVT_PER_REG); + int num_host_intr_regs = DIV_ROUND_UP(intc->data->num_host_intrs, + HMR_CH_PER_REG); + int num_event_type_regs = + DIV_ROUND_UP(intc->data->num_system_events, 32); - /* configure polarity to active high for all system interrupts */ - pruss_intc_write_reg(intc, PRU_INTC_SIPR0, 0xffffffff); - pruss_intc_write_reg(intc, PRU_INTC_SIPR1, 0xffffffff); - - /* configure type to pulse interrupt for all system interrupts */ - pruss_intc_write_reg(intc, PRU_INTC_SITR0, 0); - pruss_intc_write_reg(intc, PRU_INTC_SITR1, 0); + /* + * configure polarity (SIPR register) to active high and + * type (SITR register) to pulse interrupt for all system events + */ + for (i = 0; i < num_event_type_regs; i++) { + pruss_intc_write_reg(intc, PRU_INTC_SIPR(i), 0xffffffff); + pruss_intc_write_reg(intc, PRU_INTC_SITR(i), 0); + } - /* clear all 16 interrupt channel map registers */ - for (i = 0; i < 16; i++) + /* clear all interrupt channel map registers, 4 events per register */ + for (i = 0; i < num_chnl_map_regs; i++) pruss_intc_write_reg(intc, PRU_INTC_CMR(i), 0); - /* clear all 3 host interrupt map registers */ - for (i = 0; i < 3; i++) + /* clear all host interrupt map registers, 4 channels per register */ + for (i = 0; i < num_host_intr_regs; i++) pruss_intc_write_reg(intc, PRU_INTC_HMR(i), 0); } @@ -549,11 +588,20 @@ static int pruss_intc_probe(struct platform_device *pdev) struct resource *res; struct irq_chip *irqchip; int i, irq, count; + const struct pruss_intc_match_data *data; u8 temp_intr[MAX_NUM_HOST_IRQS] = { 0 }; + u8 max_system_events; + + data = of_device_get_match_data(dev); + if (!data) + return -ENODEV; + + max_system_events = data->num_system_events; intc = devm_kzalloc(dev, sizeof(*intc), GFP_KERNEL); if (!intc) return -ENOMEM; + intc->data = data; platform_set_drvdata(pdev, intc); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -623,8 +671,7 @@ static int pruss_intc_probe(struct platform_device *pdev) irqchip->name = dev_name(dev); intc->irqchip = irqchip; - /* always 64 events */ - intc->domain = irq_domain_add_linear(dev->of_node, MAX_PRU_SYS_EVENTS, + intc->domain = irq_domain_add_linear(dev->of_node, max_system_events, &pruss_intc_irq_domain_ops, intc); if (!intc->domain) return -ENOMEM; @@ -661,6 +708,7 @@ static int pruss_intc_probe(struct platform_device *pdev) static int pruss_intc_remove(struct platform_device *pdev) { struct pruss_intc *intc = platform_get_drvdata(pdev); + u8 max_system_events = intc->data->num_system_events; unsigned int hwirq; int i; @@ -670,15 +718,32 @@ static int pruss_intc_remove(struct platform_device *pdev) NULL); } - for (hwirq = 0; hwirq < MAX_PRU_SYS_EVENTS; hwirq++) + for (hwirq = 0; hwirq < max_system_events; hwirq++) irq_dispose_mapping(irq_find_mapping(intc->domain, hwirq)); irq_domain_remove(intc->domain); return 0; } +static const struct pruss_intc_match_data pruss_intc_data = { + .num_system_events = 64, + .num_host_intrs = 10, +}; + +static const struct pruss_intc_match_data icssg_intc_data = { + .num_system_events = 160, + .num_host_intrs = 20, +}; + static const struct of_device_id pruss_intc_of_match[] = { - { .compatible = "ti,pruss-intc", }, + { + .compatible = "ti,pruss-intc", + .data = &pruss_intc_data, + }, + { + .compatible = "ti,icssg-intc", + .data = &icssg_intc_data, + }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, pruss_intc_of_match); diff --git a/include/linux/irqchip/irq-pruss-intc.h b/include/linux/irqchip/irq-pruss-intc.h index daffc048b303..cc6f9190b04f 100644 --- a/include/linux/irqchip/irq-pruss-intc.h +++ b/include/linux/irqchip/irq-pruss-intc.h @@ -10,10 +10,10 @@ #define __LINUX_IRQ_PRUSS_INTC_H /* maximum number of system events */ -#define MAX_PRU_SYS_EVENTS 64 +#define MAX_PRU_SYS_EVENTS 160 /* maximum number of interrupt channels */ -#define MAX_PRU_CHANNELS 10 +#define MAX_PRU_CHANNELS 20 /* use -1 to mark unassigned events and channels */ #define PRU_INTC_FREE -1