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[176.86.136.19]) by smtp.gmail.com with ESMTPSA id i18sm91905591wrp.91.2019.07.31.13.29.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 Jul 2019 13:29:36 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, sboyd@kernel.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net Cc: vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org Subject: [PATCH v4 01/13] clk: qcom: gcc: limit GPLL0_AO_OUT operating frequency Date: Wed, 31 Jul 2019 22:29:17 +0200 Message-Id: <20190731202929.16443-2-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org> References: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Limit the GPLL0_AO_OUT_MAIN operating frequency as per its hardware specifications. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson Acked-by: Stephen Boyd --- drivers/clk/qcom/clk-alpha-pll.c | 8 ++++++++ drivers/clk/qcom/clk-alpha-pll.h | 1 + drivers/clk/qcom/gcc-qcs404.c | 2 +- 3 files changed, 10 insertions(+), 1 deletion(-) -- 2.22.0 diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 0ced4a5a9a17..ef51f302bdf0 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -730,6 +730,14 @@ static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate, return alpha_huayra_pll_round_rate(rate, *prate, &l, &a); } +const struct clk_ops clk_alpha_pll_fixed_ops = { + .enable = clk_alpha_pll_enable, + .disable = clk_alpha_pll_disable, + .is_enabled = clk_alpha_pll_is_enabled, + .recalc_rate = clk_alpha_pll_recalc_rate, +}; +EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops); + const struct clk_ops clk_alpha_pll_ops = { .enable = clk_alpha_pll_enable, .disable = clk_alpha_pll_disable, diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 66755f0f84fc..6b4eb74706b4 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -104,6 +104,7 @@ struct alpha_pll_config { }; extern const struct clk_ops clk_alpha_pll_ops; +extern const struct clk_ops clk_alpha_pll_fixed_ops; extern const struct clk_ops clk_alpha_pll_hwfsm_ops; extern const struct clk_ops clk_alpha_pll_postdiv_ops; extern const struct clk_ops clk_alpha_pll_huayra_ops; diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 29cf464dd2c8..18c6563889f3 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -330,7 +330,7 @@ static struct clk_alpha_pll gpll0_ao_out_main = { .parent_names = (const char *[]){ "cxo" }, .num_parents = 1, .flags = CLK_IS_CRITICAL, - .ops = &clk_alpha_pll_ops, + .ops = &clk_alpha_pll_fixed_ops, }, }, }; From patchwork Wed Jul 31 20:29:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 170237 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp4463173ile; Wed, 31 Jul 2019 13:30:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqyHnD6pgIW5N5PO3NJxIUBPnSACCI1kBb8TvE00kwtrtNrCJECYfxKg5i4Mk4C/TE95fwyC X-Received: by 2002:a63:1d0e:: with SMTP id d14mr115405365pgd.324.1564605025377; Wed, 31 Jul 2019 13:30:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564605025; cv=none; d=google.com; s=arc-20160816; b=RTX/7vJSKawPha3u6dKIDdQuMjhh5AISpBwvvgKr2XF2tC5Xi7LgSSbIrYbenqjOa5 XmACyZP3eeMnuCMbwWOnd9yRZUvw9ZY7NWb6fZ5PVtwJFDKpyxa9CXd9qrxtF5Q4aoc0 /u4Ik0JDOzOXeB0KeLl/PMWCgT70br9VnDAxg4yiY4CjICLd98eqUw5ZYgPCqQZS8MM2 Pol8bEmTyMVjEgNxw1WLknZcaGV6PCsST6FXTlKYa/bsktJSZv3LaSGY/8nGf7QLa9q/ jCaVUV+tjPA7BvpQpWA6xPrBUY1FUDMc4hA5EaI7/L5LDQf13xpJJbaKG9gyosVRFoTp oRqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Cw8s/YHZ7PvnoGSE9VFOJmJ7OcBZMxXJRhzFX2CFS/0=; b=cQBY35ZYdURWnj9DJBsIGc7gBEoE0qzBXg1wRSu75TfqJdb357Fots7gHNIXwISv3y u3Ir10owZRTEJMB6vMi9hGqi8IQJDldExUzL9MuIjTm6zElRVNsNSEi2+CKw0GWK3eyi +UwzA/4UVnP5aiFc1/ApWWdpz/5D9Il/xCsIhsYzkFHihtlhApEN8OC7ViSObss3UWdr 9WHBwW1IYBUjPcwCh0qWqxDwf/UErtcazHavzioU7xF8HPHU8K+C2uMm72AwMp3R6ruY 94UHEDdR9P/hNs1Tapteqfz6bsb1BI+9ypTm16EtNk5ZoKxz3omQZMxPnbBh6HeyYIXA K/Eg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kJBbacS2; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[176.86.136.19]) by smtp.gmail.com with ESMTPSA id i18sm91905591wrp.91.2019.07.31.13.29.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 Jul 2019 13:29:43 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, sboyd@kernel.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net Cc: vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org Subject: [PATCH v4 05/13] clk: qcom: apcs-msm8916: get parent clock names from DT Date: Wed, 31 Jul 2019 22:29:21 +0200 Message-Id: <20190731202929.16443-6-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org> References: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Allow accessing the parent clock names required for the driver operation by using the device tree node. This permits extending the driver to other platforms without having to modify its source code. For backwards compatibility leave previous values as default. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/apcs-msm8916.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) -- 2.22.0 diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c index a6c89a310b18..dd82eb1e5202 100644 --- a/drivers/clk/qcom/apcs-msm8916.c +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -19,7 +19,7 @@ static const u32 gpll0_a53cc_map[] = { 4, 5 }; -static const char * const gpll0_a53cc[] = { +static const char *gpll0_a53cc[] = { "gpll0_vote", "a53pll", }; @@ -50,6 +50,8 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) struct regmap *regmap; struct clk_init_data init = { }; int ret = -ENODEV; + const char *parents[2]; + int pll_index = 0; regmap = dev_get_regmap(parent, NULL); if (!regmap) { @@ -61,6 +63,16 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) if (!a53cc) return -ENOMEM; + /* legacy bindings only defined the pll parent clock (index = 0) with no + * name; when both of the parents are specified in the bindings, the + * pll is the second one (index = 1). + */ + if (of_clk_parent_fill(parent->of_node, parents, 2) == 2) { + gpll0_a53cc[0] = parents[0]; + gpll0_a53cc[1] = parents[1]; + pll_index = 1; + } + init.name = "a53mux"; init.parent_names = gpll0_a53cc; init.num_parents = ARRAY_SIZE(gpll0_a53cc); @@ -76,10 +88,11 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) a53cc->src_shift = 8; a53cc->parent_map = gpll0_a53cc_map; - a53cc->pclk = devm_clk_get(parent, NULL); + a53cc->pclk = of_clk_get(parent->of_node, pll_index); if (IS_ERR(a53cc->pclk)) { ret = PTR_ERR(a53cc->pclk); - dev_err(dev, "failed to get clk: %d\n", ret); + if (ret != -EPROBE_DEFER) + dev_err(dev, "failed to get clk: %d\n", ret); return ret; } @@ -87,6 +100,7 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb); if (ret) { dev_err(dev, "failed to register clock notifier: %d\n", ret); + clk_put(a53cc->pclk); return ret; } @@ -109,6 +123,8 @@ static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) err: clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + clk_put(a53cc->pclk); + return ret; } @@ -117,6 +133,7 @@ static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev) struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev); clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + clk_put(a53cc->pclk); return 0; } From patchwork Wed Jul 31 20:29:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 170229 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp4462569ile; Wed, 31 Jul 2019 13:29:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqwE+7YBTFbd9X/QL5mxCNYoiX6suH5FweYhNFtSQhUAY5QN5GCx+2JsNgaquKci3v4cFSyZ X-Received: by 2002:a62:874d:: with SMTP id i74mr48262970pfe.94.1564604991371; Wed, 31 Jul 2019 13:29:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564604991; cv=none; d=google.com; s=arc-20160816; b=u9qQFhhuN7EQLv9nT8BBM+E5jRqLhyHJ9WXF1GGnHgspQUknmWajGpG2qM4vxvxqsI JOU1VQN+HsaltA2qmAM6JXu/ITZzZrnibl2p3/RamOfqR4NMWFH17Oxegq3pgVuhFv71 pCmeJTSaWddpbJciIzq8JVswpuUhLpj2rqDN/9eyAqSXFi0ABt6babswRQ+dHCbS8eoB HaDjNjihF1OE+j8EtEEGblDUMlYO9ZIoOOKaHLlgju1EuLZXqfqsb6Ih5Gub4/GegVOX 7Yf2cAzzQjNwQ8KKDjRtnST3JBKXiUOh/acc78D6UhB+uwE/AjOaJhaMDhEFNh5W6cir fwig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=BoMlESuV3B6tPWN9XWP2L6fpdT8XV6yqfKxT2xNxK2o=; b=FwYCD5mqia7Lu3ztJUiPBjnay7Y9yjCKNcMUvcs7GJxV6yPSv9X1m8PjTssW5AzDif Ovf6Tjaj+8GSOUp6FPyLFilgGPl1SETArWbwZE6Csy82ZOWHqCE7SP4DRyYR25QkR/Wi amId5GN1ecCYTrKvg/hFrkTP0YE7Op5mLbPsDSmGUG0EyqoEMl9N2lVOIeqJt6KtAhSm GORKeUeOzW4WTXj14Emujen+wuV/AeF6q+ipWzYfiz860J2A2AUh+69ayD32AGvc4YZQ gpc0PfGHHvzFk7NLh2t65JFH7qgJFkMvdi+03FS7z80x4ZnYHfjDL8UlmCj2zfBsaiLy ejIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n6sHKkfa; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[176.86.136.19]) by smtp.gmail.com with ESMTPSA id i18sm91905591wrp.91.2019.07.31.13.29.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 Jul 2019 13:29:44 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, sboyd@kernel.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net Cc: vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org Subject: [PATCH v4 06/13] clk: qcom: hfpll: get parent clock names from DT Date: Wed, 31 Jul 2019 22:29:22 +0200 Message-Id: <20190731202929.16443-7-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org> References: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Allow accessing the parent clock name required for the driver operation using the device tree node. This permits extending the driver to other platforms without having to modify its source code. For backwards compatibility leave the previous value as default. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- drivers/clk/qcom/hfpll.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.22.0 diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c index a6de7101430c..87b7f46d27e0 100644 --- a/drivers/clk/qcom/hfpll.c +++ b/drivers/clk/qcom/hfpll.c @@ -52,6 +52,7 @@ static int qcom_hfpll_probe(struct platform_device *pdev) void __iomem *base; struct regmap *regmap; struct clk_hfpll *h; + struct clk *pclk; struct clk_init_data init = { .parent_names = (const char *[]){ "xo" }, .num_parents = 1, @@ -75,6 +76,13 @@ static int qcom_hfpll_probe(struct platform_device *pdev) 0, &init.name)) return -ENODEV; + /* get parent clock from device tree (optional) */ + pclk = devm_clk_get(dev, "xo"); + if (!IS_ERR(pclk)) + init.parent_names = (const char *[]){ __clk_get_name(pclk) }; + else if (PTR_ERR(pclk) == -EPROBE_DEFER) + return -EPROBE_DEFER; + h->d = &hdata; h->clkr.hw.init = &init; spin_lock_init(&h->lock); From patchwork Wed Jul 31 20:29:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 170235 Delivered-To: patch@linaro.org Received: by 2002:a92:512:0:0:0:0:0 with SMTP id q18csp4462725ile; Wed, 31 Jul 2019 13:30:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqw0RphhvZJtInmLoi4vwek6mRJmqi6hupTvHX+knKiatVbo4G/VlMIYgwkL3OH3EP4jIeDE X-Received: by 2002:a17:902:8489:: with SMTP id c9mr123678209plo.327.1564605000936; Wed, 31 Jul 2019 13:30:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564605000; cv=none; d=google.com; s=arc-20160816; b=rmxie9J3B6ZeE33v230Lq6WorU28+HGNL6uaWQTQjHEFvdJduxoJlrfYNzXZ3S2+9D dhnN9wwZ4jnXqVkyzVtTUefHH4ej842zrIszbk1BbL28zvRIF/wenzjIIOPnTZYeXEy9 3zRKB7DrNEhVchlY9cPuBwS582TKS01iymfU6DmTPTmQeDASzpxVnJ8as5cGcfZD7ep8 dVCb0yF6LfcKbWHVbcanFdA/3u6AboTNUfVXV1LzQte92F9YoMVuoZ977rBiVhxcHTil iBw4+UqG7pDhHeYM0LWKLf9ExgOvJMsxAmwSJJz/lWLw3SCzVrm+kFwngX0Nlkl1tFG0 UESA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8QWLof1O3nhMlU7i5ZCEmG2qQ6v7dulP8/K2lF3I37g=; b=tkybabFFA162MQ9hR0a02DO0+Mre6Ms+41+bwJyXllW7f2wEEzJd2oXgQ8hv8Eff/4 X9Ft9mPdMts300AbJKOpBEAfsAxx+N9vZwgCZpNqOeIpKR1hPSmBy2KnIe6U3kScT5wh WOHIS4MLR5DA14sHfTpFRAKpgMAERmE3yhfolZj9ZTJtAwpz/TsAui4HxKNLv3YlAf9E c2d469c6fCKTqsZlDTJhFMzsmMJG2NEVBdwc/y/u8puVkwCMe7x6OTzUo4bP3MAMt0hu OPK5YrKwHdMFUQZ9ewhNekk21OiSRxAPoE2G1D9brkCLvUl13pvVPci1TQaHY11yVDzR kZsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HTbhzaNq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[176.86.136.19]) by smtp.gmail.com with ESMTPSA id i18sm91905591wrp.91.2019.07.31.13.29.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 31 Jul 2019 13:29:54 -0700 (PDT) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, sboyd@kernel.org, david.brown@linaro.org, jassisinghbrar@gmail.com, mark.rutland@arm.com, mturquette@baylibre.com, robh+dt@kernel.org, will.deacon@arm.com, arnd@arndb.de, horms+renesas@verge.net.au, heiko@sntech.de, sibis@codeaurora.org, enric.balletbo@collabora.com, jagan@amarulasolutions.com, olof@lixom.net Cc: vkoul@kernel.org, niklas.cassel@linaro.org, georgi.djakov@linaro.org, amit.kucheria@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, khasim.mohammed@linaro.org Subject: [PATCH v4 11/13] arm64: dts: qcom: qcs404: Add the clocks for APCS mux/divider Date: Wed, 31 Jul 2019 22:29:27 +0200 Message-Id: <20190731202929.16443-12-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org> References: <20190731202929.16443-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Specify the clocks that feed the APCS mux/divider instead of using default hardcoded values in the source code. Co-developed-by: Niklas Cassel Signed-off-by: Niklas Cassel Signed-off-by: Jorge Ramirez-Ortiz Reviewed-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 3 +++ 1 file changed, 3 insertions(+) -- 2.22.0 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 3714099306b7..5b7d6258e9bf 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -857,6 +857,9 @@ compatible = "qcom,qcs404-apcs-apps-global", "syscon"; reg = <0x0b011000 0x1000>; #mbox-cells = <1>; + clocks = <&gcc GCC_GPLL0_AO_OUT_MAIN>, <&apcs_hfpll>; + clock-names = "aux", "pll"; + #clock-cells = <0>; }; apcs_hfpll: clock-controller@b016000 {