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Fri, 29 Sep 2023 17:39:49 +0000 From: Matthew Howell To: "gregkh@linuxfoundation.org" CC: Darren Beeson , "andriy.shevchenko@intel.com" , "ilpo.jarvinen@linux.intel.com" , "eff.baldwin@sealevel.com" , "linux-serial@vger.kernel.org" , Ryan Wenglarz , Matthew Howell , James Olson Subject: [PATCH V9 1/2] serial: exar: Revert "serial: exar: Add support for Sealevel 7xxxC serial cards" Thread-Topic: [PATCH V9 1/2] serial: exar: Revert "serial: exar: Add support for Sealevel 7xxxC serial cards" Thread-Index: AQHZ8vvyagtiwAEjxEmBxrU0jY0e3A== Date: Fri, 29 Sep 2023 17:39:49 +0000 Message-ID: <8ffa2f583ff142c3b0eb6cf51a7c9cef5dbfd320.camel@sealevel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Evolution 3.44.4-0ubuntu2 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=sealevel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: BY3PR05MB8419:EE_|PH8PR05MB9362:EE_ x-ms-office365-filtering-correlation-id: 5b9501d8-2eec-460b-7009-08dbc11314a3 x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; 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This has rendered 14ee78d5932a redundant. This reverts commit 14ee78d5932afeb710c8305196a676a715bfdea8. Fixes: 14ee78d5932a ("Add support for Sealevel 7xxxC serial cards") Signed-off-by: Matthew Howell Reviewed-by: Andy Shevchenko diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index 077c3ba3539e..3886f78ecbbf 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -47,12 +47,6 @@ #define PCI_SUBDEVICE_ID_USR_2980 0x0128 #define PCI_SUBDEVICE_ID_USR_2981 0x0129 -#define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001 -#define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002 -#define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004 -#define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008 -#define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010 - #define UART_EXAR_INT0 0x80 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ @@ -652,8 +646,6 @@ exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1); else if (board->num_ports) nr_ports = board->num_ports; - else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL) - nr_ports = pcidev->device & 0xff; else nr_ports = pcidev->device & 0x0f; @@ -893,12 +885,6 @@ static const struct pci_device_id exar_pci_tbl[] = { EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4), EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4), EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8), - - EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x), - EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x), - EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x), - EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x), - EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x), { 0, } }; MODULE_DEVICE_TABLE(pci, exar_pci_tbl); From patchwork Fri Sep 29 17:40:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Howell X-Patchwork-Id: 728015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AD3C8E728CC for ; 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This patch implements DTR Auto-RS485 on Sealevel cards. Signed-off-by: Matthew Howell Reviewed-by: Andy Shevchenko --- V8->V9 Changed implementation to use pci_xr17v35x_setup() instead of creating separate startup functions. diff --git a/drivers/tty/serial/8250/8250_exar.c b/drivers/tty/serial/8250/8250_exar.c index 3886f78ecbbf..f4a467d5b6aa 100644 --- a/drivers/tty/serial/8250/8250_exar.c +++ b/drivers/tty/serial/8250/8250_exar.c @@ -78,6 +78,9 @@ #define UART_EXAR_RS485_DLY(x) ((x) << 4) +#define UART_EXAR_DLD 0x02 /* Divisor Fractional */ +#define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */ + /* * IOT2040 MPIO wiring semantics: * @@ -439,6 +442,44 @@ static int generic_rs485_config(struct uart_port *port, struct ktermios *termios return 0; } +static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termios, + struct serial_rs485 *rs485) +{ + u8 __iomem *p = port->membase; + u8 old_lcr; + u8 efr; + u8 dld; + int ret; + + ret = generic_rs485_config(port, termios, rs485); + if (ret) + return ret; + + if (rs485->flags & SER_RS485_ENABLED) { + old_lcr = readb(p + UART_LCR); + + /* Set EFR[4]=1 to enable enhanced feature registers */ + efr = readb(p + UART_XR_EFR); + efr |= UART_EFR_ECB; + writeb(efr, p + UART_XR_EFR); + + /* Set MCR to use DTR as Auto-RS485 Enable signal */ + writeb(UART_MCR_OUT1, p + UART_MCR); + + /* Set LCR[7]=1 to enable access to DLD register */ + writeb(old_lcr | UART_LCR_DLAB, p + UART_LCR); + + /* Set DLD[7]=1 for inverted RS485 Enable logic */ + dld = readb(p + UART_EXAR_DLD); + dld |= UART_EXAR_DLD_485_POLARITY; + writeb(dld, p + UART_EXAR_DLD); + + writeb(old_lcr, p + UART_LCR); + } + + return 0; +} + static const struct serial_rs485 generic_rs485_supported = { .flags = SER_RS485_ENABLED, }; @@ -560,6 +601,9 @@ pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev, port->port.rs485_config = platform->rs485_config; port->port.rs485_supported = *(platform->rs485_supported); + if (pcidev->subsystem_vendor == PCI_VENDOR_ID_SEALEVEL) + port->port.rs485_config = sealevel_rs485_config; + /* * Setup the UART clock for the devices on expansion slot to * half the clock speed of the main chip (which is 125MHz)