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[178.235.177.217]) by smtp.gmail.com with ESMTPSA id cx14-20020a05640222ae00b005362bcc089csm2215701edb.67.2023.09.29.06.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Sep 2023 06:39:03 -0700 (PDT) From: Konrad Dybcio Date: Fri, 29 Sep 2023 15:38:53 +0200 Subject: [PATCH 2/2] clk: qcom: gcc-sc8280xp: Don't keep display AHB clocks always-on MIME-Version: 1.0 Message-Id: <20230929-topic-8280_ahbdisp-v1-2-72bdc38309b9@linaro.org> References: <20230929-topic-8280_ahbdisp-v1-0-72bdc38309b9@linaro.org> In-Reply-To: <20230929-topic-8280_ahbdisp-v1-0-72bdc38309b9@linaro.org> To: Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Vinod Koul Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.13-dev-0438c Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org These clocks are consumed by the dispcc[01] clock controllers, so there's no reason to keep them on from gcc probe. Remove that hack. Fixes: d65d005f9a6c ("clk: qcom: add sc8280xp GCC driver") Signed-off-by: Konrad Dybcio --- drivers/clk/qcom/gcc-sc8280xp.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-sc8280xp.c b/drivers/clk/qcom/gcc-sc8280xp.c index bfb77931e868..bf95f82a3818 100644 --- a/drivers/clk/qcom/gcc-sc8280xp.c +++ b/drivers/clk/qcom/gcc-sc8280xp.c @@ -7545,18 +7545,16 @@ static int gcc_sc8280xp_probe(struct platform_device *pdev) /* * Keep the clocks always-ON - * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, GCC_DISP_AHB_CLK, + * GCC_CAMERA_AHB_CLK, GCC_CAMERA_XO_CLK, * GCC_DISP_XO_CLK, GCC_GPU_CFG_AHB_CLK, GCC_VIDEO_AHB_CLK, - * GCC_VIDEO_XO_CLK, GCC_DISP1_AHB_CLK, GCC_DISP1_XO_CLK + * GCC_VIDEO_XO_CLK, GCC_DISP1_XO_CLK */ regmap_update_bits(regmap, 0x26004, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x26020, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0x27004, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x27028, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x28004, BIT(0), BIT(0)); regmap_update_bits(regmap, 0x28028, BIT(0), BIT(0)); - regmap_update_bits(regmap, 0xbb004, BIT(0), BIT(0)); regmap_update_bits(regmap, 0xbb028, BIT(0), BIT(0)); ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, ARRAY_SIZE(gcc_dfs_clocks));