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And they has one register based, not two as i.MX7ULP or VF610. Although the Linux Kernel driver gpio-vf610.c could work with fsl,imx7ulp-gpio compatible, it is based on some tricks did in device tree with some offset added to base address. So actually i.MX8ULP/i.MX93 is not compatible with i.MX7ULP. Last, i.MX93 is directly derived from i.MX8ULP, so make i.MX93 GPIO compatible with i.MX8ULP Signed-off-by: Peng Fan Reviewed-by: Rob Herring --- .../devicetree/bindings/gpio/gpio-vf610.yaml | 36 +++++++++++++++++++--- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml index 59427d97adf5..21199bf221ef 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: oneOf: + - const: fsl,imx8ulp-gpio - const: fsl,vf610-gpio - items: - const: fsl,imx7ulp-gpio @@ -27,16 +28,17 @@ properties: - items: - enum: - fsl,imx93-gpio - - fsl,imx8ulp-gpio - - const: fsl,imx7ulp-gpio + - const: fsl,imx8ulp-gpio reg: - description: The first reg tuple represents the PORT module, the second tuple - represents the GPIO module. + minItems: 1 maxItems: 2 interrupts: - maxItems: 1 + items: + - description: GPIO Trustzone non-secure interrupt number + - description: GPIO Trustzone secure interrupt number + minItems: 1 interrupt-controller: true @@ -78,6 +80,30 @@ required: - "#gpio-cells" - gpio-controller +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,vf610-gpio + - fsl,imx7ulp-gpio + then: + properties: + interrupts: + maxItems: 1 + reg: + items: + - description: PORT register base address + - description: GPIO register base address + else: + properties: + interrupts: + minItems: 2 + reg: + items: + - description: GPIO register base address + additionalProperties: false examples: From patchwork Tue Sep 26 03:33:20 2023 Content-Type: text/plain; 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Although the Linux Kernel driver gpio-vf610.c could work with fsl,imx7ulp-gpio compatible, it is based on some tricks did in device tree with some offset added to base address. Add a new of_device_id entry for i.MX8ULP. But to make the driver could also support old bindings, check the compatible string first, before check the device data. Signed-off-by: Peng Fan --- drivers/gpio/gpio-vf610.c | 40 ++++++++++++++++++++++++++++++++++------ 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c index dbc7ba0ee72c..49867d5db642 100644 --- a/drivers/gpio/gpio-vf610.c +++ b/drivers/gpio/gpio-vf610.c @@ -25,6 +25,7 @@ struct fsl_gpio_soc_data { /* SoCs has a Port Data Direction Register (PDDR) */ bool have_paddr; + bool have_dual_base; }; struct vf610_gpio_port { @@ -60,13 +61,22 @@ struct vf610_gpio_port { #define PORT_INT_EITHER_EDGE 0xb #define PORT_INT_LOGIC_ONE 0xc +#define IMX8ULP_GPIO_BASE_OFF 0x40 +#define IMX8ULP_BASE_OFF 0x80 + static const struct fsl_gpio_soc_data imx_data = { .have_paddr = true, + .have_dual_base = true, +}; + +static const struct fsl_gpio_soc_data imx8ulp_data = { + .have_paddr = true, }; static const struct of_device_id vf610_gpio_dt_ids[] = { { .compatible = "fsl,vf610-gpio", .data = NULL, }, { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, }, + { .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, }, { /* sentinel */ } }; @@ -263,19 +273,37 @@ static int vf610_gpio_probe(struct platform_device *pdev) struct gpio_irq_chip *girq; int i; int ret; + bool dual_base = false; port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); if (!port) return -ENOMEM; port->sdata = of_device_get_match_data(dev); - port->base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(port->base)) - return PTR_ERR(port->base); - port->gpio_base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(port->gpio_base)) - return PTR_ERR(port->gpio_base); + /* support old compatible strings */ + if (device_is_compatible(dev, "fsl,imx7ulp-gpio") && + (device_is_compatible(dev, "fsl,imx93-gpio") || + (device_is_compatible(dev, "fsl,imx8ulp-gpio")))) + dual_base = true; + + if ((port->sdata && port->sdata->have_dual_base) || dual_base) { + port->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(port->base)) + return PTR_ERR(port->base); + + port->gpio_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(port->gpio_base)) + return PTR_ERR(port->gpio_base); + } else { + port->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(port->base)) + return PTR_ERR(port->base); + + port->gpio_base = port->base + IMX8ULP_GPIO_BASE_OFF; + port->base = port->base + IMX8ULP_BASE_OFF; + } + port->irq = platform_get_irq(pdev, 0); if (port->irq < 0) From patchwork Tue Sep 26 03:33:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan \(OSS\)" X-Patchwork-Id: 726550 Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B0A37F for ; Tue, 26 Sep 2023 03:29:20 +0000 (UTC) Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2086.outbound.protection.outlook.com [40.107.6.86]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0349DC; Mon, 25 Sep 2023 20:29:17 -0700 (PDT) ARC-Seal: i=1; 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Tue, 26 Sep 2023 03:29:15 +0000 From: "Peng Fan (OSS)" Date: Tue, 26 Sep 2023 11:33:22 +0800 Subject: [PATCH v4 6/7] arm64: dts: imx8ulp: update gpio node Message-Id: <20230926-vf610-gpio-v4-6-b57b7f6e8368@nxp.com> References: <20230926-vf610-gpio-v4-0-b57b7f6e8368@nxp.com> In-Reply-To: <20230926-vf610-gpio-v4-0-b57b7f6e8368@nxp.com> To: Linus Walleij , Bartosz Golaszewski , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stefan Agner , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Marco Felsch Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Peng Fan X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1695699209; l=2557; i=peng.fan@nxp.com; s=20230812; h=from:subject:message-id; bh=OBv9Fl8cAe6WZDwRqWWAbBALhbody3v57Vb/+6bcRug=; b=hMzFP7eFJ9RATpzZ0o91C27xX0sR0zhWvWgF2ZUJeq7BRSbeMKKbI/1p7+WDtGJeuBk5QAqrG 0DUh3T8TyzeBKSNdpdxtoV0KT2dWrqv1eguNhCWfh4pA41qfeumJwVk X-Developer-Key: i=peng.fan@nxp.com; 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Now following hardware design, using one register base in device tree node. This may break users who use compatible fsl,imx7ulp-gpio to enable i.MX8ULP GPIO. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 8a6596d5a581..3921fdace792 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -484,11 +484,12 @@ fec: ethernet@29950000 { }; gpioe: gpio@2d000080 { - compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; - reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; + compatible = "fsl,imx8ulp-gpio"; + reg = <0x2d000000 0x1000>; gpio-controller; #gpio-cells = <2>; - interrupts = ; + interrupts = , + ; interrupt-controller; #interrupt-cells = <2>; clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, @@ -498,11 +499,12 @@ gpioe: gpio@2d000080 { }; gpiof: gpio@2d010080 { - compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; - reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; + compatible = "fsl,imx8ulp-gpio"; + reg = <0x2d010000 0x1000>; gpio-controller; #gpio-cells = <2>; - interrupts = ; + interrupts = , + ; interrupt-controller; #interrupt-cells = <2>; clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, @@ -533,11 +535,12 @@ pcc5: clock-controller@2da70000 { }; gpiod: gpio@2e200080 { - compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; - reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; + compatible = "fsl,imx8ulp-gpio"; + reg = <0x2e200000 0x1000>; gpio-controller; #gpio-cells = <2>; - interrupts = ; + interrupts = , + ; interrupt-controller; #interrupt-cells = <2>; clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>,