From patchwork Tue Sep 26 10:04:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 726417 Delivered-To: patch@linaro.org Received: by 2002:adf:ea87:0:b0:31d:da82:a3b4 with SMTP id s7csp2845000wrm; Tue, 26 Sep 2023 03:12:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH40eLP5GYbAJ2mYNcsSNoadZPACV+pIoKlkW2YoRq6cEmx2YZk77WD8qYG4ptyTmXZccJu X-Received: by 2002:a05:6102:11ef:b0:452:741a:b7ec with SMTP id e15-20020a05610211ef00b00452741ab7ecmr6113805vsg.33.1695723165789; Tue, 26 Sep 2023 03:12:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695723165; cv=none; d=google.com; s=arc-20160816; b=c6Ha/Z9FtTz5AMKtFgphrCHZrR5ohJ07jCbKw/VdlqFw37I348HSeExXCTVlD9LMRD 0G7Ll45HHrI8nxSGNMMBtUQyTZMCCyXN6bxSuyWSzbjxYo0GPQT29bE+40YJwMijDrNu HlTRHbY2XN5ZQmOrZCQlkdHpkUATDXjRiU2aDNz9cmZwIJ5DRfzH4MHNiEVyJerkx2ID /0HFlKAl7lnZoItxVXXbi++lejVR/LEBn098/PG9LMe4sGKj6saWdRNtpc2FPuSTTXR4 M3YZDltot5jMDIdTzPkMc8clHYalDSdrVhje6jxM636WNJwPR5K1rxTmWHenS3FjBM87 4nuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:from:reply-to:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence:mime-version :references:in-reply-to:message-id:date:subject:cc:to; bh=0UFDjTp96WyIGI6pgHFyDLanGZXfs4B6kudYtnbY3l4=; fh=S0+uYiUekNlY+vd8jPZbTHxsQBwDC5l2YHnO2B7ftdQ=; b=ljud+Dp4Q52rN3oOe8QBuZ7hI/qVqLLlbeTQe5kt66gI5pS+A5Dt28OjwE13quJELS ZIb3rDtLQhN3zsNkTiLO7TnDot149B1+TysT0+s5Z6aHbg8iHn08p911gvKAyVmz/ZnP +Kk5p/Bv30T5CiFP7jzlpWGkH9S3vZDDfxWump9DEgTLQvVoT9mgGmeko0/vHMvJ4bBV KRUmzZWQkLy+UbY0oALULKHIJKpE7eVaIFWQhj+gt8S+qPXdmVUcxcBX8u+B8SzX713e yWWgQ5A0MLHbYqoJPa+mEYArCXqPz3IyVhVMTbuHz2IvmBWKCJLj95BLoeOwM19gO6b+ h+JA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c6-20020a0ce146000000b00656432bd23fsi6850371qvl.238.2023.09.26.03.12.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Sep 2023 03:12:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ql53N-00032J-E8; Tue, 26 Sep 2023 06:12:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ql53D-0002kj-Cv; Tue, 26 Sep 2023 06:12:20 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ql53B-00059b-Ik; Tue, 26 Sep 2023 06:12:18 -0400 Received: from lhrpeml500001.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4RvwVs4r5Nz6K717; Tue, 26 Sep 2023 18:11:01 +0800 (CST) Received: from A190218597.china.huawei.com (10.126.174.16) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 26 Sep 2023 11:11:57 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFC V2 22/37] hw/acpi: Make _MAT method optional Date: Tue, 26 Sep 2023 11:04:21 +0100 Message-ID: <20230926100436.28284-23-salil.mehta@huawei.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20230926100436.28284-1-salil.mehta@huawei.com> References: <20230926100436.28284-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.126.174.16] X-ClientProxiedBy: dggems705-chm.china.huawei.com (10.3.19.182) To lhrpeml500001.china.huawei.com (7.191.163.213) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta X-Patchwork-Original-From: Salil Mehta via From: Salil Mehta Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker The GICC interface on arm64 vCPUs is statically defined in the MADT, and doesn't require a _MAT entry. Although the GICC is indicated as present by the MADT entry, it can only be used from vCPU sysregs, which aren't accessible until hot-add. Co-developed-by: Jean-Philippe Brucker Signed-off-by: Jean-Philippe Brucker Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Signed-off-by: Salil Mehta Reviewed-by: Gavin Shan --- hw/acpi/cpu.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index e1299696d3..217db99538 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -715,11 +715,13 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, aml_append(dev, method); /* build _MAT object */ - assert(adevc && adevc->madt_cpu); - adevc->madt_cpu(i, arch_ids, madt_buf, - true); /* set enabled flag */ - aml_append(dev, aml_name_decl("_MAT", - aml_buffer(madt_buf->len, (uint8_t *)madt_buf->data))); + if (adevc && adevc->madt_cpu) { + assert(adevc && adevc->madt_cpu); + adevc->madt_cpu(i, arch_ids, madt_buf, + true); /* set enabled flag */ + aml_append(dev, aml_name_decl("_MAT", + aml_buffer(madt_buf->len, (uint8_t *)madt_buf->data))); + } g_array_free(madt_buf, true); if (CPU(arch_ids->cpus[i].cpu) != first_cpu) { From patchwork Tue Sep 26 10:36:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Salil Mehta X-Patchwork-Id: 726418 Delivered-To: patch@linaro.org Received: by 2002:adf:ea87:0:b0:31d:da82:a3b4 with SMTP id s7csp2854742wrm; Tue, 26 Sep 2023 03:38:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFaPhK/TQAteQoWzjydNRdrS395gGzQRaY6k2/iunwfUenRtCPNyd5BHNnSQ7ysxm6C+Fja X-Received: by 2002:a67:b913:0:b0:452:635b:8440 with SMTP id q19-20020a67b913000000b00452635b8440mr5085560vsn.30.1695724695224; Tue, 26 Sep 2023 03:38:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695724695; cv=none; d=google.com; s=arc-20160816; b=g7D/kx8RPhXs1IUhVoQ/FyNFVEYYEQ5aVISPo5S+ig4pf4cf4lnbZDDTJxON/uImo1 qhMJDQNBDjY1NzGMLtypDuPb2grVfSZ8CUZRT/xtZxapsU/OUQxkLgBVmor5gupONZek YvXuB89JAelilbXQvyR/qpiogHAhVsHOhhFuaGCrjsFQXj7hjS96jhL461wIE+rEDVsU YJWKoxk6uV6drHz9znmzi4mHNU+fYRlxXIzxfSr5blWcpFFl9/it2ND3E5FFd4l5i9ti NUDOgNHrD8FXv4PBhTO2pW4Ut8tt8A7Zp6RUH+eLcJ9Cpnr7WtgdVzCBofOVQ0lidnER H/rA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:from:reply-to:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence:mime-version :references:in-reply-to:message-id:date:subject:cc:to; bh=ZpdISj+oiA2vFHKcNlO4HmohP3g2XDXwFTkcQw8ImzE=; fh=S0+uYiUekNlY+vd8jPZbTHxsQBwDC5l2YHnO2B7ftdQ=; b=b3oyGC9v8J3CcO2HJq4eM1bu0r7vkqrJHmrB+sQsvnOW9swmfeIhKuD9rhqGCK6uTN 8tPJ8HUR2FKF7GkIi6N50IICVhhItE5b+5cGWYzWg5NOiH408ic7hOv2c5O2qtRDWEdA AUGYaxqr8js0HLaU/MUA3P9LxvdHp6h7PQ7uXWMvq/OKLOmFXCbgNtds7EVwh14Cyq8Y bmEDwoF8CKm2iREkUlCOeAiytyEPxB7Vswv+dpFeu7SEN5MkaXOpqhQJHffz4u7beR/2 Q1HDwJvkJos7G2SCM/d9y8aOK3fnxKDVfp5eFT+y95OLX3JgncGigEZCv6F7ZnxQc6sQ RHmQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q9-20020a0ce209000000b0065b021687desi2847995qvl.61.2023.09.26.03.38.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Sep 2023 03:38:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nongnu.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ql5S4-0004R1-HB; Tue, 26 Sep 2023 06:38:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ql5S3-0004Ni-EK; Tue, 26 Sep 2023 06:37:59 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ql5S2-0001lO-05; Tue, 26 Sep 2023 06:37:59 -0400 Received: from lhrpeml500001.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4Rvx4S22lHz6K8s5; Tue, 26 Sep 2023 18:36:40 +0800 (CST) Received: from A190218597.china.huawei.com (10.126.174.16) by lhrpeml500001.china.huawei.com (7.191.163.213) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.31; Tue, 26 Sep 2023 11:37:36 +0100 To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH RFC V2 33/37] target/arm/kvm: Write CPU state back to KVM on reset Date: Tue, 26 Sep 2023 11:36:50 +0100 Message-ID: <20230926103654.34424-2-salil.mehta@huawei.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20230926103654.34424-1-salil.mehta@huawei.com> References: <20230926100436.28284-1-salil.mehta@huawei.com> <20230926103654.34424-1-salil.mehta@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.126.174.16] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To lhrpeml500001.china.huawei.com (7.191.163.213) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=salil.mehta@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Salil Mehta X-Patchwork-Original-From: Salil Mehta via From: Salil Mehta Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Philippe Brucker When a KVM vCPU is reset following a PSCI CPU_ON call, its power state is not synchronized with KVM at the moment. Because the vCPU is not marked dirty, we miss the call to kvm_arch_put_registers() that writes to KVM's MP_STATE. Force mp_state synchronization. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Salil Mehta --- target/arm/kvm.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 0e1d0692b1..8e7c68af6a 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -614,11 +614,12 @@ void kvm_arm_cpu_post_load(ARMCPU *cpu) void kvm_arm_reset_vcpu(ARMCPU *cpu) { int ret; + CPUState *cs = CPU(cpu); /* Re-init VCPU so that all registers are set to * their respective reset values. */ - ret = kvm_arm_vcpu_init(CPU(cpu)); + ret = kvm_arm_vcpu_init(cs); if (ret < 0) { fprintf(stderr, "kvm_arm_vcpu_init failed: %s\n", strerror(-ret)); abort(); @@ -635,6 +636,12 @@ void kvm_arm_reset_vcpu(ARMCPU *cpu) * for the same reason we do so in kvm_arch_get_registers(). */ write_list_to_cpustate(cpu); + + /* + * Ensure we call kvm_arch_put_registers(). The vCPU isn't marked dirty if + * it was parked in KVM and is now booting from a PSCI CPU_ON call. + */ + cs->vcpu_dirty = true; } void kvm_arm_create_host_vcpu(ARMCPU *cpu)