From patchwork Fri Jul 26 17:49:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169864 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp353444ilk; Fri, 26 Jul 2019 10:50:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqyrEbUCa6fZOPNRjktjfIqwOJyFiDtIHreRgwQWzY1go0ASxJY4wfI8IfWJQbek9JIz+M+O X-Received: by 2002:a17:906:e95:: with SMTP id p21mr72730520ejf.205.1564163454789; Fri, 26 Jul 2019 10:50:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163454; cv=none; d=google.com; s=arc-20160816; b=NhMzHR205DvbFEdsGi5NIMKxoGMZeSavoktnIiyvDaKm0f6BPSRDY8hF8bdUt+lsEv BjtDSey85gFXcCLq2zclVyeCwcPFCJAPbuXe5/k8bBRdnw3WrUnI5vnSpJRGbgPGgRQ1 fbX6NZk5fHFuCTuXPnwssJrnKkIGKVaOatrkjASyT8H8jpP3X56kBcPZ4W0B43twXNxl SLDYqzuQHr9PD82OGfKqE41kHz5ysMgSp4YlD79DHleD3EQVWpEpMdR9CAm/+/rJE84D pLhGgGy0+7Lz3LZHeeSm+fOt3RM6YcmJXIIuXfioumS5s1epAIePg19kqOIUAQzc9AYn +50Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ynwokCS+Kqgt3LfDdzexRygGm/TpfqdWtRJ/K6TofxQ=; b=oyFrItfEXHXtQhbUDw1Ls/Kp+xxkkrBcTHxtHU8RXH0cntrkA3PHk4DfNGaw/CvqvC +NdMCkHsuA9rmyCQs5WRaQlKN0ibA84GX547aK8qDK3VUKExZr2U0H6eCHypaRz8bmLq lCXwl71EHFTwJrJzGpEAqW9XQno8VICyVoDatNROgUaj4RIk3w4J/Pn46ZfZVwW7l9rg dlwn72N1C8Mt9wWkR51y9SGl6DFJLmqNBX3c6WKbSZLWBGC8+CISWADm0QWiScxO3DNn OWHtUha5UDBiXZggIymG90L5U+g3OXsib1ZwVtuNzUfPfwmo9k57/EBU7ebDFbD86PoH 7uHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oXKkjU8f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gu21si10692008ejb.329.2019.07.26.10.50.54 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:50:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=oXKkjU8f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mm-0001qR-3d for patch@linaro.org; Fri, 26 Jul 2019 13:50:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56905) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4MY-0001ks-Ry for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4MX-0007Aa-Pd for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:38 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:37653) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4MX-00076A-KW for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:37 -0400 Received: by mail-pf1-x444.google.com with SMTP id 19so24852619pfa.4 for ; Fri, 26 Jul 2019 10:50:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ynwokCS+Kqgt3LfDdzexRygGm/TpfqdWtRJ/K6TofxQ=; b=oXKkjU8fglSAI1Jty8wDUH65ezOiFiflanv1iU7NYrrwB/qUNs7CJHIvK3eHLc6yJh vvfKYGb5XJCTgGneoT8ZzCTyuCWTywlHOcGOgGfxyHrGMeYP9YNN5ZJZ9lYxS+UikDKN x6NaBqJ2fTIeCKyhV8N6PJ/4AzT8lRR2oVtoOPT1rzONK4nBYbOPdHbTko7VQzmwYlQ4 tA4UwkjLpwjIQp6YQ8eYt5FNLZUlX3Dk3jnptgCokx/9J1CWJdbewYYCXKK6jg/YeDQb n8Ia07lzEC9oS+n+RvYVNor2nRRqHhxIto7TFlUl8myyIKiBDTn+hSPVBmlC7eRWvu11 fL9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ynwokCS+Kqgt3LfDdzexRygGm/TpfqdWtRJ/K6TofxQ=; b=tdXzd95eI10P3EqYQf7ZDm7lxcx+GjWi2knYxeHu5zGjDr+FuvMgQYbCa5WN4paanq bvu1dyjBVYAW1tDzBd3Ypea+MqaykJPERzAxIz85iFaIU1fTsiWz3dUCj2ZAemPlHILN wL/8ppXpK1DTTVVz/2QHDEQvK8DndLTWchFFY4dZrySUk6buuxRE3QwSXlrrWMFaLr7n u57fZ8/wPqZYTw47TU/JilDl15c0+F/KflNzFiYRBg4aktRsILMSNH5wbiKBy7Ux5KJ+ ototNItibZlEMKimACBin8EeNZeexMOZBHLkR9ru8SLoSWXcrw3rVu1cVj8IqO1fGB5E 9NIA== X-Gm-Message-State: APjAAAXk7FhcfSNdysMF6wX1BSpm6zHmUP0O/wZwB4yTwwIzz9NfQCPF iTRa9GeVpvAewbJNWUdNR0NwzY1B8kc= X-Received: by 2002:a63:2c8:: with SMTP id 191mr91125178pgc.139.1564163435378; Fri, 26 Jul 2019 10:50:35 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.34 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:26 -0700 Message-Id: <20190726175032.6769-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 01/67] decodetree: Allow !function with no input bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With this, we can have the function return a value from the DisasContext. Signed-off-by: Richard Henderson --- scripts/decodetree.py | 5 ++++- tests/decode/succ_function.decode | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) create mode 100644 tests/decode/succ_function.decode -- 2.17.1 diff --git a/scripts/decodetree.py b/scripts/decodetree.py index d7a59d63ac..4259d87a95 100755 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -195,7 +195,10 @@ class MultiField: """Class representing a compound instruction field""" def __init__(self, subs, mask): self.subs = subs - self.sign = subs[0].sign + if len(subs): + self.sign = subs[0].sign + else: + self.sign = 0 self.mask = mask def __str__(self): diff --git a/tests/decode/succ_function.decode b/tests/decode/succ_function.decode new file mode 100644 index 0000000000..632a9de252 --- /dev/null +++ b/tests/decode/succ_function.decode @@ -0,0 +1,2 @@ +%foo !function=foo +foo 00000000000000000000000000000000 %foo From patchwork Fri Jul 26 17:49:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169867 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp353642ilk; Fri, 26 Jul 2019 10:51:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqwQl7OdZMkr3t1byHHPSmD78ZdRbXwf6OiMndMrB+8wxzKihqem7FgCPgEyF2frWXid1kWm X-Received: by 2002:a0c:ae31:: with SMTP id y46mr69348003qvc.172.1564163467774; Fri, 26 Jul 2019 10:51:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163467; cv=none; d=google.com; s=arc-20160816; b=AhCP9hYeffksHlhegIEuzhcep7keRraOxMXr9YjcApl+hES9m39Ia5yRQqlkhRERZz BweEbx5mVJXsbdBC8U4m9fUkmCJevVrydILui7xri1Y/DA77BLA9j1sq7oBj3Nr/oGYr DjOyfTZAVgwiYkvGwCvGDf4kruBUQXCM7oYAjqWa4FUkvKa+YR9YlAhzcGfISdNt9Yil u8wGtSqxLosAv8BgrYYN9It1mMwsdBJ3CkA9VCJ4ME+aI7GCvRSJArUBhzGNOnKMJHDe RPDdNNvz/RC8AXCG+WM0j+yDlvjzwmFuM/LcZ4EintlVVIqLnBGVsojVWDlCwZ/rENow zZWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=7SlZHRojqaDrAigAWryRfk9aPa/pHb9UCpOA1gKKEjI=; b=HOGQX6/Ed03Wv65NHy0rzrCeazf7DYxj2ZArh1FlCvj7t/X5v/36jek/OEkSncv5l/ 1eAWqnIwnynXUJwVBa94HCQUG3lMKeI9u2o4py7xIapZkzb76alKySMYbQTje0epp+tZ h+y9xJmn1xWa4BPey3jGlTS2o1I29ru1tCZP8DjJfwNlVQXgFYvCuhzaiGkJ95A9VdV0 bVe/hHvKMz1wDAPG1+S7yCgxpzBvkqJ/GEG/8k3e3mow1qsJwigcOHe39Ul7qdjhfSoJ Hwj5W8cWkDNyb48QMJ2tcrHECbiMivwJzLpPEj6Oh9cTz6M2W3ipKgkxiSg9Dm8vNVCr GnXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LERFRk9H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 32si36187536qvj.16.2019.07.26.10.51.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:51:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LERFRk9H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42176 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4N0-0002rH-Vk for patch@linaro.org; Fri, 26 Jul 2019 13:51:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57156) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Me-0001tO-Mf for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Ma-0007I4-6H for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:44 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:34816) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4MZ-00079o-07 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:40 -0400 Received: by mail-pf1-x443.google.com with SMTP id u14so24877361pfn.2 for ; Fri, 26 Jul 2019 10:50:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7SlZHRojqaDrAigAWryRfk9aPa/pHb9UCpOA1gKKEjI=; b=LERFRk9HPSpHkSWvqJP4AF45a9EYb5Hly5D8dtugH9nx6e5yN/PBTDdNVSaC2Rts31 I9XoErtG+r8XTfVdEckBmiGAPqhWfBMELsm6p4JKVeKzA58YEOSL3yC3rAHZWj7pj/3b vH8LgHNeGhFo8VFDCDNmA50gkU7fx0GIfY3T5weG71XGK/mSdw0NhZmlARR/ExKUUFJr J395y0zBgnnyRcfCAfQR/WXkiG9p1IlwCoATCETpAjkokWM7Pxz4+HXASJTxNKMle2uq pK0IOLV8xEMXWsFX0ee+zgX5VDbmQv0h+Z/lRHo/bhji6L0C/mQLRWIFFw5iZGgtNHKp 4/iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7SlZHRojqaDrAigAWryRfk9aPa/pHb9UCpOA1gKKEjI=; b=DuogEeP2ac3Hmjo4QpEkgUL/wGsdVEje0gkTSx0bkRxNgR9shSoDe0Hc79B7jtf11l gb9tNqnJZ706degd+Fd72kIFx/sd2wXfnz/11oFVobrCvrAyjGIF4HMQgeaZXmYwwzel ABbGXuGSlwSCeX8LrdqK0YwrnpPdTjGHH24Zz6a/8gTCUBVHQN7ypruPd8GxZx7x/gZ1 kHnN1kzK5xkzdz0eUMxkB3O++qYmSbRNkBd+3Kkw8DNsTVhMmxr8HAIyBpHkqNek/VRf pHn+SFuRoFWBkrsXM6rLfuanbKcTbEduPfK5Rte6gDfkEHYucyAgg8vexZiNJPxxTBz5 woXQ== X-Gm-Message-State: APjAAAXbOXG/+ZjcXYJ16MfcEQmzi3ZwVMFISsfO8RfJogXBJQBiWL/v Uux21wHEeogmjgdI3g8t4brzKxwLc9c= X-Received: by 2002:a63:2252:: with SMTP id t18mr92745343pgm.5.1564163436713; Fri, 26 Jul 2019 10:50:36 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.35 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:27 -0700 Message-Id: <20190726175032.6769-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 02/67] target/arm: Remove offset argument to gen_exception_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The address of the current insn is still available in s->base.pc_next. Signed-off-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 6 +++--- target/arm/translate.c | 32 ++++++++++++++++---------------- 2 files changed, 19 insertions(+), 19 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 092eb5ec53..e7389bc057 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -96,10 +96,10 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) { if (s->fp_excp_el) { if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), + gen_exception_insn(s, EXCP_NOCP, syn_uncategorized(), s->fp_excp_el); } else { - gen_exception_insn(s, 4, EXCP_UDEF, + gen_exception_insn(s, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); } @@ -108,7 +108,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); - gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), + gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), default_exception_el(s)); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 7853462b21..33f78296eb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1247,11 +1247,11 @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) s->base.is_jmp = DISAS_NORETURN; } -static void gen_exception_insn(DisasContext *s, int offset, int excp, - int syn, uint32_t target_el) +static void gen_exception_insn(DisasContext *s, int excp, int syn, + uint32_t target_el) { gen_set_condexec(s); - gen_set_pc_im(s, s->pc - offset); + gen_set_pc_im(s, s->base.pc_next); gen_exception(excp, syn, target_el); s->base.is_jmp = DISAS_NORETURN; } @@ -1298,7 +1298,7 @@ static inline void gen_hlt(DisasContext *s, int imm) return; } - gen_exception_insn(s, s->thumb ? 2 : 4, EXCP_UDEF, syn_uncategorized(), + gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), default_exception_el(s)); } @@ -3175,7 +3175,7 @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, undef: /* If we get here then some access check did not pass */ - gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), exc_target); + gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), exc_target); return false; } @@ -3569,7 +3569,7 @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn) * for attempts to execute invalid vfp/neon encodings with FP disabled. */ if (s->fp_excp_el) { - gen_exception_insn(s, 4, EXCP_UDEF, + gen_exception_insn(s, EXCP_UDEF, syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } @@ -4840,7 +4840,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) * for attempts to execute invalid vfp/neon encodings with FP disabled. */ if (s->fp_excp_el) { - gen_exception_insn(s, 4, EXCP_UDEF, + gen_exception_insn(s, EXCP_UDEF, syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } @@ -6968,7 +6968,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) } if (s->fp_excp_el) { - gen_exception_insn(s, 4, EXCP_UDEF, + gen_exception_insn(s, EXCP_UDEF, syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } @@ -7091,7 +7091,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) off_rm = vfp_reg_offset(0, rm); } if (s->fp_excp_el) { - gen_exception_insn(s, 4, EXCP_UDEF, + gen_exception_insn(s, EXCP_UDEF, syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); return 0; } @@ -7584,7 +7584,7 @@ static void gen_srs(DisasContext *s, * For the UNPREDICTABLE cases we choose to UNDEF. */ if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) { - gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3); + gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), 3); return; } @@ -7620,7 +7620,7 @@ static void gen_srs(DisasContext *s, } if (undef) { - gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), + gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), default_exception_el(s)); return; } @@ -7711,7 +7711,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) * UsageFault exception. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(), + gen_exception_insn(s, EXCP_INVSTATE, syn_uncategorized(), default_exception_el(s)); return; } @@ -9254,7 +9254,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; default: illegal_op: - gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), + gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), default_exception_el(s)); break; } @@ -10288,7 +10288,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } /* All other insns: NOCP */ - gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), + gen_exception_insn(s, EXCP_NOCP, syn_uncategorized(), default_exception_el(s)); break; } @@ -10972,7 +10972,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } return; illegal_op: - gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), + gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), default_exception_el(s)); } @@ -11809,7 +11809,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) return; illegal_op: undef: - gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(), + gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), default_exception_el(s)); } From patchwork Fri Jul 26 17:49:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169866 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp353605ilk; Fri, 26 Jul 2019 10:51:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqz0VilkzYU1SuSKmXsrECOTrOimd0JeozV2J/QUbuMDbvcch8npSYl/Gy9dZC8LKjOMgMXL X-Received: by 2002:a37:b843:: with SMTP id i64mr61030728qkf.77.1564163465065; Fri, 26 Jul 2019 10:51:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163465; cv=none; d=google.com; s=arc-20160816; b=dWdo1miOZ8XM9QvfhsOrlr2iF3FcW8QB7MaiW6EgYpuXf63tV+X5+IC+noE0Gb6PYC aCFVF2vg09OBnHDEWJ85Sun59MkgQUQCY1gxi9OkhUO2g1qxTzqTt/J5Pmwn4xMcn5Mn splWB82Aon1t/WVO63xq0F6TaZA0WQyJXVkMq789sZ1BMUsk3VTmiWdb1VgEkEXyoDFk 1czaQlaALS46yOVbAZqW0wPwi524OSdKTD+Iq5k3ameIHVnpg7WRIfbBPplOE73Wj8/6 CwT6NhHsv6erB6MTo3WpK3aENi0/l8yuhkitA4nrvgJvOoyzLhRLLl5ei3472NrnGQFD ibJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=0JuwQx0rsSZ8qsmRHdUvrfpwMYNiERG9Y6tvmeQiWIA=; b=Nz38fc0c0hruaChDD1PUjKdzIPMc78xkUJhrBvWVwTJrPctGAp1OoI2KFKFII03mxT wv2St06A/29DGUXbJrWoiPJa2WKmI9VrcrW27urZ22w/TF98YvK4edI/nfk9UOb/xDxl AvnSqMD1RkHXie6Fz7mzGrG+DcZ/PMwKagDcvs33FgmU7RkQb2wsGXWUYqxhBr6LdE+D IJF98OQhva/fkmBHENYAfmuo9APhcWBIbLvJyoK83qQrnjTJhrbe5SClMDpMLNuG10Fk vYDh0SgAHNclYXUytA5spCpj8mumYsgyY+4H7DbtBMKzbrsNgHUqc5Kqa4YU+zBfCsQE 1Qhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mdDlubgV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s67si33395696qke.146.2019.07.26.10.51.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:51:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mdDlubgV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42168 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4My-0001rP-0P for patch@linaro.org; Fri, 26 Jul 2019 13:51:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57004) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mb-0001lW-7p for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Ma-0007IJ-8i for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:41 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:38249) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Ma-0007D6-2u for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:40 -0400 Received: by mail-pf1-x443.google.com with SMTP id y15so24860118pfn.5 for ; Fri, 26 Jul 2019 10:50:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=0JuwQx0rsSZ8qsmRHdUvrfpwMYNiERG9Y6tvmeQiWIA=; b=mdDlubgVyDpI0gBB/9wS4I3ZOTQgv4PpfZOk+KWeOqCkAjg83eDxHSixsyqM/xsBH/ BUVd6oQhdvo5O9aiW5mkGLz7dEIhy3r0ivcthlWlYuq4gGzBsfLKkHKBneIkiO919vcx t1WvOzaFxWjUepiRoMhwm5dfyd/rmBatVGkWj0EmEZAEC+syAvh0jVEbFIZmuA+YoA6t ysnYu1tw3IFx1kJynkc7h3HfJyre+u0vB8LD4He5RzXNQMnMiQlfcT2jvVgTb3AVFOfw y/ZcEUS0wdrLVSzBk/yeO36PMtHFp9rn7/FUPQRpmh53uzbZ+jZYm8uuGIhZtB1sk5lg sDDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=0JuwQx0rsSZ8qsmRHdUvrfpwMYNiERG9Y6tvmeQiWIA=; b=ffr9owdpy1THOs+hARYCoc8X4jsBDORmRC5DodLJbcTaaX9LYmZlWbBkd0l+zBsGpm A9UTEDG4CCA1RY3eeUjiDWfCYJjbXTYh3aa5UccM3aPOcu13zxbxZ1OQDlkVhjFP/q4e 8ShejMFIY64eOj11x0OjVQe6fqZTzmsFYMtTImp0Mu52kVHwCTOeJsBEZ3CfhaYinZ5c VGNkrZexU/Bsg9CERrIbBLmX0grd+iGk25ti9mygn/GyCSLG3Jmdul2WfImVVNN+z56/ 5P8Y2qLi8WddPqRuJfC1YXo2v02IL715fzYIRh5FljGT6vWMkr4vndpnqHXgfFeqYXbU 7c6g== X-Gm-Message-State: APjAAAUXdiiip2N6vUUj1a1A83wCiKcVGxYGemS8bSqPSUdiFsEvLNnV 7whWKJxx4AU24jCSfNUe4ogaRTgdPNY= X-Received: by 2002:a17:90a:3463:: with SMTP id o90mr101503225pjb.15.1564163437889; Fri, 26 Jul 2019 10:50:37 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.36 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:28 -0700 Message-Id: <20190726175032.6769-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 03/67] target/arm: Remove offset argument to gen_exception_bkpt_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The address of the current insn is still available in s->base.pc_next. Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 33f78296eb..19b126d4f3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1256,12 +1256,12 @@ static void gen_exception_insn(DisasContext *s, int excp, int syn, s->base.is_jmp = DISAS_NORETURN; } -static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn) +static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) { TCGv_i32 tcg_syn; gen_set_condexec(s); - gen_set_pc_im(s, s->pc - offset); + gen_set_pc_im(s, s->base.pc_next); tcg_syn = tcg_const_i32(syn); gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); tcg_temp_free_i32(tcg_syn); @@ -8139,7 +8139,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 1: /* bkpt */ ARCH(5); - gen_exception_bkpt_insn(s, 4, syn_aa32_bkpt(imm16, false)); + gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false)); break; case 2: /* Hypervisor call (v7) */ @@ -11611,7 +11611,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) { int imm8 = extract32(insn, 0, 8); ARCH(5); - gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true)); + gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); break; } From patchwork Fri Jul 26 17:49:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169868 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp354270ilk; Fri, 26 Jul 2019 10:51:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqw4n6GOvc/XYnMcLwpQQ6/1jGEwXx8dRapcEzsJQHlBHAKYd8BQr6Wrx7tfYOZtinjQTIPJ X-Received: by 2002:a50:987a:: with SMTP id h55mr85248641edb.108.1564163509664; Fri, 26 Jul 2019 10:51:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163509; cv=none; d=google.com; s=arc-20160816; b=QJ5/X7IDk/vS1ubIyRAdHi9Q+9HsYL0qnyT3ZnBvF0a4XN+DeYeZwzpzkJuTxZPUL+ 7jB3qgbL9cgxGF3or4+d/uM+4c02hyIqILFqgzRaniBOzWX6Qsy8APzIdy6mtU2C8jJf nad8BTUCFAUWW2H7BCvlffL88/HwNWqiNKyUTZCqr7jznRtnhPGhJKzLWiZPRnkONHlU n+i/4dHrgIEhCMTowI5vUrTvbTgGz/K7Gh1Zo+2IU8VaEXZYeRC1pFs5vZAsdoOtPkT+ mcUWaAgW6AuRM+U6MKF6uHe2yWAVBSOMhlwAnK7qsJSwVDiiWpgbOI9ItQ5pEh9uvp/X tLpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=hX3AW17o2PIgWW1hwgb4F4i9rjNSXrxFa91FWtRbpGo=; b=B5TTQyI6765WErlRyoSNTdoc0vdLVErJZgGOwU6mk1jJGQoI9meNbqeNWxOMnI64JQ hXVhmnjNSU32nfmfNYTW6/ODOUgNN86uensHakN5ykorfD1WrEe8tx7xftOwAU6q7a3d LMtlxYklBMZVZhVYkDS4Ll79PAQOBIcKk9caBqKEym/1CYoxYYcA1UQp5eQ5xuR4dHVm 9WxrOGf+cxryqKeVHDemnUt5kfvzekshr0Z5KoBx+M51/ZqLFcHTmSKqsLVNwwMlQqX8 AP/RaN+xFtWE3fP4LPH72CkTST0hmrz7RUuyWYxh7PVK6YIR4OgLVq/80POyFRZ6A2eO vCvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gLloNoZO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q18si11051506eju.227.2019.07.26.10.51.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:51:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gLloNoZO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42196 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nf-0005nu-9Y for patch@linaro.org; Fri, 26 Jul 2019 13:51:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57120) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Md-0001pV-Up for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mc-0007Ok-Rt for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:43 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:43171) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mc-0007Hs-Lk for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:42 -0400 Received: by mail-pl1-x643.google.com with SMTP id 4so18030133pld.10 for ; Fri, 26 Jul 2019 10:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hX3AW17o2PIgWW1hwgb4F4i9rjNSXrxFa91FWtRbpGo=; b=gLloNoZOxtLByK/MTAwGv6CqokWdIJ7gMXXF9egTgTBWUsY6ZOo5ryePADqYcs71y4 GEmlszug5YpaT4L+LTC6lFAofXr2J8Vnb1w+80oi8P0WfwcFBLeMN95dIr7IHKsSp5QU dXi5YcfuRUs3UvRJamcM+bSv72P9koioiekJg1/5gI+mzfdDCHLJA7KIMvDbC2IOAhI4 ldJRiPTDMBoynB2mBsKBu+y79Ro2DUABd4M2m6s2K3TceLQh2f9FVJOiWcwfYUl2qIf6 KDE4rvwKc78uHf8ygfhD+xBBpBDuTbFiYKSVZkKRiC0FmGRgHkHcSnmVBH/tl6nwonq8 vWYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hX3AW17o2PIgWW1hwgb4F4i9rjNSXrxFa91FWtRbpGo=; b=OUOVDFhwx8TnD3ugpGTKkhYl1m1UCMxP2wiB+bY9bW4qv7YA7Tz4z5wLtBrpsHsAoL BXqsj/o2H5BZqq83A757iGh1z4xYsrL35MKLcCSYkTuXjAGc/hqK1ia1eDwECd6qzVzA FyhYOL/NjHOzqOZaFHRCpObvgtQ+ku/EWrUbFlaUkFZbK56llwuGiRo3jG2D97n0AoNj Xa0+BnC2m/73LPsnOpZCdEsG58ZHxoRL2VTR39aLCeL1MMFuokztTd/pNrKtawxrRsom cNbsH3UmqxSNm6laVvaaTkmrYYh6g89EHkoyJCBGOxZiT2kdpK60jMs/p0ePM6LB03G5 sljA== X-Gm-Message-State: APjAAAVTZlUNyWz37rbj7HhmSu7mnT3i8qwo0u3rInjD1QzSZkvM8yQj /M+QdWZ+aHGFjPbLjzho+/jwgfWk6C4= X-Received: by 2002:a17:902:2ac8:: with SMTP id j66mr93064289plb.273.1564163439414; Fri, 26 Jul 2019 10:50:39 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.38 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:29 -0700 Message-Id: <20190726175032.6769-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 04/67] target/arm: Remove offset argument to gen_exception_internal_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The actual argument is 0 for all callers. Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 19b126d4f3..0848fb933a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1239,10 +1239,10 @@ static inline void gen_smc(DisasContext *s) s->base.is_jmp = DISAS_SMC; } -static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) +static void gen_exception_internal_insn(DisasContext *s, int excp) { gen_set_condexec(s); - gen_set_pc_im(s, s->pc - offset); + gen_set_pc_im(s, s->pc); gen_exception_internal(excp); s->base.is_jmp = DISAS_NORETURN; } @@ -1294,7 +1294,7 @@ static inline void gen_hlt(DisasContext *s, int imm) s->current_el != 0 && #endif (imm == (s->thumb ? 0x3c : 0xf000))) { - gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); + gen_exception_internal_insn(s, EXCP_SEMIHOST); return; } @@ -11984,7 +11984,7 @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, /* End the TB early; it's likely not going to be executed */ dc->base.is_jmp = DISAS_TOO_MANY; } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + gen_exception_internal_insn(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be properly cleared -- thus we From patchwork Fri Jul 26 17:49:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169869 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp354496ilk; Fri, 26 Jul 2019 10:52:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqzhrOGmsRO8mZJQuQv/u1VLFdSswiB3IIdkLb9YO51DU7Z8fu0STlyGrfoo3SxUdWuBM2mQ X-Received: by 2002:a17:906:b34d:: with SMTP id cd13mr73581674ejb.107.1564163524681; Fri, 26 Jul 2019 10:52:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163524; cv=none; d=google.com; s=arc-20160816; b=FvUBctx4EkrCuk7EZJ/9Ggqkf7jBt+AiH1MEdiqanTITIH8atsQ8upSGB0Tfyeo3eW 4E6YZJO3RN8J1PAL0/BvJleEQsL1ao3J+vifE4bisGQRQZEtZLIQajgAdY0eTA0T3CLZ oSfmW9Npey0pmpB+c68f3cNw4vXKscxXN2VoaBkASgDuvWb60dDid60Z7Q2aNiQtcBrt zDu8/3sOXbyBq1d0kay5TDv9akuFEfwbDUZEQoyohdJ8yIZ7AfGFvXMeYRbgLvMXQUxp EX3oBMC3m9rY6ZPTSYEPazewdp+FMRW8PRhunNYSFt90KW18FqT9u24pnBDhWrajCrWd Vr6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=7qMkBV6xIInqYLHQbsNGGIckvY18Pfy+zYd9EjT4q5E=; b=ZYw3MStuF7lBlKA3bN2PenKPtuEqN0qgwnAXawx6brQR429EBhfUZNLtfzzfneJfGn jSjXUdRWVAxXXtiOs80Asbn5Bh9hLrkG7iRlJPRgQ5TKNWm/z9JnLShWhvHowwOCEuN6 0wOuQ1w9x75Ix0A9y36dC8ywZWVKD9Th1aJQpCTj4Ft6IR1b2N8ljnFwzE66/36eJh7d 8J6+4wlhRkowpKWmNiGFmPQedyPaPywnI2HMjh15FR5mr9mdKMzN10jdvaBn9h3DkOh5 gCfnJqS7ix+Dm8M5eOLoXBHaRNDudN+oYvW5Nc/BEs2JkrCuxNcO4Q7+aPS/9HvNnXIB Crsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HsnHg8Za; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t2si13362999edq.237.2019.07.26.10.52.04 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:52:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HsnHg8Za; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nu-0005zX-MD for patch@linaro.org; Fri, 26 Jul 2019 13:52:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57076) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mc-0001mQ-Tj for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mb-0007Me-RM for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:42 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:38137) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mb-0007LC-Ln for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:41 -0400 Received: by mail-pl1-x644.google.com with SMTP id az7so25001434plb.5 for ; Fri, 26 Jul 2019 10:50:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7qMkBV6xIInqYLHQbsNGGIckvY18Pfy+zYd9EjT4q5E=; b=HsnHg8ZaUxSGLCpbuDc4pmqUNrk330qSqmCO7NJTJx3m/vp85OhDyq2sIfoOQMvEbC zwJTp6aCdSb8Vzb5I3MzM/8NsArcdkXmTDaputpA722tHqznS9eORwuHooib+qqP6QPX i4jgNJnIHUVe00Xv060oFeiZXLFCKKhZWa5JReNbzYgaAUay+JlIWvlmRee4OYAushcY 4plOVDzEuzXkEswad/+xa69p7Z7piLmNqV87qxYkjE+jbdyvH9bjbZxUdW5Y5JYhJ+3Y kEciIOkrHb7VL37Qaa59SQ0V+Er9+A7aybjUXqZYyK8jIcVNVueuEv6o3qiwkRkNOKkv wNmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7qMkBV6xIInqYLHQbsNGGIckvY18Pfy+zYd9EjT4q5E=; b=Myr/zzSA4NqkVChSo8NuqX9ct8Ff6dxoBjTt49ei+Xe3pVPBgfABOq40dhFcAWrTVj Pea5JmwdfKFXK19jQ5ekTPYmpuZ70E4kFNyZwZhsrWflSL/h1kJpo25u89tspI1GrCUl 2U116H9I76FGyGgJbi5h8cxsGkDo5SL0FJ3AfBryG3F4bek27dleUN8vjUI6e7ocpmaa 017kzFnjOp2yu2+9J3W16bTT6avrQjNz70Cui46ydJR14Tcfcy2DnJBaaG0vtacU8JUT cLcPY4INIfZn2JpZqn6W4VI0eKXgl2d3Ez6MEfjafJrzT3Yb/u10DzIbIXfzfdw/KvHv mP0g== X-Gm-Message-State: APjAAAU2rKZseSAH0O2scxPtUJkV4tAIfxkR0iodlgJrZx3qWZ5ZLm7n UYPtOxZpqrX44eBbA4qgSqzMXH87DdI= X-Received: by 2002:a17:902:4201:: with SMTP id g1mr97729634pld.300.1564163440520; Fri, 26 Jul 2019 10:50:40 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.39 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:30 -0700 Message-Id: <20190726175032.6769-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 05/67] target/arm: Use the saved value of the insn address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The address of the current insn is still available in s->base.pc_next, and need not be recomputed from s->pc - 4. Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 0848fb933a..595385e1b1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1212,7 +1212,7 @@ static inline void gen_hvc(DisasContext *s, int imm16) * as an undefined insn by runtime configuration (ie before * the insn really executes). */ - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); gen_helper_pre_hvc(cpu_env); /* Otherwise we will treat this as a real exception which * happens after execution of the insn. (The distinction matters @@ -1231,7 +1231,7 @@ static inline void gen_smc(DisasContext *s) */ TCGv_i32 tmp; - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tmp = tcg_const_i32(syn_aa32_smc()); gen_helper_pre_smc(cpu_env, tmp); tcg_temp_free_i32(tmp); @@ -3190,7 +3190,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) /* Sync state because msr_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tcg_reg = load_reg(s, rn); tcg_tgtmode = tcg_const_i32(tgtmode); tcg_regno = tcg_const_i32(regno); @@ -3212,7 +3212,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) /* Sync state because mrs_banked() can raise exceptions */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tcg_reg = tcg_temp_new_i32(); tcg_tgtmode = tcg_const_i32(tgtmode); tcg_regno = tcg_const_i32(regno); @@ -7219,7 +7219,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); tmpptr = tcg_const_ptr(ri); tcg_syn = tcg_const_i32(syndrome); tcg_isread = tcg_const_i32(isread); @@ -7629,7 +7629,7 @@ static void gen_srs(DisasContext *s, tmp = tcg_const_i32(mode); /* get_r13_banked() will raise an exception if called from System mode */ gen_set_condexec(s); - gen_set_pc_im(s, s->pc - 4); + gen_set_pc_im(s, s->base.pc_next); gen_helper_get_r13_banked(addr, cpu_env, tmp); tcg_temp_free_i32(tmp); switch (amode) { From patchwork Fri Jul 26 17:49:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169872 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp355044ilk; Fri, 26 Jul 2019 10:52:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqxnIx0DCxEnt8g0l9/HUJqAHkSKp+X4Tpl3m6CosNMXnBEtHrE+BfbsYbrc7RCdT+t54B84 X-Received: by 2002:a0c:e6cb:: with SMTP id l11mr67959804qvn.136.1564163559121; Fri, 26 Jul 2019 10:52:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163559; cv=none; d=google.com; s=arc-20160816; b=S7a+TupN5tvJRkK0OQxzZWuJAkebpPkMs9doVnwE5YN+6T86KMCKFWb80jVEwkKiqD 6jSw+Vde7WXiEsBA036Ox1Yxf2AqjADtswhqIfp2d3bDhFatf8fp6nNpqYlWRWm0BAGb if3LCAitKW/bGWDfY8wYdPXrvp/Msczjjgo0crUNVnbGDhOJ/h6W737fMfzkqXAZea+9 fKSSdhZU4HIabza0nxzaTB53iidPnqfwdbYDm8HEug6f80YkbjWVS9KOtbseErofhj1L 0CTwnpHeQVsTRuze8/9j8R0POw6ZmiVKtyrmGqBaikZARvELsEVAUFdCB6WBt5e7oYCy 1WLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=6LNL9cQ9yWdMRQZwn41TfZpx+HeuRN2JtOhgGfdhQks=; b=W8k02AVB8umzY2iIkt9czBWdbIba4BsbusNd9KM9NfdUGTmSoBXgEkyDClngZkqdyR wnwgyZVV21JFPzPJwxQZD+CwZznn4TtLnOR725HAFlXIzRv9B3T2A5ybP/+96hVZUFEe 5bJZf5Bk0rCX28sQYJSKod1kmtC1sHLTbTG1DVI8nWBb9wZr4qiSwB5LpFoHr5vIn9EV AwEiEL/YfArY9M+bH9X7MPwQDMqhIak9zuhJqtiO/YghIulIQw5oqxCLXm47V6QWjf2M KKm+6APuNfd7epVHhJ2PNFiyybf/UHdxH37s1XhwDw6YvCTYOZ06uFs5cl9ZkOt5xI5N 1Vdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AEPIVRJL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k55si12453939qtb.327.2019.07.26.10.52.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:52:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=AEPIVRJL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4OS-00012I-Ph for patch@linaro.org; Fri, 26 Jul 2019 13:52:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57202) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mf-0001yU-MA for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Me-0007SK-3e for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:45 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:43778) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Md-0007Nt-SD for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:44 -0400 Received: by mail-pg1-x541.google.com with SMTP id f25so25099263pgv.10 for ; Fri, 26 Jul 2019 10:50:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6LNL9cQ9yWdMRQZwn41TfZpx+HeuRN2JtOhgGfdhQks=; b=AEPIVRJLeTkmpkjpMSvPSsr7TtKp5T8GAvionYrUfv63wLNamHKVC0JHNww/VFwegK 2iz+YmbJ1Xhk5BHFySQCkFZoNeWTwvAevyfV2FmjiKi7xh/jnWrMpdTh1CMezdw9Lf8c C8R++Kwe3wfsdrjB8p2hGze3Kac2MS7ytX+sM9446ZmAObLxSg4pclC19AIm1cTTCHm9 z7JpWshbvctFgUrhJuz55H8kaCAgC0YHwlolii2pXJlT4udtrYrU9QTbaSHghBAib7J9 PvMT/0mGE2p0JmIll4Ge2riBl3XXvJDMLtfTugWD6cfid7uDJ9b0ydrudecJbo6pcUjl bOdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6LNL9cQ9yWdMRQZwn41TfZpx+HeuRN2JtOhgGfdhQks=; b=rPaj0WWRDj8uTEFbheeF8YwY507MRpWp8cxj2EgWn2WXwL34D1pfXEgQ1wRjfjKe14 viivIAg4r9FJw7q3u9KxeG2YTKwnkabh2DwtkjSu1N3uijp4r7Kyr6aYQB5cu8H7yUTa 3gnTko/04vhOuweqbELbCvqAe8ErcjuHf3WCUTJphqjZ/6BG5rLEZ0KsXx3QtDSq/zsB M4jbHbONPKy4EiZimdXcXtJ0xUE0sS5C0iNIMnP13XgWolq5Gj2W9GLpkm3jz/JMmo41 WNcaym2FWlnGPChd88Oc8C+3uIozz18tInQb4LWI9rlhPfAv7BBtMfmluyxwBgJktdVK mZ/Q== X-Gm-Message-State: APjAAAVSjmEYOFqpM6dSvUO18D1jyzUtrkdX161zy4rM+IDjr0lYLxP6 IAvEDT3tvDhGbLgZDHbYqI76t5TSVVE= X-Received: by 2002:a17:90a:4803:: with SMTP id a3mr101406097pjh.58.1564163441598; Fri, 26 Jul 2019 10:50:41 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.40 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:31 -0700 Message-Id: <20190726175032.6769-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 06/67] target/arm: Introduce pc_read X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We currently have 3 different ways of computing the architectural value of "PC" as seen in the ARM ARM. The value of s->pc has been incremented past the current insn, but that is all. Thus for a32, PC = s->pc + 4; for t32, PC = s->pc; for t16, PC = s->pc + 2. These differing computations make it impossible at present to unify the various code paths. Let s->pc_read hold the architectural value of PC for all cases. Signed-off-by: Richard Henderson --- target/arm/translate.h | 10 ++++++++ target/arm/translate.c | 53 ++++++++++++++++++------------------------ 2 files changed, 32 insertions(+), 31 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.h b/target/arm/translate.h index a20f6e2056..2dfdd8ca66 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -9,7 +9,17 @@ typedef struct DisasContext { DisasContextBase base; const ARMISARegisters *isar; + /* + * Summary of the various values for "PC": + * base.pc_next -- the start of the current insn + * pc -- the start of the next insn + * pc_read -- the value for "PC" in the ARM ARM; + * in arm mode, the current insn + 8; + * in thumb mode, the current insn + 4; + * in aa64 mode, unused. + */ target_ulong pc; + target_ulong pc_read; target_ulong page_start; uint32_t insn; /* Nonzero if this instruction has been conditionally skipped. */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 595385e1b1..a48e9a90f8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -200,13 +200,7 @@ static inline void store_cpu_offset(TCGv_i32 var, int offset) static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg) { if (reg == 15) { - uint32_t addr; - /* normally, since we updated PC, we need only to add one insn */ - if (s->thumb) - addr = (long)s->pc + 2; - else - addr = (long)s->pc + 4; - tcg_gen_movi_i32(var, addr); + tcg_gen_movi_i32(var, s->pc_read); } else { tcg_gen_mov_i32(var, cpu_R[reg]); } @@ -7868,16 +7862,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* branch link and change to thumb (blx ) */ int32_t offset; - val = (uint32_t)s->pc; tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, val); + tcg_gen_movi_i32(tmp, s->pc); store_reg(s, 14, tmp); /* Sign-extend the 24-bit offset */ offset = (((int32_t)insn) << 8) >> 8; + val = s->pc_read; /* offset * 4 + bit24 * 2 + (thumb bit) */ val += (offset << 2) | ((insn >> 23) & 2) | 1; - /* pipeline offset */ - val += 4; /* protected by ARCH(5); above, near the start of uncond block */ gen_bx_im(s, val); return; @@ -9154,9 +9146,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* store */ if (i == 15) { /* special case: r15 = PC + 8 */ - val = (long)s->pc + 4; tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, val); + tcg_gen_movi_i32(tmp, s->pc_read); } else if (user) { tmp = tcg_temp_new_i32(); tmp2 = tcg_const_i32(i); @@ -9222,14 +9213,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) int32_t offset; /* branch (and link) */ - val = (int32_t)s->pc; if (insn & (1 << 24)) { tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, val); + tcg_gen_movi_i32(tmp, s->pc); store_reg(s, 14, tmp); } offset = sextract32(insn << 2, 0, 26); - val += offset + 4; + val = s->pc_read + offset; gen_jmp(s, val); } break; @@ -9484,7 +9474,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } addr = tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, s->pc & ~3); + tcg_gen_movi_i32(addr, s->pc_read & ~3); } else { addr = load_reg(s, rn); } @@ -9590,7 +9580,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Table Branch. */ if (rn == 15) { addr = tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, s->pc); + tcg_gen_movi_i32(addr, s->pc_read); } else { addr = load_reg(s, rn); } @@ -9609,7 +9599,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } tcg_temp_free_i32(addr); tcg_gen_shli_i32(tmp, tmp, 1); - tcg_gen_addi_i32(tmp, tmp, s->pc); + tcg_gen_addi_i32(tmp, tmp, s->pc_read); store_reg(s, 15, tmp); } else { bool is_lasr = false; @@ -10342,7 +10332,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_gen_movi_i32(cpu_R[14], s->pc | 1); } - offset += s->pc; + offset += s->pc_read; if (insn & (1 << 12)) { /* b/bl */ gen_jmp(s, offset); @@ -10583,7 +10573,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) offset |= (insn & (1 << 11)) << 8; /* jump to the offset */ - gen_jmp(s, s->pc + offset); + gen_jmp(s, s->pc_read + offset); } } else { /* @@ -10694,7 +10684,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } else { /* Add/sub 12-bit immediate. */ if (rn == 15) { - offset = s->pc & ~(uint32_t)3; + offset = s->pc_read & ~(uint32_t)3; if (insn & (1 << 23)) offset -= imm; else @@ -10830,8 +10820,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (rn == 15) { addr = tcg_temp_new_i32(); /* PC relative. */ - /* s->pc has already been incremented by 4. */ - imm = s->pc & 0xfffffffc; + imm = s->pc_read & 0xfffffffc; if (insn & (1 << 23)) imm += insn & 0xfff; else @@ -11077,7 +11066,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) if (insn & (1 << 11)) { rd = (insn >> 8) & 7; /* load pc-relative. Bit 1 of PC is ignored. */ - val = s->pc + 2 + ((insn & 0xff) * 4); + val = s->pc_read + ((insn & 0xff) * 4); val &= ~(uint32_t)2; addr = tcg_temp_new_i32(); tcg_gen_movi_i32(addr, val); @@ -11464,7 +11453,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } else { /* PC. bit 1 is ignored. */ tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2); + tcg_gen_movi_i32(tmp, s->pc_read & ~(uint32_t)2); } val = (insn & 0xff) * 4; tcg_gen_addi_i32(tmp, tmp, val); @@ -11584,7 +11573,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); tcg_temp_free_i32(tmp); offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; - val = (uint32_t)s->pc + 2; + val = s->pc_read; val += offset; gen_jmp(s, val); break; @@ -11750,7 +11739,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) arm_skip_unless(s, cond); /* jump to the offset */ - val = (uint32_t)s->pc + 2; + val = s->pc_read; offset = ((int32_t)insn << 24) >> 24; val += offset << 1; gen_jmp(s, val); @@ -11776,9 +11765,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) break; } /* unconditional branch */ - val = (uint32_t)s->pc; + val = s->pc_read; offset = ((int32_t)insn << 21) >> 21; - val += (offset << 1) + 2; + val += offset << 1; gen_jmp(s, val); break; @@ -11802,7 +11791,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */ uint32_t uoffset = ((int32_t)insn << 21) >> 9; - tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset); + tcg_gen_movi_i32(cpu_R[14], s->pc_read + uoffset); } break; } @@ -12055,6 +12044,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) insn = arm_ldl_code(env, dc->pc, dc->sctlr_b); dc->insn = insn; + dc->pc_read = dc->pc + 8; dc->pc += 4; disas_arm_insn(dc, insn); @@ -12123,6 +12113,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) insn = arm_lduw_code(env, dc->pc, dc->sctlr_b); is_16bit = thumb_insn_is_16bit(dc, insn); + dc->pc_read = dc->pc + 4; dc->pc += 2; if (!is_16bit) { uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b); From patchwork Fri Jul 26 17:49:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169871 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp354815ilk; Fri, 26 Jul 2019 10:52:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqxDhBTF4T6UjZliS4Ytx6ZPC340O76/OJo+hCS8b13jqvgfFhF4WXtQvLKwUMkEzdNfkyZa X-Received: by 2002:a17:906:1911:: with SMTP id a17mr73956563eje.290.1564163545216; Fri, 26 Jul 2019 10:52:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163545; cv=none; d=google.com; s=arc-20160816; b=gD47RgPyfenmdnsIjGIecSKE99d7suY44CrFDv2+xmpiELh2/kj3yoj6dxZQf8mMxM FEf86E9a7lSuIS8uAlKnsAZQAjC9A2CmNpVJVNk45kJVbOgAweQ21eBRmFBIOZ+U6v6L odMKeV2IcghvLYAFgZIr4peY6Vh5bhT/sy2eF3w75U0lO4APRzB6Wisk607usrZfwNbd dfvGkJLK5r+3jQDLipXfdAxFej51Was3cowC1MSyYXbEIB32RJvdW1AByeBsq95gh/x4 pvPZf9V6EJilElQrzjR0mHQKJLTQ12y2IYezcc9ZO95uPtd7ppb52VpQGxvssUUDM87o m8wg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Pnib07gWtNaIz4hXa+LeNfIkt6V2ivnRlJh4fSqlOtg=; b=iZB5//BGcdXlnCxkeIURGgERCml/ZkjZmx8tn0oXW6O3tE9PGrnrV4vYWs/B8Z88MV 8g5AGdxn6IbcBXtr0u4MVxoLrxCFQVqr45+DFt5ryn2Z2jJ4bJsLX93PlzpP7uSyiPYX tLrwf+ymIShK+WBYT9mtxd/Op5enLb1ZaGmSNj7v4s+C890AXMNZNtDag/pD62HR32Xm zkCaIsuy813zAoiN9pHVtNchMfKR8yTB5x3pNYEx88MaYnCrZaQLDs4J1fLXf6WXSNPX uA8I8l0dXgJkmqgoEjK0G0j89czc+FbO9DNtY1uKGffDWzqysjU60bkEgS3Ik+XBfVGJ /roA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yymeXIZo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q18si11052247eju.227.2019.07.26.10.52.24 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:52:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yymeXIZo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42218 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4OE-00079W-DG for patch@linaro.org; Fri, 26 Jul 2019 13:52:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57204) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mf-0001yj-Px for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Me-0007Sb-6U for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:45 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:47016) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Md-0007Qi-UX for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:44 -0400 Received: by mail-pf1-x443.google.com with SMTP id c3so1719748pfa.13 for ; Fri, 26 Jul 2019 10:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Pnib07gWtNaIz4hXa+LeNfIkt6V2ivnRlJh4fSqlOtg=; b=yymeXIZoGGWSsCTrKP+HCYXDSwRBBeCIMq4Mz+1ZRSsqYYuYyAHFTqVM7/UZVqagaw cYLawWwjccTvUpZcE6D7P8sp/narzyhkCsCBk0HkNwN2Z5AbkhN0x9nXEar4B4rIt3M8 iHhcyjrmB1NMA9nJDtLOE1K9EleEN+/nU9i+704l6d1+RPamG3rDiOQet3vsoR4aHneN z1K7IZmrGFG6v+CqRGp21XnFVdFW1LJSzQey7maUCB/3NRE3czaxTLFxaqeQkSeyuSYR R1+m6ZXKkZ+5jslzWSc9QlJYhraVgGKsMKgS73u/+QAyB+Br1dBsDobT5wRNSci6XbRn D2ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Pnib07gWtNaIz4hXa+LeNfIkt6V2ivnRlJh4fSqlOtg=; b=FwmgrD8/5NpMJwYQNFwqT3j9j9fm8DMDtUZlP8GfYQMdgDxlT2pmcVI2EVCRpRWtxH zg7LmCLTA/0pYqz959/q/kssNYRy6FbYCvPjPhefKnT9wXIGyK/k5DjPAc5C9DKnlSNA nFcd4pbNC9V2IKRXauyvtkTcAxJDH2992La8Bv9qZ1xLMGlqK4mFNDJiV/6hJ9MUQHpH Ala2Wd3AN6pL9hq/lzlxgk/cqOM336LyuNzHpvVQp0e61Zexdi+pVffcaqVnUvrQ5qp7 NrlerC16y3PfXPgvtecjrC2Qxwbig9cHHki+WlFO09AyHvxu4tK4CSGAasORjUTu0xCD QYjg== X-Gm-Message-State: APjAAAV7pMqEvPXa8NwQN0putQd2OeO/LGc0tjl8v02WU3xfPAaHDRx9 e4i6R9Tft3RMTNUC0Ju0FyaKArOnIfk= X-Received: by 2002:a62:2d3:: with SMTP id 202mr23838214pfc.131.1564163442663; Fri, 26 Jul 2019 10:50:42 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.41 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:32 -0700 Message-Id: <20190726175032.6769-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 07/67] target/arm: Introduce add_reg_for_lit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Used only on the thumb side so far, but will be more obvious once we start unifying the implementation of A32+T32. Signed-off-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 34 +------ target/arm/translate.c | 163 +++++++++++++++------------------ 2 files changed, 76 insertions(+), 121 deletions(-) -- 2.17.1 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index e7389bc057..4066b2febf 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -941,14 +941,7 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a) offset = -offset; } - if (s->thumb && a->rn == 15) { - /* This is actually UNPREDICTABLE */ - addr = tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, s->pc & ~2); - } else { - addr = load_reg(s, a->rn); - } - tcg_gen_addi_i32(addr, addr, offset); + addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i32(); if (a->l) { gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); @@ -983,14 +976,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a) offset = -offset; } - if (s->thumb && a->rn == 15) { - /* This is actually UNPREDICTABLE */ - addr = tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, s->pc & ~2); - } else { - addr = load_reg(s, a->rn); - } - tcg_gen_addi_i32(addr, addr, offset); + addr = add_reg_for_lit(s, a->rn, offset); tmp = tcg_temp_new_i64(); if (a->l) { gen_aa32_ld64(s, tmp, addr, get_mem_index(s)); @@ -1029,13 +1015,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a) return true; } - if (s->thumb && a->rn == 15) { - /* This is actually UNPREDICTABLE */ - addr = tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, s->pc & ~2); - } else { - addr = load_reg(s, a->rn); - } + addr = add_reg_for_lit(s, a->rn, 0); if (a->p) { /* pre-decrement */ tcg_gen_addi_i32(addr, addr, -(a->imm << 2)); @@ -1112,13 +1092,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a) return true; } - if (s->thumb && a->rn == 15) { - /* This is actually UNPREDICTABLE */ - addr = tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, s->pc & ~2); - } else { - addr = load_reg(s, a->rn); - } + addr = add_reg_for_lit(s, a->rn, 0); if (a->p) { /* pre-decrement */ tcg_gen_addi_i32(addr, addr, -(a->imm << 2)); diff --git a/target/arm/translate.c b/target/arm/translate.c index a48e9a90f8..5e2dd8bb16 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -214,6 +214,23 @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg) return tmp; } +/* + * Create a new temp, incremented by OFS, except PC is aligned but not + * incremented for thumb. This is used for load/store for which use of + * PC implies (literal), or ADD that implies ADR. + */ +static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + + if (reg == 15) { + tcg_gen_movi_i32(tmp, (s->pc_read & ~3) + ofs); + } else { + tcg_gen_addi_i32(tmp, cpu_R[reg], ofs); + } + return tmp; +} + /* Set a CPU register. The source must be a temporary and will be marked as dead. */ static void store_reg(DisasContext *s, int reg, TCGv_i32 var) @@ -9468,16 +9485,12 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) */ bool wback = extract32(insn, 21, 1); - if (rn == 15) { - if (insn & (1 << 21)) { - /* UNPREDICTABLE */ - goto illegal_op; - } - addr = tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, s->pc_read & ~3); - } else { - addr = load_reg(s, rn); + if (rn == 15 && (insn & (1 << 21))) { + /* UNPREDICTABLE */ + goto illegal_op; } + + addr = add_reg_for_lit(s, rn, 0); offset = (insn & 0xff) * 4; if ((insn & (1 << 23)) == 0) { offset = -offset; @@ -10683,27 +10696,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); } else { /* Add/sub 12-bit immediate. */ - if (rn == 15) { - offset = s->pc_read & ~(uint32_t)3; - if (insn & (1 << 23)) - offset -= imm; - else - offset += imm; - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, offset); - store_reg(s, rd, tmp); + if (insn & (1 << 23)) { + imm = -imm; + } + tmp = add_reg_for_lit(s, rn, imm); + if (rn == 13 && rd == 13) { + /* ADD SP, SP, imm or SUB SP, SP, imm */ + store_sp_checked(s, tmp); } else { - tmp = load_reg(s, rn); - if (insn & (1 << 23)) - tcg_gen_subi_i32(tmp, tmp, imm); - else - tcg_gen_addi_i32(tmp, tmp, imm); - if (rn == 13 && rd == 13) { - /* ADD SP, SP, imm or SUB SP, SP, imm */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } + store_reg(s, rd, tmp); } } } @@ -10817,60 +10818,51 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } memidx = get_mem_index(s); - if (rn == 15) { - addr = tcg_temp_new_i32(); - /* PC relative. */ - imm = s->pc_read & 0xfffffffc; - if (insn & (1 << 23)) - imm += insn & 0xfff; - else - imm -= insn & 0xfff; - tcg_gen_movi_i32(addr, imm); + imm = insn & 0xfff; + if (insn & (1 << 23)) { + /* PC relative or Positive offset. */ + addr = add_reg_for_lit(s, rn, imm); + } else if (rn == 15) { + /* PC relative with negative offset. */ + addr = add_reg_for_lit(s, rn, -imm); } else { addr = load_reg(s, rn); - if (insn & (1 << 23)) { - /* Positive offset. */ - imm = insn & 0xfff; - tcg_gen_addi_i32(addr, addr, imm); - } else { - imm = insn & 0xff; - switch ((insn >> 8) & 0xf) { - case 0x0: /* Shifted Register. */ - shift = (insn >> 4) & 0xf; - if (shift > 3) { - tcg_temp_free_i32(addr); - goto illegal_op; - } - tmp = load_reg(s, rm); - if (shift) - tcg_gen_shli_i32(tmp, tmp, shift); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - break; - case 0xc: /* Negative offset. */ - tcg_gen_addi_i32(addr, addr, -imm); - break; - case 0xe: /* User privilege. */ - tcg_gen_addi_i32(addr, addr, imm); - memidx = get_a32_user_mem_index(s); - break; - case 0x9: /* Post-decrement. */ - imm = -imm; - /* Fall through. */ - case 0xb: /* Post-increment. */ - postinc = 1; - writeback = 1; - break; - case 0xd: /* Pre-decrement. */ - imm = -imm; - /* Fall through. */ - case 0xf: /* Pre-increment. */ - writeback = 1; - break; - default: + imm = insn & 0xff; + switch ((insn >> 8) & 0xf) { + case 0x0: /* Shifted Register. */ + shift = (insn >> 4) & 0xf; + if (shift > 3) { tcg_temp_free_i32(addr); goto illegal_op; } + tmp = load_reg(s, rm); + tcg_gen_shli_i32(tmp, tmp, shift); + tcg_gen_add_i32(addr, addr, tmp); + tcg_temp_free_i32(tmp); + break; + case 0xc: /* Negative offset. */ + tcg_gen_addi_i32(addr, addr, -imm); + break; + case 0xe: /* User privilege. */ + tcg_gen_addi_i32(addr, addr, imm); + memidx = get_a32_user_mem_index(s); + break; + case 0x9: /* Post-decrement. */ + imm = -imm; + /* Fall through. */ + case 0xb: /* Post-increment. */ + postinc = 1; + writeback = 1; + break; + case 0xd: /* Pre-decrement. */ + imm = -imm; + /* Fall through. */ + case 0xf: /* Pre-increment. */ + writeback = 1; + break; + default: + tcg_temp_free_i32(addr); + goto illegal_op; } } @@ -11066,10 +11058,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) if (insn & (1 << 11)) { rd = (insn >> 8) & 7; /* load pc-relative. Bit 1 of PC is ignored. */ - val = s->pc_read + ((insn & 0xff) * 4); - val &= ~(uint32_t)2; - addr = tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, val); + addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4); tmp = tcg_temp_new_i32(); gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); @@ -11447,16 +11436,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) * - Add PC/SP (immediate) */ rd = (insn >> 8) & 7; - if (insn & (1 << 11)) { - /* SP */ - tmp = load_reg(s, 13); - } else { - /* PC. bit 1 is ignored. */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->pc_read & ~(uint32_t)2); - } val = (insn & 0xff) * 4; - tcg_gen_addi_i32(tmp, tmp, val); + tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val); store_reg(s, rd, tmp); break; From patchwork Fri Jul 26 17:49:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169874 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp355301ilk; Fri, 26 Jul 2019 10:52:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqzF6MBaaIMk21iXEPaJjQBIKjZ10eEYUwJFnPELlIssLzWuSAr8zGr8d/Qm/tsxb8k23qg7 X-Received: by 2002:aed:2241:: with SMTP id o1mr68013588qtc.233.1564163575110; Fri, 26 Jul 2019 10:52:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163575; cv=none; d=google.com; s=arc-20160816; b=RSHyIMyPbvSZPHdWcnbF9scUmDYFK1QVRORHG2ZI3eyQ/IvaMOKvqE1OHlXV0opS6L t8fwUX+7Xxze1nF4K+j07S+uFfxjfnZZ8Q9DXJTRJjFtLsDuc0RQfK/yoguF6iaUDbY0 ncL4ADRaTt7Ykv6NUu4NivbT0QVCDAVJzTiHK9Tp0NhgtHsm5rAym+KzfhUiDOmQuUxr 5uNz5C+I7oDIogIYIpmAQ6Cjnf5rH7p+q4U0jbKfOOyVFU2fSPQRCGbOb63EqxDWpESi z4lIYXpAEI1lXvqAur8gtvieqoemEhv+lXM3ZeljOT8FboFQwm748dvY4mgE7ieqHwLH lpUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aps50xe7CceEtOuNm5w6u+s65ojahSCeZEPTzeYb2Dc=; b=C/D6ZfzqTIVBv4P2DjQoNw+UNifUn/4HtF4IHViqoEp2roAWFckBQVDfoRumpyADTa hhwRxKN9QgCQy/Tv2lESIr4Mdkq8ML9WptP8rCXEJXXjL387LHXrI2YYHll4jFbzxJk0 MGkX6+pFGwkzcqvd1PJXzp4+nV7jSsAFZZEZxfhwOhG5rvH5VKGC1W11DOwZm2U9Tg2j zoUddE1J+oONt6zoysZLIPuDDcWPwZljNapGEV9AgMtc0eKG5CXlazqSf7kQBMX6CPC9 TviipF+m/jBhD6ynb1QJabGqkUPbXU61vDDt/JK2i2BTy2KjtTi98VI+g5cyjEIeTM03 kCrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OUdEzYa8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n18si31534380qkk.191.2019.07.26.10.52.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:52:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OUdEzYa8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Oj-0002FZ-61 for patch@linaro.org; Fri, 26 Jul 2019 13:52:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57299) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mj-00029E-8e for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mh-0007ab-5f for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:48 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:44162) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mg-0007Tc-Vz for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:47 -0400 Received: by mail-pf1-x444.google.com with SMTP id t16so24825652pfe.11 for ; Fri, 26 Jul 2019 10:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aps50xe7CceEtOuNm5w6u+s65ojahSCeZEPTzeYb2Dc=; b=OUdEzYa8SNfl74dE7aT6MwUI/pOTiIrNiw17RqWvxMcwtWmNvLDxWFx+wt16lCxiYs eNE78fLQL1V/WgNjmGRWl0Yp8dfq36CS61hQRz6hSf/LOCki2+ptyYwwGifOoK2k0H8K ErHfEigw0OEW+/7MQ/xwXez7wLEOyZmt5KGCzVnhhU/oDJsEwaUfq9rumsHSZW+sDGRA vGQGGJF4hiGk78/M1Z8FE6Tuu2o+JJa59UibkAo0O1le2UrbjndcO4i+DmMBvsjHNcwN d9wmRS6fvhQGFwcO6AAWQk6xv/ZF+OM1Am788PuAyk4KGdxFb9aDxgwUNtfy3BK0jSEP ZZCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aps50xe7CceEtOuNm5w6u+s65ojahSCeZEPTzeYb2Dc=; b=VC4+B6pW2LbDkedPj9cFY7oEjqhn4+xVa9fhQamP7AbTtcrvuVvWiWReQ/b8tuLS3M cUOfpxj/PllkHior2RxhfGPg2twtpGHwNxJIFRWGC8/Rp5dQB1tgoZ/+xeeAsL6NuNVI VVjckHMvygIIM3ED7UudEKSMQnxt83zvh8ptj192nP1BWm67fSWoLOv13m/DQ95+i7NS rMQzt3Fo2tCgdp9H8nG9hq1BlXSoCiHvYPl6yBXSnupXwSX6Ck1gGV7kOOohyK64ivVF 7dyzI2O3cwzgik+UQeDmAG8JM6JhJJ9OXL+DMQOfF4qkPnVH/P6IrgwoIco5ox2ejKBl rIlg== X-Gm-Message-State: APjAAAVJ6KbgKEw1OhdUk2MFKLqucsBrqw1bih6bbAmmFY2IQnmXAkM2 OcmaeNOXfThqsQEMRfUnrgSwavgaJI4= X-Received: by 2002:a62:ae01:: with SMTP id q1mr22905447pff.219.1564163443819; Fri, 26 Jul 2019 10:50:43 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.42 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:33 -0700 Message-Id: <20190726175032.6769-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 08/67] target/arm: Use store_reg_from_load in thumb2 code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There is an extra always-true ARMv5 test, but this will become more obvious once we start unifying the implementation of A32+T32. Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 5e2dd8bb16..e316eeb312 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9773,13 +9773,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Load. */ tmp = tcg_temp_new_i32(); gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == 15) { - gen_bx_excret(s, tmp); - } else if (i == rn) { + if (i == rn) { loaded_var = tmp; loaded_base = 1; } else { - store_reg(s, i, tmp); + store_reg_from_load(s, i, tmp); } } else { /* Store. */ @@ -10914,11 +10912,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(addr); goto illegal_op; } - if (rs == 15) { - gen_bx_excret(s, tmp); - } else { - store_reg(s, rs, tmp); - } + store_reg_from_load(s, rs, tmp); } else { /* Store. */ tmp = load_reg(s, rs); From patchwork Fri Jul 26 17:49:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169882 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp356992ilk; Fri, 26 Jul 2019 10:54:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqyC0fAb/i8FQ4ymUnUvIvTiCE1pCmdJkT/BiTkRt/PBTJk6+pEl8zs7gjebkAxL46+d6keD X-Received: by 2002:a50:9846:: with SMTP id h6mr82138747edb.263.1564163677745; Fri, 26 Jul 2019 10:54:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163677; cv=none; d=google.com; s=arc-20160816; b=B8jdBHMKQjheiGhVvdAJpZULgZtEJHw+rIh5RPRJnDDj214/FAsMUFdQgqPhrPM8W4 jJlPyZdOPXeAbyQ8H21JtljNG8Z0W6ScghMbB213GL9Ss67jVrDQ2WRDH/pVbMi1cX9w QV3Wf0wNmKPYSwf5liWdANy+X2p9WMDFFVhA5XcBtrLBYfdr/f80jos+D8DtHcuvoJfe rbLSH3WL3YyEymCwhzjXMLb0MrM00MRhatblb8J/MHG+hmjNGtABRvFZVdBncnqXO35i UylYqzLj7zsF9bo/pDamWIos15rfZtgGntWrvnT4iPDn1rYAgM2gJi2yLG92UJCMFm3t I8jQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Za01uaUS+E1JffTVMwXCPiCzGTAwavbcztjEMPVjIIo=; b=fKqVx73ZcJm1Ww8VxQDgOWmp5nFNlx23jmbKekqKL3gvCSaNDIHkaySR1crdN7bIEc zHYtG6BB06G0UgqLRxS4TH5Fz9sCnZgI/e+4PxqRGaMDsGlyRfLr/XIl2hx9j07a/jAQ 6HLAgvj+MyHVuBvjvzt5YJ4wwS34EKpsL4toOYqtQTmPqeFkXXZ1/M3swCUUgcUmgH6d AQbCAe9A+ijKLHSY8lHPcOAaO1fCV7xonmYnr8QmXzpTarXzWy1H/ygJBTGgJ4th/ZHS 3YwB/0soDCRbIJmS3gK/FUH8aIrSXit7gs/eMJDB9PQNYR+Qs1X6d0HkT1aITyesOTfS wbHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HTQ12VGS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e27si13082178edd.353.2019.07.26.10.54.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:54:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HTQ12VGS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4QO-00018v-41 for patch@linaro.org; Fri, 26 Jul 2019 13:54:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57491) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mo-0002Yi-3y for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mm-0007p5-Vw for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:53 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:33404) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mm-0007Vn-Qh for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:52 -0400 Received: by mail-pg1-x543.google.com with SMTP id f20so15877252pgj.0 for ; Fri, 26 Jul 2019 10:50:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Za01uaUS+E1JffTVMwXCPiCzGTAwavbcztjEMPVjIIo=; b=HTQ12VGSu11D/hpOGCcoiE8mxbiVZ3ioQ3SLZdSbQEZH39gCfmq0Mh5LPP8IieKPXp 0isbaob2Qo4YwKI6fZVEtrdoD8ztCbcZGEtg8pMg/d4o18VvoF8xfao3HEFjMbdVYf9Q mfy4XWlk/VlSJQbiP1T8QlHLUbK/1k5ORD96UxIbYWkz9qg6PnvZ89eFsHrBSwzSLmFg g3xkzZf86Ctk+l9grsBxtF4joI1GtQ2uqIOUrOVYdrbtgh4Ud1hhsGvZ0ABp3OOCuPuG hazMVjv5wzqDF+g6/aPVeebrWcoJLlw5BdXdigpaO07muKqZG7XRnfc0Pfv9OJwQ8u7k fHBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Za01uaUS+E1JffTVMwXCPiCzGTAwavbcztjEMPVjIIo=; b=T9/Jmf7tc6MOiXe0bjFx+Rt/f8ALuLZjwS1rNNegojUwqj1X2Pjz+RrOBbPosb5Wpp xBSfx50Iy/fIuS3eUsQvf3n6hBtfYTejebmfJ3yPz4dCf/DaUpyYRD0aGP6OMgOkLz9p +Uvt8FYk3oaDDKTBwLZFZKyvjlwUcBgY5sLbzS8YrXJ2COHnnivAIs0USES1ZtnKyUC1 ZAma92Oa9OrRU29aAtKIH8RyNO3WwRnnlLuVMZ0a8OtpvhgRGuQwh3ykiTlL5v+fv5QG Fb6Ya8MHQ9KTnusNrrxkAtnZp9SlGzxYp4dWrgbyAammXc1e5uPAMLot66LNs0Ja7vEF LqEg== X-Gm-Message-State: APjAAAWHBOtBKnPAFixVH0g/hiwn5eevBFvYd/RkoqmeTFlEYCox0r3o eMt12sRv00hau6LSb0Bpw9Sqc+9S4yQ= X-Received: by 2002:a63:b904:: with SMTP id z4mr90747529pge.388.1564163444774; Fri, 26 Jul 2019 10:50:44 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.43 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:34 -0700 Message-Id: <20190726175032.6769-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 09/67] target/arm: Fold a pc load into load_reg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index e316eeb312..53c46fcdc4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9161,11 +9161,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } } else { /* store */ - if (i == 15) { - /* special case: r15 = PC + 8 */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->pc_read); - } else if (user) { + if (user && i != 15) { tmp = tcg_temp_new_i32(); tmp2 = tcg_const_i32(i); gen_helper_get_user_reg(tmp, cpu_env, tmp2); From patchwork Fri Jul 26 17:49:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169877 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp356191ilk; Fri, 26 Jul 2019 10:53:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqwmr9IFiNeRMtrp6jlh7dfYFIe7Jbqc4MQvNWG8pt9/Qk+JL/aWSJAX6osU4mSxuJ7F0Gia X-Received: by 2002:a0c:af8a:: with SMTP id s10mr70460821qvc.182.1564163630653; Fri, 26 Jul 2019 10:53:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163630; cv=none; d=google.com; s=arc-20160816; b=pHhzYv4FD3UBV0j2zTkg5BAQTu93Mo1idcGkPS+Mvzs/MC7WSUfmyks+V3jOGkT7kR G+rwbbsf6c/R9pSVlyo+Me9EVgvnAGmDRPEV1AoX0mdywByaS+8JPbgVrtAwOHr1rz9z yULeBrzmu/cS0L+mq+4mhOpVEDN9x7zEZANZX1MyQcMcNvu0JUEdfv72PvUP1W+FMu+7 i/GamtO1hD5Nfj5kfvZ0z3Ka7QHWmp854h+r3KSQDRSsz/T586NrN1wA3qU5VhVj6gZw 2lTXdgHlLARyvThk3zHkcB2u+r4v4I1l+TII+8Pl2xh2WQuWsQXcHdq89oyOBTvyJ9EK s3Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=6AlrLPoHEa++V99L7+ZXhJHR2MnP9U+NbGuctJWMxJE=; b=j2BBjJOzCVoBbhAfsHBcs1zKwJs9RsQpHvrKI2ZmJZlqOFwmoEN+SxPVTPvdRM3SM9 TihtVhNsMO2kzG1WyOUlIM14crSWLMmA/OASZfm9WbF7AKwYzMOdD+XiGe99KYqXj1e4 WzMK+4hjmR43HorUXDFhoAvTjZoSaLnf4IEu+MrcVaNZCYrtKkp7s3XFTgsQhMKgv9IW YDUYAUocGOELZb8me2Ixe71BkHcXdiWn2lpjcrgERblf6lbKbsZdYD8dPXj0GJa35yLz imTlkzMpfa0peQ4hABxNbem9FLBSgDcY1vhpzhrG8f3yk27GF8XlNMPXeZ/xV+DHnzrr nJhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mqb8bBC+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u184si30741586qka.86.2019.07.26.10.53.50 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:53:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mqb8bBC+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Pd-0006LK-OQ for patch@linaro.org; Fri, 26 Jul 2019 13:53:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57318) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mk-0002Cg-34 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mh-0007cb-KX for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:48 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:39239) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mh-0007Ze-Dl for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:47 -0400 Received: by mail-pf1-x442.google.com with SMTP id f17so20863474pfn.6 for ; Fri, 26 Jul 2019 10:50:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6AlrLPoHEa++V99L7+ZXhJHR2MnP9U+NbGuctJWMxJE=; b=mqb8bBC+RsDkqdEMK9OWURwjjLzi83s/2TP/cn0X/bcMBMFQt9jPUJkzStfa+59HBK VPfzXXkPsdu6+vc1IGIME0HhVU4rjindrTnDcc2gsfOmvMEuxo/Wby2TgPPhaj74alAh 3Rrn9UUznq3sT9Qb/hxM61DUtZgUPB8OYHG/B2WRCnebxf7M5KL4W6NMfCHg49MzTWiQ 8J9jGvodc2fCCXPPFtZ5i6l3aYJMIESIxRBPzVrd+RMBx5JgcOOOhdL6a8h4FoVj98Uo A1pPHfz96ZQCZmXlpsD2V/JWP+5Zh45+415MhmiXeNhmOROQpD04BLmMV+u5K3AaquZB 88wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6AlrLPoHEa++V99L7+ZXhJHR2MnP9U+NbGuctJWMxJE=; b=f6BVbJAo+INOLeqfD+WPkagReXhn+e5Me4OHPt0K8SymZL3l/mZz+z6i2n7lb5z4KM zc70RP9UqBXhBj1e5+ern0y5W2CMuIdZlv43UiWI1flh1iLshUWO+t1e5Uj1Nult464C N4IT5kv3xlQvHxILWC6p1QbmJfCpPl+PDmOKxPMgegNttM8u/BV5gUvDE4RbxBceaxNV tz/+xHZ7KINky6OLwQesAydZdRMr3mwnBzR9lMCL0ihbbYJzNH7reUxCNGvQc4Ue8b4U Q2/FYwBmz/Wi8swsiqO9kKHCit7Pz+dFhgqR0S5XaZEo9DF6y1M9T1fcLyVLGRi3yJFw QW+Q== X-Gm-Message-State: APjAAAVGxMMOB4dBCjLwiS4SbXDz/f5U/6V7aLLdgeJPhooy3kH0URUl idAiYoBgeh8r7qeZdCUyY3BopTIdBEg= X-Received: by 2002:a63:ec48:: with SMTP id r8mr16802349pgj.387.1564163446138; Fri, 26 Jul 2019 10:50:46 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.45 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:35 -0700 Message-Id: <20190726175032.6769-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will shortly be calling this function much more often. Signed-off-by: Richard Henderson --- target/arm/translate.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 53c46fcdc4..36419025db 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7705,8 +7705,14 @@ static void arm_gen_condlabel(DisasContext *s) /* Skip this instruction if the ARM condition is false */ static void arm_skip_unless(DisasContext *s, uint32_t cond) { - arm_gen_condlabel(s); - arm_gen_test_cc(cond ^ 1, s->condlabel); + /* + * Conditionally skip the insn. Note that both 0xe and 0xf mean + * "always"; 0xf is not "never". + */ + if (cond < 0xe) { + arm_gen_condlabel(s); + arm_gen_test_cc(cond ^ 1, s->condlabel); + } } static void disas_arm_insn(DisasContext *s, unsigned int insn) @@ -7944,11 +7950,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } goto illegal_op; } - if (cond != 0xe) { - /* if not always execute, we generate a conditional jump to - next instruction */ - arm_skip_unless(s, cond); - } + + arm_skip_unless(s, cond); + if ((insn & 0x0f900000) == 0x03000000) { if ((insn & (1 << 21)) == 0) { ARCH(6T2); @@ -12095,15 +12099,7 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) dc->insn = insn; if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) { - uint32_t cond = dc->condexec_cond; - - /* - * Conditionally skip the insn. Note that both 0xe and 0xf mean - * "always"; 0xf is not "never". - */ - if (cond < 0x0e) { - arm_skip_unless(dc, cond); - } + arm_skip_unless(dc, dc->condexec_cond); } if (is_16bit) { From patchwork Fri Jul 26 17:49:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169924 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp368600ilk; Fri, 26 Jul 2019 11:05:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqzdKCGZPIgEGeDLnt3n6PBJ71kp+y+7uPkqCWOe7aG7Tiz7omnPufDPIc1uBvdV2DvntIGN X-Received: by 2002:a17:906:5ad0:: with SMTP id x16mr75395629ejs.23.1564164302473; Fri, 26 Jul 2019 11:05:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164302; cv=none; d=google.com; s=arc-20160816; b=uI/cjSy5Yg54Hbkop7aJ8nvN3kZS67sgHL9k8ArJsm/KJPcwTj/xeelnDmtIvwzZb7 fb/1P1aLpIf3MMU39UFQvatmFUMkksenPTp32veKmKBtdojxk/J0iXyohcZkbMP+dsiw yjeaR5aOH0irkUz82sePtLBHfhZOJOcso34G+4CR7mLLG6lKenn0Uy/SMX2CnJ82zQlE 6rgbxUAbkcbb+wEO8ylF7gh9sMrIKjVRX5L+s/4UYr+Dk9ay2CGmaIFKJRUGO28ZA97X soQ8nUJKxV3ydFzK4eeSjTH1pbbP2Rwe2I11jgdftgpEYlTem8fqe0pdXaWQ0Qw+i+G5 xL1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=sBwbqU4X+hNE91dFDdhNVeb0wgaIhMrDk27NuEJee50=; b=Sl6EHi6hw43fgNea9la7XUTdMJk/dsSBVwkHlqlG6acnWSBZrYqT4emeZ8v3Gw8okW 79JhSKO1aGItrqHQqRQPbu7z06fO+An+2p1nLPe7MsMGs0EwLANbdeljZDI6NWx2i888 vGOg6csqfhBeLiUNrfTXq+xuXaEP4mGo37wAOTxSPa4HBd0ka260/Uj2aJtNon7v4KUf AukZshWF+v4uouULdU1KtygPMSq87HZD0ZRrqoBSTOZpON1A8IFpq5T2htESeb8hYhoN 71Ka7Bld111qc+/DnJhsnOsRnV2F0tIEjtfQW4ia0BKtjuvjCadb9a8cPs6rdX7O98Ns bo7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KKS7nzsL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j47si12487672ede.381.2019.07.26.11.05.02 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:05:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KKS7nzsL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4aS-0007vU-PB for patch@linaro.org; Fri, 26 Jul 2019 14:05:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59465) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nr-0007DG-Ib for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nn-0001Dz-KX for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:57 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:47016) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mk-0007dp-IT for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:53 -0400 Received: by mail-pf1-x442.google.com with SMTP id c3so1719837pfa.13 for ; Fri, 26 Jul 2019 10:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sBwbqU4X+hNE91dFDdhNVeb0wgaIhMrDk27NuEJee50=; b=KKS7nzsLDVSNc1VvbWRcglwTfyMTZEEnYUte/KDEWGqNeypXRZCXi1Dtie8xRm3mZF qh/mWdgvddeWWyGwhkf3086WYUK0u23Tb5sb3tyAxdZLnUB310agADpJVgVq/Fgsiflp niYozs+Qo6EGdY4n9T3uk82z2B2K01L3LjGYUqwVt+CCk0tgYJ+Kp9lFGnVh1vO/g920 JYKsXJ0KbM6lDHmR1zICJrVUejvqArz/dEDBp8HLokInn3uxP0BspjK8pPkirhkXy7fu Vnz467al7dYqUppYkJGdH1ofy2YeDDIX764PRJA7X8mm/uhXbFcTTQZzq/y3hvcz4KFc WMnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sBwbqU4X+hNE91dFDdhNVeb0wgaIhMrDk27NuEJee50=; b=dqJBqXjhmU53GuhFtdWP8Ljor5Yps5h0B02GOPEd4GnXRKQu/olL4Z7PpLBAvnhbcF jZupEJqkMY3qy7UbjUuifjHXvBKRja8FAko+IGKswQjt/QwBv2LjY5/8NPrgmU8/K/C0 6Pr3yba5CTEHKyOPqS+btlFpSC3+3NjxQj7Y33aab7gQXzvNNeV6SG5d0aXEQ88gxJ0o +blZ8tZyVLKyQJmLzj+m84dSxWmfDfy50LUj5j9qWsQdmuIexQd28lQ1Hwr1cjfui2L1 HR5AEbPA4O94e4j9JCh7r/ZZgdBJZgrUHLbwIEunqVGP+UgFu+d/ZebMJYJ839vTJP78 OaSw== X-Gm-Message-State: APjAAAV/lsQQn0cloKZrC0CGL5deaq/XZvDS3VO0XAO6roBR116MtVHL j+U2N4dbhJFDzNXNaZYlqY4nsbEgLlQ= X-Received: by 2002:a17:90a:c68c:: with SMTP id n12mr99655403pjt.33.1564163447257; Fri, 26 Jul 2019 10:50:47 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.46 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:36 -0700 Message-Id: <20190726175032.6769-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add the infrastructure that will become the new decoder. No instructions adjusted so far. Signed-off-by: Richard Henderson --- target/arm/translate.c | 45 +++++++++++++++++++++++++++++++++++- target/arm/Makefile.objs | 18 +++++++++++++++ target/arm/a32-uncond.decode | 23 ++++++++++++++++++ target/arm/a32.decode | 23 ++++++++++++++++++ target/arm/t32.decode | 20 ++++++++++++++++ 5 files changed, 128 insertions(+), 1 deletion(-) create mode 100644 target/arm/a32-uncond.decode create mode 100644 target/arm/a32.decode create mode 100644 target/arm/t32.decode -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 36419025db..4738b91957 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7715,6 +7715,33 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) } } +/* + * Include the generated decoders. + * Note that the T32 decoder reuses some of the trans_* functions + * initially declared by the A32 decoder, which results in duplicate + * declaration warnings. Suppress them. + */ + +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE +# pragma GCC diagnostic push +# pragma GCC diagnostic ignored "-Wredundant-decls" +# ifdef __clang__ +# pragma GCC diagnostic ignored "-Wtypedef-redefinition" +# endif +#endif + +#include "decode-a32.inc.c" +#include "decode-a32-uncond.inc.c" +#include "decode-t32.inc.c" + +#ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE +# pragma GCC diagnostic pop +#endif + +/* + * Legacy decoder. + */ + static void disas_arm_insn(DisasContext *s, unsigned int insn) { unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; @@ -7733,7 +7760,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) return; } cond = insn >> 28; - if (cond == 0xf){ + + if (cond == 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we * choose to UNDEF. In ARMv5 and above the space is used * for miscellaneous unconditional instructions. @@ -7741,6 +7769,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) ARCH(5); /* Unconditional instructions. */ + if (disas_a32_uncond(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if (((insn >> 25) & 7) == 1) { /* NEON Data processing. */ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { @@ -7953,6 +7986,11 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) arm_skip_unless(s, cond); + if (disas_a32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + if ((insn & 0x0f900000) == 0x03000000) { if ((insn & (1 << 21)) == 0) { ARCH(6T2); @@ -9440,6 +9478,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) ARCH(6T2); } + if (disas_t32(s, insn)) { + return; + } + /* fall back to legacy decoder */ + rn = (insn >> 16) & 0xf; rs = (insn >> 12) & 0xf; rd = (insn >> 8) & 0xf; diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 5cafc1eb6c..7806b4dac0 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -28,9 +28,27 @@ target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(D $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\ "GEN", $(TARGET_DIR)$@) +target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c +target/arm/translate.o: target/arm/decode-a32.inc.c +target/arm/translate.o: target/arm/decode-a32-uncond.inc.c +target/arm/translate.o: target/arm/decode-t32.inc.c obj-y += tlb_helper.o debug_helper.o obj-y += translate.o op_helper.o diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode new file mode 100644 index 0000000000..8dee26d3b6 --- /dev/null +++ b/target/arm/a32-uncond.decode @@ -0,0 +1,23 @@ +# A32 unconditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All insns that have 0xf in insn[31:28] are decoded here. +# All of those that have a COND field in insn[31:28] are in a32.decode +# diff --git a/target/arm/a32.decode b/target/arm/a32.decode new file mode 100644 index 0000000000..2d84a02861 --- /dev/null +++ b/target/arm/a32.decode @@ -0,0 +1,23 @@ +# A32 conditional instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# +# All of the insn that have a COND field in insn[31:28] are here. +# All insns that have 0xf in insn[31:28] are in a32u.decode. +# diff --git a/target/arm/t32.decode b/target/arm/t32.decode new file mode 100644 index 0000000000..ac01fb6958 --- /dev/null +++ b/target/arm/t32.decode @@ -0,0 +1,20 @@ +# Thumb2 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# From patchwork Fri Jul 26 17:49:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169873 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp355206ilk; Fri, 26 Jul 2019 10:52:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqwnjLKwe+4BH6GI0F5oRpKWhLp48KqXi2iTrjCZYiaWQMcfTraWMR3g6JAq99N6Fh0ws116 X-Received: by 2002:a05:620a:1443:: with SMTP id i3mr65863511qkl.11.1564163569090; Fri, 26 Jul 2019 10:52:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163569; cv=none; d=google.com; s=arc-20160816; b=t5bLwTG6eAqsmv6/iZXnHjMPn8zrnzDccGiZoXcPaH7AnOcNWS4HQSr+GPcqQ/FRpd wRnGl7+qC7PneyOAr45fZRjGAVdyOt7iUvVzvNLXT7EOSBNL2Zn0PI16HNOZuorIFYl0 1EgSOtsXaAMUpoI93kPhpFaaHoVcP8cdpKHpqxvjXV0ICStWW+tzM1jdK5Y30wVM2vlg gQXWK51ukN8oDcDI8K5eGb/rhJK1VDuo3XWwVhIxjadqhDI1Mc/0ElauRPhDmPRIgiar CeOuV30zLYxeQBM3syztK/00U/A3t/QzHFn6T90YSyUCmbXlJrBkciEnqU2GKD8Pr920 HmjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=nQkh2An2kFZsAIQLEJuPgVfqt44IAx9vqtUtFyE7/Qo=; b=FCOTYWnJgop1ay1lgjLS1gOd/k+o7FuSUHLnjm1bDuAAYRFoTYJpDfFKDmccVhQcZO QCnlWEbIKOmRAuL0VZYpt/acHIA7lKHY0Hyt+Y9+yCQV/1uKSJ8M5TnW16Fh1xbjPUix HG2CJrhux8QI3HnaB66Ljt71cRZUDkPMHIzA/2MXsA62TV60lm1L55gfAvmEofVNSTzs TfdqLMAFvi7OJidXNK9BE/IoLEfUDPysuroUk+yGyVla3VY56NjNiuEIZtfv3ZZsf8io KwOIh+zNpA3rs7PV5NEandsGh/ubY9q50IQC+HsVZnZQFQZNgJuan6+wMk6c57t45Toe eDmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nHLntBke; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m51si37173506qvc.179.2019.07.26.10.52.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:52:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nHLntBke; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Oa-0001a9-Q6 for patch@linaro.org; Fri, 26 Jul 2019 13:52:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57433) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mm-0002Pc-Uc for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mj-0007hy-Q4 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:51 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:42185) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mj-0007g1-JA for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:49 -0400 Received: by mail-pg1-x542.google.com with SMTP id t132so25100896pgb.9 for ; Fri, 26 Jul 2019 10:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nQkh2An2kFZsAIQLEJuPgVfqt44IAx9vqtUtFyE7/Qo=; b=nHLntBkexNHKSWsXkmEB+IE2sg7znr577TTLhAa2uCifkD4yBhqMItocTfOLYc7eSg bNBDzDu0VhHCU3UnX0pVqWALgpBK/Cp1BTz9mEcn1RATqWNF2NlGAIT3KGGJ98y8HMlF ULMa8sV3oOzMrPKknF6yU9SLmx+aXECNG0s1leBp+3kpURqs+j+wBnwpOt1DbZ4Oz9go os4g/MTQXVloASFGIfbPuRtOgy2ufcTo5ZMA450lETtXaaH1JMhJd/H24AWfpLLIOxxf Lho9Hwd3SpN/FOQx6Zm6FJ6yZ/vOVJ/Qbz8JdTfYxZhyc4TDpzDlHza+9/JO7lZP6JVq BZZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nQkh2An2kFZsAIQLEJuPgVfqt44IAx9vqtUtFyE7/Qo=; b=GozWpePHFKZMKwTbHttFYAlqhwWnVuw49xBqo3xp/osXLLdxfp3TDw4MUgE5Onv+mp 5WLaBeaoivGw8dLfG24tIdJfe0xKtoWJPFQt7I3k82BCPfo6Qs0C/lYN1OUMV8k0UZ2T eIVwK2e3OMEsqIpxZ4FHFm/7JTrt9D01PviZXZr3Ed/xJxGUVguEAEjU3SmsFDa+HpMK vzGEVYvqo5bYPvQYRncAF1aDyHfbLb5oWrlMggJuHEW65IBznkgWyUOamJZtSlbxUwem t6IbC29bklRyESO2KFVJrLtslNxvPzWmv+1MWKI2VWjOpPT+D+Q3pAWj0rqJNGQaivOM EW5g== X-Gm-Message-State: APjAAAWPffWTMMLgg5wUl46h4PYfEi9MAQmm4fO0pn7kl3Rga5461Ta/ V7Km9dhGGizEkezhOXGAauACwnEKdKo= X-Received: by 2002:a17:90a:b903:: with SMTP id p3mr97691321pjr.79.1564163448309; Fri, 26 Jul 2019 10:50:48 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.47 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:37 -0700 Message-Id: <20190726175032.6769-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 12/67] target/arm: Introduce gen_illegal_op X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Unify the code sequence for generating an illegal opcode exception. Signed-off-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 3 +-- target/arm/translate.c | 21 +++++++++++---------- 2 files changed, 12 insertions(+), 12 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 4066b2febf..1b08930649 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -108,8 +108,7 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) if (!s->vfp_enabled && !ignore_vfp_enabled) { assert(!arm_dc_feature(s, ARM_FEATURE_M)); - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + gen_illegal_op(s); return false; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 4738b91957..0f21ee9ce7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1279,6 +1279,12 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) s->base.is_jmp = DISAS_NORETURN; } +static void gen_illegal_op(DisasContext *s) +{ + gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), + default_exception_el(s)); +} + /* Force a TB lookup after an instruction that changes the CPU state. */ static inline void gen_lookup_tb(DisasContext *s) { @@ -1309,8 +1315,7 @@ static inline void gen_hlt(DisasContext *s, int imm) return; } - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + gen_illegal_op(s); } static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, @@ -7631,8 +7636,7 @@ static void gen_srs(DisasContext *s, } if (undef) { - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + gen_illegal_op(s); return; } @@ -9299,8 +9303,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; default: illegal_op: - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + gen_illegal_op(s); break; } } @@ -10990,8 +10993,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } return; illegal_op: - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + gen_illegal_op(s); } static void disas_thumb_insn(DisasContext *s, uint32_t insn) @@ -11816,8 +11818,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) return; illegal_op: undef: - gen_exception_insn(s, EXCP_UDEF, syn_uncategorized(), - default_exception_el(s)); + gen_illegal_op(s); } static bool insn_crosses_page(CPUARMState *env, DisasContext *s) From patchwork Fri Jul 26 17:49:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169880 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp356905ilk; Fri, 26 Jul 2019 10:54:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqwDzmrQ29zsm+oi+7/LO65JTemJOazRTPD0R0Uz0GdApt7+rIYAfM+WPV7KIzjdmSPY44CD X-Received: by 2002:a50:a4ef:: with SMTP id x44mr85252315edb.304.1564163672124; Fri, 26 Jul 2019 10:54:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163672; cv=none; d=google.com; s=arc-20160816; b=vQH3/T8hvNsjzWQ/JRv3a1WdPpn4K4g5/qUVFgVBlHB1P24y8aDP2r1luzuK76eH/W TLRJ2OAo+lx4w7g1pyfr9+qcBYNMZuxbF7stS/HRmbGdFTkZYmbNuiIL6rc5lEv9sKNz A8TFy7XyFMm82IlX0Q7lyWB3F4y5UA+IMfkSXfXNzzuy2+XDhs93+B0UHsIj33Xps1Xv SQEbK7Zc6Lq28zBa8cdfrpdgBHo0WCkWslG/NTt6/PTCSsSbHCEmTaaT8L2WfV1eInUn z+P46USkS43Q4Rq/mpiKgrYMTPDCql1NCWTWfWSCpoYL9NHgch6FRt2uMikAzgPTmujD kQ2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=H+C2V+j8/JNNNhWaoLPsj+V4nwfuzqa8kDIsrAt6EtU=; b=q749eSdbxTdgbTpjYfN9YorT2e8oVlgvPye06KDwlxVjIUNp32ZG9JitQApizeYwxW lXSoGdHmpw2sCxHlT26FtPKaq7AX7WYivKRub5EbryRDw9Q18TIuDb8Cs4c0l6hvOMbr baBvV2SX2YXmoC/eiJyx6V5pBhICJNLtQBAbySpmcVdGWnlkgfaMzmG7dF7RAhKypUDx 5OKIr8J4pJuVz3p4TQl7CVU222Brhg9Y5IaTZSpRqMEL8n75lfvnDwMu1d0LwJ5/Bzqf 0MDIojhpdFo5XCLhYOcpxOlQ3E8R5xzPrMik8sP5AdKghF5QI3d7Pr+tqoYGc1DqSCfH eKhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=K2LVzuza; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e54si11964591eda.324.2019.07.26.10.54.31 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:54:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=K2LVzuza; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4QE-0000Pb-L4 for patch@linaro.org; Fri, 26 Jul 2019 13:54:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57533) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mo-0002cK-Vd for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Ml-0007lj-H2 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:54 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:37653) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Ml-0007k3-5Q for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:51 -0400 Received: by mail-pf1-x441.google.com with SMTP id 19so24852872pfa.4 for ; Fri, 26 Jul 2019 10:50:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=H+C2V+j8/JNNNhWaoLPsj+V4nwfuzqa8kDIsrAt6EtU=; b=K2LVzuzaCiJT74unyEQFC8duZqRYfuKK2aORw7+RItencmqNK7/7yFtxyXfn4oOhnl 5xmts6lCJRWAsJbTfRBOWHdkvCOKNu4sG7bGHVKxqQBu1521wDRfOwPzbuAlXxGmFQ9k QqD/q9hw17Kgi9yZh2rpoPImAP5jrgevhN6yTay56xkj7uOxw8YKSaOLChO1cxdQkOBh dy7DO4dwDl4wwro3XRi4x1KGWA9w9RwPKVFojeDYSaVGW10CVtBComkJQqRzdXTUvxrj YdZjdOLNAMwWsjkItcHVTDUPAB2/i1Ot2borV5X1I87AqgG0tMJlbxOx2rzeRrBuOauK Iq9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=H+C2V+j8/JNNNhWaoLPsj+V4nwfuzqa8kDIsrAt6EtU=; b=UXq4b/7OBULqGiqMsE8NRBzpxxek5gGzSOTXtRLNnyYmZ7A16EtYj6PF2qJmSlzM8S 2aEIeGEk6RS+8vXMKuEStgd/Tvs9xwW2camjBckayBdoswWMsUcxOIDhuKJm5m+SqGjo o8EekQ31IhbShKiWZp0ts0NyAxPffkrFffb0O8y+2aQLhGCWjjSH2T4tScJhMZe4ACiU T1umbhOIwGAEHCcce+Exmmgg4ZOTpS2WqmdZuanMvGpi0hrVD2+gmMF0DuSd7HSzQsUB Cdxgupy6LBo3EcIDf5DUQngOQO5iNFriLiQhtsA9EBCXzk8Gn1BTeZVLogFZP3RTfBsr VDlw== X-Gm-Message-State: APjAAAUi0a2eFabFLRZxWcCEGxrF8sqExWrE9tjkkEQKugwHGaKBNSJg 9akCIzfUZq/eJsHaVuVIO6H0aDYpblA= X-Received: by 2002:a17:90a:37e9:: with SMTP id v96mr97152975pjb.10.1564163449467; Fri, 26 Jul 2019 10:50:49 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.48 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:38 -0700 Message-Id: <20190726175032.6769-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Do these all in one lump because these are all logically intertwined. Signed-off-by: Richard Henderson --- target/arm/translate.c | 747 ++++++++++++++++++++--------------------- target/arm/a32.decode | 84 +++++ target/arm/t32.decode | 91 +++++ 3 files changed, 536 insertions(+), 386 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 0f21ee9ce7..ee7d53dfa5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -480,12 +480,6 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_temp_free_i32(t1); } -/* Set CF to the top bit of var. */ -static void gen_set_CF_bit31(TCGv_i32 var) -{ - tcg_gen_shri_i32(cpu_CF, var, 31); -} - /* Set N and Z flags from var. */ static inline void gen_logic_CC(TCGv_i32 var) { @@ -905,25 +899,6 @@ void arm_gen_test_cc(int cc, TCGLabel *label) arm_free_cc(&cmp); } -static const uint8_t table_logic_cc[16] = { - 1, /* and */ - 1, /* xor */ - 0, /* sub */ - 0, /* rsb */ - 0, /* add */ - 0, /* adc */ - 0, /* sbc */ - 0, /* rsc */ - 1, /* andl */ - 1, /* xorl */ - 0, /* cmp */ - 0, /* cmn */ - 1, /* orr */ - 1, /* mov */ - 1, /* bic */ - 1, /* mvn */ -}; - static inline void gen_set_condexec(DisasContext *s) { if (s->condexec_mask) { @@ -7719,6 +7694,49 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) } } +/* + * Constant expanders for the decoders. + */ + +static int times_2(DisasContext *s, int x) +{ + return x * 2; +} + +/* Return only the rotation part of T32ExpandImm. */ +static int t32_expandimm_rot(DisasContext *s, int x) +{ + return x & 0xc00 ? extract32(x, 7, 5) : 0; +} + +/* Return the unrotated immediate from T32ExpandImm. */ +static int t32_expandimm_imm(DisasContext *s, int x) +{ + int imm = extract32(x, 0, 8); + + switch (extract32(x, 8, 4)) { + case 0: /* XY */ + /* Nothing to do. */ + break; + case 1: /* 00XY00XY */ + imm |= imm << 16; + break; + case 2: /* XY00XY00 */ + imm |= imm << 16; + imm <<= 8; + break; + case 3: /* XYXYXYXY */ + imm |= imm << 8; + imm |= imm << 16; + break; + default: + /* Rotated constant. */ + imm |= 0x80; + break; + } + return imm; +} + /* * Include the generated decoders. * Note that the T32 decoder reuses some of the trans_* functions @@ -7742,6 +7760,314 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) # pragma GCC diagnostic pop #endif +/* Helpers to swap operands for reverse-subtract. */ +static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_sub_i32(dst, b, a); +} + +static void gen_rsb_CC(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_CC(dst, b, a); +} + +static void gen_rsc(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sub_carry(dest, b, a); +} + +static void gen_rsc_CC(TCGv_i32 dest, TCGv_i32 a, TCGv_i32 b) +{ + gen_sbc_CC(dest, b, a); +} + +/* + * Helper for the data processing routines. + * After the computation store the results back. + * This may be suppressed altogether (STREG_NONE), require a runtime + * check against the stack limits (STREG_SP_CHECK), or generate an + * exception return. Oh, or store into a register. + */ +typedef enum { + STREG_NORMAL, + STREG_NONE, + STREG_SP_CHECK, + STREG_EXC_RET, +} StoreRegKind; + +static bool store_reg_flags(DisasContext *s, int rd, + TCGv_i32 val, StoreRegKind kind) +{ + switch (kind) { + case STREG_NORMAL: + break; + case STREG_NONE: + tcg_temp_free_i32(val); + return true; + case STREG_SP_CHECK: + if (rd == 13) { + store_sp_checked(s, val); + return true; + } + break; + case STREG_EXC_RET: + gen_exception_return(s, val); + return true; + default: + g_assert_not_reached(); + } + /* ALUWritePC: Interworking only from a32 mode. */ + if (s->thumb) { + store_reg(s, rd, val); + } else { + store_reg_bx(s, rd, val); + } + return true; +} + +/* + * Data Processing (register) + * + * Operate, with set flags, one register source, + * one immediate shifted register source, and a destination. + * Here, we return the result without storing into a destination. + */ +static TCGv_i32 op_s_rrr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc) +{ + TCGv_i32 tmp1, tmp2; + + tmp2 = load_reg(s, a->rm); + gen_arm_shift_im(tmp2, a->shty, a->shim, logic_cc); + tmp1 = load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return tmp1; +} + +static TCGv_i32 op_s_rxr_shi(DisasContext *s, arg_s_rrr_shi *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc) +{ + TCGv_i32 tmp; + + tmp = load_reg(s, a->rm); + gen_arm_shift_im(tmp, a->shty, a->shim, logic_cc); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return tmp; +} + +/* + * Data-processing (register-shifted register) + * + * Operate, with set flags, one register source, + * one register shifted register source, and a destination. + * Here, we return the result without storing into a destination. + */ +static TCGv_i32 op_s_rrr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 = load_reg(s, a->rs); + tmp2 = load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + tmp1 = load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return tmp1; +} + +static TCGv_i32 op_s_rxr_shr(DisasContext *s, arg_s_rrr_shr *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc) +{ + TCGv_i32 tmp1, tmp2; + + tmp1 = load_reg(s, a->rs); + tmp2 = load_reg(s, a->rm); + gen_arm_shift_reg(tmp2, a->shty, tmp1, logic_cc); + + gen(tmp2, tmp2); + if (logic_cc) { + gen_logic_CC(tmp2); + } + return tmp2; +} + +/* + * Data-processing (immediate) + * + * Operate, with set flags, one register source, + * one rotated immediate, and a destination. + * Here, we return the result without storing into a destination. + */ +static TCGv_i32 op_s_rri_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), + int logic_cc) +{ + TCGv_i32 tmp1, tmp2; + uint32_t imm; + + imm = ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp2 = tcg_const_i32(imm); + tmp1 = load_reg(s, a->rn); + + gen(tmp1, tmp1, tmp2); + tcg_temp_free_i32(tmp2); + + if (logic_cc) { + gen_logic_CC(tmp1); + } + return tmp1; +} + +static TCGv_i32 op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a, + void (*gen)(TCGv_i32, TCGv_i32), + int logic_cc) +{ + TCGv_i32 tmp; + uint32_t imm; + + imm = ror32(a->imm, a->rot); + if (logic_cc && a->rot) { + tcg_gen_movi_i32(cpu_CF, imm >> 31); + } + tmp = tcg_const_i32(imm); + + gen(tmp, tmp); + if (logic_cc) { + gen_logic_CC(tmp); + } + return tmp; +} + +#define DO_ANY3(NAME, OPERATION, LOGIC_CC, FLAGS) \ +static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ +{ \ + StoreRegKind flags = FLAGS; \ + TCGv_i32 val = op_s_rrr_shi(s, a, OPERATION, LOGIC_CC); \ + return store_reg_flags(s, a->rd, val, flags); \ +} \ +static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ +{ \ + StoreRegKind flags = FLAGS; \ + TCGv_i32 val = op_s_rrr_shr(s, a, OPERATION, LOGIC_CC); \ + return store_reg_flags(s, a->rd, val, flags); \ +} \ +static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \ +{ \ + StoreRegKind flags = FLAGS; \ + TCGv_i32 val = op_s_rri_rot(s, a, OPERATION, LOGIC_CC); \ + return store_reg_flags(s, a->rd, val, flags); \ +} + +#define DO_ANY2(NAME, OPERATION, LOGIC_CC, FLAGS) \ +static bool trans_##NAME##_rrri(DisasContext *s, arg_s_rrr_shi *a) \ +{ \ + StoreRegKind flags = FLAGS; \ + TCGv_i32 val = op_s_rxr_shi(s, a, OPERATION, LOGIC_CC); \ + return store_reg_flags(s, a->rd, val, flags); \ +} \ +static bool trans_##NAME##_rrrr(DisasContext *s, arg_s_rrr_shr *a) \ +{ \ + StoreRegKind flags = FLAGS; \ + TCGv_i32 val = op_s_rxr_shr(s, a, OPERATION, LOGIC_CC); \ + return store_reg_flags(s, a->rd, val, flags); \ +} \ +static bool trans_##NAME##_rri(DisasContext *s, arg_s_rri_rot *a) \ +{ \ + StoreRegKind flags = FLAGS; \ + TCGv_i32 val = op_s_rxi_rot(s, a, OPERATION, LOGIC_CC); \ + return store_reg_flags(s, a->rd, val, flags); \ +} + +#define DO_LOGIC(NAME, OPERATION, FLAGS) DO_ANY3(NAME, OPERATION, a->s, FLAGS) + +DO_LOGIC(AND, tcg_gen_and_i32, STREG_NORMAL) +DO_LOGIC(EOR, tcg_gen_xor_i32, STREG_NORMAL) +DO_LOGIC(ORR, tcg_gen_or_i32, STREG_NORMAL) +DO_LOGIC(BIC, tcg_gen_andc_i32, STREG_NORMAL) + +DO_ANY2(MOV, tcg_gen_mov_i32, a->s, + ({ + int result = STREG_SP_CHECK; + if (a->s && a->rd == 15) { + if (IS_USER(s)) { + return false; + } + result = STREG_EXC_RET; + } + result; + })) + +DO_ANY2(MVN, tcg_gen_not_i32, a->s, STREG_NORMAL) + +DO_ANY3(RSB, a->s ? gen_rsb_CC : gen_rsb, false, STREG_NORMAL) +DO_ANY3(ADC, a->s ? gen_adc_CC : gen_add_carry, false, STREG_NORMAL) +DO_ANY3(SBC, a->s ? gen_sbc_CC : gen_sub_carry, false, STREG_NORMAL) +DO_ANY3(RSC, a->s ? gen_rsc_CC : gen_rsc, false, STREG_NORMAL) + +DO_ANY3(TST, tcg_gen_and_i32, true, STREG_NONE) +DO_ANY3(TEQ, tcg_gen_xor_i32, true, STREG_NONE) +DO_ANY3(CMN, gen_add_CC, false, STREG_NONE) +DO_ANY3(CMP, gen_sub_CC, false, STREG_NONE) + +DO_ANY3(SUB, a->s ? gen_sub_CC : tcg_gen_sub_i32, false, + ({ + int result = STREG_SP_CHECK; + if (a->s && a->rd == 15) { + if (IS_USER(s)) { + return false; + } + result = STREG_EXC_RET; + } else if (a->rn == 13) { + result = STREG_SP_CHECK; + } + result; + })) + +DO_ANY3(ADD, a->s ? gen_add_CC : tcg_gen_add_i32, false, + a->rn == 13 ? STREG_SP_CHECK : STREG_NORMAL) + +/* + * ORN is only available with T32, and so there is no c_s_rrr_shr decode. + * Using the DO_LOGIC macro would create an unused function. + */ +static bool trans_ORN_rrri(DisasContext *s, arg_s_rrr_shi *a) +{ + TCGv_i32 val = op_s_rrr_shi(s, a, tcg_gen_orc_i32, a->s); + return store_reg_flags(s, a->rd, val, STREG_NORMAL); +} + +static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) +{ + TCGv_i32 val = op_s_rri_rot(s, a, tcg_gen_orc_i32, a->s); + return store_reg_flags(s, a->rd, val, STREG_NORMAL); +} + +#undef DO_ANY +#undef DO_LOGIC + /* * Legacy decoder. */ @@ -8273,184 +8599,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } else if (((insn & 0x0e000000) == 0 && (insn & 0x00000090) != 0x90) || ((insn & 0x0e000000) == (1 << 25))) { - int set_cc, logic_cc, shiftop; - - op1 = (insn >> 21) & 0xf; - set_cc = (insn >> 20) & 1; - logic_cc = table_logic_cc[op1] & set_cc; - - /* data processing instruction */ - if (insn & (1 << 25)) { - /* immediate operand */ - val = insn & 0xff; - shift = ((insn >> 8) & 0xf) * 2; - if (shift) { - val = (val >> shift) | (val << (32 - shift)); - } - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - if (logic_cc && shift) { - gen_set_CF_bit31(tmp2); - } - } else { - /* register */ - rm = (insn) & 0xf; - tmp2 = load_reg(s, rm); - shiftop = (insn >> 5) & 3; - if (!(insn & (1 << 4))) { - shift = (insn >> 7) & 0x1f; - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - } else { - rs = (insn >> 8) & 0xf; - tmp = load_reg(s, rs); - gen_arm_shift_reg(tmp2, shiftop, tmp, logic_cc); - } - } - if (op1 != 0x0f && op1 != 0x0d) { - rn = (insn >> 16) & 0xf; - tmp = load_reg(s, rn); - } else { - tmp = NULL; - } - rd = (insn >> 12) & 0xf; - switch(op1) { - case 0x00: - tcg_gen_and_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x01: - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x02: - if (set_cc && rd == 15) { - /* SUBS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_sub_CC(tmp, tmp, tmp2); - gen_exception_return(s, tmp); - } else { - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } else { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - } - break; - case 0x03: - if (set_cc) { - gen_sub_CC(tmp, tmp2, tmp); - } else { - tcg_gen_sub_i32(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x04: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x05: - if (set_cc) { - gen_adc_CC(tmp, tmp, tmp2); - } else { - gen_add_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x06: - if (set_cc) { - gen_sbc_CC(tmp, tmp, tmp2); - } else { - gen_sub_carry(tmp, tmp, tmp2); - } - store_reg_bx(s, rd, tmp); - break; - case 0x07: - if (set_cc) { - gen_sbc_CC(tmp, tmp2, tmp); - } else { - gen_sub_carry(tmp, tmp2, tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x08: - if (set_cc) { - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x09: - if (set_cc) { - tcg_gen_xor_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - } - tcg_temp_free_i32(tmp); - break; - case 0x0a: - if (set_cc) { - gen_sub_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0b: - if (set_cc) { - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp); - break; - case 0x0c: - tcg_gen_or_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - case 0x0d: - if (logic_cc && rd == 15) { - /* MOVS r15, ... is used for exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - gen_exception_return(s, tmp2); - } else { - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - } - break; - case 0x0e: - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (logic_cc) { - gen_logic_CC(tmp); - } - store_reg_bx(s, rd, tmp); - break; - default: - case 0x0f: - tcg_gen_not_i32(tmp2, tmp2); - if (logic_cc) { - gen_logic_CC(tmp2); - } - store_reg_bx(s, rd, tmp2); - break; - } - if (op1 != 0x0f && op1 != 0x0d) { - tcg_temp_free_i32(tmp2); - } + /* Data-processing (reg, reg-shift-reg, imm). */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { /* other instructions */ op1 = (insn >> 24) & 0xf; @@ -9348,89 +9499,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) return true; } -/* Return true if this is a Thumb-2 logical op. */ -static int -thumb2_logic_op(int op) -{ - return (op < 8); -} - -/* Generate code for a Thumb-2 data processing operation. If CONDS is nonzero - then set condition code flags based on the result of the operation. - If SHIFTER_OUT is nonzero then set the carry flag for logical operations - to the high bit of T1. - Returns zero if the opcode is valid. */ - -static int -gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, - TCGv_i32 t0, TCGv_i32 t1) -{ - int logic_cc; - - logic_cc = 0; - switch (op) { - case 0: /* and */ - tcg_gen_and_i32(t0, t0, t1); - logic_cc = conds; - break; - case 1: /* bic */ - tcg_gen_andc_i32(t0, t0, t1); - logic_cc = conds; - break; - case 2: /* orr */ - tcg_gen_or_i32(t0, t0, t1); - logic_cc = conds; - break; - case 3: /* orn */ - tcg_gen_orc_i32(t0, t0, t1); - logic_cc = conds; - break; - case 4: /* eor */ - tcg_gen_xor_i32(t0, t0, t1); - logic_cc = conds; - break; - case 8: /* add */ - if (conds) - gen_add_CC(t0, t0, t1); - else - tcg_gen_add_i32(t0, t0, t1); - break; - case 10: /* adc */ - if (conds) - gen_adc_CC(t0, t0, t1); - else - gen_adc(t0, t1); - break; - case 11: /* sbc */ - if (conds) { - gen_sbc_CC(t0, t0, t1); - } else { - gen_sub_carry(t0, t0, t1); - } - break; - case 13: /* sub */ - if (conds) - gen_sub_CC(t0, t0, t1); - else - tcg_gen_sub_i32(t0, t0, t1); - break; - case 14: /* rsb */ - if (conds) - gen_sub_CC(t0, t1, t0); - else - tcg_gen_sub_i32(t0, t1, t0); - break; - default: /* 5, 6, 7, 9, 12, 15. */ - return 1; - } - if (logic_cc) { - gen_logic_CC(t0); - if (shifter_out) - gen_set_CF_bit31(t1); - } - return 0; -} - /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { @@ -9442,9 +9510,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) TCGv_i32 addr; TCGv_i64 tmp64; int op; - int shiftop; - int conds; - int logic_cc; /* * ARMv6-M supports a limited subset of Thumb2 instructions. @@ -9881,33 +9946,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); } else { /* Data processing register constant shift. */ - if (rn == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rn); - } - tmp2 = load_reg(s, rm); - - shiftop = (insn >> 4) & 3; - shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - conds = (insn & (1 << 20)) != 0; - logic_cc = (conds && thumb2_logic_op(op)); - gen_arm_shift_im(tmp2, shiftop, shift, logic_cc); - if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - if (rd == 13 && - ((op == 2 && rn == 15) || - (op == 8 && rn == 13) || - (op == 13 && rn == 13))) { - /* MOV SP, ... or ADD SP, SP, ... or SUB SP, SP, ... */ - store_sp_checked(s, tmp); - } else if (rd != 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 13: /* Misc data processing. */ @@ -9915,22 +9955,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (op < 4 && (insn & 0xf000) != 0xf000) goto illegal_op; switch (op) { - case 0: /* Register controlled shift. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if ((insn & 0x70) != 0) - goto illegal_op; - /* - * 0b1111_1010_0xxx_xxxx_1111_xxxx_0000_xxxx: - * - MOV, MOVS (register-shifted register), flagsetting - */ - op = (insn >> 21) & 3; - logic_cc = (insn & (1 << 20)) != 0; - gen_arm_shift_reg(tmp, op, tmp2, logic_cc); - if (logic_cc) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; + case 0: /* Register controlled shift, in decodetree */ + goto illegal_op; case 1: /* Sign/zero extend. */ op = (insn >> 20) & 7; switch (op) { @@ -10753,60 +10779,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } } else { - /* - * 0b1111_0x0x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate) - */ - int shifter_out = 0; - /* modified 12-bit immediate. */ - shift = ((insn & 0x04000000) >> 23) | ((insn & 0x7000) >> 12); - imm = (insn & 0xff); - switch (shift) { - case 0: /* XY */ - /* Nothing to do. */ - break; - case 1: /* 00XY00XY */ - imm |= imm << 16; - break; - case 2: /* XY00XY00 */ - imm |= imm << 16; - imm <<= 8; - break; - case 3: /* XYXYXYXY */ - imm |= imm << 16; - imm |= imm << 8; - break; - default: /* Rotated constant. */ - shift = (shift << 1) | (imm >> 7); - imm |= 0x80; - imm = imm << (32 - shift); - shifter_out = 1; - break; - } - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, imm); - rn = (insn >> 16) & 0xf; - if (rn == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rn); - } - op = (insn >> 21) & 0xf; - if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0, - shifter_out, tmp, tmp2)) - goto illegal_op; - tcg_temp_free_i32(tmp2); - rd = (insn >> 8) & 0xf; - if (rd == 13 && rn == 13 - && (op == 8 || op == 13)) { - /* ADD(S) SP, SP, imm or SUB(S) SP, SP, imm */ - store_sp_checked(s, tmp); - } else if (rd != 15) { - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } + /* Data-processing (modified immediate) */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 2d84a02861..1db621576f 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -21,3 +21,87 @@ # All of the insn that have a COND field in insn[31:28] are here. # All insns that have 0xf in insn[31:28] are in a32u.decode. # + +&s_rrr_shi s rd rn rm shim shty +&s_rrr_shr s rn rd rm rs shty +&s_rri_rot s rn rd imm rot + +# Data-processing (register) + +@s_rrr_shi ---- ... .... s:1 rn:4 rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi +@s_rxr_shi ---- ... .... s:1 .... rd:4 shim:5 shty:2 . rm:4 \ + &s_rrr_shi rn=0 +@S_xrr_shi ---- ... .... . rn:4 .... shim:5 shty:2 . rm:4 \ + &s_rrr_shi s=1 rd=0 + +AND_rrri .... 000 0000 . .... .... ..... .. 0 .... @s_rrr_shi +EOR_rrri .... 000 0001 . .... .... ..... .. 0 .... @s_rrr_shi +SUB_rrri .... 000 0010 . .... .... ..... .. 0 .... @s_rrr_shi +RSB_rrri .... 000 0011 . .... .... ..... .. 0 .... @s_rrr_shi +ADD_rrri .... 000 0100 . .... .... ..... .. 0 .... @s_rrr_shi +ADC_rrri .... 000 0101 . .... .... ..... .. 0 .... @s_rrr_shi +SBC_rrri .... 000 0110 . .... .... ..... .. 0 .... @s_rrr_shi +RSC_rrri .... 000 0111 . .... .... ..... .. 0 .... @s_rrr_shi +TST_rrri .... 000 1000 1 .... 0000 ..... .. 0 .... @S_xrr_shi +TEQ_rrri .... 000 1001 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMP_rrri .... 000 1010 1 .... 0000 ..... .. 0 .... @S_xrr_shi +CMN_rrri .... 000 1011 1 .... 0000 ..... .. 0 .... @S_xrr_shi +ORR_rrri .... 000 1100 . .... .... ..... .. 0 .... @s_rrr_shi +MOV_rrri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi +BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi +MVN_rrri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi + +# Data-processing (register-shifted register) + +@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr +@s_rxr_shr ---- ... .... s:1 .... rd:4 rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rn=0 +@S_xrr_shr ---- ... .... . rn:4 .... rs:4 . shty:2 . rm:4 \ + &s_rrr_shr rd=0 s=1 + +AND_rrrr .... 000 0000 . .... .... .... 0 .. 1 .... @s_rrr_shr +EOR_rrrr .... 000 0001 . .... .... .... 0 .. 1 .... @s_rrr_shr +SUB_rrrr .... 000 0010 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSB_rrrr .... 000 0011 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADD_rrrr .... 000 0100 . .... .... .... 0 .. 1 .... @s_rrr_shr +ADC_rrrr .... 000 0101 . .... .... .... 0 .. 1 .... @s_rrr_shr +SBC_rrrr .... 000 0110 . .... .... .... 0 .. 1 .... @s_rrr_shr +RSC_rrrr .... 000 0111 . .... .... .... 0 .. 1 .... @s_rrr_shr +TST_rrrr .... 000 1000 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +TEQ_rrrr .... 000 1001 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMP_rrrr .... 000 1010 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +CMN_rrrr .... 000 1011 1 .... 0000 .... 0 .. 1 .... @S_xrr_shr +ORR_rrrr .... 000 1100 . .... .... .... 0 .. 1 .... @s_rrr_shr +MOV_rrrr .... 000 1101 . 0000 .... .... 0 .. 1 .... @s_rxr_shr +BIC_rrrr .... 000 1110 . .... .... .... 0 .. 1 .... @s_rrr_shr +MVN_rrrr .... 000 1111 . 0000 .... .... 0 .. 1 .... @s_rxr_shr + +# Data-processing (immediate) + +%a32extrot 8:4 !function=times_2 + +@s_rri_rot ---- ... .... s:1 rn:4 rd:4 .... imm:8 \ + &s_rri_rot rot=%a32extrot +@s_rxi_rot ---- ... .... s:1 .... rd:4 .... imm:8 \ + &s_rri_rot rot=%a32extrot rn=0 +@S_xri_rot ---- ... .... . rn:4 .... .... imm:8 \ + &s_rri_rot rot=%a32extrot rd=0 s=1 + +AND_rri .... 001 0000 . .... .... ............ @s_rri_rot +EOR_rri .... 001 0001 . .... .... ............ @s_rri_rot +SUB_rri .... 001 0010 . .... .... ............ @s_rri_rot +RSB_rri .... 001 0011 . .... .... ............ @s_rri_rot +ADD_rri .... 001 0100 . .... .... ............ @s_rri_rot +ADC_rri .... 001 0101 . .... .... ............ @s_rri_rot +SBC_rri .... 001 0110 . .... .... ............ @s_rri_rot +RSC_rri .... 001 0111 . .... .... ............ @s_rri_rot +TST_rri .... 001 1000 1 .... 0000 ............ @S_xri_rot +TEQ_rri .... 001 1001 1 .... 0000 ............ @S_xri_rot +CMP_rri .... 001 1010 1 .... 0000 ............ @S_xri_rot +CMN_rri .... 001 1011 1 .... 0000 ............ @S_xri_rot +ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot +MOV_rri .... 001 1101 . 0000 .... ............ @s_rxi_rot +BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot +MVN_rri .... 001 1111 . 0000 .... ............ @s_rxi_rot diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ac01fb6958..7bfd8ee854 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -18,3 +18,94 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot + +# Data-processing (register-shifted register) + +MOV_rrrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \ + &s_rrr_shr rn=0 + +# Data-processing (register) + +%imm5_12_6 12:3 6:2 + +@s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=%imm5_12_6 +@s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \ + &s_rrr_shi shim=%imm5_12_6 rn=0 +@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \ + &s_rrr_shi shim=%imm5_12_6 s=1 rd=0 + +{ + TST_rrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi + AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi +} +BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi +{ + MOV_rrri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi + ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + MVN_rrri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi + ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi +} +{ + TEQ_rrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi + EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi +} +# PKHBT, PKHTB at opc1 = 0110 +{ + CMN_rrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi + ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi +} +ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi +SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi +{ + CMP_rrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi + SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi +} +RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi + +# Data-processing (immediate) + +%t32extrot 26:1 12:3 0:8 !function=t32_expandimm_rot +%t32extimm 26:1 12:3 0:8 !function=t32_expandimm_imm + +@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=%t32extimm rot=%t32extrot +@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \ + &s_rri_rot imm=%t32extimm rot=%t32extrot rn=0 +@S_xri_rot ....... .... . rn:4 . ... .... ........ \ + &s_rri_rot imm=%t32extimm rot=%t32extrot s=1 rd=0 + +{ + TST_rri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot + AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot +} +BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot +{ + MOV_rri 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot + ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot +} +{ + MVN_rri 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot + ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot +} +{ + TEQ_rri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot + EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot +} +{ + CMN_rri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot + ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot +} +ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot +SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot +{ + CMP_rri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot + SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot +} +RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot From patchwork Fri Jul 26 17:49:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169870 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp354519ilk; Fri, 26 Jul 2019 10:52:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqw4Hvx7FpkzIo0Woa4k/AWRbEdkZVsRnNUGtQ/Kuv6mUmVfX7mBg/3GdMNaNghGCt1DkZuQ X-Received: by 2002:a17:906:eb93:: with SMTP id mh19mr72695164ejb.42.1564163526093; Fri, 26 Jul 2019 10:52:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163526; cv=none; d=google.com; s=arc-20160816; b=odrMpjeZ1BkZijGDaM0naIEMQCxdX9vBBDbUfu6bv3hzHzyMRHrKZ7N5D/mI02sZB8 MfIheUgLtFwTmSWqjtbZfh61JBxTJpYS2u0yAl/Nj11ZZmZqa93s8d02i9SeL+XcgTh/ TxIFbeebboQqZePezYWHco6m/MC4v5oIrd+8Yp9H9hXMMc2zdf0t3ZsscgIohjSPy2IY m5lhCfqdAEiek1A1mRJZarzgN0XY4Z2dPLhoYPf/L4Ss5m4TGBPDLEZGL5fmgkFjIL1N 8P3VEA5WMkGfYE0fjYyI293n5ocZqpz083rnyPtDSs6vlJmebmAbQArPkfXIsVj83AWK V2qA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=GoQmT1N8IU0T5z5+kFmORBhM2hYdVyMn2yGubYbJrVU=; b=Fnw/5sJBbKKxPEcGCE5UW4qLcrf5ftwD14G1PTnPQBYZblnm3zjVXj/TtZGKxLAIg4 rTkj0htdF43pcbNx1UA47be5Pg9aT17/B3SATWv68EWy/IQvdc0yeVlqkf83WqxfB0gY igthtRQHpyocQxVmHM4p5z4ko8+A4kdSK/LH2km4mE3vbMlobDwr/07h6m7vv9vhzA8R UoI4b+xyn/yMH/y3Tw7dhZ1mMxpxN+LAgSmNbb6rXp4FjwSAkYB6ITc6Ts4UN+Eupk1m n+zfEXtZ9LmZD6GUua/+4gqp6wF9MfiHWwDInRUn577sK6fivWfuoMGTm7w3l91jsVMF g+PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GBfq2eFV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h12si12821050edn.290.2019.07.26.10.52.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:52:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=GBfq2eFV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42216 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nw-0006yN-43 for patch@linaro.org; Fri, 26 Jul 2019 13:52:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57605) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mq-0002lQ-VX for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mo-0007tj-22 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:55 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:42696) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mn-0007kv-Kp for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:53 -0400 Received: by mail-pl1-x629.google.com with SMTP id ay6so25055652plb.9 for ; Fri, 26 Jul 2019 10:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GoQmT1N8IU0T5z5+kFmORBhM2hYdVyMn2yGubYbJrVU=; b=GBfq2eFV1G5lsZB/WX3pGNcloK6upS0papCHl/UXrwsYp5VXqeYW+fLFC8i1eTjELU 78mEuOAAPL62ASIEUm7glkaNSqiIwf3v+hfKZozFCTGrapHYABQoTawYkcyIc2ELBzOK SDon1V+FkCkxbhdQUBR62bfEnK4o47FvBHI/jb5SNAvH9sEwEbh7+tU80Hqx0zoaIqCp zAGCM0GktRXRroLWSimtWX8meuOOc44a1reUuCXyhavWA9FvSyXUXywRTpR9oT8mCQrI pMkFFbdwSZUvOlq9kGujkuPpQPT43/HIdDiqOdWwidXFN7pmCdDdtU6TVjdDnajrMchR lOHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GoQmT1N8IU0T5z5+kFmORBhM2hYdVyMn2yGubYbJrVU=; b=DBbBlXkW+B0ArNuRNY0zoZIfk01izB44b2ngfRu3RaKDbV6t6lPGWwqIrhGTi78qUf /k2TMjnJo4eb6WmcitWm+itKTYYTaUAI8dtfR6UVdgSrYUGfFv2XcHJ4jdN6jbQXXXjW JG4bdEhmmZA9tutwv4EjS/bdoFWdDitvzJWfz3ac/y1Cf2qsJXT7c8Ys0Yu4coiyYEPM izq1LrUu6wudRa2A7NCUMvVsB0C13IdDFitSfIl1whbtMEtoyZYwa1xOPA5bvdbPV5QS lq/i9HyGh3ZpW2MEcnqM6/ze/57uF/pAauOJVSPjNpsb9Hh4aOlHPi34uHKXct18vmVK LYDA== X-Gm-Message-State: APjAAAXqkWhY4BYDcOdzWlJ0nqWb794FMq5W99ptTQ2WxE81GM/n2q0t JPJPEUmsCy4u7/jAD8bFvpgtrFHYT6Q= X-Received: by 2002:a17:902:8ec3:: with SMTP id x3mr95853641plo.313.1564163450345; Fri, 26 Jul 2019 10:50:50 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.49 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:39 -0700 Message-Id: <20190726175032.6769-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::629 Subject: [Qemu-devel] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 214 ++++++++++++++++++++++++----------------- target/arm/a32.decode | 17 ++++ target/arm/t32.decode | 19 ++++ 3 files changed, 163 insertions(+), 87 deletions(-) -- 2.17.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index ee7d53dfa5..354a52d36c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7376,21 +7376,6 @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val) store_reg(s, rhigh, tmp); } -/* load a 32-bit value from a register and perform a 64-bit accumulate. */ -static void gen_addq_lo(DisasContext *s, TCGv_i64 val, int rlow) -{ - TCGv_i64 tmp; - TCGv_i32 tmp2; - - /* Load value and extend to 64 bits. */ - tmp = tcg_temp_new_i64(); - tmp2 = load_reg(s, rlow); - tcg_gen_extu_i32_i64(tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_gen_add_i64(val, val, tmp); - tcg_temp_free_i64(tmp); -} - /* load and add a 64-bit value from a register pair. */ static void gen_addq(DisasContext *s, TCGv_i64 val, int rlow, int rhigh) { @@ -8068,6 +8053,128 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) #undef DO_ANY #undef DO_LOGIC +/* + * Multiply and multiply accumulate + */ + +static bool op_mla(DisasContext *s, arg_s_rrrr *a, bool add) +{ + TCGv_i32 t1, t2; + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + if (add) { + t2 = load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + if (a->s) { + gen_logic_CC(t1); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_MUL(DisasContext *s, arg_MUL *a) +{ + return op_mla(s, a, false); +} + +static bool trans_MLA(DisasContext *s, arg_MLA *a) +{ + return op_mla(s, a, true); +} + +static bool trans_MLS(DisasContext *s, arg_MLS *a) +{ + TCGv_i32 t1, t2; + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + tcg_gen_mul_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + t2 = load_reg(s, a->ra); + tcg_gen_sub_i32(t1, t2, t1); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_mlal(DisasContext *s, arg_s_rrrr *a, bool uns, bool add) +{ + TCGv_i32 t0, t1, t2, t3; + + t0 = load_reg(s, a->rm); + t1 = load_reg(s, a->rn); + if (uns) { + tcg_gen_mulu2_i32(t0, t1, t0, t1); + } else { + tcg_gen_muls2_i32(t0, t1, t0, t1); + } + if (add) { + t2 = load_reg(s, a->ra); + t3 = load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, t3); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + } + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); + if (a->s) { + gen_logicq_cc(t0, t1); + } + return true; +} + +static bool trans_UMULL(DisasContext *s, arg_UMULL *a) +{ + return op_mlal(s, a, true, false); +} + +static bool trans_SMULL(DisasContext *s, arg_SMULL *a) +{ + return op_mlal(s, a, false, false); +} + +static bool trans_UMLAL(DisasContext *s, arg_UMLAL *a) +{ + return op_mlal(s, a, true, true); +} + +static bool trans_SMLAL(DisasContext *s, arg_SMLAL *a) +{ + return op_mlal(s, a, false, true); +} + +static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) +{ + TCGv_i32 t0, t1, t2, zero; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 = load_reg(s, a->rm); + t1 = load_reg(s, a->rn); + tcg_gen_mulu2_i32(t0, t1, t0, t1); + zero = tcg_const_i32(0); + t2 = load_reg(s, a->ra); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + t2 = load_reg(s, a->rd); + tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); + tcg_temp_free_i32(t2); + tcg_temp_free_i32(zero); + store_reg(s, a->ra, t0); + store_reg(s, a->rd, t1); + return true; +} + + /* * Legacy decoder. */ @@ -8612,71 +8719,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) sh = (insn >> 5) & 3; if (sh == 0) { if (op1 == 0x0) { - rd = (insn >> 16) & 0xf; - rn = (insn >> 12) & 0xf; - rs = (insn >> 8) & 0xf; - rm = (insn) & 0xf; - op1 = (insn >> 20) & 0xf; - switch (op1) { - case 0: case 1: case 2: case 3: case 6: - /* 32 bit mul */ - tmp = load_reg(s, rs); - tmp2 = load_reg(s, rm); - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 22)) { - /* Subtract (mls) */ - ARCH(6T2); - tmp2 = load_reg(s, rn); - tcg_gen_sub_i32(tmp, tmp2, tmp); - tcg_temp_free_i32(tmp2); - } else if (insn & (1 << 21)) { - /* Add */ - tmp2 = load_reg(s, rn); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - break; - case 4: - /* 64 bit mul double accumulate (UMAAL) */ - ARCH(6); - tmp = load_reg(s, rs); - tmp2 = load_reg(s, rm); - tmp64 = gen_mulu_i64_i32(tmp, tmp2); - gen_addq_lo(s, tmp64, rn); - gen_addq_lo(s, tmp64, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - break; - case 8: case 9: case 10: case 11: - case 12: case 13: case 14: case 15: - /* 64 bit mul: UMULL, UMLAL, SMULL, SMLAL. */ - tmp = load_reg(s, rs); - tmp2 = load_reg(s, rm); - if (insn & (1 << 22)) { - tcg_gen_muls2_i32(tmp, tmp2, tmp, tmp2); - } else { - tcg_gen_mulu2_i32(tmp, tmp2, tmp, tmp2); - } - if (insn & (1 << 21)) { /* mult accumulate */ - TCGv_i32 al = load_reg(s, rn); - TCGv_i32 ah = load_reg(s, rd); - tcg_gen_add2_i32(tmp, tmp2, tmp, tmp2, al, ah); - tcg_temp_free_i32(al); - tcg_temp_free_i32(ah); - } - if (insn & (1 << 20)) { - gen_logicq_cc(tmp, tmp2); - } - store_reg(s, rn, tmp); - store_reg(s, rd, tmp2); - break; - default: - goto illegal_op; - } + /* Multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { rn = (insn >> 16) & 0xf; rd = (insn >> 12) & 0xf; @@ -10292,13 +10337,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } if (op & 4) { - /* umaal */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i64(tmp64); - goto illegal_op; - } - gen_addq_lo(s, tmp64, rs); - gen_addq_lo(s, tmp64, rd); + /* umaal, in decodetree */ + goto illegal_op; } else if (op & 0x40) { /* 64-bit accumulate. */ gen_addq(s, tmp64, rs, rd); diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 1db621576f..71846b79fd 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -25,6 +25,8 @@ &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot +&s_rrrr s rd rn rm ra +&rrrr rd rn rm ra # Data-processing (register) @@ -105,3 +107,18 @@ ORR_rri .... 001 1100 . .... .... ............ @s_rri_rot MOV_rri .... 001 1101 . 0000 .... ............ @s_rxi_rot BIC_rri .... 001 1110 . .... .... ............ @s_rri_rot MVN_rri .... 001 1111 . 0000 .... ............ @s_rxi_rot + +# Multiply and multiply accumulate + +@s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr +@s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0 +@rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr + +MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn +MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn +UMAAL .... 0000 010 0 .... .... .... 1001 .... @rdamn +MLS .... 0000 011 0 .... .... .... 1001 .... @rdamn +UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn +UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn +SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn +SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7bfd8ee854..8e301ed2a1 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -22,6 +22,8 @@ &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra +&rrrr !extern rd rn rm ra # Data-processing (register-shifted register) @@ -109,3 +111,20 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot + +# Multiply and multiply accumulate + +@s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 +@s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0 +@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr + +{ + MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm + MLA 1111 1011 0000 .... .... .... 0000 .... @s0_rnadm +} +MLS 1111 1011 0000 .... .... .... 0001 .... @rnadm +SMULL 1111 1011 1000 .... .... .... 0000 .... @s0_rnadm +UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm +SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm +UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm +UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm From patchwork Fri Jul 26 17:49:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169890 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp358565ilk; Fri, 26 Jul 2019 10:56:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqxxJpvFJcAsifa7Shx75mmX5uUBmJGAyn0TNHyHf14rMDgPtdmtXkPPiTNVTWZh1PDwT7nt X-Received: by 2002:a17:906:504e:: with SMTP id e14mr74343388ejk.204.1564163780052; Fri, 26 Jul 2019 10:56:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163780; cv=none; d=google.com; s=arc-20160816; b=iK3hrMonBVGUdBaTLytf+n2ay6VWg25Am99SA3Bf7v8HOaLvLQcUUyqLjIqyQnYJhj aE75ARFgAHdgHD1i3uGXRzGp2BT2CbZjwnlfpHgV5KDIr5mnN3FtOqW+03IPTiPpMhPF 0H28o7UMTY7mhCsGOzmT5q7s/WpRZymap2U1aF3sfTSKHk5bTVBaZ6YhxlyNTtMu0y76 DFyR/qdWM1HEf4BkgBdefb8vqJPT8mT06wuAFjK5n+PWuc7W90Sm09D9pJq+McZLtxBg 7Sk/aiuYT0xI9TkLM6b1r5RQ6mS2sK5RxDbq0ZUt9Vf/4FY68+rWGMhZO3MQpWZNxrZB GZyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=oJFhsjTpA90uLnkSb8PliACzOJvjF9fpzncu9tcD1hw=; b=Uv4zaq++XbQ2W4aW6G54GkqI1P8K0uVsoMD5esUdKT4ErwwCytL+srZqpFRbgtGZe9 F4oLXHCbzUXP0DOfrWIq8qKpN6ixtXTdpavGu2hHyftf0XSnFtckGwQZNGv1JFfGwNkm d1vVs2WlWGqpqD+NkemSEFbwE816WqX7dE7cQbxLhNzTmDEC05dk3zErqBoPLmuqSf86 AH9Zzo1WVCVsmvvvXC/FORE9pQfhZsHqEoluec4X63kfOQVsx9Gza+72BGvAqXYa0d2Q M8LsZX3trxg9YqdcPoHFO+FF1EPfv44ohl9aLdSQjiLI3EY1NSJUlt6ZuZHnQRqqrEFk /X6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aWUgNkmd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x1si14049640eda.437.2019.07.26.10.56.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:56:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=aWUgNkmd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4S1-0007hS-Kp for patch@linaro.org; Fri, 26 Jul 2019 13:56:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57582) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mq-0002id-Hs for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mo-0007wV-Ul for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:56 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:46158) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mo-0007nI-Nm for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:54 -0400 Received: by mail-pg1-x52d.google.com with SMTP id k189so6067897pgk.13 for ; Fri, 26 Jul 2019 10:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oJFhsjTpA90uLnkSb8PliACzOJvjF9fpzncu9tcD1hw=; b=aWUgNkmdWXEo6kR8q9PDUyX+wB7jKa/AFdJ6Jys42PvIqwzqopjF/6h/6ieaYqWvPv bmS1gdB5b93+PUfkw0nJgufPFpswf78rQdYN9LIvGkoAdmj+miV5T/IL/RofwvNzG1mq TBUX9h3WqEy6u9bcZZuKKmTj+17EmcuRn9f+3DqOo4ehAxSN03XEF2XU/AtEE8Mai4k+ 7n8TOPiHRtNuEWVnqcumd1oKgu2ISQ0OBpQba//8e3Hu8SuRnum7CLgbqZm2cpvzKuJY BUCu/4Fgdb5zcTH8BfxbXOv8926Gaw6SlnUIJa98zBOu7OTGOOCkvc65+GkvYPrlBAqF OOZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oJFhsjTpA90uLnkSb8PliACzOJvjF9fpzncu9tcD1hw=; b=AvoEht9Vqntz2+A6ZYoZ4+G/Y9dlzeRLKZHSOvTaHTwSvXqXFpatNvRRaHbcr8CyO+ Q0AYEGt7ulesUC1WzrYvZlxxAbTm/lfJV5bKl3BCXi1kebNMw1Ys5WvnWjdSf2wR7Ln3 09ogLQReBNVuVcpKh/cQcKrhX8aY9D2umZ2i2PJALU8D6sByXZUmTGz/+8QFaErw/WxS pU1qZ+EsOfgf7iMmsDBl5wNrA/vN3gdqA8KeXDwENd89NB4nAM9tnfjPY2h6Ao3XUzmK jaRPEnTuTs9DBqwZ+/sTuPt16GJlsBjPZyhrNI53FeNnhcesCfeDCd/hGcaU8DVbtC1x Axrw== X-Gm-Message-State: APjAAAVWgelOjOC7gZerAmE0glVfek1QRAofbGbt8O2rJMPD3HKwj/72 xVxh4H9xPvYFhB8+I0YUcjEFaCNFf28= X-Received: by 2002:a17:90a:2023:: with SMTP id n32mr95173627pjc.3.1564163451357; Fri, 26 Jul 2019 10:50:51 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.50 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:40 -0700 Message-Id: <20190726175032.6769-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52d Subject: [Qemu-devel] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/helper.h | 1 - target/arm/op_helper.c | 15 --------- target/arm/translate.c | 74 +++++++++++++++++++++++++++--------------- target/arm/a32.decode | 10 ++++++ target/arm/t32.decode | 9 +++++ 5 files changed, 66 insertions(+), 43 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.h b/target/arm/helper.h index 132aa1682e..1fb2cb5a77 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -6,7 +6,6 @@ DEF_HELPER_3(add_saturate, i32, env, i32, i32) DEF_HELPER_3(sub_saturate, i32, env, i32, i32) DEF_HELPER_3(add_usaturate, i32, env, i32, i32) DEF_HELPER_3(sub_usaturate, i32, env, i32, i32) -DEF_HELPER_2(double_saturate, i32, env, s32) DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_NO_RWG_SE, s32, s32, s32) DEF_HELPER_FLAGS_2(udiv, TCG_CALL_NO_RWG_SE, i32, i32, i32) DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 1ab91f915e..142239b03a 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -135,21 +135,6 @@ uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b) return res; } -uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val) -{ - uint32_t res; - if (val >= 0x40000000) { - res = ~SIGNBIT; - env->QF = 1; - } else if (val <= (int32_t)0xc0000000) { - res = SIGNBIT; - env->QF = 1; - } else { - res = val << 1; - } - return res; -} - uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b) { uint32_t res = a + b; diff --git a/target/arm/translate.c b/target/arm/translate.c index 354a52d36c..85f829c1bb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8174,6 +8174,47 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL *a) return true; } +/* + * Saturating addition and subtraction + */ + +static bool op_qaddsub(DisasContext *s, arg_rrr *a, bool add, bool doub) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 = load_reg(s, a->rm); + t1 = load_reg(s, a->rn); + if (doub) { + gen_helper_add_saturate(t1, cpu_env, t1, t1); + } + if (add) { + gen_helper_add_saturate(t0, cpu_env, t0, t1); + } else { + gen_helper_sub_saturate(t0, cpu_env, t0, t1); + } + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_QADDSUB(NAME, ADD, DOUB) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_qaddsub(s, a, ADD, DOUB); \ +} + +DO_QADDSUB(QADD, true, false) +DO_QADDSUB(QSUB, false, false) +DO_QADDSUB(QDADD, true, true) +DO_QADDSUB(QDSUB, false, true) + +#undef DO_QADDSUB /* * Legacy decoder. @@ -8582,21 +8623,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) store_reg(s, rd, tmp); break; } - case 0x5: /* saturating add/subtract */ - ARCH(5TE); - rd = (insn >> 12) & 0xf; - rn = (insn >> 16) & 0xf; - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rn); - if (op1 & 2) - gen_helper_double_saturate(tmp2, cpu_env, tmp2); - if (op1 & 1) - gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 0x5: + /* Saturating addition and subtraction. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x6: /* ERET */ if (op1 != 3) { goto illegal_op; @@ -10070,18 +10100,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { /* Saturating add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if (op & 1) - gen_helper_double_saturate(tmp, cpu_env, tmp); - if (op & 2) - gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp); - else - gen_helper_add_saturate(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } else { switch (op) { case 0x0a: /* rbit */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 71846b79fd..af6712a9e8 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -27,6 +27,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr rd rn rm # Data-processing (register) @@ -122,3 +123,12 @@ UMULL .... 0000 100 . .... .... .... 1001 .... @s_rdamn UMLAL .... 0000 101 . .... .... .... 1001 .... @s_rdamn SMULL .... 0000 110 . .... .... .... 1001 .... @s_rdamn SMLAL .... 0000 111 . .... .... .... 1001 .... @s_rdamn + +# Saturating addition and subtraction + +@rndm ---- .... .... rn:4 rd:4 .... .... rm:4 &rrr + +QADD .... 0001 0000 .... .... 0000 0101 .... @rndm +QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm +QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm +QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 8e301ed2a1..7a27b5cc5c 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr !extern rd rn rm # Data-processing (register-shifted register) @@ -117,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -128,3 +130,10 @@ UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm + +# Data-processing (two source registers) + +QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm +QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm +QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm +QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm From patchwork Fri Jul 26 17:49:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169885 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp357755ilk; Fri, 26 Jul 2019 10:55:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqwTCfUY5OZoWP0LqkIoCxBmPG5bnvfpbkmjIoIsmFAubVt2RlwUIQV/uK0l28r1Bc+Ep0j2 X-Received: by 2002:a50:9273:: with SMTP id j48mr84787737eda.285.1564163728695; Fri, 26 Jul 2019 10:55:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163728; cv=none; d=google.com; s=arc-20160816; b=ElQ2Mpl4bIkL1clM1czMvgVlUndH1UMxPKG/stlkr5yMq0nwiIbLcDYZwwAnUQAEf4 oXffApEDY9C4cc//NAAWr+WuxBJsWu8tzx9trrHxMXR4jVz5UcSLu05XZx4Wh4WXgkce Wkq1o9oKIpBh8nNc1sGYUegmPgd0HqWItCchB4S/ml9gBn0BEpwNhTvLWHyghPbzRF6C Jm8+I0ZppyUN6B+5SyAqSw67W2SaqWPMWbzomRS01K9buUskB+ej9z8Q/sjyE0uwAI7O cao2ucTMBDsm+c7g2pAqBNtcTJ6JbmSEvNW1ldxL+vnl1Gssjm3AHErerKoua46YCMOT w1cg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=JPiuu3u1DmYNP4L34gockHhxl16pnGlsBhgu6OkkWuU=; b=abQAzbqJPbXCNn8bxV4BHTKpYaXJy8CC4RVVIpBm11PJOv646crxFkIFxWHOsIqmqO rCyNf1t8n0S17WD8MNgavA4XyVuRgPtEckmlvLeWXJn6dE17i8Dp5v2RsXbNincWuobK vevkF0CaQey4nX2cxZfcLiHd9s9pOMsbm5ZuTA2SmQBbVLvegTxsXTUmBXqkc6/1UyMi OPzgChm9vD8xPYRlD/kaVwpywdlrp4KzSkdf+xxUaDM4ZLVye+Tm03PEaJ/urj+cK+m0 1P7ivcZu+13aVnrsSuufI7I2QyUC3NrJulwgP7Gn7H4K4jP3hVnuhcYgZd4wReDl8CBW LTgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QYbNRNgX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o26si13873188edc.423.2019.07.26.10.55.28 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:55:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QYbNRNgX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4R8-0004AP-Tr for patch@linaro.org; Fri, 26 Jul 2019 13:55:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57571) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mq-0002hF-0C for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mo-0007tZ-1B for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:55 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:44162) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mn-0007q1-Mi for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:53 -0400 Received: by mail-pf1-x442.google.com with SMTP id t16so24825823pfe.11 for ; Fri, 26 Jul 2019 10:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JPiuu3u1DmYNP4L34gockHhxl16pnGlsBhgu6OkkWuU=; b=QYbNRNgXdZGj9qhpjtN4eQN4EHQevH9YvrcnCSLLOZlur9GVFEJt8OVbtSr32Ns9NB TUBn/+s2Sj2YajhssU7McRA6yh/mS8vqYKJiH95hDu9zQQZ5JKQMVfB9h9UyDeT9psaJ h43OpXVGWtHmw8FR2yIHU0zMs9a1VwF4UGhfIHHGyBLAMVuIO720Pq0pxEDllAMdGoGK qWKWyOBmkeS0qeAZrqqabyc91VElQCPWKwO56r5SWDYIIqs/+RzajlDSW1dbtY8WednL 3Fp+3fxV5h3GRQNwzol88WWKlbrJaLAkVO1qKvY1xJFPjrqxATbTieGW31Fcp0lDZF1t fRQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JPiuu3u1DmYNP4L34gockHhxl16pnGlsBhgu6OkkWuU=; b=Ca3XYqFDHzOnPqhrOrXMdd0/TkFycwfqumOgrKIZKaULJNi0cVZ1xZEuPoawMAjoyJ PXtTgd/+9lpnqr6RWuus/zYTSYI+J9uHTHUvXfCEzHHnLuGRq72YTB2P1rzrvzgxo99Y xwgd6ZIAZ/JqjKX/oIivpTEb8OpZHHWg0pPomOEmihm7zPzTWZrZHAcYpVSaN6EOoWcX S1rTMIs2P1pb1x+gw58OF/XIlG82d2EbL+v+XnrBeFkcjgBgFgxtPbDwZYil+PNVxkvD p3RoSh9NLNMzKEWzofAHpCSig/NWNrLisAulhQ5ZBJ6Fa13rkJ75L8aIlPBfZqJTUlYA TviA== X-Gm-Message-State: APjAAAUepuv25yPUTrtAc7gXcOnhWV4YAM6ss4RKruVX4a5T7X/7tHek 9hArFIGcN6pBao4hmNwbKdbsBIc9EqQ= X-Received: by 2002:a62:1456:: with SMTP id 83mr23588261pfu.228.1564163452439; Fri, 26 Jul 2019 10:50:52 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.51 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:41 -0700 Message-Id: <20190726175032.6769-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 216 ++++++++++++++++++++++------------------- target/arm/a32.decode | 20 ++++ target/arm/t32.decode | 29 ++++++ 3 files changed, 167 insertions(+), 98 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 85f829c1bb..2140671eb2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8216,6 +8216,114 @@ DO_QADDSUB(QDSUB, false, true) #undef DO_QADDSUB +/* + * Halfword multiply and multiply accumulate + */ + +static bool op_smlaxxx(DisasContext *s, arg_rrrr *a, + int add_long, bool nt, bool mt) +{ + TCGv_i32 t0, t1, tl, th; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_5TE) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + gen_mulxy(t0, t1, nt, mt); + tcg_temp_free_i32(t1); + + switch (add_long) { + case 0: + store_reg(s, a->rd, t0); + break; + case 1: + t1 = load_reg(s, a->ra); + gen_helper_add_setq(t0, cpu_env, t0, t1); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + break; + case 2: + tl = load_reg(s, a->ra); + th = load_reg(s, a->rd); + tcg_gen_add2_i32(tl, th, tl, th, t0, t1); + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); + store_reg(s, a->ra, tl); + store_reg(s, a->rd, th); + } + return true; +} + +#define DO_SMLAX(NAME, add, nt, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlaxxx(s, a, add, nt, mt); \ +} + +DO_SMLAX(SMULBB, 0, 0, 0) +DO_SMLAX(SMULBT, 0, 0, 1) +DO_SMLAX(SMULTB, 0, 1, 0) +DO_SMLAX(SMULTT, 0, 1, 1) + +DO_SMLAX(SMLABB, 1, 0, 0) +DO_SMLAX(SMLABT, 1, 0, 1) +DO_SMLAX(SMLATB, 1, 1, 0) +DO_SMLAX(SMLATT, 1, 1, 1) + +DO_SMLAX(SMLALBB, 2, 0, 0) +DO_SMLAX(SMLALBT, 2, 0, 1) +DO_SMLAX(SMLALTB, 2, 1, 0) +DO_SMLAX(SMLALTT, 2, 1, 1) + +#undef DO_SMLAX + +static bool op_smlawx(DisasContext *s, arg_rrrr *a, bool add, bool mt) +{ + TCGv_i32 t0, t1; + + if (!ENABLE_ARCH_5TE) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + /* + * Since the nominal result is product<47:16>, shift the 16-bit + * input up by 16 bits, so that the result is at product<63:32>. + */ + if (mt) { + tcg_gen_andi_i32(t1, t1, 0xffff0000); + } else { + tcg_gen_shli_i32(t1, t1, 16); + } + tcg_gen_muls2_i32(t0, t1, t0, t1); + tcg_temp_free_i32(t0); + if (add) { + t0 = load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t0); + tcg_temp_free_i32(t0); + } + store_reg(s, a->rd, t1); + return true; +} + +#define DO_SMLAWX(NAME, add, mt) \ +static bool trans_##NAME(DisasContext *s, arg_rrrr *a) \ +{ \ + return op_smlawx(s, a, add, mt); \ +} + +DO_SMLAWX(SMULWB, 0, 0) +DO_SMLAWX(SMULWT, 0, 1) +DO_SMLAWX(SMLAWB, 1, 0) +DO_SMLAWX(SMLAWT, 1, 1) + +#undef DO_SMLAWX + /* * Legacy decoder. */ @@ -8680,56 +8788,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } break; } - case 0x8: /* signed multiply */ + case 0x8: case 0xa: case 0xc: case 0xe: - ARCH(5TE); - rs = (insn >> 8) & 0xf; - rn = (insn >> 12) & 0xf; - rd = (insn >> 16) & 0xf; - if (op1 == 1) { - /* (32 * 16) >> 16 */ - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - if (sh & 4) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 = gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if ((sh & 2) == 0) { - tmp2 = load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } else { - /* 16 * 16 */ - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - gen_mulxy(tmp, tmp2, sh & 2, sh & 4); - tcg_temp_free_i32(tmp2); - if (op1 == 2) { - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rn, rd); - gen_storeq_reg(s, rn, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - if (op1 == 0) { - tmp2 = load_reg(s, rn); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - } - } - break; + /* Halfword multiply and multiply accumulate. */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; default: goto illegal_op; } @@ -10189,11 +10254,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ switch ((insn >> 20) & 7) { case 0: /* 32 x 32 -> 32 */ + case 1: /* 16 x 16 -> 32 */ + case 3: /* 32 * 16 -> 32msb */ + /* in decodetree */ + goto illegal_op; case 7: /* Unsigned sum of absolute differences. */ break; - case 1: /* 16 x 16 -> 32 */ case 2: /* Dual multiply add. */ - case 3: /* 32 * 16 -> 32msb */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { @@ -10205,27 +10272,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); tmp2 = load_reg(s, rm); switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs != 15) { - tmp2 = load_reg(s, rs); - if (op) - tcg_gen_sub_i32(tmp, tmp2, tmp); - else - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; - case 1: /* 16 x 16 -> 32 */ - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - if (rs != 15) { - tmp2 = load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ if (op) @@ -10249,23 +10295,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp2); } break; - case 3: /* 32 * 16 -> 32msb */ - if (op) - tcg_gen_sari_i32(tmp2, tmp2, 16); - else - gen_sxth(tmp2); - tmp64 = gen_muls_i64_i32(tmp, tmp2); - tcg_gen_shri_i64(tmp64, tmp64, 16); - tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - if (rs != 15) - { - tmp2 = load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ tmp64 = gen_muls_i64_i32(tmp, tmp2); if (rs != 15) { @@ -10340,17 +10369,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp64 = gen_mulu_i64_i32(tmp, tmp2); } else { if (op & 8) { - /* smlalxy */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - goto illegal_op; - } - gen_mulxy(tmp, tmp2, op & 2, op & 1); - tcg_temp_free_i32(tmp2); - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); + /* smlalxy, in decodetree */ + goto illegal_op; } else { /* Signed 64-bit multiply */ tmp64 = gen_muls_i64_i32(tmp, tmp2); diff --git a/target/arm/a32.decode b/target/arm/a32.decode index af6712a9e8..8dc74dfdb8 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -114,6 +114,7 @@ MVN_rri .... 001 1111 . 0000 .... ............ @s_rxi_rot @s_rdamn ---- .... ... s:1 rd:4 ra:4 rm:4 .... rn:4 &s_rrrr @s_rd0mn ---- .... ... s:1 rd:4 .... rm:4 .... rn:4 &s_rrrr ra=0 @rdamn ---- .... ... . rd:4 ra:4 rm:4 .... rn:4 &rrrr +@rd0mn ---- .... ... . rd:4 .... rm:4 .... rn:4 &rrrr ra=0 MUL .... 0000 000 . .... 0000 .... 1001 .... @s_rd0mn MLA .... 0000 001 . .... .... .... 1001 .... @s_rdamn @@ -132,3 +133,22 @@ QADD .... 0001 0000 .... .... 0000 0101 .... @rndm QSUB .... 0001 0010 .... .... 0000 0101 .... @rndm QDADD .... 0001 0100 .... .... 0000 0101 .... @rndm QDSUB .... 0001 0110 .... .... 0000 0101 .... @rndm + +# Halfword multiply and multiply accumulate + +SMLABB .... 0001 0000 .... .... .... 1000 .... @rdamn +SMLABT .... 0001 0000 .... .... .... 1100 .... @rdamn +SMLATB .... 0001 0000 .... .... .... 1010 .... @rdamn +SMLATT .... 0001 0000 .... .... .... 1110 .... @rdamn +SMLAWB .... 0001 0010 .... .... .... 1000 .... @rdamn +SMULWB .... 0001 0010 .... 0000 .... 1010 .... @rd0mn +SMLAWT .... 0001 0010 .... .... .... 1100 .... @rdamn +SMULWT .... 0001 0010 .... 0000 .... 1110 .... @rd0mn +SMLALBB .... 0001 0100 .... .... .... 1000 .... @rdamn +SMLALBT .... 0001 0100 .... .... .... 1100 .... @rdamn +SMLALTB .... 0001 0100 .... .... .... 1010 .... @rdamn +SMLALTT .... 0001 0100 .... .... .... 1110 .... @rdamn +SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn +SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn +SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn +SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 7a27b5cc5c..e611ac4969 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -118,6 +118,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 @s0_rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &s_rrrr ra=0 s=0 @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr +@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr { @@ -130,6 +131,34 @@ UMULL 1111 1011 1010 .... .... .... 0000 .... @s0_rnadm SMLAL 1111 1011 1100 .... .... .... 0000 .... @s0_rnadm UMLAL 1111 1011 1110 .... .... .... 0000 .... @s0_rnadm UMAAL 1111 1011 1110 .... .... .... 0110 .... @rnadm +{ + SMULWB 1111 1011 0011 .... 1111 .... 0000 .... @rn0dm + SMLAWB 1111 1011 0011 .... .... .... 0000 .... @rnadm +} +{ + SMULWT 1111 1011 0011 .... 1111 .... 0001 .... @rn0dm + SMLAWT 1111 1011 0011 .... .... .... 0001 .... @rnadm +} +{ + SMULBB 1111 1011 0001 .... 1111 .... 0000 .... @rn0dm + SMLABB 1111 1011 0001 .... .... .... 0000 .... @rnadm +} +{ + SMULBT 1111 1011 0001 .... 1111 .... 0001 .... @rn0dm + SMLABT 1111 1011 0001 .... .... .... 0001 .... @rnadm +} +{ + SMULTB 1111 1011 0001 .... 1111 .... 0010 .... @rn0dm + SMLATB 1111 1011 0001 .... .... .... 0010 .... @rnadm +} +{ + SMULTT 1111 1011 0001 .... 1111 .... 0011 .... @rn0dm + SMLATT 1111 1011 0001 .... .... .... 0011 .... @rnadm +} +SMLALBB 1111 1011 1100 .... .... .... 1000 .... @rnadm +SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm +SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm +SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm # Data-processing (two source registers) From patchwork Fri Jul 26 17:49:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169875 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp355312ilk; Fri, 26 Jul 2019 10:52:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqyl38pMq6Qi4lRyHoKCgcxU8QAJeODr7EimBh1pMNLOrR5Vr4NufczCbWrHs6YQSNKjRNId X-Received: by 2002:ae9:f016:: with SMTP id l22mr64213778qkg.51.1564163576391; Fri, 26 Jul 2019 10:52:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163576; cv=none; d=google.com; s=arc-20160816; b=KadY5f1vxhOb3sE1urTfSNJFVL9M9JXV2ySka2fawi14v7HDQ1VIy/+JjedpauITMD GBNi++DgCltoiAq4GgH7OORuiWl8HWJXWuG4bzvoaO0dq7ab3gMldlSXr2SnfeI6/2Bt vht/lCf7jbOurehEa0AaCNKa5LSSVqm2Nb1sPnf4FHUSz4nx9VOPamfw5Z8q6QxM5HDO VaKw8er7pmW9FjR3mm0OH0Y/Et0zdQ+Caf44VYe7nVsQqeuPFZvLBeD8pfAwdx5fVeFy 8sYWEcJQI4gbrR3nmZuI9JmjRpcyROvp0WEqQ/DrbScFhZ/ETys/uaOw8vpXKwiZLcwu iXQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4ALWL+uoJUM+006aGewT3E/ArRPeObW9mCQYZxOKNhg=; b=AaNGx1X+EL7tI7PaPC+hTJ+IOOa9l/XSvwZOF+HjdtRZX2hxIwUfgNTyssfBraGGNG QOMdD+zb3sq2L/rLs9X0LRYvfVhb+bfQbewO1ZStAD7R3LPW9YWWHK2l/PJFW/lIxISa 97XEY4hmJt1BUdK16JXkBx4QTtLYebWtEhlAvG1rc28Z/xFm/gOKFnA7y+SN2GVkM2J9 dstKCpvj9Eh1Vg5OfIKsBEOkLE4a8mbcLwfDPMNTnzoyr0lT1SlNdRuNMrww1w8qCEVV f4UB+ry1G8H8e+p3rWBbGR9WHFJin8kNJv195pXKXhNatpR7eDWLN4e0YB31y8fd0vej nuMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ukzzjtgk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q31si18616761qta.349.2019.07.26.10.52.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:52:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ukzzjtgk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Ok-0002Gn-8a for patch@linaro.org; Fri, 26 Jul 2019 13:52:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57637) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Ms-0002oM-Ku for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mq-0007zy-62 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:57 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:38251) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mq-0007v5-0a for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:56 -0400 Received: by mail-pf1-x442.google.com with SMTP id y15so24860433pfn.5 for ; Fri, 26 Jul 2019 10:50:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4ALWL+uoJUM+006aGewT3E/ArRPeObW9mCQYZxOKNhg=; b=UkzzjtgkD3XEQARx/R51cETEunwutE29JNVmjuiVAQYcmK/Xv3BwkhKofr9fDDyTct 2gU575BmE1wSjA0Dgs40/lZleoJHxagmioyMn0e4pGsCwATXkZNp5jAdRWcFaipXFPJl RGyuR72Pv1d98IKUHAgJuV4L3C/QfG5KI05zsX/TaN+GUPJfPtkzCh8OCn70XHQZVY3H i469v3RIHnYEBajRgk1UxJx/O2vaFAVVAWQIEMQVCkezHHLyPoFrAaRTETYqcfYCpJew liA3mtdb+IOt5lpll76H9rFwo1Lpkxal0+jNcf52YcBnTsPZui5QIS354FMqqLG5+IN1 SE3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4ALWL+uoJUM+006aGewT3E/ArRPeObW9mCQYZxOKNhg=; b=uF8Vrrq9KS5e0fb/SKUnayRnSAf491Bt0UZcG2oHTSk2btjCchVIU4SkOoA5fCnS4g +FiyVA1gw1M3r2V+rLCg+p+xgWCy11L+eOSuxIxR9XgfAJwR9ReI/ST3C0AvBObp/HW/ 1aQ9xvjgWUVMWa8GljYQQvShjUZBuFPDh1IQfS8roESmu52loW9cqApXWu1ggqu2JJao I/5gz38Sq4vqpl0E6CxjnfWb+cjiLRCeaVhi14AGGfo6QplfkbOvizkYrFqZx5vtIbNe 06dlCz+wv6RU+wZxLCGnnv5xXZWndrqL2W3e306Fd6zZMoi6Rrmlai8QmwlsniEhTeT1 vH4Q== X-Gm-Message-State: APjAAAWVEf2ZpFq52f0b6LYJp0jWHHJ2fHTA1lucNwR0qVuFjQLN3EBQ e9hmQgcE9Ppyz/9qR12lQZa7O+5O0B4= X-Received: by 2002:aa7:8218:: with SMTP id k24mr22624844pfi.221.1564163453745; Fri, 26 Jul 2019 10:50:53 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.52 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:42 -0700 Message-Id: <20190726175032.6769-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 61 +++++++++++++++++++++++++++++------------- target/arm/a32.decode | 25 +++++++++++++++++ target/arm/t32.decode | 17 ++++++++++++ 3 files changed, 84 insertions(+), 19 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 2140671eb2..36c815caf3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8324,6 +8324,44 @@ DO_SMLAWX(SMLAWT, 1, 1) #undef DO_SMLAWX +/* + * MSR (immediate) and hints + */ + +static bool trans_YIELD(DisasContext *s, arg_YIELD *a) +{ + gen_nop_hint(s, 1); + return true; +} + +static bool trans_WFE(DisasContext *s, arg_WFE *a) +{ + gen_nop_hint(s, 2); + return true; +} + +static bool trans_WFI(DisasContext *s, arg_WFI *a) +{ + gen_nop_hint(s, 2); + return true; +} + +static bool trans_NOP(DisasContext *s, arg_NOP *a) +{ + return true; +} + +static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) +{ + uint32_t val = ror32(a->imm, a->rot * 2); + uint32_t mask = msr_mask(s, a->mask, a->r); + + if (gen_set_psr_im(s, mask, a->r, val)) { + gen_illegal_op(s); + } + return true; +} + /* * Legacy decoder. */ @@ -8594,22 +8632,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } store_reg(s, rd, tmp); } else { - if (((insn >> 12) & 0xf) != 0xf) - goto illegal_op; - if (((insn >> 16) & 0xf) == 0) { - gen_nop_hint(s, insn & 0xff); - } else { - /* CPSR = immediate */ - val = insn & 0xff; - shift = ((insn >> 8) & 0xf) * 2; - if (shift) - val = (val >> shift) | (val << (32 - shift)); - i = ((insn & (1 << 22)) != 0); - if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i), - i, val)) { - goto illegal_op; - } - } + /* MSR (immediate) and hints */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); } } else if ((insn & 0x0f900000) == 0x01000000 && (insn & 0x00000090) != 0x00000090) { @@ -10569,9 +10594,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; break; case 2: /* cps, nop-hint. */ - if (((insn >> 8) & 7) == 0) { - gen_nop_hint(s, insn & 0xff); - } + /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ if (IS_USER(s)) break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 8dc74dfdb8..4cefba6f0e 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -22,6 +22,7 @@ # All insns that have 0xf in insn[31:28] are in a32u.decode. # +&empty &s_rrr_shi s rd rn rm shim shty &s_rrr_shr s rn rd rm rs shty &s_rri_rot s rn rd imm rot @@ -152,3 +153,27 @@ SMULBB .... 0001 0110 .... 0000 .... 1000 .... @rd0mn SMULBT .... 0001 0110 .... 0000 .... 1100 .... @rd0mn SMULTB .... 0001 0110 .... 0000 .... 1010 .... @rd0mn SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn + +# MSR (immediate) and hints + +&msr_i r mask rot imm +@msr_i ---- .... .... mask:4 .... rot:4 imm:8 &msr_i + +{ + { + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + # The canonical nop ends in 00000000, but the whole of the + # rest of the space executes as nop if otherwise unsupported. + NOP ---- 0011 0010 0000 1111 ---- ---- ---- + } + # Note mask = 0 is covered by NOP + MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=0 +} +MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index e611ac4969..b4f0a9632d 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -166,3 +167,19 @@ QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm + +# Branches and miscellaneous control + +{ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- +} From patchwork Fri Jul 26 17:49:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169876 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp355986ilk; Fri, 26 Jul 2019 10:53:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqz0P5Mv8cu8Aqq0yqy762HCMr0fuuy6dJtweb/u/Yb8XJZMJiOkaB1EAGmk2kMPlyG7Ryy4 X-Received: by 2002:a0c:b012:: with SMTP id k18mr69828047qvc.74.1564163618175; Fri, 26 Jul 2019 10:53:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163618; cv=none; d=google.com; s=arc-20160816; b=fhflY42sIjmdovmP0xf0kUlbBmPmWKD2VB35U5wmueswqY7jdERDgQswqWLZyYgTh/ eWOti+jN8H1L08Kd3LBDsK2lkrtj8G5ks1gv25OxJcPsPzB5ljq1G3gMbXI7QylarAWS 650ch+Y1bo+aSiv66DOIFP5kYGb7heGkBWkufWZm19XFSuDLvPivtW489hroJ3snYMKL ovdXXgHcrnODKwg1SKSPPp4ON8fazHNeOd/ZnX4pPWkGUccH0StPMOzJ2L9rkwUXzRYX KbCUshU/WorplJS42G35bFjJDKNsodNBcuf9m5fIvVHZnvcSjH3QINsU2iFBF1o1DnlJ Acng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Ko4pYTSBEN/+JP+TS7Nhd6jgGRonS+CZaYZwT+yeEyg=; b=ubEdv3JWAzFSagFMNmhSfpP6XdPA0KKs9342ZGxnPkiV+71iAFNlmiOP3PEukplBwB 9GMY9//SerI/WpSNx6EnhNcOyJm5XW0w8yhjR2KXf8nXpCbKlm9+02NSR+0uAqY+vBat JGr1Mq7V3jcGx1VBfUq7SsaQb3iT9POezIzZDqPathXLdOzO9KS9eVCay2C7C0/YR+ZZ 8KXgt27M+ZA4Jj9npEPsXm8U5E4kCUacfJmJ3EuzS4DB7hm2NgpEkQaNgOserpJMjHCH Qdp7VfjfJvoNTQQF93RCTF5TPguBHAntA/T4qj9VFsxjPYWKEytz+AV9e0LuZ8sLXfqg JXgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SG6P8pI8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s124si3960446qkb.5.2019.07.26.10.53.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:53:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SG6P8pI8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42274 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4PQ-0005Mu-2u for patch@linaro.org; Fri, 26 Jul 2019 13:53:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57722) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mu-0002wp-EI for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mr-00083H-Jq for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:59 -0400 Received: from mail-pg1-x52e.google.com ([2607:f8b0:4864:20::52e]:33662) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mr-0007ya-C5 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:57 -0400 Received: by mail-pg1-x52e.google.com with SMTP id f20so15877473pgj.0 for ; Fri, 26 Jul 2019 10:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ko4pYTSBEN/+JP+TS7Nhd6jgGRonS+CZaYZwT+yeEyg=; b=SG6P8pI8qkJAEgA7PTPQrZHh/YV0zDxbwIhBxnbXnakas53rMcPWnIo2TZKRf3EPKM RaP0nIfYs2firqBy8Nr8pxwntotEVYidfrH+W5g7i3eg+gPiwzpzT4fuHaStKxuquVbi PpvV6E1JJj9lVdMbyQgZc7TZJIjf3AtdKxjlJ9yuozJFFv9+WeWgDTCbY6KFWCNdxaON w/1V/4hOEGHBupFyETJGyeA0sGA9KQGM6e4NLxgVNygjt4NcPRIbrUv5+V8UhIF4DhTI qQ69GYNWA/0sCncSBbKQw+fNieabe3fReIHclfVqFFCKUdYuax1Q9OyVmdOtVjklkKar KRAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ko4pYTSBEN/+JP+TS7Nhd6jgGRonS+CZaYZwT+yeEyg=; b=f25tbAE1Ircna286AWKc7XanOsL5J9MLGTfulUJtNz7eV6kGOlkY8B1peMmTx/qdYV kyFxbXHqiwjaFXdiLmEY88AIxtHey2HxZlxgKRFzxac3Gpq/0pBWP2pXkdi2mBV04XvM eUySZYY3EDA1PrDN/xLEJgXVnzc1QlSfZcJ6CNrRURd3b7rPLultvLCdWC4eypekH4Wy I5ddQKxjh0w40HsQ5PU7qGzjxy7d8zpKEg6a1/2NCxbd/H35gEskf4ZKCP54OASiXdl9 mGXIjg49WYXeViHLqhaVUmC+fFLCFA8fFZ0BUxMgXgKoCmyibsXd88HsZ+Z33csIVsq3 s0CA== X-Gm-Message-State: APjAAAX3pKyffHXVhvjCA9KyAjBczAvI81o4go5oSxpY/WaOtqBQyKKF lWMiV/rJtE+4ATxSKuqTvSBEaPk3/yw= X-Received: by 2002:a63:5402:: with SMTP id i2mr65383463pgb.414.1564163454738; Fri, 26 Jul 2019 10:50:54 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.53 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:43 -0700 Message-Id: <20190726175032.6769-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52e Subject: [Qemu-devel] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 226 ++++++++++++++++++----------------------- target/arm/a32.decode | 14 +++ target/arm/t32.decode | 40 ++++++-- 3 files changed, 142 insertions(+), 138 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 36c815caf3..fa0c048b38 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8362,6 +8362,93 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) return true; } +/* + * Miscellaneous instructions + */ + +static bool trans_MRS_bank(DisasContext *s, arg_MRS_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_mrs_banked(s, a->r, a->sysm, a->rd); + return true; +} + +static bool trans_MSR_bank(DisasContext *s, arg_MSR_bank *a) +{ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_msr_banked(s, a->r, a->sysm, a->rn); + return true; +} + +static bool trans_MRS_reg(DisasContext *s, arg_MRS_reg *a) +{ + TCGv_i32 tmp; + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + if (a->r) { + if (IS_USER(s)) { + gen_illegal_op(s); + return true; + } + tmp = load_cpu_field(spsr); + } else { + tmp = tcg_temp_new_i32(); + gen_helper_cpsr_read(tmp, cpu_env); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_reg(DisasContext *s, arg_MSR_reg *a) +{ + TCGv_i32 tmp; + uint32_t mask = msr_mask(s, a->mask, a->r); + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp = load_reg(s, a->rn); + if (gen_set_psr(s, mask, a->r, tmp)) { + gen_illegal_op(s); + } + return true; +} + +static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7m *a) +{ + TCGv_i32 tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + tmp = tcg_const_i32(a->sysm); + gen_helper_v7m_mrs(tmp, cpu_env, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) +{ + TCGv_i32 addr, reg; + + if (!arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + addr = tcg_const_i32((a->mask << 10) | a->sysm); + reg = load_reg(s, a->rn); + gen_helper_v7m_msr(cpu_env, addr, reg); + tcg_temp_free_i32(addr); + tcg_temp_free_i32(reg); + gen_lookup_tb(s); + return true; +} + /* * Legacy decoder. */ @@ -8643,46 +8730,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) sh = (insn >> 4) & 0xf; rm = insn & 0xf; switch (sh) { - case 0x0: /* MSR, MRS */ - if (insn & (1 << 9)) { - /* MSR (banked) and MRS (banked) */ - int sysm = extract32(insn, 16, 4) | - (extract32(insn, 8, 1) << 4); - int r = extract32(insn, 22, 1); - - if (op1 & 1) { - /* MSR (banked) */ - gen_msr_banked(s, r, sysm, rm); - } else { - /* MRS (banked) */ - int rd = extract32(insn, 12, 4); - - gen_mrs_banked(s, r, sysm, rd); - } - break; - } - - /* MSR, MRS (for PSRs) */ - if (op1 & 1) { - /* PSR = reg */ - tmp = load_reg(s, rm); - i = ((op1 & 2) != 0); - if (gen_set_psr(s, msr_mask(s, (insn >> 16) & 0xf, i), i, tmp)) - goto illegal_op; - } else { - /* reg = PSR */ - rd = (insn >> 12) & 0xf; - if (op1 & 2) { - if (IS_USER(s)) - goto illegal_op; - tmp = load_cpu_field(spsr); - } else { - tmp = tcg_temp_new_i32(); - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - } - break; + case 0x0: + /* MSR/MRS (banked/register) */ + /* All done in decodetree. Illegal ops already signalled. */ + g_assert_not_reached(); case 0x1: if (op1 == 1) { /* branch/exchange thumb (bx). */ @@ -10559,40 +10610,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } else { op = (insn >> 20) & 7; switch (op) { - case 0: /* msr cpsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp = load_reg(s, rn); - /* the constant is the mask and SYSm fields */ - addr = tcg_const_i32(insn & 0xfff); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - break; - } - /* fall through */ - case 1: /* msr spsr. */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - - if (extract32(insn, 5, 1)) { - /* MSR (banked) */ - int sysm = extract32(insn, 8, 4) | - (extract32(insn, 4, 1) << 4); - int r = op & 1; - - gen_msr_banked(s, r, sysm, rm); - break; - } - - /* MSR (for PSRs) */ - tmp = load_reg(s, rn); - if (gen_set_psr(s, - msr_mask(s, (insn >> 8) & 0xf, op == 1), - op == 1, tmp)) - goto illegal_op; - break; + case 0: /* msr cpsr, in decodetree */ + case 1: /* msr spsr, in decodetree */ + goto illegal_op; case 2: /* cps, nop-hint. */ /* nop hints in decodetree */ /* Implemented as NOP in user mode. */ @@ -10684,61 +10704,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } gen_exception_return(s, tmp); break; - case 6: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm = extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 0, sysm, rd); - break; - } - - if (extract32(insn, 16, 4) != 0xf) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_M) && - extract32(insn, 0, 8) != 0) { - goto illegal_op; - } - - /* mrs cpsr */ - tmp = tcg_temp_new_i32(); - if (arm_dc_feature(s, ARM_FEATURE_M)) { - addr = tcg_const_i32(insn & 0xff); - gen_helper_v7m_mrs(tmp, cpu_env, addr); - tcg_temp_free_i32(addr); - } else { - gen_helper_cpsr_read(tmp, cpu_env); - } - store_reg(s, rd, tmp); - break; - case 7: /* MRS */ - if (extract32(insn, 5, 1) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - /* MRS (banked) */ - int sysm = extract32(insn, 16, 4) | - (extract32(insn, 4, 1) << 4); - - gen_mrs_banked(s, 1, sysm, rd); - break; - } - - /* mrs spsr. */ - /* Not accessible in user mode. */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - - if (extract32(insn, 16, 4) != 0xf || - extract32(insn, 0, 8) != 0) { - goto illegal_op; - } - - tmp = load_cpu_field(spsr); - store_reg(s, rd, tmp); - break; + case 6: /* MRS, in decodetree */ + case 7: /* MSR, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 4cefba6f0e..50449fa8ec 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,10 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&msr_reg rn r mask +&mrs_reg rd r +&msr_bank rn r sysm +&mrs_bank rd r sysm # Data-processing (register) @@ -177,3 +181,13 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn MSR_imm .... 0011 0010 .... 1111 .... .... .... @msr_i r=0 } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 + +# Miscellaneous instructions + +%sysm 8:1 16:4 + +MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm +MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm + +MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg +MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg diff --git a/target/arm/t32.decode b/target/arm/t32.decode index b4f0a9632d..40a2c520c1 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,10 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&msr_reg !extern rn r mask +&mrs_reg !extern rd r +&msr_bank !extern rn r sysm +&mrs_bank !extern rd r sysm # Data-processing (register-shifted register) @@ -170,16 +174,34 @@ QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm # Branches and miscellaneous control +%msr_sysm 4:1 8:4 +%mrs_sysm 4:1 16:4 + { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + &mrs_bank sysm=%mrs_sysm + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + &msr_bank sysm=%msr_sysm + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } } From patchwork Fri Jul 26 17:49:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169892 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp359213ilk; Fri, 26 Jul 2019 10:57:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqwv1ND1i4GfHZ/659U5Qog6cpcb5mRUKLFQxNcca44o06mZ52HIrlnf8zjgGzYbkTBB+K7/ X-Received: by 2002:a50:a544:: with SMTP id z4mr82510313edb.71.1564163825250; Fri, 26 Jul 2019 10:57:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163825; cv=none; d=google.com; s=arc-20160816; b=xXd5xWO0ki5s7UD41en/e0WIBTinPsH99hWWbaCtyXtPHH86s4GXECllRSauw33AqS btdQQ+wZ2iY2mUqNYfASP4m0/psFg3pfN+ydKUFpnzEgKSar3BLxbJ8d4h96YsoLb5ui fyi+TuyV+pT5AickX12F/nBzwhmqHuWPZe3zNX9CY13DIxhDu7XD7Pv5pHBX99vAcwyV Lx5xqIKXcnTMAUztsvNkNblJueH6gdpKXH3YbuiU1vS0YtnxdtDW8pVaVwjnmPrLHM53 ZCI5tMNPE08JcQn2UVRn/dzDd98/BjXzZ6utltmMKEWZEsOw/eejykZjERWPMXKPrlJN ZWIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=yeeH2D/Nsh9oAvCAiY/tPwxLxmb7stM68Oiu9y5meMM=; b=eAoTCSEEJFU4sRdNucEi+wM7iK2vfI4xOvdJwOsTjhvJHBDTc2ljsXfo0lAWz7IDX5 lY/8WPW20X+bbv/SE9f67NYN5L5Oaw8mHBfTFkdugIrOkRZySfXrOCjyqf2uFKGE8zIP 9azmJwfOpp9FmH9BPPCjRdppRCU5TyUwrzqzZQ0uun1kH3vK6fLFp+pEggL2hJ23e62N Aa6gsUyVgMgcJbIKA6Tl1QAQTnUG2wBUWuWmjHpKOd4A9VEY9yGNPbb0tSVMzlLOSt/o YE5crClfSZgpbyA4DsoxDseRahqJFMJ1rcUbY3SSkXZtcM4ebxzgwNZ8diweMwnB1bjb UVlA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YTYGwF+p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y10si12948277edc.352.2019.07.26.10.57.05 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:57:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=YTYGwF+p; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42422 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Sj-0002p9-1n for patch@linaro.org; Fri, 26 Jul 2019 13:57:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58000) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4N2-0003U0-Cc for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mz-0008Nf-NL for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:07 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:39642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Ms-00081d-FA for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:05 -0400 Received: by mail-pg1-x543.google.com with SMTP id u17so25110612pgi.6 for ; Fri, 26 Jul 2019 10:50:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yeeH2D/Nsh9oAvCAiY/tPwxLxmb7stM68Oiu9y5meMM=; b=YTYGwF+pR7Ljd40OJHMptB6C2AK62uTb9fNiZMUNXgx1OxfnPs/VS4x/x0bAYdgKjk +WSzyaxlT6CiM/29cFZxOqLkGhqYFIkIo72hpyRyvbyd/L4YAnm6+BbnDVoEiL2dYj1N eetePY7PWshCWWxv9i5ud4uH5TsSAczA6T0cnpYKosnDF3h4sah1h2azvYlagij0i8Uy vUXnXhac3xquLb4VAZDtl5GadryG+PwAmhwc6T/yPZMo1sFgGv5PuUpyEXKLoW4jJIHi pt3M/GEPi5FFs17dzCqsXYTSB7mytqRBTAon19m+YRXH60ghPxqGVgmKcbsmcdnSD6ds PIBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yeeH2D/Nsh9oAvCAiY/tPwxLxmb7stM68Oiu9y5meMM=; b=cQ++LI1zFHFI79Uy94vRzrMUBVUc2SBjz39UoeA9FSGBmdA9VxVqjjG7X5OfYsIMpK ++gD0BwBbuYV3BEOkF8hUrAzuHU4GSovog8AHYFndn7Jg4Rsx8hPNu7a+OaVRYK9L4x3 PwD0T749lTb+095zLksuNzPKtsKXvquznhn2jQOaOJBH+XXZTK1oMto4zXheHt17wUyC YGaAqHf4XhHqip78ylMA3h9SxS28HbEac55PMjHVFLEa5BOLJC5SxlFFaXbNPO/Ry4nq 7WCPcL4NQpJ1k0sxz7R9HAg1HkCPlZXm8SDLcXKP7TSQbX3QYYaI+9REcwMYL/AYpIW2 xNoQ== X-Gm-Message-State: APjAAAVuczhivrwHGRk2I4Uhkg2RMDAcbKzABkNwX/m+6ruXrHFYxJBJ xXSb0gqlDR8QjPcabgYBuFPuB5bhOdg= X-Received: by 2002:aa7:9481:: with SMTP id z1mr23635241pfk.92.1564163456219; Fri, 26 Jul 2019 10:50:56 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.54 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:44 -0700 Message-Id: <20190726175032.6769-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 19/67] target/arm: Convert Cyclic Redundancy Check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 121 +++++++++++++++++++---------------------- target/arm/a32.decode | 9 +++ target/arm/t32.decode | 7 +++ 3 files changed, 72 insertions(+), 65 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index fa0c048b38..ed7041d0e4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8362,6 +8362,57 @@ static bool trans_MSR_imm(DisasContext *s, arg_MSR_imm *a) return true; } +/* + * Cyclic Redundancy Check + */ + +static bool op_crc32(DisasContext *s, arg_rrr *a, bool c, TCGMemOp sz) +{ + TCGv_i32 t1, t2, t3; + + if (!dc_isar_feature(aa32_crc32, s)) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + switch (sz) { + case MO_8: + gen_uxtb(t2); + break; + case MO_16: + gen_uxth(t2); + break; + case MO_32: + break; + default: + g_assert_not_reached(); + } + t3 = tcg_const_i32(1 << sz); + if (c) { + gen_helper_crc32c(t1, t1, t2, t3); + } else { + gen_helper_crc32(t1, t1, t2, t3); + } + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + store_reg(s, a->rd, t1); + return true; +} + +#define DO_CRC32(NAME, c, sz) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ + { return op_crc32(s, a, c, sz); } + +DO_CRC32(CRC32B, false, MO_8) +DO_CRC32(CRC32H, false, MO_16) +DO_CRC32(CRC32W, false, MO_32) +DO_CRC32(CRC32CB, true, MO_8) +DO_CRC32(CRC32CH, true, MO_16) +DO_CRC32(CRC32CW, true, MO_32) + +#undef DO_CRC32 + /* * Miscellaneous instructions */ @@ -8774,39 +8825,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) gen_bx(s, tmp); break; case 0x4: - { - /* crc32/crc32c */ - uint32_t c = extract32(insn, 8, 4); - - /* Check this CPU supports ARMv8 CRC instructions. - * op1 == 3 is UNPREDICTABLE but handle as UNDEFINED. - * Bits 8, 10 and 11 should be zero. - */ - if (!dc_isar_feature(aa32_crc32, s) || op1 == 0x3 || (c & 0xd) != 0) { - goto illegal_op; - } - - rn = extract32(insn, 16, 4); - rd = extract32(insn, 12, 4); - - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if (op1 == 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (op1 == 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 = tcg_const_i32(1 << op1); - if (c & 0x2) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - store_reg(s, rd, tmp); - break; - } + /* crc32 */ + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; case 0x5: /* Saturating addition and subtraction. */ /* All done in decodetree. Reach here for illegal ops. */ @@ -10256,16 +10277,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } break; - case 0x20: /* crc32/crc32c */ + case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: case 0x28: case 0x29: case 0x2a: - if (!dc_isar_feature(aa32_crc32, s)) { - goto illegal_op; - } - break; + goto illegal_op; default: goto illegal_op; } @@ -10294,33 +10312,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0x18: /* clz */ tcg_gen_clzi_i32(tmp, tmp, 32); break; - case 0x20: - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - { - /* crc32/crc32c */ - uint32_t sz = op & 0x3; - uint32_t c = op & 0x8; - - tmp2 = load_reg(s, rm); - if (sz == 0) { - tcg_gen_andi_i32(tmp2, tmp2, 0xff); - } else if (sz == 1) { - tcg_gen_andi_i32(tmp2, tmp2, 0xffff); - } - tmp3 = tcg_const_i32(1 << sz); - if (c) { - gen_helper_crc32c(tmp, tmp, tmp2, tmp3); - } else { - gen_helper_crc32(tmp, tmp, tmp2, tmp3); - } - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); - break; - } default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 50449fa8ec..5751e615cd 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -182,6 +182,15 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .... @rd0mn } MSR_imm .... 0011 0110 .... 1111 .... .... .... @msr_i r=1 +# Cyclic Redundancy Check + +CRC32B .... 0001 0000 .... .... 0000 0100 .... @rndm +CRC32H .... 0001 0010 .... .... 0000 0100 .... @rndm +CRC32W .... 0001 0100 .... .... 0000 0100 .... @rndm +CRC32CB .... 0001 0000 .... .... 0010 0100 .... @rndm +CRC32CH .... 0001 0010 .... .... 0010 0100 .... @rndm +CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm + # Miscellaneous instructions %sysm 8:1 16:4 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 40a2c520c1..30971787d4 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -172,6 +172,13 @@ QSUB 1111 1010 1000 .... 1111 .... 1010 .... @rndm QDADD 1111 1010 1000 .... 1111 .... 1001 .... @rndm QDSUB 1111 1010 1000 .... 1111 .... 1011 .... @rndm +CRC32B 1111 1010 1100 .... 1111 .... 1000 .... @rndm +CRC32H 1111 1010 1100 .... 1111 .... 1001 .... @rndm +CRC32W 1111 1010 1100 .... 1111 .... 1010 .... @rndm +CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm +CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm +CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm + # Branches and miscellaneous control %msr_sysm 4:1 8:4 From patchwork Fri Jul 26 17:49:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169881 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp356967ilk; Fri, 26 Jul 2019 10:54:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqyWru4pND7gAOrfbhdnT1Ltw1RStAm0Yo5AT8J9Ycav9gVm6wNrGO5/UAeFvj9OYcU3nRJs X-Received: by 2002:a05:6402:1658:: with SMTP id s24mr84206710edx.288.1564163676127; Fri, 26 Jul 2019 10:54:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163676; cv=none; d=google.com; s=arc-20160816; b=mKk7Gx/dQwe6j9PJMzWcq6soABIk7pFDog/w/W9PqbnOlxny6cFvMWiQxPIOuTnbcs OwMSB9a5IosDZxlKkz7MFiL5d4AwCnq7uvamYsX/OhePTX7VDzdEoPBvu0cUY1iABf6d mvIIBxQo18FWXRd/S/aLDmSQlzMEsYKflVUm1xZ5PRZsZsGR1l5LLGNI9Gdhagkp96Q1 3husNWN/uEcXa1+rdEUrDXslBN1ejSpDzBBi+acDlA5N8bTZAqdSjifXuhI7Xl9aELO+ 4T16sFBX2zhnKDdNvHJVi7itnk2LssW5wsfS1WbF5uQshKA61NHKwZomghb+bozgINYz trcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=huKGKNTHhMAQYotnG12iGCpac4tzd+qILlBM8dReHjw=; b=f9/ZaBEf7NY/8E4a3xd89u1fT5QVinMVkDBh4K2mlVRVdIHqxCLaM/Pb7NugEvfjEM aw6OrCfxcaSi3p2MZVOAipRpQCghIJ1GnX9WKYlvgQgrdMBI+L9fkmDJUl6Jzii5AEKv J5LfQeTWmuI53hTg3yirDm0sfa5NVK/5Tzu/5M9HjOjfhnZW2dz5LgaE/ksJsEJxpjqM zQFQ77Z4+o907/b687DQzEcoGMdU9A8PsqMOuogPhpuZY4hNcUnHicx8DJRel7h1CKk5 As1uD0kYjEww7ufgqkT0B3AICSdkZI1XlDjWWcIR02NPJJDetYCP7j27TiCzGNdXgj9l D+6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jMfWkLTr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h4si7814711ejj.127.2019.07.26.10.54.35 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:54:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=jMfWkLTr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42320 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4QM-00006P-Kp for patch@linaro.org; Fri, 26 Jul 2019 13:54:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57779) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mu-00032X-Sm for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Ms-00085f-Rt for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:00 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:43172) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Ms-000848-J9 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:50:58 -0400 Received: by mail-pl1-x641.google.com with SMTP id 4so18030380pld.10 for ; Fri, 26 Jul 2019 10:50:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=huKGKNTHhMAQYotnG12iGCpac4tzd+qILlBM8dReHjw=; b=jMfWkLTryN7tAbDeHKBPic2jIb1HBpMyRuEeMb8G2f4qeSgDIv/W6wxA2HcZjix8EB gfgqObU8D4SqtRPvBh0HYDwZba1Hq0KN9DbcFqLyoWNDMpxu/lFCM9qRoNj1mpHSOc9c CzN9kDtOVk+B5pk96pfv2vPDjUS4AQsDsvQBM3V6z3BOVsimbUVFafnoSFKrveexDrMM Y0lhn86ttRdgzqc87XySdU7ZMv/B3N8hVqAofAxeI7bxJKbjxiyBFGne8cy+cHfM4MPh KGNHeKV++/1IfYVKckZXkb2yKtbjEYvA4JsLLPHQKCUVpiqlC9UBjZ8pg0l97kqU3dxU vutg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=huKGKNTHhMAQYotnG12iGCpac4tzd+qILlBM8dReHjw=; b=C+oiaEAUzQdj1eNSAZ9LfCHK8K8smPrc4vecifJyN5eQNo5sCkcc9Cu+WQl+i6Be++ xVKS8zPyYhmJlwyyxmQe6qNSUJWx7Z860Z3fSt/XnBvyfZI0ku8dxfwHcwKZB3BTFPuv 6n2/EXhuptkOVs3kIX3XjVMCS2ojVMdDAdRF5+9tPUi1fWKvbcfS6D5rkO+tZoNmMQ1j TSviv2j6ot4JAav4isauOFmUm8Qh0AHeSYUvxpVUqDrC1czAROG+bZzR1P35bktoO+Aa hkL5ZkGTATgJcnFM+TAmZzy8H1LpLO1WQmxV8o6MjwlCF7+qsD10TjKP4Rey2Cazrl4V rHoA== X-Gm-Message-State: APjAAAUv3px7NioNbhGZLiiNOckwFY1Qbq/1+Gqk1mz2s0pUoB0N44ew +YxNEBEUrKM7O7aeOX+jmNJAAOdJ+fA= X-Received: by 2002:a17:902:a612:: with SMTP id u18mr94716011plq.181.1564163457290; Fri, 26 Jul 2019 10:50:57 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.56 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:45 -0700 Message-Id: <20190726175032.6769-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This fixes an exiting bug with the T5 encoding of SUBS PC, LR, #IMM, in that it may be executed from user mode as with any other encoding of SUBS, not as ERET. Signed-off-by: Richard Henderson --- target/arm/translate.c | 273 +++++++++++++++-------------------------- target/arm/a32.decode | 21 ++++ target/arm/t32.decode | 20 +++ 3 files changed, 143 insertions(+), 171 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index ed7041d0e4..09310b1c3a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8500,6 +8500,101 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a) return true; } +static bool trans_BX(DisasContext *s, arg_BX *a) +{ + if (!ENABLE_ARCH_4T) { + return false; + } + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BXJ(DisasContext *s, arg_BXJ *a) +{ + if (!ENABLE_ARCH_5J || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + /* Trivial implementation equivalent to bx. */ + gen_bx(s, load_reg(s, a->rm)); + return true; +} + +static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp = load_reg(s, a->rm); + tcg_gen_movi_i32(cpu_R[14], s->pc | s->thumb); + gen_bx(s, tmp); + return true; +} + +static bool trans_CLZ(DisasContext *s, arg_CLZ *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_5) { + return false; + } + tmp = load_reg(s, a->rm); + tcg_gen_clzi_i32(tmp, tmp, 32); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_ERET(DisasContext *s, arg_ERET *a) +{ + TCGv_i32 tmp; + + if (IS_USER(s) || !arm_dc_feature(s, ARM_FEATURE_V7VE)) { + return false; + } + if (s->current_el == 2) { + /* ERET from Hyp uses ELR_Hyp, not LR */ + tmp = load_cpu_field(elr_el[2]); + } else { + tmp = load_reg(s, 14); + } + gen_exception_return(s, tmp); + return true; +} + +static bool trans_HLT(DisasContext *s, arg_HLT *a) +{ + gen_hlt(s, a->imm); + return true; +} + +static bool trans_BKPT(DisasContext *s, arg_BKPT *a) +{ + if (!ENABLE_ARCH_5) { + return false; + } + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + return true; +} + +static bool trans_HVC(DisasContext *s, arg_HVC *a) +{ + if (!ENABLE_ARCH_7 || IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_hvc(s, a->imm); + return true; +} + +static bool trans_SMC(DisasContext *s, arg_SMC *a) +{ + if (!ENABLE_ARCH_6K || IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } + gen_smc(s); + return true; +} + /* * Legacy decoder. */ @@ -8777,124 +8872,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } else if ((insn & 0x0f900000) == 0x01000000 && (insn & 0x00000090) != 0x00000090) { /* miscellaneous instructions */ - op1 = (insn >> 21) & 3; - sh = (insn >> 4) & 0xf; - rm = insn & 0xf; - switch (sh) { - case 0x0: - /* MSR/MRS (banked/register) */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - case 0x1: - if (op1 == 1) { - /* branch/exchange thumb (bx). */ - ARCH(4T); - tmp = load_reg(s, rm); - gen_bx(s, tmp); - } else if (op1 == 3) { - /* clz */ - ARCH(5); - rd = (insn >> 12) & 0xf; - tmp = load_reg(s, rm); - tcg_gen_clzi_i32(tmp, tmp, 32); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; - case 0x2: - if (op1 == 1) { - ARCH(5J); /* bxj */ - /* Trivial implementation equivalent to bx. */ - tmp = load_reg(s, rm); - gen_bx(s, tmp); - } else { - goto illegal_op; - } - break; - case 0x3: - if (op1 != 1) - goto illegal_op; - - ARCH(5); - /* branch link/exchange thumb (blx) */ - tmp = load_reg(s, rm); - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->pc); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - case 0x4: - /* crc32 */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - case 0x5: - /* Saturating addition and subtraction. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 0x6: /* ERET */ - if (op1 != 3) { - goto illegal_op; - } - if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { - goto illegal_op; - } - if ((insn & 0x000fff0f) != 0x0000000e) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - - if (s->current_el == 2) { - tmp = load_cpu_field(elr_el[2]); - } else { - tmp = load_reg(s, 14); - } - gen_exception_return(s, tmp); - break; - case 7: - { - int imm16 = extract32(insn, 0, 4) | (extract32(insn, 8, 12) << 4); - switch (op1) { - case 0: - /* HLT */ - gen_hlt(s, imm16); - break; - case 1: - /* bkpt */ - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false)); - break; - case 2: - /* Hypervisor call (v7) */ - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - break; - case 3: - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - break; - default: - g_assert_not_reached(); - } - break; - } - case 0x8: - case 0xa: - case 0xc: - case 0xe: - /* Halfword multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - default: - goto illegal_op; - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if (((insn & 0x0e000000) == 0 && (insn & 0x00000090) != 0x90) || ((insn & 0x0e000000) == (1 << 25))) { @@ -10270,13 +10249,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0x08: /* rev */ case 0x09: /* rev16 */ case 0x0b: /* revsh */ - case 0x18: /* clz */ break; case 0x10: /* sel */ if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { goto illegal_op; } break; + case 0x18: /* clz, in decodetree */ case 0x20: /* crc32/crc32c, in decodetree */ case 0x21: case 0x22: @@ -10309,9 +10288,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmp3); tcg_temp_free_i32(tmp2); break; - case 0x18: /* clz */ - tcg_gen_clzi_i32(tmp, tmp, 32); - break; default: g_assert_not_reached(); } @@ -10578,26 +10554,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; if (insn & (1 << 26)) { - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (!(insn & (1 << 20))) { - /* Hypervisor call (v7) */ - int imm16 = extract32(insn, 16, 4) << 12 - | extract32(insn, 0, 12); - ARCH(7); - if (IS_USER(s)) { - goto illegal_op; - } - gen_hvc(s, imm16); - } else { - /* Secure monitor call (v6+) */ - ARCH(6K); - if (IS_USER(s)) { - goto illegal_op; - } - gen_smc(s); - } + /* hvc, smc, in decodetree */ + goto illegal_op; } else { op = (insn >> 20) & 7; switch (op) { @@ -10666,35 +10624,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } break; - case 4: /* bxj */ - /* Trivial implementation equivalent to bx. - * This instruction doesn't exist at all for M-profile. - */ - if (arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - tmp = load_reg(s, rn); - gen_bx(s, tmp); - break; - case 5: /* Exception return. */ - if (IS_USER(s)) { - goto illegal_op; - } - if (rn != 14 || rd != 15) { - goto illegal_op; - } - if (s->current_el == 2) { - /* ERET from Hyp uses ELR_Hyp, not LR */ - if (insn & 0xff) { - goto illegal_op; - } - tmp = load_cpu_field(elr_el[2]); - } else { - tmp = load_reg(s, rn); - tcg_gen_subi_i32(tmp, tmp, insn & 0xff); - } - gen_exception_return(s, tmp); - break; + case 4: /* bxj, in decodetree */ + case 5: /* eret, in decodetree */ case 6: /* MRS, in decodetree */ case 7: /* MSR, in decodetree */ goto illegal_op; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 5751e615cd..32d1833037 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -29,6 +29,9 @@ &s_rrrr s rd rn rm ra &rrrr rd rn rm ra &rrr rd rn rm +&rr rd rm +&r rm +&i imm &msr_reg rn r mask &mrs_reg rd r &msr_bank rn r sysm @@ -194,9 +197,27 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm # Miscellaneous instructions %sysm 8:1 16:4 +%imm16_8_0 8:12 0:4 + +@rm ---- .... .... .... .... .... .... rm:4 &r +@rdm ---- .... .... .... rd:4 .... .... rm:4 &rr +@i16 ---- .... .... .... .... .... .... .... &i imm=%imm16_8_0 MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm MRS_reg ---- 0001 0 r:1 00 1111 rd:4 0000 0000 0000 &mrs_reg MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg + +BX .... 0001 0010 1111 1111 1111 0001 .... @rm +BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm +BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm + +CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm + +ERET ---- 0001 0110 0000 0000 0000 0110 1110 + +HLT .... 0001 0000 .... .... .... 0111 .... @i16 +BKPT .... 0001 0010 .... .... .... 0111 .... @i16 +HVC .... 0001 0100 .... .... .... 0111 .... @i16 +SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 30971787d4..abd233180d 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,9 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&rr !extern rd rm +&r !extern rm +&i !extern imm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -125,6 +128,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot @rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr @rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0 @rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr +@rdm .... .... .... .... .... rd:4 .... rm:4 &rr { MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm @@ -179,10 +183,15 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm +# Ignore Rn, as allowed by constrained unpredictable. +# This matches the behaviour of the legacy decoder. +CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm + # Branches and miscellaneous control %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 +%imm16_16_0 16:4 0:12 { { @@ -211,4 +220,15 @@ CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for + # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + &s_rri_rot rot=0 s=1 rd=15 rn=14 + } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ + &i imm=%imm16_16_0 } From patchwork Fri Jul 26 17:49:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169878 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp356278ilk; Fri, 26 Jul 2019 10:53:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqwS/uhwyili8kIKG4/Lq3Mhy50y4gWTT+1WD612yX3B/fmeWhGHm7dP8KPeiOyJ12u0H9Jn X-Received: by 2002:aed:3461:: with SMTP id w88mr67815813qtd.13.1564163635272; Fri, 26 Jul 2019 10:53:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163635; cv=none; d=google.com; s=arc-20160816; b=tul/0GwDR49BOhPwtQn8D5ZCBUSDcgY/PaJv2S77UCJra1htcZAoXRoN9H8oL+W8SW OjlBtF+fCOpIQzIPcUN2KpDF+cE5DFpQ2/BZvL3kdH9+Nb4p2Ge+9AoBpwzw9yyaBCWR 8SoI65niwONnr+aKN7P4Rh/a7eX/06gQ72iHLeJNnGgiRVZX1lVEfJV4X1AbH/rLY1AY qsH6e1n5LaUDpfwjMiUSP3lTKKPGeNkRNlSv0jIStM9MEYfpFM9uhoRyBJ3yVaDp91Gl 44S6yYxayBNHYX/osxGcmj32Fnh+MKMexshVqs3miEZkXIuw26peC2O0Ns3rOFHJQqJ6 tmKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ukXEAQeVlVRr0NDtltS3ky/umJGI1MT5scY2efu29x8=; b=bMeRoT+EfRmmCJ5yp47L645TpL3MbIGCQHGDdniAcKHWEr8/Kf1vV0qWiUcUgoevbk AdkSxrrecfyK+ZkXRDOStRBbOgWcaGUze5MguTakvBjQpfCaExpS0v972vhReLzjSE7n TfchvJIxzkIpDKlRKssCYRh+PSAV1j05pqZ76GcGSAIaW/C6DDHgGYxsug00ydGigBdm 22/ynStypnz1px57q54HeigLi4f5eke8IwNnFfnIGwoUaeYH95rx/6i/DyDXyVSu8Tbt F9VtlLqKLK7CS6JA05ogmxvSlY4kCA5btYozK/pSMirS3SIZ4t4624IlJcZckCT2+PuB Kn2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rGfwYEjj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h28si21390564qvd.53.2019.07.26.10.53.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:53:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=rGfwYEjj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Ph-0005mZ-37 for patch@linaro.org; Fri, 26 Jul 2019 13:53:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57835) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Mx-00038w-98 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mu-00088X-2A for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:02 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:39971) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mt-00086Z-Qu for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:00 -0400 Received: by mail-pg1-x544.google.com with SMTP id w10so25118261pgj.7 for ; Fri, 26 Jul 2019 10:50:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ukXEAQeVlVRr0NDtltS3ky/umJGI1MT5scY2efu29x8=; b=rGfwYEjjH1zbSGoLAJkn1Y0CKXSSsSU6We6F5QakfoswaOEfaMrNaZ/MOXtJlSCY83 NXT7YNqwfoZ+o3ayyQJL/+X55FLA8xpHycQCUezKhoIe1BKw5qAiy6H6Y7ct6LRRSUQo vaT5TzUetA99hu5m0vG67feKLagNoji2lCMdpYjHmr2FfGJ7o6Yp4jmotB24+WyTvPMI kg6YjfWWY/pt0A4hnE8Xf+Tz/FdoCXkZ1kc2J7Nipq5FwbU6rnQAuBhzr6/rzKXMqQX7 6mhYm3YdVIl2HyoBT1mhBNgSOuGStzODjPvdMP5r9ZHD+9a8V7bxYm5o0swrkltZHVe7 RfEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ukXEAQeVlVRr0NDtltS3ky/umJGI1MT5scY2efu29x8=; b=LKTjomBDEWW26YGO8KbVC9FGqKZqGvAzg88QCr/sDji9kBukMBhxqmAjMLpbxF1Qh9 gdyAEaByJCfQHFHVt/kvn+J8RxNP/cN796q4WnTCjub2sdzt319Yj56gl32D1aJqUnzR AcGls2PSgQygdmEARptA1ifmwQMATT/OcYhs0PAJcCX5n6I143+fs6Np+MoypEGMXw7d cMmSNg3SJVmCThT7d5UdHfJCdMBwNiomewmDOk2DwqytF8LL7lXutdVFXFue91ZOE3JP 2sFQLpsETaakP9aAJ+1v2t98sde59uq9Y4MPPArs17BPi8DXaKJ/jvouis6K2SWueUnr PkLg== X-Gm-Message-State: APjAAAXGC07t+0P2b4Yx7cOol6vr19gX7mbcKrPO2nvkXMxNAU95ZQzq YUOjSW0pBCuBfOqXNMD/DQmrEQoUM2M= X-Received: by 2002:a63:36cc:: with SMTP id d195mr51512589pga.157.1564163458590; Fri, 26 Jul 2019 10:50:58 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.57 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:46 -0700 Message-Id: <20190726175032.6769-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 24 +++++++++++++----------- target/arm/a32.decode | 1 + target/arm/t32.decode | 19 +++++++++++++++++++ 3 files changed, 33 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 09310b1c3a..d19131d594 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7683,6 +7683,11 @@ static void arm_skip_unless(DisasContext *s, uint32_t cond) * Constant expanders for the decoders. */ +static int negate(DisasContext *s, int x) +{ + return -x; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -8053,6 +8058,12 @@ static bool trans_ORN_rri(DisasContext *s, arg_s_rri_rot *a) #undef DO_ANY #undef DO_LOGIC +static bool trans_ADR(DisasContext *s, arg_ri *a) +{ + store_reg_bx(s, a->rd, add_reg_for_lit(s, 15, a->imm)); + return true; +} + /* * Multiply and multiply accumulate */ @@ -10758,17 +10769,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } store_reg(s, rd, tmp); } else { - /* Add/sub 12-bit immediate. */ - if (insn & (1 << 23)) { - imm = -imm; - } - tmp = add_reg_for_lit(s, rn, imm); - if (rn == 13 && rd == 13) { - /* ADD SP, SP, imm or SUB SP, SP, imm */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } + /* Add/sub 12-bit immediate, in decodetree */ + goto illegal_op; } } } else { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 32d1833037..baae62dea9 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -30,6 +30,7 @@ &rrrr rd rn rm ra &rrr rd rn rm &rr rd rm +&ri rd imm &r rm &i imm &msr_reg rn r mask diff --git a/target/arm/t32.decode b/target/arm/t32.decode index abd233180d..69e81ef71a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -27,6 +27,7 @@ &rrrr !extern rd rn rm ra &rrr !extern rd rn rm &rr !extern rd rm +&ri !extern rd imm &r !extern rm &i !extern imm &msr_reg !extern rn r mask @@ -121,6 +122,24 @@ SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot } RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot +# Data processing (plain binary immediate) + +%imm12_26_12_0 26:1 12:3 0:8 +%neg12_26_12_0 26:1 12:3 0:8 !function=negate +@s0_rri_12 .... ... .... . rn:4 . ... rd:4 ........ \ + &s_rri_rot imm=%imm12_26_12_0 rot=0 s=0 + +{ + ADR 1111 0.1 0000 0 1111 0 ... rd:4 ........ \ + &ri imm=%imm12_26_12_0 + ADD_rri 1111 0.1 0000 0 .... 0 ... .... ........ @s0_rri_12 +} +{ + ADR 1111 0.1 0101 0 1111 0 ... rd:4 ........ \ + &ri imm=%neg12_26_12_0 + SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 +} + # Multiply and multiply accumulate @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 From patchwork Fri Jul 26 17:49:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169896 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp360110ilk; Fri, 26 Jul 2019 10:58:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqyXwDmgUI2Mwi1fz/mIFjW2/EPYSvbjj3IZg5+MJ81wy9Tcsz6Xy/TYQa2ujFtwMKuHAx08 X-Received: by 2002:a17:906:c3d0:: with SMTP id cj16mr73534805ejb.96.1564163880509; Fri, 26 Jul 2019 10:58:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163880; cv=none; d=google.com; s=arc-20160816; b=OlrKGzuK1Ln6gwbIDYzoaZGf6Qd7fuiZd+OSBlFsF67aSxBrAhyhlUUZFhmb9y136e yhL80tRyVFp2LsFTSRXHOOp9yDQ/uCUv++nr6AOhZJ/How3X/geIfKdukg0WrKRiznuD 96T1vXobDXz0kGKyU6O95MUh/VfsjiZC6bVPp/2l+wImqvCJN67NrTNn29O+KI3IpXGT L86dAE5mRF5fRpLntv1X5z/t5hSvvIJMgAB4vqJtAVdVWJp0Zgc6hdJET9tQ60VI6vsY a5vz6Q4mOwzOTgS2ziXlwr8PoKHbaLzwXvv4Rrsi4zr2fwdrqGaVvqdslpMynf9S5buD KdqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RjoqqIeCZ/U4WjTuzNxHJM9AhqObp5hIxK8F6+VRchM=; b=JaqjGpoXfYSj4SLS0viACIPsl3xIdvzt5ijRMUkD9Qj1GEi8qo9DwzHI3Fy+uQZXyk p58symNc9mgyV6C8ppkwFjnpRVrU9xN6ZQuVQMTPYWnpce4eLRfBVIgzXGCcOaurMYre cztWgDziq4Lk0h35zOmPFirwpwAZwUDgN6B+k7s1NpP2exi2hTEW6Hk7ZaXaMi3oYg7t 1laCHqivAkzOnW737Y33whHPS30yE1EdUu+hvkfIBpxc93M+8EGu+1dvFLuTU6Vp1lZe KpG7i+LCt8xXo84x0NmZ9Khd6D32TbA9lt8RZJ7i4OXgmgl1QQ2njpG0yPMYgDsOTmsU E0kQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LKbnQn9R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l8si12819066eda.181.2019.07.26.10.58.00 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:58:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LKbnQn9R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42452 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Tc-0005i9-SC for patch@linaro.org; Fri, 26 Jul 2019 13:57:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58058) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4N2-0003b1-Uv for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4My-0008JP-0p for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:07 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:44807) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mx-0008Ci-Ms for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:03 -0400 Received: by mail-pl1-x636.google.com with SMTP id t14so24991525plr.11 for ; Fri, 26 Jul 2019 10:51:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RjoqqIeCZ/U4WjTuzNxHJM9AhqObp5hIxK8F6+VRchM=; b=LKbnQn9RKcNlcSl2fZGAIdJWPNSDp4yKZvO7rz1fn96zW6i7QYVaPTPjcSDv+vf1Qq VzNuWHOh+uXusVGJxoOVwCTSqlW0c1gW3NOeHt2zrTk2OfzQtxae2ABwvpGiDJ2W4G7W aAZ2zAFbBIFkpYpPs0ElGf6gZcJlk5GMihT7CVn+Cy/x+eCpO9i+6aI3xue6vQGMV0Ha SYuPviLi7aw+xZ1i9bzMBYkWtC5z/lcaUvrH5C9R0gyu+GA/qfHEuES0ZqPOTU69Yg2V mGqbUnb3DzX8KPTvWJMKh2fGNBZn8j3HKxNJfv/NX7JtBQTFli8IxrGLQfRMGKR2QPlz bd6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RjoqqIeCZ/U4WjTuzNxHJM9AhqObp5hIxK8F6+VRchM=; b=oUDHPrEd3UgQEaawcsh0GNNR5j1MZLjuXDeYkl8TuTy+trlASH0E9SjPFA4+xJxuSl m5OEBrnwa/tyqti0Df8jB4skhnmYUN2YdubjR4PfRHV+A0rpjrYDEaf3UesZOaO5yv37 Budz/Tvmx69AZgmkADZYpwJg8jTufVBL2Wr0ayayKIcX+mbp+YlsZI7HSPs2cuEFvNg2 +TD+gYF4FGVJKIFggFdeNIWXECnV9VGIM8ExIjYz8m5p82Z8oMk66MtDd8mctv21hDWY M7DetCa80b9cqv2lUQWUcF2hSayBTVySgF0yTcl2CHC/Jlviumav5nt9AgOHxyDRrDWL tBpw== X-Gm-Message-State: APjAAAWYW3GzppyJaVplTCWEIm0JxDkK0zv/aOEROq7SYIzhh2hWjwsE TlTYYhURZIqLVR/gd0HEV9qn4G3+7+Q= X-Received: by 2002:a17:902:e703:: with SMTP id co3mr1093210plb.119.1564163459852; Fri, 26 Jul 2019 10:50:59 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.50.58 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:50:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:47 -0700 Message-Id: <20190726175032.6769-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::636 Subject: [Qemu-devel] [PATCH 22/67] target/arm: Convert load/store (register, immediate, literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 793 ++++++++++++++++++----------------------- target/arm/a32.decode | 120 +++++++ target/arm/t32.decode | 141 ++++++++ 3 files changed, 611 insertions(+), 443 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index d19131d594..73cb624ebd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1293,62 +1293,6 @@ static inline void gen_hlt(DisasContext *s, int imm) gen_illegal_op(s); } -static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, - TCGv_i32 var) -{ - int val, rm, shift, shiftop; - TCGv_i32 offset; - - if (!(insn & (1 << 25))) { - /* immediate */ - val = insn & 0xfff; - if (!(insn & (1 << 23))) - val = -val; - if (val != 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* shift/register */ - rm = (insn) & 0xf; - shift = (insn >> 7) & 0x1f; - shiftop = (insn >> 5) & 3; - offset = load_reg(s, rm); - gen_arm_shift_im(offset, shiftop, shift, 0); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - -static inline void gen_add_datah_offset(DisasContext *s, unsigned int insn, - int extra, TCGv_i32 var) -{ - int val, rm; - TCGv_i32 offset; - - if (insn & (1 << 22)) { - /* immediate */ - val = (insn & 0xf) | ((insn >> 4) & 0xf0); - if (!(insn & (1 << 23))) - val = -val; - val += extra; - if (val != 0) - tcg_gen_addi_i32(var, var, val); - } else { - /* register */ - if (extra) - tcg_gen_addi_i32(var, var, extra); - rm = (insn) & 0xf; - offset = load_reg(s, rm); - if (!(insn & (1 << 23))) - tcg_gen_sub_i32(var, var, offset); - else - tcg_gen_add_i32(var, var, offset); - tcg_temp_free_i32(offset); - } -} - static TCGv_ptr get_fpstatus_ptr(int neon) { TCGv_ptr statusptr = tcg_temp_new_ptr(); @@ -7693,6 +7637,11 @@ static int times_2(DisasContext *s, int x) return x * 2; } +static int times_4(DisasContext *s, int x) +{ + return x * 4; +} + /* Return only the rotation part of T32ExpandImm. */ static int t32_expandimm_rot(DisasContext *s, int x) { @@ -8606,6 +8555,341 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } +/* + * Load/store register index + */ + +static ISSInfo make_issinfo(DisasContext *s, int rd, bool p, bool w) +{ + ISSInfo ret; + + /* ISS not valid if writeback */ + if (p & !w) { + ret = rd; + } else { + ret = ISSInvalid; + } + return ret; +} + +static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a) +{ + TCGv_i32 addr = load_reg(s, a->rn); + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + if (a->p) { + TCGv_i32 ofs = load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } + return addr; +} + +static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + TCGv_i32 ofs = load_reg(s, a->rm); + gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); + if (a->u) { + tcg_gen_add_i32(addr, addr, ofs); + } else { + tcg_gen_sub_i32(addr, addr, ofs); + } + tcg_temp_free_i32(ofs); + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_rr(DisasContext *s, arg_ldst_rr *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr = op_addr_rr_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure correct behavior with overlapping index registers. + */ + op_addr_rr_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_rr(DisasContext *s, arg_ldst_rr *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr = op_addr_rr_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, 0); + return true; +} + +static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + addr = op_addr_rr_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt + 1, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_rr_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + addr = op_addr_rr_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = load_reg(s, a->rt + 1); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_rr_post(s, a, addr, -4); + return true; +} + +/* + * Load/store immediate index + */ + +static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a) +{ + int ofs = a->imm; + + if (!a->u) { + ofs = -ofs; + } + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + /* + * Stackcheck. Here we know 'addr' is the current SP; + * U is set if we're moving SP up, else down. It is + * UNKNOWN whether the limit check triggers when SP starts + * below the limit and ends up above it; we chose to do so. + */ + if (!a->u) { + TCGv_i32 newsp = tcg_temp_new_i32(); + tcg_gen_addi_i32(newsp, cpu_R[13], ofs); + gen_helper_v8m_stackcheck(cpu_env, newsp); + tcg_temp_free_i32(newsp); + } else { + gen_helper_v8m_stackcheck(cpu_env, cpu_R[13]); + } + } + + return add_reg_for_lit(s, a->rn, a->p ? ofs : 0); +} + +static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a, + TCGv_i32 addr, int address_offset) +{ + if (!a->p) { + address_offset += (a->u ? a->imm : -a->imm); + } else if (!a->w) { + tcg_temp_free_i32(addr); + return; + } + tcg_gen_addi_i32(addr, addr, address_offset); + store_reg(s, a->rn, addr); +} + +static bool op_load_ri(DisasContext *s, arg_ldst_ri *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w); + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + + /* + * Perform base writeback before the loaded value to + * ensure coriect behavior with overlapping index registers. + */ + op_addr_ri_post(s, a, addr, 0); + store_reg_from_load(s, a->rt, tmp); + return true; +} + +static bool op_store_ri(DisasContext *s, arg_ldst_ri *a, + TCGMemOp mop, int mem_idx) +{ + ISSInfo issinfo = make_issinfo(s, a->rt, a->p, a->w) | ISSIsWrite; + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data); + disas_set_da_iss(s, mop, issinfo); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, 0); + return true; +} + +static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, a->rt, tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + store_reg(s, rt2, tmp); + + /* LDRD w/ base writeback is undefined if the registers overlap. */ + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_LDRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_ldrd_ri(s, a, a->rt + 1); +} + +static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b = { + .u = a->u, .w = a->w, .p = a->p, + .rn = a->rn, .rt = a->rt, .imm = a->imm + }; + return op_ldrd_ri(s, &b, a->rt2); +} + +static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2) +{ + int mem_idx = get_mem_index(s); + TCGv_i32 addr, tmp; + + addr = op_addr_ri_pre(s, a); + + tmp = load_reg(s, a->rt); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + tcg_gen_addi_i32(addr, addr, 4); + + tmp = load_reg(s, rt2); + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data); + tcg_temp_free_i32(tmp); + + op_addr_ri_post(s, a, addr, -4); + return true; +} + +static bool trans_STRD_ri_a32(DisasContext *s, arg_ldst_ri *a) +{ + if (!ENABLE_ARCH_5TE || (a->rt & 1)) { + return false; + } + return op_strd_ri(s, a, a->rt + 1); +} + +static bool trans_STRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a) +{ + arg_ldst_ri b = { + .u = a->u, .w = a->w, .p = a->p, + .rn = a->rn, .rt = a->rt, .imm = a->imm + }; + return op_strd_ri(s, &b, a->rt2); +} + +#define DO_LDST(NAME, WHICH, MEMOP) \ +static bool trans_##NAME##_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_ri(DisasContext *s, arg_ldst_ri *a) \ +{ \ + return op_##WHICH##_ri(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} \ +static bool trans_##NAME##_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_mem_index(s)); \ +} \ +static bool trans_##NAME##T_rr(DisasContext *s, arg_ldst_rr *a) \ +{ \ + return op_##WHICH##_rr(s, a, MEMOP, get_a32_user_mem_index(s)); \ +} + +DO_LDST(LDR, load, MO_UL) +DO_LDST(LDRB, load, MO_UB) +DO_LDST(LDRH, load, MO_UW) +DO_LDST(LDRSB, load, MO_SB) +DO_LDST(LDRSH, load, MO_SW) + +DO_LDST(STR, store, MO_UL) +DO_LDST(STRB, store, MO_UB) +DO_LDST(STRH, store, MO_UW) + +#undef DO_LDST + /* * Legacy decoder. */ @@ -9060,100 +9344,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } } } else { - int address_offset; - bool load = insn & (1 << 20); - bool wbit = insn & (1 << 21); - bool pbit = insn & (1 << 24); - bool doubleword = false; - ISSInfo issinfo; - - /* Misc load/store */ - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - - /* ISS not valid if writeback */ - issinfo = (pbit & !wbit) ? rd : ISSInvalid; - - if (!load && (sh & 2)) { - /* doubleword */ - ARCH(5TE); - if (rd & 1) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - load = (sh & 1) == 0; - doubleword = true; - } - - addr = load_reg(s, rn); - if (pbit) { - gen_add_datah_offset(s, insn, 0, addr); - } - address_offset = 0; - - if (doubleword) { - if (!load) { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = load_reg(s, rd + 1); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } else { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - rd++; - } - address_offset = -4; - } else if (load) { - /* load */ - tmp = tcg_temp_new_i32(); - switch (sh) { - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - case 2: - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - default: - case 3: - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), - issinfo); - break; - } - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), issinfo); - tcg_temp_free_i32(tmp); - } - /* Perform base writeback before the loaded value to - ensure correct behavior with overlapping index registers. - ldrd with base writeback is undefined if the - destination and index registers overlap. */ - if (!pbit) { - gen_add_datah_offset(s, insn, address_offset, addr); - store_reg(s, rn, addr); - } else if (wbit) { - if (address_offset) - tcg_gen_addi_i32(addr, addr, address_offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (load) { - /* Complete the load. */ - store_reg(s, rd, tmp); - } + /* Extra load/store (register) instructions */ + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; } break; case 0x4: @@ -9461,58 +9654,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) break; } do_ldst: - /* Check for undefined extension instructions - * per the ARM Bible IE: - * xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx - */ - sh = (0xf << 20) | (0xf << 4); - if (op1 == 0x7 && ((insn & sh) == sh)) - { - goto illegal_op; - } - /* load/store byte/word */ - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - tmp2 = load_reg(s, rn); - if ((insn & 0x01200000) == 0x00200000) { - /* ldrt/strt */ - i = get_a32_user_mem_index(s); - } else { - i = get_mem_index(s); - } - if (insn & (1 << 24)) - gen_add_data_offset(s, insn, tmp2); - if (insn & (1 << 20)) { - /* load */ - tmp = tcg_temp_new_i32(); - if (insn & (1 << 22)) { - gen_aa32_ld8u_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_ld32u_iss(s, tmp, tmp2, i, rd); - } - } else { - /* store */ - tmp = load_reg(s, rd); - if (insn & (1 << 22)) { - gen_aa32_st8_iss(s, tmp, tmp2, i, rd); - } else { - gen_aa32_st32_iss(s, tmp, tmp2, i, rd); - } - tcg_temp_free_i32(tmp); - } - if (!(insn & (1 << 24))) { - gen_add_data_offset(s, insn, tmp2); - store_reg(s, rn, tmp2); - } else if (insn & (1 << 21)) { - store_reg(s, rn, tmp2); - } else { - tcg_temp_free_i32(tmp2); - } - if (insn & (1 << 20)) { - /* Complete the load. */ - store_reg_from_load(s, rd, tmp); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0x08: case 0x09: { @@ -9814,75 +9957,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) s->condexec_mask = 0; } } else if (insn & 0x01200000) { - /* 0b1110_1000_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (post-indexed) - * 0b1111_1001_x10x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (literal and immediate) - * 0b1111_1001_x11x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store dual (pre-indexed) - */ - bool wback = extract32(insn, 21, 1); - - if (rn == 15 && (insn & (1 << 21))) { - /* UNPREDICTABLE */ - goto illegal_op; - } - - addr = add_reg_for_lit(s, rn, 0); - offset = (insn & 0xff) * 4; - if ((insn & (1 << 23)) == 0) { - offset = -offset; - } - - if (s->v8m_stackcheck && rn == 13 && wback) { - /* - * Here 'addr' is the current SP; if offset is +ve we're - * moving SP up, else down. It is UNKNOWN whether the limit - * check triggers when SP starts below the limit and ends - * up above it; check whichever of the current and final - * SP is lower, so QEMU will trigger in that situation. - */ - if ((int32_t)offset < 0) { - TCGv_i32 newsp = tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, offset); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, offset); - offset = 0; - } - if (insn & (1 << 20)) { - /* ldrd */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rs, tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* strd */ - tmp = load_reg(s, rs); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - tcg_gen_addi_i32(addr, addr, 4); - tmp = load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - if (wback) { - /* Base writeback. */ - tcg_gen_addi_i32(addr, addr, offset - 4); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* load/store dual, in decodetree */ + goto illegal_op; } else if ((insn & (1 << 23)) == 0) { /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx * - load/store exclusive word @@ -10780,184 +10856,15 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } break; - case 12: /* Load/store single data item. */ - { - int postinc = 0; - int writeback = 0; - int memidx; - ISSInfo issinfo; - + case 12: if ((insn & 0x01100000) == 0x01000000) { if (disas_neon_ls_insn(s, insn)) { goto illegal_op; } break; } - op = ((insn >> 21) & 3) | ((insn >> 22) & 4); - if (rs == 15) { - if (!(insn & (1 << 20))) { - goto illegal_op; - } - if (op != 2) { - /* Byte or halfword load space with dest == r15 : memory hints. - * Catch them early so we don't emit pointless addressing code. - * This space is a mix of: - * PLD/PLDW/PLI, which we implement as NOPs (note that unlike - * the ARM encodings, PLDW space doesn't UNDEF for non-v7MP - * cores) - * unallocated hints, which must be treated as NOPs - * UNPREDICTABLE space, which we NOP or UNDEF depending on - * which is easiest for the decoding logic - * Some space which must UNDEF - */ - int op1 = (insn >> 23) & 3; - int op2 = (insn >> 6) & 0x3f; - if (op & 2) { - goto illegal_op; - } - if (rn == 15) { - /* UNPREDICTABLE, unallocated hint or - * PLD/PLDW/PLI (literal) - */ - return; - } - if (op1 & 1) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - if ((op2 == 0) || ((op2 & 0x3c) == 0x30)) { - return; /* PLD/PLDW/PLI or unallocated hint */ - } - /* UNDEF space, or an UNPREDICTABLE */ - goto illegal_op; - } - } - memidx = get_mem_index(s); - imm = insn & 0xfff; - if (insn & (1 << 23)) { - /* PC relative or Positive offset. */ - addr = add_reg_for_lit(s, rn, imm); - } else if (rn == 15) { - /* PC relative with negative offset. */ - addr = add_reg_for_lit(s, rn, -imm); - } else { - addr = load_reg(s, rn); - imm = insn & 0xff; - switch ((insn >> 8) & 0xf) { - case 0x0: /* Shifted Register. */ - shift = (insn >> 4) & 0xf; - if (shift > 3) { - tcg_temp_free_i32(addr); - goto illegal_op; - } - tmp = load_reg(s, rm); - tcg_gen_shli_i32(tmp, tmp, shift); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - break; - case 0xc: /* Negative offset. */ - tcg_gen_addi_i32(addr, addr, -imm); - break; - case 0xe: /* User privilege. */ - tcg_gen_addi_i32(addr, addr, imm); - memidx = get_a32_user_mem_index(s); - break; - case 0x9: /* Post-decrement. */ - imm = -imm; - /* Fall through. */ - case 0xb: /* Post-increment. */ - postinc = 1; - writeback = 1; - break; - case 0xd: /* Pre-decrement. */ - imm = -imm; - /* Fall through. */ - case 0xf: /* Pre-increment. */ - writeback = 1; - break; - default: - tcg_temp_free_i32(addr); - goto illegal_op; - } - } - - issinfo = writeback ? ISSInvalid : rs; - - if (s->v8m_stackcheck && rn == 13 && writeback) { - /* - * Stackcheck. Here we know 'addr' is the current SP; - * if imm is +ve we're moving SP up, else down. It is - * UNKNOWN whether the limit check triggers when SP starts - * below the limit and ends up above it; we chose to do so. - */ - if ((int32_t)imm < 0) { - TCGv_i32 newsp = tcg_temp_new_i32(); - - tcg_gen_addi_i32(newsp, addr, imm); - gen_helper_v8m_stackcheck(cpu_env, newsp); - tcg_temp_free_i32(newsp); - } else { - gen_helper_v8m_stackcheck(cpu_env, addr); - } - } - - if (writeback && !postinc) { - tcg_gen_addi_i32(addr, addr, imm); - } - - if (insn & (1 << 20)) { - /* Load. */ - tmp = tcg_temp_new_i32(); - switch (op) { - case 0: - gen_aa32_ld8u_iss(s, tmp, addr, memidx, issinfo); - break; - case 4: - gen_aa32_ld8s_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_ld16u_iss(s, tmp, addr, memidx, issinfo); - break; - case 5: - gen_aa32_ld16s_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_ld32u_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - store_reg_from_load(s, rs, tmp); - } else { - /* Store. */ - tmp = load_reg(s, rs); - switch (op) { - case 0: - gen_aa32_st8_iss(s, tmp, addr, memidx, issinfo); - break; - case 1: - gen_aa32_st16_iss(s, tmp, addr, memidx, issinfo); - break; - case 2: - gen_aa32_st32_iss(s, tmp, addr, memidx, issinfo); - break; - default: - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(addr); - goto illegal_op; - } - tcg_temp_free_i32(tmp); - } - if (postinc) - tcg_gen_addi_i32(addr, addr, imm); - if (writeback) { - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - } - break; + /* Load/store single data item, in decodetree */ + goto illegal_op; default: goto illegal_op; } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index baae62dea9..9789042ca0 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -37,6 +37,8 @@ &mrs_reg rd r &msr_bank rn r sysm &mrs_bank rd r sysm +&ldst_rr p w u rn rt rm shimm shtype +&ldst_ri p w u rn rt imm # Data-processing (register) @@ -222,3 +224,121 @@ HLT .... 0001 0000 .... .... .... 0111 .... @i16 BKPT .... 0001 0010 .... .... .... 0111 .... @i16 HVC .... 0001 0100 .... .... .... 0111 .... @i16 SMC ---- 0001 0110 0000 0000 0000 0111 imm:4 &i + +# Load/Store Dual, Half, Signed Byte (register) + +@ldst_rr_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=1 shimm=0 shtype=0 +@ldst_rr_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=0 w=0 shimm=0 shtype=0 + +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_pw0 +STRH_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRD_rr .... 000. .0.0 .... .... 0000 1101 .... @ldst_rr_p1w + +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_pw0 +STRD_rr .... 000. .0.0 .... .... 0000 1111 .... @ldst_rr_p1w + +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_pw0 +LDRH_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p1w + +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_pw0 +LDRSB_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p1w + +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_pw0 +LDRSH_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p1w + +# Note the unpriv load/stores use the previously invalid P=0, W=1 encoding, +# and act as normal post-indexed (P=0, W=0). +@ldst_rr_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... rm:4 \ + &ldst_rr p=0 w=0 shimm=0 shtype=0 + +STRHT_rr .... 000. .0.0 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRHT_rr .... 000. .0.1 .... .... 0000 1011 .... @ldst_rr_p0w1 +LDRSBT_rr .... 000. .0.1 .... .... 0000 1101 .... @ldst_rr_p0w1 +LDRSHT_rr .... 000. .0.1 .... .... 0000 1111 .... @ldst_rr_p0w1 + +# Load/Store word and unsigned byte (register) + +@ldst_rs_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=1 +@ldst_rs_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=0 w=0 + +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_pw0 +STR_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p1w +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_pw0 +STRB_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p1w + +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDR_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p1w +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_pw0 +LDRB_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p1w + +@ldst_rs_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 shimm:5 shtype:2 . rm:4 \ + &ldst_rr p=0 w=0 + +STRT_rr .... 011. .0.0 .... .... .... ...0 .... @ldst_rs_p0w1 +STRBT_rr .... 011. .1.0 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRT_rr .... 011. .0.1 .... .... .... ...0 .... @ldst_rs_p0w1 +LDRBT_rr .... 011. .1.1 .... .... .... ...0 .... @ldst_rs_p0w1 + +# Load/Store Dual, Half, Signed Byte (immediate) + +%imm8s_8_0 8:4 0:4 +@ldst_ri8_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=%imm8s_8_0 p=1 +@ldst_ri8_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=%imm8s_8_0 p=0 w=0 + +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_pw0 +STRH_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRD_ri_a32 .... 000. .1.0 .... .... .... 1101 .... @ldst_ri8_p1w + +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_pw0 +STRD_ri_a32 .... 000. .1.0 .... .... .... 1111 .... @ldst_ri8_p1w + +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_pw0 +LDRH_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p1w + +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_pw0 +LDRSB_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p1w + +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_pw0 +LDRSH_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p1w + +# Note the unpriv load/stores use the previously invalid P=0, W=1 encoding, +# and act as normal post-indexed (P=0, W=0). +@ldst_ri8_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 .... .... .... \ + &ldst_ri imm=%imm8s_8_0 p=0 w=0 + +STRHT_ri .... 000. .1.0 .... .... .... 1011 .... @ldst_ri8_p0w1 +LDRHT_ri .... 000. .1.1 .... .... .... 1011 .... @ldst_ri8_p0w1 +LDRSBT_ri .... 000. .1.1 .... .... .... 1101 .... @ldst_ri8_p0w1 +LDRSHT_ri .... 000. .1.1 .... .... .... 1111 .... @ldst_ri8_p0w1 + +# Load/Store word and unsigned byte (immediate) + +@ldst_ri12_p1w ---- ...1 u:1 . w:1 . rn:4 rt:4 imm:12 &ldst_ri p=1 +@ldst_ri12_pw0 ---- ...0 u:1 . 0 . rn:4 rt:4 imm:12 &ldst_ri p=0 w=0 + +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p1w +STR_ri .... 010. .0.0 .... .... ............ @ldst_ri12_pw0 +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p1w +STRB_ri .... 010. .1.0 .... .... ............ @ldst_ri12_pw0 + +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p1w +LDR_ri .... 010. .0.1 .... .... ............ @ldst_ri12_pw0 +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p1w +LDRB_ri .... 010. .1.1 .... .... ............ @ldst_ri12_pw0 + +@ldst_ri12_p0w1 ---- ...0 u:1 . 1 . rn:4 rt:4 imm:12 &ldst_ri p=0 w=0 + +STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p0w1 +STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p0w1 +LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p0w1 +LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p0w1 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 69e81ef71a..0d379ed0d9 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -34,6 +34,8 @@ &mrs_reg !extern rd r &msr_bank !extern rn r sysm &mrs_bank !extern rd r sysm +&ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm # Data-processing (register-shifted register) @@ -251,3 +253,142 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 } + +# Load/store (register, immediate, literal) + +@ldst_rr .... .... .... rn:4 rt:4 ...... shimm:2 rm:4 \ + &ldst_rr p=1 w=0 u=1 shtype=0 +@ldst_ri_idx .... .... .... rn:4 rt:4 . p:1 u:1 . imm:8 \ + &ldst_ri w=1 +@ldst_ri_neg .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=1 w=0 u=0 +@ldst_ri_unp .... .... .... rn:4 rt:4 .... imm:8 \ + &ldst_ri p=1 w=0 u=1 +@ldst_ri_pos .... .... .... rn:4 rt:4 imm:12 \ + &ldst_ri p=1 w=0 u=1 +@ldst_ri_lit .... .... u:1 ... .... rt:4 imm:12 \ + &ldst_ri p=1 w=0 rn=15 + +STRB_rr 1111 1000 0000 .... .... 000000 .. .... @ldst_rr +STRB_ri 1111 1000 0000 .... .... 1..1 ........ @ldst_ri_idx +STRB_ri 1111 1000 0000 .... .... 1100 ........ @ldst_ri_neg +STRBT_ri 1111 1000 0000 .... .... 1110 ........ @ldst_ri_unp +STRB_ri 1111 1000 1000 .... .... ............ @ldst_ri_pos + +STRH_rr 1111 1000 0010 .... .... 000000 .. .... @ldst_rr +STRH_ri 1111 1000 0010 .... .... 1..1 ........ @ldst_ri_idx +STRH_ri 1111 1000 0010 .... .... 1100 ........ @ldst_ri_neg +STRHT_ri 1111 1000 0010 .... .... 1110 ........ @ldst_ri_unp +STRH_ri 1111 1000 1010 .... .... ............ @ldst_ri_pos + +STR_rr 1111 1000 0100 .... .... 000000 .. .... @ldst_rr +STR_ri 1111 1000 0100 .... .... 1..1 ........ @ldst_ri_idx +STR_ri 1111 1000 0100 .... .... 1100 ........ @ldst_ri_neg +STRT_ri 1111 1000 0100 .... .... 1110 ........ @ldst_ri_unp +STR_ri 1111 1000 1100 .... .... ............ @ldst_ri_pos + +# Note that Load, unsigned (literal) overlaps all other load encodings. +{ + { + NOP 1111 1000 -001 1111 1111 ------------ # PLD + LDRB_ri 1111 1000 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1001 ---- 1111 ------------ # PLD + LDRB_ri 1111 1000 1001 .... .... ............ @ldst_ri_pos + } + LDRB_ri 1111 1000 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0001 ---- 1111 1100 -------- # PLD + LDRB_ri 1111 1000 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRBT_ri 1111 1000 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0001 ---- 1111 000000 -- ---- # PLD + LDRB_rr 1111 1000 0001 .... .... 000000 .. .... @ldst_rr + } +} +{ + { + NOP 1111 1000 -011 1111 1111 ------------ # PLD + LDRH_ri 1111 1000 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1000 1011 ---- 1111 ------------ # PLDW + LDRH_ri 1111 1000 1011 .... .... ............ @ldst_ri_pos + } + LDRH_ri 1111 1000 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1000 0011 ---- 1111 1100 -------- # PLDW + LDRH_ri 1111 1000 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRHT_ri 1111 1000 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1000 0011 ---- 1111 000000 -- ---- # PLDW + LDRH_rr 1111 1000 0011 .... .... 000000 .. .... @ldst_rr + } +} +{ + LDR_ri 1111 1000 .101 1111 .... ............ @ldst_ri_lit + LDR_ri 1111 1000 1101 .... .... ............ @ldst_ri_pos + LDR_ri 1111 1000 0101 .... .... 1..1 ........ @ldst_ri_idx + LDR_ri 1111 1000 0101 .... .... 1100 ........ @ldst_ri_neg + LDRT_ri 1111 1000 0101 .... .... 1110 ........ @ldst_ri_unp + LDR_rr 1111 1000 0101 .... .... 000000 .. .... @ldst_rr +} +# NOPs here are PLI. +{ + { + NOP 1111 1001 -001 1111 1111 ------------ + LDRSB_ri 1111 1001 .001 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1001 ---- 1111 ------------ + LDRSB_ri 1111 1001 1001 .... .... ............ @ldst_ri_pos + } + LDRSB_ri 1111 1001 0001 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0001 ---- 1111 1100 -------- + LDRSB_ri 1111 1001 0001 .... .... 1100 ........ @ldst_ri_neg + } + LDRSBT_ri 1111 1001 0001 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0001 ---- 1111 000000 -- ---- + LDRSB_rr 1111 1001 0001 .... .... 000000 .. .... @ldst_rr + } +} +# NOPs here are unallocated memory hints, treated as NOP. +{ + { + NOP 1111 1001 -011 1111 1111 ------------ + LDRSH_ri 1111 1001 .011 1111 .... ............ @ldst_ri_lit + } + { + NOP 1111 1001 1011 ---- 1111 ------------ + LDRSH_ri 1111 1001 1011 .... .... ............ @ldst_ri_pos + } + LDRSH_ri 1111 1001 0011 .... .... 1..1 ........ @ldst_ri_idx + { + NOP 1111 1001 0011 ---- 1111 1100 -------- + LDRSH_ri 1111 1001 0011 .... .... 1100 ........ @ldst_ri_neg + } + LDRSHT_ri 1111 1001 0011 .... .... 1110 ........ @ldst_ri_unp + { + NOP 1111 1001 0011 ---- 1111 000000 -- ---- + LDRSH_rr 1111 1001 0011 .... .... 000000 .. .... @ldst_rr + } +} + +%imm8x4 0:8 !function=times_4 +&ldst_ri2 p w u rn rt rt2 imm +@ldstd_ri8 .... .... u:1 ... rn:4 rt:4 rt2:4 ........ \ + &ldst_ri2 imm=%imm8x4 + +STRD_ri_t32 1110 1000 .110 .... .... .... ........ @ldstd_ri8 w=1 p=0 +LDRD_ri_t32 1110 1000 .111 .... .... .... ........ @ldstd_ri8 w=1 p=0 + +STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=0 p=1 +LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 + +STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 +LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 From patchwork Fri Jul 26 17:49:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169884 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp357663ilk; Fri, 26 Jul 2019 10:55:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqzn6uHG1nSgARpey5rgX/lRihQlVUDmi7abx+Dowi2tgFrIBDmoZ1U2ACNj0tiCafFQCTxB X-Received: by 2002:a05:6402:14d4:: with SMTP id f20mr81897768edx.125.1564163722155; Fri, 26 Jul 2019 10:55:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163722; cv=none; d=google.com; s=arc-20160816; b=uNjO1W6tVuIFso4swI6kbyyIOnv/vproLNPn2Tnaht9Jr2WFNxPEziiWRAxNwEpyF8 2WseZ8uCNKnESb9Q18C5U67q11Fe9lNu+KTReiHJojhgeI3qjHodEBiEzHpWAr9fmkbX ll0kXFLgOF0tXs8hx1k5PJEgKj36ax50AHbet3ky3xwj3OHqtoskVyborCB45q+1Dv6i v9U75bKsm6L6g1854CimVsDkZNZlTjXPmn3Yv8PBy/lZFdP+3+MhS8F+rWeJOVcs/ZmK PUO+0FZi5YOxscFs7BqoKFqozYqYlSTV2+3tfUmNDTLoA0FtQ0zr4ZoB1m/IeT3J4y0v osgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=UQ07c4ep2Pcf/e+Y3eYe2vH+RAjRFAYTFfhUhpRt/AQ=; b=VSBYxREhr7mQNNGRjMaGf08eLMYvOHzPyF1CbP42sam/CZsRo/cvYxgySFQ/vfZMHm O7LuBN2Pchem9FZlPpqEOmeTdbU9adYaUo1ZEIhos0ApUvHbhHm6na5COpKipUEiBhc3 +kCY9C1C3su8IzzC1oS62LUNOfIRhlHkwiZ4+XDz0mtaMeK4TgJNeyGdWhIgIj3XFahx inmbGJXrq1vxmtrAQDrAdylN0NQhAEuFQC425PRzgcmIQcs3n8NM/c0/89FRDQuNMiYL 5q1cvURBcbhd3yKsU93xMB9uREtiBidVRvHHhPfzHIuPUnujSnI8gpJXjdGZ8bIKwQYY /jiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=w0w6krZ0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k27si13258803edb.284.2019.07.26.10.55.21 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:55:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=w0w6krZ0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42366 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4R3-0004EX-GX for patch@linaro.org; Fri, 26 Jul 2019 13:55:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57960) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4N0-0003QQ-CF for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mw-0008Fn-Pw for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:06 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:46755) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mw-0008EN-Fu for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:02 -0400 Received: by mail-pl1-x642.google.com with SMTP id c2so24992705plz.13 for ; Fri, 26 Jul 2019 10:51:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UQ07c4ep2Pcf/e+Y3eYe2vH+RAjRFAYTFfhUhpRt/AQ=; b=w0w6krZ0XFNimoa4tsqekOt61XoTXIyXXy21HpBq+A2hST4ENC8fLgpJMNAXjiE1hD p9xQLUfXOQ45KE04NiCiWW1IQIOQ/2LnSv9MuJFCcqIQSOiQI7miDuXecMo/z3ylAT8z oRF0OCesIyhP8GhinVT2tjUYclunUlG3XymPuZ/dhtVQhzGplEkKkHszPYtZt55/MPKi CQG3M8jT74DbTa++vaRW206xXwZv0cb6Baa/8NP84zRnCBSjYIyshezo8nVvrvo1XE1O ULaggsk/8j5ShP0lcY6U9hy04hHQDNxIO7R28Ez2+GCtLR3cAzbhpRFqaxpP03HHr/DK dXbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UQ07c4ep2Pcf/e+Y3eYe2vH+RAjRFAYTFfhUhpRt/AQ=; b=L+HGpMGXsUJttOBvjOX0NurnYC5zk53JXP7n8rO2npFNnvYGal8spaLpxnPyYbINgj NQjtv1TbHVBT/r6GXyN8Ud/hGg/oH+C8nlZQFHzxol+4lRwAyJ81j+m0H6SudL51zKN/ lhKYYCytdJpCxLwrxj5eZ1zw1kSrU9wJQ1zWiweof0an3DHqwOesiABU2p8rcEI+0L4g DW3ZJRMsk0J3wWspWZxI2dIk1SLWHzY5iyvy8nY/ispg6kijAEo6weosFdTkmbHgf2nT XHMcFpQ4NNGwparLIWXaDEOj8jrKMI6m+DzTyZIG1NYl2LA5Vxogym1mAkHTPRDFR2sx EIXA== X-Gm-Message-State: APjAAAXHEfXdRjuyGFb00P15ZLv5I8mF8poFS0Qig8mFJZ6SiXn63rwK 3lARI+dDIKofBk/1QGEBaFEUSRnr/aE= X-Received: by 2002:a17:902:f301:: with SMTP id gb1mr95883003plb.292.1564163461023; Fri, 26 Jul 2019 10:51:01 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.00 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:48 -0700 Message-Id: <20190726175032.6769-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH 23/67] target/arm: Convert Synchronization primitives X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 560 ++++++++++++++++++++++------------------- target/arm/a32.decode | 48 ++++ target/arm/t32.decode | 46 ++++ 3 files changed, 396 insertions(+), 258 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 73cb624ebd..74e54b7efb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8890,6 +8890,302 @@ DO_LDST(STRH, store, MO_UW) #undef DO_LDST +/* + * Synchronization primitives + */ + +static bool op_swp(DisasContext *s, arg_SWP *a, TCGMemOp opc) +{ + TCGv_i32 addr, tmp; + TCGv taddr; + + opc |= s->be_data; + addr = load_reg(s, a->rn); + taddr = gen_aa32_addr(s, addr, opc); + tcg_temp_free_i32(addr); + + tmp = load_reg(s, a->rt2); + tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, get_mem_index(s), opc); + tcg_temp_free(taddr); + + store_reg(s, a->rt, tmp); + return true; +} + +static bool trans_SWP(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UL | MO_ALIGN); +} + +static bool trans_SWPB(DisasContext *s, arg_SWP *a) +{ + return op_swp(s, a, MO_UB); +} + +/* + * Load/Store Exclusive and Load-Acquire/Store-Release + */ + +static bool op_strex(DisasContext *s, arg_STREX *a, TCGMemOp mop, bool rel) +{ + TCGv_i32 addr; + + if (rel) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + } + + addr = tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_store_exclusive(s, a->rd, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STREX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_strex(s, a, MO_32, false); +} + +static bool trans_STREXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K || (a->rt & 1)) { + return false; + } + a->rt2 = a->rt + 1; + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXD_t32(DisasContext *s, arg_STREX *a) +{ + return op_strex(s, a, MO_64, false); +} + +static bool trans_STREXB(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_8, false); +} + +static bool trans_STREXH(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_strex(s, a, MO_16, false); +} + +static bool trans_STLEX(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_32, true); +} + +static bool trans_STLEXD_a32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8 || (a->rt & 1)) { + return false; + } + a->rt2 = a->rt + 1; + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXD_t32(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_64, true); +} + +static bool trans_STLEXB(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_8, true); +} + +static bool trans_STLEXH(DisasContext *s, arg_STREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_strex(s, a, MO_16, true); +} + +static bool op_stl(DisasContext *s, arg_STL *a, TCGMemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr = load_reg(s, a->rn); + + tmp = load_reg(s, a->rt); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite); + + tcg_temp_free_i32(tmp); + tcg_temp_free_i32(addr); + return true; +} + +static bool trans_STL(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UL); +} + +static bool trans_STLB(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UB); +} + +static bool trans_STLH(DisasContext *s, arg_STL *a) +{ + return op_stl(s, a, MO_UW); +} + +static bool op_ldrex(DisasContext *s, arg_LDREX *a, TCGMemOp mop, bool acq) +{ + TCGv_i32 addr; + + addr = tcg_temp_local_new_i32(); + load_reg_var(s, addr, a->rn); + tcg_gen_addi_i32(addr, addr, a->imm); + + gen_load_exclusive(s, a->rt, a->rt2, addr, mop); + tcg_temp_free_i32(addr); + + if (acq) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } + return true; +} + +static bool trans_LDREX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_ldrex(s, a, MO_32, false); +} + +static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K || (a->rt & 1)) { + return false; + } + a->rt2 = a->rt + 1; + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXD_t32(DisasContext *s, arg_LDREX *a) +{ + return op_ldrex(s, a, MO_64, false); +} + +static bool trans_LDREXB(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_8, false); +} + +static bool trans_LDREXH(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + return op_ldrex(s, a, MO_16, false); +} + +static bool trans_LDAEX(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_32, true); +} + +static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8 || (a->rt & 1)) { + return false; + } + a->rt2 = a->rt + 1; + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXD_t32(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_64, true); +} + +static bool trans_LDAEXB(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_8, true); +} + +static bool trans_LDAEXH(DisasContext *s, arg_LDREX *a) +{ + if (!ENABLE_ARCH_8) { + return false; + } + return op_ldrex(s, a, MO_16, true); +} + +static bool op_lda(DisasContext *s, arg_LDA *a, TCGMemOp mop) +{ + TCGv_i32 addr, tmp; + + if (!ENABLE_ARCH_8) { + return false; + } + addr = load_reg(s, a->rn); + + tmp = tcg_temp_new_i32(); + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data); + disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel); + tcg_temp_free_i32(addr); + + store_reg(s, a->rt, tmp); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + return true; +} + +static bool trans_LDA(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UL); +} + +static bool trans_LDAB(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UB); +} + +static bool trans_LDAH(DisasContext *s, arg_LDA *a) +{ + return op_lda(s, a, MO_UW); +} + /* * Legacy decoder. */ @@ -9182,172 +9478,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x0: case 0x1: /* multiplies, extra load/stores */ - sh = (insn >> 5) & 3; - if (sh == 0) { - if (op1 == 0x0) { - /* Multiply and multiply accumulate. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - if (insn & (1 << 23)) { - /* load/store exclusive */ - bool is_ld = extract32(insn, 20, 1); - bool is_lasr = !extract32(insn, 8, 1); - int op2 = (insn >> 8) & 3; - op1 = (insn >> 21) & 0x3; - - switch (op2) { - case 0: /* lda/stl */ - if (op1 == 1) { - goto illegal_op; - } - ARCH(8); - break; - case 1: /* reserved */ - goto illegal_op; - case 2: /* ldaex/stlex */ - ARCH(8); - break; - case 3: /* ldrex/strex */ - if (op1) { - ARCH(6K); - } else { - ARCH(6); - } - break; - } - - addr = tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - if (op2 == 0) { - if (is_ld) { - tmp = tcg_temp_new_i32(); - switch (op1) { - case 0: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 2: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - case 3: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, - get_mem_index(s), - rd | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rd, tmp); - } else { - rm = insn & 0xf; - tmp = load_reg(s, rm); - switch (op1) { - case 0: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 2: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - case 3: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, - get_mem_index(s), - rm | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - switch (op1) { - case 0: /* ldrex */ - gen_load_exclusive(s, rd, 15, addr, 2); - break; - case 1: /* ldrexd */ - gen_load_exclusive(s, rd, rd + 1, addr, 3); - break; - case 2: /* ldrexb */ - gen_load_exclusive(s, rd, 15, addr, 0); - break; - case 3: /* ldrexh */ - gen_load_exclusive(s, rd, 15, addr, 1); - break; - default: - abort(); - } - } else { - rm = insn & 0xf; - switch (op1) { - case 0: /* strex */ - gen_store_exclusive(s, rd, rm, 15, addr, 2); - break; - case 1: /* strexd */ - gen_store_exclusive(s, rd, rm, rm + 1, addr, 3); - break; - case 2: /* strexb */ - gen_store_exclusive(s, rd, rm, 15, addr, 0); - break; - case 3: /* strexh */ - gen_store_exclusive(s, rd, rm, 15, addr, 1); - break; - default: - abort(); - } - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } - } else if ((insn & 0x00300f00) == 0) { - /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx - * - SWP, SWPB - */ - - TCGv taddr; - TCGMemOp opc = s->be_data; - - rm = (insn) & 0xf; - - if (insn & (1 << 22)) { - opc |= MO_UB; - } else { - opc |= MO_UL | MO_ALIGN; - } - - addr = load_reg(s, rn); - taddr = gen_aa32_addr(s, addr, opc); - tcg_temp_free_i32(addr); - - tmp = load_reg(s, rm); - tcg_gen_atomic_xchg_i32(tmp, taddr, tmp, - get_mem_index(s), opc); - tcg_temp_free(taddr); - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - } - } else { - /* Extra load/store (register) instructions */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; break; case 0x4: case 0x5: @@ -9994,15 +10126,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } goto illegal_op; } - addr = tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - tcg_gen_addi_i32(addr, addr, (insn & 0xff) << 2); - if (insn & (1 << 20)) { - gen_load_exclusive(s, rs, 15, addr, 2); - } else { - gen_store_exclusive(s, rd, rs, 15, addr, 2); - } - tcg_temp_free_i32(addr); + /* Load/store exclusive, in decodetree */ + goto illegal_op; } else if ((insn & (7 << 5)) == 0) { /* Table Branch. */ if (rn == 15) { @@ -10029,89 +10154,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_gen_addi_i32(tmp, tmp, s->pc_read); store_reg(s, 15, tmp); } else { - bool is_lasr = false; - bool is_ld = extract32(insn, 20, 1); - int op2 = (insn >> 6) & 0x3; - op = (insn >> 4) & 0x3; - switch (op2) { - case 0: - goto illegal_op; - case 1: - /* Load/store exclusive byte/halfword/doubleword */ - if (op == 2) { - goto illegal_op; - } - ARCH(7); - break; - case 2: - /* Load-acquire/store-release */ - if (op == 3) { - goto illegal_op; - } - /* Fall through */ - case 3: - /* Load-acquire/store-release exclusive */ - ARCH(8); - is_lasr = true; - break; - } - - if (is_lasr && !is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - } - - addr = tcg_temp_local_new_i32(); - load_reg_var(s, addr, rn); - if (!(op2 & 1)) { - if (is_ld) { - tmp = tcg_temp_new_i32(); - switch (op) { - case 0: /* ldab */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 1: /* ldah */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 2: /* lda */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - store_reg(s, rs, tmp); - } else { - tmp = load_reg(s, rs); - switch (op) { - case 0: /* stlb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 1: /* stlh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - case 2: /* stl */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), - rs | ISSIsAcqRel); - break; - default: - abort(); - } - tcg_temp_free_i32(tmp); - } - } else if (is_ld) { - gen_load_exclusive(s, rs, rd, addr, op); - } else { - gen_store_exclusive(s, rm, rs, rd, addr, op); - } - tcg_temp_free_i32(addr); - - if (is_lasr && is_ld) { - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); - } + /* Load/store exclusive, load-acq/store-rel, in decodetree */ + goto illegal_op; } } else { /* Load/store multiple, RFE, SRS. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 9789042ca0..1267cebaf4 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -39,6 +39,8 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&strex rn rd rt rt2 imm +&ldrex rn rt rt2 imm # Data-processing (register) @@ -342,3 +344,49 @@ STRT_ri .... 010. .0.0 .... .... ............ @ldst_ri12_p0w1 STRBT_ri .... 010. .1.0 .... .... ............ @ldst_ri12_p0w1 LDRT_ri .... 010. .0.1 .... .... ............ @ldst_ri12_p0w1 LDRBT_ri .... 010. .1.1 .... .... ............ @ldst_ri12_p0w1 + +# Synchronization primitives + +@swp ---- .... .... rn:4 rt:4 .... .... rt2:4 + +SWP .... 0001 0000 .... .... 0000 1001 .... @swp +SWPB .... 0001 0100 .... .... 0000 1001 .... @swp + +# Load/Store Exclusive and Load-Acquire/Store-Release +# +# Note rt2 for STREXD/LDREXD is set by the helper after checking rt is even. + +@strex ---- .... .... rn:4 rd:4 .... .... rt:4 \ + &strex imm=0 rt2=15 +@ldrex ---- .... .... rn:4 rt:4 .... .... .... \ + &ldrex imm=0 rt2=15 +@stl ---- .... .... rn:4 .... .... .... rt:4 \ + &ldrex imm=0 rt2=15 + +STREX .... 0001 1000 .... .... 1111 1001 .... @strex +STREXD_a32 .... 0001 1010 .... .... 1111 1001 .... @strex +STREXB .... 0001 1100 .... .... 1111 1001 .... @strex +STREXH .... 0001 1110 .... .... 1111 1001 .... @strex + +STLEX .... 0001 1000 .... .... 1110 1001 .... @strex +STLEXD_a32 .... 0001 1010 .... .... 1110 1001 .... @strex +STLEXB .... 0001 1100 .... .... 1110 1001 .... @strex +STLEXH .... 0001 1110 .... .... 1110 1001 .... @strex + +STL .... 0001 1000 .... 1111 1100 1001 .... @stl +STLB .... 0001 1100 .... 1111 1100 1001 .... @stl +STLH .... 0001 1110 .... 1111 1100 1001 .... @stl + +LDREX .... 0001 1001 .... .... 1111 1001 1111 @ldrex +LDREXD_a32 .... 0001 1011 .... .... 1111 1001 1111 @ldrex +LDREXB .... 0001 1101 .... .... 1111 1001 1111 @ldrex +LDREXH .... 0001 1111 .... .... 1111 1001 1111 @ldrex + +LDAEX .... 0001 1001 .... .... 1110 1001 1111 @ldrex +LDAEXD_a32 .... 0001 1011 .... .... 1110 1001 1111 @ldrex +LDAEXB .... 0001 1101 .... .... 1110 1001 1111 @ldrex +LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex + +LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex +LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex +LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 0d379ed0d9..62bcf60d57 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -36,6 +36,8 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&strex !extern rn rd rt rt2 imm +&ldrex !extern rn rt rt2 imm # Data-processing (register-shifted register) @@ -392,3 +394,47 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 + +# Load/Store Exclusive and Load-Acquire/Store-Release + +@strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ + &strex rt2=15 imm=%imm8x4 +@strex_0 .... .... .... rn:4 rt:4 .... .... rd:4 \ + &strex rt2=15 imm=0 +@strex_d .... .... .... rn:4 rt:4 rt2:4 .... rd:4 \ + &strex imm=0 + +@ldrex_i .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=15 imm=%imm8x4 +@ldrex_0 .... .... .... rn:4 rt:4 .... .... .... \ + &ldrex rt2=15 imm=0 +@ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ + &ldrex imm=0 + +STREX 1110 1000 0100 .... .... .... .... .... @strex_i +STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 +STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 +STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d + +STLEX 1110 1000 1100 .... .... 1111 1110 .... @strex_0 +STLEXB 1110 1000 1100 .... .... 1111 1100 .... @strex_0 +STLEXH 1110 1000 1100 .... .... 1111 1101 .... @strex_0 +STLEXD_t32 1110 1000 1100 .... .... .... 1111 .... @strex_d + +STL 1110 1000 1100 .... .... 1111 1010 1111 @ldrex_0 +STLB 1110 1000 1100 .... .... 1111 1000 1111 @ldrex_0 +STLH 1110 1000 1100 .... .... 1111 1001 1111 @ldrex_0 + +LDREX 1110 1000 0101 .... .... 1111 .... .... @ldrex_i +LDREXB 1110 1000 1101 .... .... 1111 0100 1111 @ldrex_0 +LDREXH 1110 1000 1101 .... .... 1111 0101 1111 @ldrex_0 +LDREXD_t32 1110 1000 1101 .... .... .... 0111 1111 @ldrex_d + +LDAEX 1110 1000 1101 .... .... 1111 1110 1111 @ldrex_0 +LDAEXB 1110 1000 1101 .... .... 1111 1100 1111 @ldrex_0 +LDAEXH 1110 1000 1101 .... .... 1111 1101 1111 @ldrex_0 +LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d + +LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 +LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 +LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 From patchwork Fri Jul 26 17:49:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169883 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp357531ilk; Fri, 26 Jul 2019 10:55:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqwD9G4LI2sDeJzEtAqrpRDXCmgCgw3oMYxou1DYfGB+2qJ4ekcw9Vd0o1D8p5aOt7ROK5Wt X-Received: by 2002:a50:ae8f:: with SMTP id e15mr83225642edd.74.1564163713276; Fri, 26 Jul 2019 10:55:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163713; cv=none; d=google.com; s=arc-20160816; b=YPdjOwjXKy/y8r6MvvhbUQmcgADj6DbhtnZz1HpgbdG1/XWLRM+AtqrIIWLDaioV9+ PIcGN//A1eVLUvTVcE97wq1C6vKxuAiPdD4aqzSUKT5/qpOcAqeVnNMMe6gPjQkIv0rE pR4511uHwdDmUnQImpAjtgRZ3XSo5XRtF0qVxphkJEGZt3hH9GZRFFxmbMMY7cIDh68k oFTDgwLk0qw2oRbxD0EFHpyYZpE2PBq7lJ0dHdzne1o6geWHQugscbYJlb1cedVEoqvA xXTNZbcaA7QnrjqYS4Xfedlh5lO6bDGk80bMpzHLKA3ypvENNxRnzsRJh2xZNDwpReJg eAjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=KDqMHilsFSyAuM+TBQ81iYiWxxVpobopuXe2EkWbMJY=; b=xSv2bCc6tsP8uuX4nihwbhA/FKTNn3uhgc9KxR/WBywTljfAz1q3FcHgvNq6RsfLzw 0bTzPsMT1zzZqXtUJIxu57TwEtrGBolQZnGvFgHGmxVySLpcZDe0ilDECEvMmWSAqzqd QSYqXe18xUHR32Aqg6OK/FUSTLwHpg/qxOSxwpzQWOhZPr6cMBHP5J43a1SLV12W8KLm e8i30GFR7PNXy2J0SogI5PabFgm4/SET1pV5eySkomwJ+DY7FndEfFrIOuuXsrq6Q8C+ aQMZALyVN6Z16Z2agokA+KDNQE9UM8jZ+jp6WcWhnp+d3XxsDM2Jzm2oKwJcls1v9fJf cFmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="n//mIpdu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k2si12798223eds.64.2019.07.26.10.55.12 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:55:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="n//mIpdu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Qw-0003qC-NY for patch@linaro.org; Fri, 26 Jul 2019 13:55:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58017) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4N1-0003Wm-Rz for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mx-0008JB-W3 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:07 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:38418) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mx-0008Gh-MK for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:03 -0400 Received: by mail-pf1-x42b.google.com with SMTP id y15so24860584pfn.5 for ; Fri, 26 Jul 2019 10:51:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=KDqMHilsFSyAuM+TBQ81iYiWxxVpobopuXe2EkWbMJY=; b=n//mIpduCcnAamCEltxYUgUYpsHCm3X0hDFeKZfVD693VklzNMlN8ySnrcQW+1vsZv BRUhEX1bpInpNzo+WZBgY21GyGxowLT87yD2fw9caG+Hg1M9hXBTIN7UaKrL57N79yVz YI+Ux0cey2DEbdU2PAUXcI7PNJmg8/UjBA6zckvn8zonXvlEdt0T2CWogVEmBEW8bhk9 iukHeseQuBX3k2PJg/qylHvVpzpoe9C/0D/+ClYAbjo7rIQEU7tYeRSxnOwqi9ISUfib 8GQS8473oiRZS8AynbUSDdanCFXhOTS4Rup+U5Z8Yc8IjFGv+AERQ9nudFlGqWs0z5/Q +Mgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=KDqMHilsFSyAuM+TBQ81iYiWxxVpobopuXe2EkWbMJY=; b=cNc//p0UUJ2q69Hqo31I6qWmihZq/srp/Z+u9tJXaqx9GqarMc8J0HrHaNfyzkTRYW Ot/KlCuykiIV0X89Arf0MQ7zfBNkQziJg9JyIJCxrTST3ZqpQQAajsRK9UhvSyNTkfft bGPZGC2WNttCzRCOqdfh39ZiJyoq1le05xYKUoDsnf5bE026AZ6FwdCJyo9AjqOmy3s/ FFOOG2VR385xCW2mSNmHRCXbEG5n11NkTv4RHyJYATLlQtKO6wYnjCqogpWal+6JOEO7 2mhAoWNrEQn+V+yHMGrLwNQv7xYBuhI7tOUeW/PnJYsI/2oD5mbXGmuQPKc7k9WCCkuH 2cVw== X-Gm-Message-State: APjAAAUbR+OJTSByl15YfdeTI58Rj6MuoIVO6HR8w5wbvcmbZfgQ/Uwf 1Y4Re2ehrifgXZ4JFRznVRjyCDV/sZQ= X-Received: by 2002:a17:90a:d996:: with SMTP id d22mr99372813pjv.86.1564163462300; Fri, 26 Jul 2019 10:51:02 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.01 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:49 -0700 Message-Id: <20190726175032.6769-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42b Subject: [Qemu-devel] [PATCH 24/67] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 201 +++++++++++++++++++++-------------------- target/arm/a32.decode | 20 ++++ target/arm/t32.decode | 19 ++++ 3 files changed, 144 insertions(+), 96 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 74e54b7efb..bcc890c458 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9186,6 +9186,104 @@ static bool trans_LDAH(DisasContext *s, arg_LDA *a) return op_lda(s, a, MO_UW); } +/* + * Media instructions + */ + +static bool trans_USADA8(DisasContext *s, arg_USADA8 *a) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + gen_helper_usad8(t1, t1, t2); + tcg_temp_free_i32(t2); + if (a->ra != 15) { + t2 = load_reg(s, a->ra); + tcg_gen_add_i32(t1, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool op_bfx(DisasContext *s, arg_UBFX *a, bool u) +{ + TCGv_i32 tmp; + int width = a->widthm1 + 1; + int shift = a->lsb; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp = load_reg(s, a->rn); + if (shift + width > 32) { + gen_illegal_op(s); + } else if (width < 32) { + if (u) { + tcg_gen_extract_i32(tmp, tmp, shift, width); + } else { + tcg_gen_sextract_i32(tmp, tmp, shift, width); + } + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SBFX(DisasContext *s, arg_SBFX *a) +{ + return op_bfx(s, a, false); +} + +static bool trans_UBFX(DisasContext *s, arg_UBFX *a) +{ + return op_bfx(s, a, true); +} + +static bool trans_BFCI(DisasContext *s, arg_BFCI *a) +{ + TCGv_i32 tmp; + int msb = a->msb, lsb = a->lsb; + int width; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + if (msb < lsb) { + /* UNPREDICTABLE; we choose to UNDEF */ + gen_illegal_op(s); + return true; + } + + width = msb + 1 - lsb; + if (a->rn == 15) { + /* BFC */ + tmp = tcg_const_i32(0); + } else { + /* BFI */ + tmp = load_reg(s, a->rn); + } + if (width != 32) { + TCGv_i32 tmp2 = load_reg(s, a->rd); + tcg_gen_deposit_i32(tmp, tmp2, tmp, lsb, width); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_UDF(DisasContext *s, arg_UDF *a) +{ + gen_illegal_op(s); + return true; +} + /* * Legacy decoder. */ @@ -9723,65 +9821,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } break; case 3: - op1 = ((insn >> 17) & 0x38) | ((insn >> 5) & 7); - switch (op1) { - case 0: /* Unsigned sum of absolute differences. */ - ARCH(6); - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd != 15) { - tmp2 = load_reg(s, rd); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - break; - case 0x20: case 0x24: case 0x28: case 0x2c: - /* Bitfield insert/clear. */ - ARCH(6T2); - shift = (insn >> 7) & 0x1f; - i = (insn >> 16) & 0x1f; - if (i < shift) { - /* UNPREDICTABLE; we choose to UNDEF */ - goto illegal_op; - } - i = i + 1 - shift; - if (rm == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rm); - } - if (i != 32) { - tmp2 = load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, i); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rd, tmp); - break; - case 0x12: case 0x16: case 0x1a: case 0x1e: /* sbfx */ - case 0x32: case 0x36: case 0x3a: case 0x3e: /* ubfx */ - ARCH(6T2); - tmp = load_reg(s, rm); - shift = (insn >> 7) & 0x1f; - i = ((insn >> 16) & 0x1f) + 1; - if (shift + i > 32) - goto illegal_op; - if (i < 32) { - if (op1 & 0x20) { - tcg_gen_extract_i32(tmp, tmp, shift, i); - } else { - tcg_gen_sextract_i32(tmp, tmp, shift, i); - } - } - store_reg(s, rd, tmp); - break; - default: - goto illegal_op; - } - break; + /* USAD, BFI, BFC, SBFX, UBFX */ + /* Done by decodetree */ + goto illegal_op; } break; } @@ -10430,10 +10472,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0: /* 32 x 32 -> 32 */ case 1: /* 16 x 16 -> 32 */ case 3: /* 32 * 16 -> 32msb */ + case 7: /* Unsigned sum of absolute differences. */ /* in decodetree */ goto illegal_op; - case 7: /* Unsigned sum of absolute differences. */ - break; case 2: /* Dual multiply add. */ case 4: /* Dual multiply subtract. */ case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ @@ -10487,15 +10528,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_gen_extrl_i64_i32(tmp, tmp64); tcg_temp_free_i64(tmp64); break; - case 7: /* Unsigned sum of absolute differences. */ - gen_helper_usad8(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rs != 15) { - tmp2 = load_reg(s, rs); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; } store_reg(s, rd, tmp); break; @@ -10806,32 +10838,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); } switch (op) { - case 2: /* Signed bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_sextract_i32(tmp, tmp, shift, imm); - } - break; - case 6: /* Unsigned bitfield extract. */ - imm++; - if (shift + imm > 32) - goto illegal_op; - if (imm < 32) { - tcg_gen_extract_i32(tmp, tmp, shift, imm); - } - break; - case 3: /* Bitfield insert/clear. */ - if (imm < shift) - goto illegal_op; - imm = imm + 1 - shift; - if (imm != 32) { - tmp2 = load_reg(s, rd); - tcg_gen_deposit_i32(tmp, tmp2, tmp, shift, imm); - tcg_temp_free_i32(tmp2); - } - break; + case 2: /* Signed bitfield extract, in decodetree */ + case 6: /* Unsigned bitfield extract, in decodetree */ + case 3: /* Bitfield insert/clear, in decodetree */ case 7: goto illegal_op; default: /* Saturate. */ diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 1267cebaf4..7f51d04a91 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -41,6 +41,8 @@ &ldst_ri p w u rn rt imm &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm +&bfx rd rn lsb widthm1 +&bfi rd rn lsb msb # Data-processing (register) @@ -390,3 +392,21 @@ LDAEXH .... 0001 1111 .... .... 1110 1001 1111 @ldrex LDA .... 0001 1001 .... .... 1100 1001 1111 @ldrex LDAB .... 0001 1101 .... .... 1100 1001 1111 @ldrex LDAH .... 0001 1111 .... .... 1100 1001 1111 @ldrex + +# Media instructions + +# usad8 is usada8 w/ ra=15 +USADA8 ---- 0111 1000 rd:4 ra:4 rm:4 0001 rn:4 + +# ubfx and sbfx +@bfx ---- .... ... widthm1:5 rd:4 lsb:5 ... rn:4 &bfx + +SBFX .... 0111 101 ..... .... ..... 101 .... @bfx +UBFX .... 0111 111 ..... .... ..... 101 .... @bfx + +# bfc is bfi w/ rn=15 +BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi + +# While we could get UDEF by not including this, add the pattern for +# documentation and to conflict with any other typos in this file. +UDF 1110 0111 1111 ---- ---- ---- 1111 ---- diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 62bcf60d57..a4a69ad38f 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -38,6 +38,8 @@ &ldst_ri !extern p w u rn rt imm &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm +&bfx !extern rd rn lsb widthm1 +&bfi !extern rd rn lsb msb # Data-processing (register-shifted register) @@ -144,6 +146,19 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } +# Saturate, bitfield + +@bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ + &bfx lsb=%imm5_12_6 +@bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ + &bfi lsb=%imm5_12_6 + +SBFX 1111 0011 010 0 .... 0 ... .... ..0..... @bfx +UBFX 1111 0011 110 0 .... 0 ... .... ..0..... @bfx + +# bfc is bfi w/ rn=15 +BFCI 1111 0011 011 0 .... 0 ... .... ..0..... @bfi + # Multiply and multiply accumulate @s0_rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &s_rrrr s=0 @@ -192,6 +207,9 @@ SMLALBT 1111 1011 1100 .... .... .... 1001 .... @rnadm SMLALTB 1111 1011 1100 .... .... .... 1010 .... @rnadm SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm +# usad8 is usada8 w/ ra=15 +USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm + # Data-processing (two source registers) QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm @@ -254,6 +272,7 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- } # Load/store (register, immediate, literal) From patchwork Fri Jul 26 17:49:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169889 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp358478ilk; Fri, 26 Jul 2019 10:56:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqzljNgSUNk3+sdBO3ppFl/NYWajfnE1g9271+84YBKLQgMzWX6KW2sxBN0UpeO7AY2p3AGE X-Received: by 2002:a50:e619:: with SMTP id y25mr83773874edm.247.1564163773954; Fri, 26 Jul 2019 10:56:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163773; cv=none; d=google.com; s=arc-20160816; b=qqdLOcFyO8L80dgFEf0JwOieiAGAc+XsLyXKdVLUpOUYQ/9XgifFbaxzWUMacVZsey L+rZ2dm6TJZkCCOaeVcEiPij97PtLndOlWDhtmX/Uk3plNL275OWhL2gxW6HdyRUWCK9 NauXFuL473qiWVB1CgOeiqMDR+sc2/iiaaO5nx/VImr+Kx8WsWqJbdJSghi8MOxQA0SC F3RQvIHboSA0NPkQO/Xey3Y5enzNKUtnu4n8+B8+6bEKvOEVZ1gEzW9zBfQQ+UCZs40b VWQYtLhUCMpArjHtInNfwK8A6vSCP7iq5/FHI6+1SJqwW/Ph4moCvSptUFEMcZbRoWTg zKfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5xQm9xXL0dcSRS8lKo8UqXrdmM2JLCd5ELSIuDiSRZI=; b=fxiNvZzartA/00lqFdUzYPkOq08XRlEkg9odjalD1j5uEkT302R2Ok8C2YneazwmPf mdeSFApPgthQCtvHMLbJY3YA3cv11Ag4+a9yGxNR077RT9Y7IAz/b4ctI/fbxnbCXNDA 42kfpzhSXPhLyArasAtuwYuuxYDDNV/ZhgGXlu5DFRKMujnKVrHepp7gpzZVoRj2CjvJ s7UY0ujMCACQK+qumeDOlvis4vVl+J1L05/Ov1AudThVQvUCfLzBOm7M/V+A7do1uQRZ KRN1CaAXcpY5A8Wq0e/cfWqe8m/jSQogoH7ugkvKxOZBLhod9fVWKFxKH839NrpoejKp FfSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Qnl5zoUb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e28si14075319edb.265.2019.07.26.10.56.13 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:56:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Qnl5zoUb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Rv-0007uP-18 for patch@linaro.org; Fri, 26 Jul 2019 13:56:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58005) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4N1-0003Ua-B6 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Mz-0008ML-97 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:07 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:43783) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Mz-0008KP-0C for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:05 -0400 Received: by mail-pg1-x543.google.com with SMTP id f25so25099696pgv.10 for ; Fri, 26 Jul 2019 10:51:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5xQm9xXL0dcSRS8lKo8UqXrdmM2JLCd5ELSIuDiSRZI=; b=Qnl5zoUbDyTeSy9FoVTo+2TjdbOC64m/skN+R379siNQbwKWOg9C6AxzkdNMzd9VWJ FSfbfnpyBrHlNL+xAN7hMfifnnafjdL5q6p9ibK0y8n1xmOviH6cSHVxhFSuTIWD4Cjv o3xJ9qLQOq/kfKkL15JoRMW7y1q4vg3un+a7GOpjTspfQGvXo/4cEuDXjHW9rZ3GN3FS i1PAxNKGZW80BSS0jTZ3zNpZ1DO0fTD8l9c3MVytBCNjTvCL0m54NMIz6GnDhzjHVBlH okpQCdSETPh5l5pCTaDLnm/Q+VxUddbCIkwfmFMecWBgCczlSkZxOk6HkyH8E/Qpckvz 1yRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5xQm9xXL0dcSRS8lKo8UqXrdmM2JLCd5ELSIuDiSRZI=; b=YPQQ6xH++175VnbymocYhIUO9556K5TRsaiPYC8LFGYxC+C4HmSGJCj0vXKuV+yYWZ /X2JtYt6nRxtJQXuA6WTsiHVcazIPcMlPkas5JBoY3yN7irDhe5/iyaDQMLg5CNjqvAE XS2nsTE6QNxF/y1xEHM5R1491w28aQDOWFPE8zjQBuOflxg5/wYazBttubwRPlW/hpz/ z+PhZSBbM+G5QQeAlv/4pujLlXCslcjKkYeZsuvA8gc8XGe3kXebzDuWkyF/6SlXOGhR RgMCXBKWvGwqL88JlR6Nv6FN1BpJfXbecwZJKPVBBHEjUvbKt2z2JJZ/9wx4a2mQc1qy yinw== X-Gm-Message-State: APjAAAUQIhmC3rLmP+StysgOJ0OXhanr1M3KFSo15xC+QDsOarHqBaRo vgtgybB9XRWgEzXYkCT3up15tZfXvMo= X-Received: by 2002:a63:9dcb:: with SMTP id i194mr47137469pgd.444.1564163463593; Fri, 26 Jul 2019 10:51:03 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.02 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:50 -0700 Message-Id: <20190726175032.6769-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 25/67] target/arm: Convert Parallel addition and subtraction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 229 ++++++++++++++++++++--------------------- target/arm/a32.decode | 44 ++++++++ target/arm/t32.decode | 44 ++++++++ 3 files changed, 200 insertions(+), 117 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index bcc890c458..8f2b5dcb02 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -696,99 +696,6 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, int shiftop, tcg_temp_free_i32(shift); } -#define PAS_OP(pfx) \ - switch (op2) { \ - case 0: gen_pas_helper(glue(pfx,add16)); break; \ - case 1: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 2: gen_pas_helper(glue(pfx,subaddx)); break; \ - case 3: gen_pas_helper(glue(pfx,sub16)); break; \ - case 4: gen_pas_helper(glue(pfx,add8)); break; \ - case 7: gen_pas_helper(glue(pfx,sub8)); break; \ - } -static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_ptr tmp; - - switch (op1) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 1: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 5: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 2: - PAS_OP(q); - break; - case 3: - PAS_OP(sh); - break; - case 6: - PAS_OP(uq); - break; - case 7: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - -/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */ -#define PAS_OP(pfx) \ - switch (op1) { \ - case 0: gen_pas_helper(glue(pfx,add8)); break; \ - case 1: gen_pas_helper(glue(pfx,add16)); break; \ - case 2: gen_pas_helper(glue(pfx,addsubx)); break; \ - case 4: gen_pas_helper(glue(pfx,sub8)); break; \ - case 5: gen_pas_helper(glue(pfx,sub16)); break; \ - case 6: gen_pas_helper(glue(pfx,subaddx)); break; \ - } -static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b) -{ - TCGv_ptr tmp; - - switch (op2) { -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp) - case 0: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(s) - tcg_temp_free_ptr(tmp); - break; - case 4: - tmp = tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE)); - PAS_OP(u) - tcg_temp_free_ptr(tmp); - break; -#undef gen_pas_helper -#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b) - case 1: - PAS_OP(q); - break; - case 2: - PAS_OP(sh); - break; - case 5: - PAS_OP(uq); - break; - case 6: - PAS_OP(uh); - break; -#undef gen_pas_helper - } -} -#undef PAS_OP - /* * Generate a conditional based on ARM condition code cc. * This is common between ARM and Aarch64 targets. @@ -9284,6 +9191,114 @@ static bool trans_UDF(DisasContext *s, arg_UDF *a) return true; } +/* + * Parallel addition and subtraction + */ + +static bool op_par_addsub(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 t0, t1; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + + gen(t0, t0, t1); + + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +static bool op_par_addsub_ge(DisasContext *s, arg_rrr *a, + void (*gen)(TCGv_i32, TCGv_i32, + TCGv_i32, TCGv_ptr)) +{ + TCGv_i32 t0, t1; + TCGv_ptr ge; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t0 = load_reg(s, a->rn); + t1 = load_reg(s, a->rm); + + ge = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE)); + gen(t0, t0, t1, ge); + + tcg_temp_free_ptr(ge); + tcg_temp_free_i32(t1); + store_reg(s, a->rd, t0); + return true; +} + +#define DO_PAR_ADDSUB(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub(s, a, helper); \ +} + +#define DO_PAR_ADDSUB_GE(NAME, helper) \ +static bool trans_##NAME(DisasContext *s, arg_rrr *a) \ +{ \ + return op_par_addsub_ge(s, a, helper); \ +} + +DO_PAR_ADDSUB_GE(SADD16, gen_helper_sadd16) +DO_PAR_ADDSUB_GE(SASX, gen_helper_saddsubx) +DO_PAR_ADDSUB_GE(SSAX, gen_helper_ssubaddx) +DO_PAR_ADDSUB_GE(SSUB16, gen_helper_ssub16) +DO_PAR_ADDSUB_GE(SADD8, gen_helper_sadd8) +DO_PAR_ADDSUB_GE(SSUB8, gen_helper_ssub8) + +DO_PAR_ADDSUB_GE(UADD16, gen_helper_uadd16) +DO_PAR_ADDSUB_GE(UASX, gen_helper_uaddsubx) +DO_PAR_ADDSUB_GE(USAX, gen_helper_usubaddx) +DO_PAR_ADDSUB_GE(USUB16, gen_helper_usub16) +DO_PAR_ADDSUB_GE(UADD8, gen_helper_uadd8) +DO_PAR_ADDSUB_GE(USUB8, gen_helper_usub8) + +DO_PAR_ADDSUB(QADD16, gen_helper_qadd16) +DO_PAR_ADDSUB(QASX, gen_helper_qaddsubx) +DO_PAR_ADDSUB(QSAX, gen_helper_qsubaddx) +DO_PAR_ADDSUB(QSUB16, gen_helper_qsub16) +DO_PAR_ADDSUB(QADD8, gen_helper_qadd8) +DO_PAR_ADDSUB(QSUB8, gen_helper_qsub8) + +DO_PAR_ADDSUB(UQADD16, gen_helper_uqadd16) +DO_PAR_ADDSUB(UQASX, gen_helper_uqaddsubx) +DO_PAR_ADDSUB(UQSAX, gen_helper_uqsubaddx) +DO_PAR_ADDSUB(UQSUB16, gen_helper_uqsub16) +DO_PAR_ADDSUB(UQADD8, gen_helper_uqadd8) +DO_PAR_ADDSUB(UQSUB8, gen_helper_uqsub8) + +DO_PAR_ADDSUB(SHADD16, gen_helper_shadd16) +DO_PAR_ADDSUB(SHASX, gen_helper_shaddsubx) +DO_PAR_ADDSUB(SHSAX, gen_helper_shsubaddx) +DO_PAR_ADDSUB(SHSUB16, gen_helper_shsub16) +DO_PAR_ADDSUB(SHADD8, gen_helper_shadd8) +DO_PAR_ADDSUB(SHSUB8, gen_helper_shsub8) + +DO_PAR_ADDSUB(UHADD16, gen_helper_uhadd16) +DO_PAR_ADDSUB(UHASX, gen_helper_uhaddsubx) +DO_PAR_ADDSUB(UHSAX, gen_helper_uhsubaddx) +DO_PAR_ADDSUB(UHSUB16, gen_helper_uhsub16) +DO_PAR_ADDSUB(UHADD8, gen_helper_uhadd8) +DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) + +#undef DO_PAR_ADDSUB +#undef DO_PAR_ADDSUB_GE + /* * Legacy decoder. */ @@ -9593,16 +9608,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) rs = (insn >> 8) & 0xf; switch ((insn >> 23) & 3) { case 0: /* Parallel add/subtract. */ - op1 = (insn >> 20) & 7; - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - sh = (insn >> 5) & 7; - if ((op1 & 3) == 0 || sh == 5 || sh == 6) - goto illegal_op; - gen_arm_parallel_addsub(op1, sh, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + /* Done by decodetree */ + goto illegal_op; case 1: if ((insn & 0x00700020) == 0) { /* Halfword pack. */ @@ -10396,20 +10403,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } store_reg(s, rd, tmp); break; - case 2: /* SIMD add/subtract. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - op = (insn >> 20) & 7; - shift = (insn >> 4) & 7; - if ((op & 3) == 3 || (shift & 3) == 3) - goto illegal_op; - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - gen_thumb2_parallel_addsub(op, shift, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; + case 2: /* SIMD add/subtract, in decodetree */ + goto illegal_op; case 3: /* Other data processing. */ op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); if (op < 4) { diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 7f51d04a91..2e0f74044f 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -410,3 +410,47 @@ BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi # While we could get UDEF by not including this, add the pattern for # documentation and to conflict with any other typos in this file. UDF 1110 0111 1111 ---- ---- ---- 1111 ---- + +# Parallel addition and subtraction + +SADD16 .... 0110 0001 .... .... 1111 0001 .... @rndm +SASX .... 0110 0001 .... .... 1111 0011 .... @rndm +SSAX .... 0110 0001 .... .... 1111 0101 .... @rndm +SSUB16 .... 0110 0001 .... .... 1111 0111 .... @rndm +SADD8 .... 0110 0001 .... .... 1111 1001 .... @rndm +SSUB8 .... 0110 0001 .... .... 1111 1111 .... @rndm + +QADD16 .... 0110 0010 .... .... 1111 0001 .... @rndm +QASX .... 0110 0010 .... .... 1111 0011 .... @rndm +QSAX .... 0110 0010 .... .... 1111 0101 .... @rndm +QSUB16 .... 0110 0010 .... .... 1111 0111 .... @rndm +QADD8 .... 0110 0010 .... .... 1111 1001 .... @rndm +QSUB8 .... 0110 0010 .... .... 1111 1111 .... @rndm + +SHADD16 .... 0110 0011 .... .... 1111 0001 .... @rndm +SHASX .... 0110 0011 .... .... 1111 0011 .... @rndm +SHSAX .... 0110 0011 .... .... 1111 0101 .... @rndm +SHSUB16 .... 0110 0011 .... .... 1111 0111 .... @rndm +SHADD8 .... 0110 0011 .... .... 1111 1001 .... @rndm +SHSUB8 .... 0110 0011 .... .... 1111 1111 .... @rndm + +UADD16 .... 0110 0101 .... .... 1111 0001 .... @rndm +UASX .... 0110 0101 .... .... 1111 0011 .... @rndm +USAX .... 0110 0101 .... .... 1111 0101 .... @rndm +USUB16 .... 0110 0101 .... .... 1111 0111 .... @rndm +UADD8 .... 0110 0101 .... .... 1111 1001 .... @rndm +USUB8 .... 0110 0101 .... .... 1111 1111 .... @rndm + +UQADD16 .... 0110 0110 .... .... 1111 0001 .... @rndm +UQASX .... 0110 0110 .... .... 1111 0011 .... @rndm +UQSAX .... 0110 0110 .... .... 1111 0101 .... @rndm +UQSUB16 .... 0110 0110 .... .... 1111 0111 .... @rndm +UQADD8 .... 0110 0110 .... .... 1111 1001 .... @rndm +UQSUB8 .... 0110 0110 .... .... 1111 1111 .... @rndm + +UHADD16 .... 0110 0111 .... .... 1111 0001 .... @rndm +UHASX .... 0110 0111 .... .... 1111 0011 .... @rndm +UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm +UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm +UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm +UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index a4a69ad38f..99673929c0 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -457,3 +457,47 @@ LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 + +# Parallel addition and subtraction + +SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm +QADD8 1111 1010 1000 .... 1111 .... 0001 .... @rndm +SHADD8 1111 1010 1000 .... 1111 .... 0010 .... @rndm +UADD8 1111 1010 1000 .... 1111 .... 0100 .... @rndm +UQADD8 1111 1010 1000 .... 1111 .... 0101 .... @rndm +UHADD8 1111 1010 1000 .... 1111 .... 0110 .... @rndm + +SADD16 1111 1010 1001 .... 1111 .... 0000 .... @rndm +QADD16 1111 1010 1001 .... 1111 .... 0001 .... @rndm +SHADD16 1111 1010 1001 .... 1111 .... 0010 .... @rndm +UADD16 1111 1010 1001 .... 1111 .... 0100 .... @rndm +UQADD16 1111 1010 1001 .... 1111 .... 0101 .... @rndm +UHADD16 1111 1010 1001 .... 1111 .... 0110 .... @rndm + +SASX 1111 1010 1010 .... 1111 .... 0000 .... @rndm +QASX 1111 1010 1010 .... 1111 .... 0001 .... @rndm +SHASX 1111 1010 1010 .... 1111 .... 0010 .... @rndm +UASX 1111 1010 1010 .... 1111 .... 0100 .... @rndm +UQASX 1111 1010 1010 .... 1111 .... 0101 .... @rndm +UHASX 1111 1010 1010 .... 1111 .... 0110 .... @rndm + +SSUB8 1111 1010 1100 .... 1111 .... 0000 .... @rndm +QSUB8 1111 1010 1100 .... 1111 .... 0001 .... @rndm +SHSUB8 1111 1010 1100 .... 1111 .... 0010 .... @rndm +USUB8 1111 1010 1100 .... 1111 .... 0100 .... @rndm +UQSUB8 1111 1010 1100 .... 1111 .... 0101 .... @rndm +UHSUB8 1111 1010 1100 .... 1111 .... 0110 .... @rndm + +SSUB16 1111 1010 1101 .... 1111 .... 0000 .... @rndm +QSUB16 1111 1010 1101 .... 1111 .... 0001 .... @rndm +SHSUB16 1111 1010 1101 .... 1111 .... 0010 .... @rndm +USUB16 1111 1010 1101 .... 1111 .... 0100 .... @rndm +UQSUB16 1111 1010 1101 .... 1111 .... 0101 .... @rndm +UHSUB16 1111 1010 1101 .... 1111 .... 0110 .... @rndm + +SSAX 1111 1010 1110 .... 1111 .... 0000 .... @rndm +QSAX 1111 1010 1110 .... 1111 .... 0001 .... @rndm +SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm +USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm +UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm +UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm From patchwork Fri Jul 26 17:49:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169888 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp358438ilk; Fri, 26 Jul 2019 10:56:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqyen2G2ti5jtgcfuQTAOZx2PG1lgSRPY9tmOM06as71i2LumM11hcA2Ng7kM0wSP87Ozwnx X-Received: by 2002:a17:906:c446:: with SMTP id ck6mr74086651ejb.190.1564163771238; Fri, 26 Jul 2019 10:56:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163771; cv=none; d=google.com; s=arc-20160816; b=DpzQmfxkzO42esmQSmBourxC25SpE0tq1XoiNWiu+gNmvrq9OnYuIDnB1/KKBFkvCS 9g/sYLe/7PRC12Oh0Xff0IOhbUGStjx3g2i6CRJcn4r7+4zifiQ0JajmKS6JlIYZuIBn 49tdk1Fq4yZsIgOqV/wynwjQVTOLEzcSMD9fhsUbf6gc8Vqik4gxP/qqv4AaReApDne8 qcs44tXc4YweYwBLd9wcSCpj2TNq3yPootCn4+9NSFZzzdCWEzZ1VLvQnpwJ35WYDMMD pIyX7Ljc8YhEF01kMXg5Ak80wPVat69b6p2xSLWFwHdfq1dJiEPNOFMlfw+VMIjGpySp wszA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=SSDBvIc5VrWmHI0q6O3eYkyrazatA+zZiU/6XBOYB8I=; b=LvhnBzIsg1HJ091Whw3DbxE01nvkXHZhctu4aHbfh9Q5ddvMzu6ul0O+zK3xsWP09i ScZmbx0AwIbti40xi+wzbx3i5GEuQWMhO1mYcnV8b9LhuOuIO4Ar+I4HQcJ897CXVgpi 821gZ02wFzTESpz25ZI7/0xPbZ6QiU1rMqqs+9dk8izwBygNkrakwB0yEadpiwV1Jfc+ Rdvwm1QNOHdu5drz2PZf70fC81aDtsZ347XXAx85rj8QBlq6e3fiDmUazUu/KAJ9hMmW m7yvvCcJg0P14hsfbQIUfkBXRYfYD+XtDswRyy18AVF+mFK94kvBGb/1JvwCjWft/g8s GQdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=G0UkbkIJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id dc19si11423594ejb.324.2019.07.26.10.56.10 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:56:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=G0UkbkIJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42386 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Rl-0007OD-LZ for patch@linaro.org; Fri, 26 Jul 2019 13:56:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58120) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4N4-0003jd-N5 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4N1-0008RN-4c for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:10 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:36332) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4N0-0008Ow-Nl for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:07 -0400 Received: by mail-pg1-x542.google.com with SMTP id l21so25108424pgm.3 for ; Fri, 26 Jul 2019 10:51:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SSDBvIc5VrWmHI0q6O3eYkyrazatA+zZiU/6XBOYB8I=; b=G0UkbkIJV2em0FhVqk+MUKv7xotYjW6Ze7uZ9pHX9dwx4+TEdMVoiAmkKs0RPXH/qt eNPRXXDqAr7pEyQP1D8ONbVNL5BWcz+4bX1EF/XMPNXTshmT+/TgZqrlo/Dxu1axSqK3 p7c23MPIAOOBNL4zTTp8SPtZJAug7kliX2mRBT+6RgK9G32PbbEOjULij/sVezfPEDnz PSX042OqVf/OhGOWKUvX133uXfJOer+KWK7KozQqYn2IlzOJtcKP73iwRgdTybvV2RkT 9T9NruN8HE7KvnMQ9uOrwGSPIS4WQ352hbdJZMSuY0KFzRXNi4ynfqx0Z6YvMZCJXJxB pvNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SSDBvIc5VrWmHI0q6O3eYkyrazatA+zZiU/6XBOYB8I=; b=uG0hmpvy+C18pVF7DdZzGhfvNGtEXZ9b6vr9gssYt46pCQR2o+yknBUG8tpB+KeyTd bSHXBDTB2Andkn+SlAsDPTaaaN0R0XUVqEa+CCMiuQ+sv55v8zSXfTZnTfSEvlQpqELc vkV7g/S0dKtI6NgBqbQZqvQDxB9gCWeIIV/sUYfcFHf1eh+Oe+wcJQuUptXZ8jHj8i/v x+mknhAsJ2l2VNRCcfL2H13cDbJ4zj96se7QsrOYkGxiJf7XQEOjCavmsO6bb1wuOHkk PXylvbL3/tLnb87reUaM3QnWLUeoRjllzCw4NQtKQjR76NzyafzO9/HOZ+cp3uS2OkFF Zreg== X-Gm-Message-State: APjAAAVBzhnO4USGOM0cOW7A2AQ3VBL1Fs85PUvKvG5U+aBMqadxXo6M kNb2W2CGMglDmmUaJlvYoENrPAAIAm4= X-Received: by 2002:a63:e213:: with SMTP id q19mr91250784pgh.180.1564163465042; Fri, 26 Jul 2019 10:51:05 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.03 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:51 -0700 Message-Id: <20190726175032.6769-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 26/67] target/arm: Convert Packing, unpacking, saturation, and reversal X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 554 +++++++++++++++++------------------------ target/arm/a32.decode | 32 +++ target/arm/t32.decode | 37 ++- 3 files changed, 302 insertions(+), 321 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 8f2b5dcb02..11e74135fd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -364,7 +364,7 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) } /* Byteswap each halfword. */ -static void gen_rev16(TCGv_i32 var) +static void gen_rev16(TCGv_i32 dest, TCGv_i32 var) { TCGv_i32 tmp = tcg_temp_new_i32(); TCGv_i32 mask = tcg_const_i32(0x00ff00ff); @@ -372,17 +372,17 @@ static void gen_rev16(TCGv_i32 var) tcg_gen_and_i32(tmp, tmp, mask); tcg_gen_and_i32(var, var, mask); tcg_gen_shli_i32(var, var, 8); - tcg_gen_or_i32(var, var, tmp); + tcg_gen_or_i32(dest, var, tmp); tcg_temp_free_i32(mask); tcg_temp_free_i32(tmp); } /* Byteswap low halfword and sign extend. */ -static void gen_revsh(TCGv_i32 var) +static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) { tcg_gen_ext16u_i32(var, var); tcg_gen_bswap16_i32(var, var); - tcg_gen_ext16s_i32(var, var); + tcg_gen_ext16s_i32(dest, var); } /* Return (b << 32) + a. Mark inputs as dead */ @@ -467,7 +467,7 @@ static void gen_swap_half(TCGv_i32 var) t0 = (t0 + t1) ^ tmp; */ -static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) +static void gen_add16(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { TCGv_i32 tmp = tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, t0, t1); @@ -475,9 +475,8 @@ static void gen_add16(TCGv_i32 t0, TCGv_i32 t1) tcg_gen_andi_i32(t0, t0, ~0x8000); tcg_gen_andi_i32(t1, t1, ~0x8000); tcg_gen_add_i32(t0, t0, t1); - tcg_gen_xor_i32(t0, t0, tmp); + tcg_gen_xor_i32(dest, t0, tmp); tcg_temp_free_i32(tmp); - tcg_temp_free_i32(t1); } /* Set N and Z flags from var. */ @@ -6390,7 +6389,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } break; case NEON_2RM_VREV16: - gen_rev16(tmp); + gen_rev16(tmp, tmp); break; case NEON_2RM_VCLS: switch (size) { @@ -9299,16 +9298,229 @@ DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8) #undef DO_PAR_ADDSUB #undef DO_PAR_ADDSUB_GE +/* + * Packing, unpacking, saturation, and reversal + */ + +static bool trans_PKH(DisasContext *s, arg_PKH *a) +{ + TCGv_i32 tn, tm; + int shift = a->imm; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + tn = load_reg(s, a->rn); + tm = load_reg(s, a->rm); + if (a->tb) { + /* PKHTB */ + if (shift == 0) { + shift = 31; + } + tcg_gen_sari_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tn, tm, 0, 16); + } else { + /* PKHBT */ + tcg_gen_shli_i32(tm, tm, shift); + tcg_gen_deposit_i32(tn, tm, tn, 0, 16); + } + tcg_temp_free_i32(tm); + store_reg(s, a->rd, tn); + return true; +} + +static bool op_sat(DisasContext *s, arg_sat *a, + void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp, satimm; + int shift = a->imm; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp = load_reg(s, a->rn); + if (a->sh) { + tcg_gen_sari_i32(tmp, tmp, shift ? shift : 31); + } else { + tcg_gen_shli_i32(tmp, tmp, shift); + } + + satimm = tcg_const_i32(a->satimm); + gen(tmp, cpu_env, tmp, satimm); + tcg_temp_free_i32(satimm); + + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SSAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_ssat); +} + +static bool trans_USAT(DisasContext *s, arg_sat *a) +{ + return op_sat(s, a, gen_helper_usat); +} + +static bool trans_SSAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_ssat16); +} + +static bool trans_USAT16(DisasContext *s, arg_sat *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_sat(s, a, gen_helper_usat16); +} + +static bool op_xta(DisasContext *s, arg_rrr_rot *a, + void (*gen_extract)(TCGv_i32, TCGv_i32), + void (*gen_add)(TCGv_i32, TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6) { + return false; + } + + tmp = load_reg(s, a->rm); + /* + * TODO: In many cases we could do a shift instead of a rotate. + * Combined with a simple extend, that becomes an extract. + */ + if (a->rot != 0) { + tcg_gen_rotri_i32(tmp, tmp, a->rot * 8); + } + gen_extract(tmp, tmp); + + if (a->rn != 15) { + TCGv_i32 tmp2 = load_reg(s, a->rn); + gen_add(tmp, tmp, tmp2); + tcg_temp_free_i32(tmp2); + } + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_SXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16s_i32, tcg_gen_add_i32); +} + +static bool trans_SXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_sxtb16, gen_add16); +} + +static bool trans_UXTAB(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext8u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAH(DisasContext *s, arg_rrr_rot *a) +{ + return op_xta(s, a, tcg_gen_ext16u_i32, tcg_gen_add_i32); +} + +static bool trans_UXTAB16(DisasContext *s, arg_rrr_rot *a) +{ + if (s->thumb && !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { + return false; + } + return op_xta(s, a, gen_helper_uxtb16, gen_add16); +} + +static bool trans_SEL(DisasContext *s, arg_rrr *a) +{ + TCGv_i32 t1, t2, t3; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + t3 = tcg_temp_new_i32(); + tcg_gen_ld_i32(t3, cpu_env, offsetof(CPUARMState, GE)); + gen_helper_sel_flags(t1, t3, t1, t2); + tcg_temp_free_i32(t3); + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool op_rr(DisasContext *s, arg_rr *a, + void (*gen)(TCGv_i32, TCGv_i32)) +{ + TCGv_i32 tmp; + + tmp = load_reg(s, a->rm); + gen(tmp, tmp); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_REV(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, tcg_gen_bswap32_i32); +} + +static bool trans_REV16(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_rev16); +} + +static bool trans_REVSH(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + return op_rr(s, a, gen_revsh); +} + +static bool trans_RBIT(DisasContext *s, arg_rr *a) +{ + if (!ENABLE_ARCH_6T2) { + return false; + } + return op_rr(s, a, gen_helper_rbit); +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, shift, rm, rs, rn, rd, sh; + unsigned int cond, val, op1, i, rm, rs, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; TCGv_i64 tmp64; @@ -9611,116 +9823,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* Done by decodetree */ goto illegal_op; case 1: - if ((insn & 0x00700020) == 0) { - /* Halfword pack. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - shift = (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - /* pkhtb */ - if (shift == 0) - shift = 31; - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_andi_i32(tmp, tmp, 0xffff0000); - tcg_gen_ext16u_i32(tmp2, tmp2); - } else { - /* pkhbt */ - if (shift) - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); - } - tcg_gen_or_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00200020) == 0x00200000) { - /* [us]sat */ - tmp = load_reg(s, rm); - shift = (insn >> 7) & 0x1f; - if (insn & (1 << 6)) { - if (shift == 0) - shift = 31; - tcg_gen_sari_i32(tmp, tmp, shift); - } else { - tcg_gen_shli_i32(tmp, tmp, shift); - } - sh = (insn >> 16) & 0x1f; - tmp2 = tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00300fe0) == 0x00200f20) { - /* [us]sat16 */ - tmp = load_reg(s, rm); - sh = (insn >> 16) & 0x1f; - tmp2 = tcg_const_i32(sh); - if (insn & (1 << 22)) - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - else - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x00700fe0) == 0x00000fa0) { - /* Select bytes. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - tmp3 = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE)); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((insn & 0x000003e0) == 0x00000060) { - tmp = load_reg(s, rm); - shift = (insn >> 10) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - if (shift != 0) - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op1 = (insn >> 20) & 7; - switch (op1) { - case 0: gen_sxtb16(tmp); break; - case 2: gen_sxtb(tmp); break; - case 3: gen_sxth(tmp); break; - case 4: gen_uxtb16(tmp); break; - case 6: gen_uxtb(tmp); break; - case 7: gen_uxth(tmp); break; - default: goto illegal_op; - } - if (rn != 15) { - tmp2 = load_reg(s, rn); - if ((op1 & 3) == 0) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - } else if ((insn & 0x003f0f60) == 0x003f0f20) { - /* rev */ - tmp = load_reg(s, rm); - if (insn & (1 << 22)) { - if (insn & (1 << 7)) { - gen_revsh(tmp); - } else { - ARCH(6T2); - gen_helper_rbit(tmp, tmp); - } - } else { - if (insn & (1 << 7)) - gen_rev16(tmp); - else - tcg_gen_bswap32_i32(tmp, tmp); - } - store_reg(s, rd, tmp); - } else { - goto illegal_op; - } - break; + /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ + /* Done by decodetree */ + goto illegal_op; case 2: /* Multiplies (Type 3). */ switch ((insn >> 20) & 0x7) { case 5: @@ -10053,11 +10158,10 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, shift, offset; + uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 tmp3; TCGv_i32 addr; TCGv_i64 tmp64; int op; @@ -10313,155 +10417,18 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } break; case 5: - - op = (insn >> 21) & 0xf; - if (op == 6) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - /* Halfword pack. */ - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); - if (insn & (1 << 5)) { - /* pkhtb */ - if (shift == 0) - shift = 31; - tcg_gen_sari_i32(tmp2, tmp2, shift); - tcg_gen_andi_i32(tmp, tmp, 0xffff0000); - tcg_gen_ext16u_i32(tmp2, tmp2); - } else { - /* pkhbt */ - if (shift) - tcg_gen_shli_i32(tmp2, tmp2, shift); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000); - } - tcg_gen_or_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else { - /* Data processing register constant shift. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 13: /* Misc data processing. */ op = ((insn >> 22) & 6) | ((insn >> 7) & 1); if (op < 4 && (insn & 0xf000) != 0xf000) goto illegal_op; switch (op) { case 0: /* Register controlled shift, in decodetree */ - goto illegal_op; - case 1: /* Sign/zero extend. */ - op = (insn >> 20) & 7; - switch (op) { - case 0: /* SXTAH, SXTH */ - case 1: /* UXTAH, UXTH */ - case 4: /* SXTAB, SXTB */ - case 5: /* UXTAB, UXTB */ - break; - case 2: /* SXTAB16, SXTB16 */ - case 3: /* UXTAB16, UXTB16 */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - default: - goto illegal_op; - } - if (rn != 15) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - } - tmp = load_reg(s, rm); - shift = (insn >> 4) & 3; - /* ??? In many cases it's not necessary to do a - rotate, a shift is sufficient. */ - if (shift != 0) - tcg_gen_rotri_i32(tmp, tmp, shift * 8); - op = (insn >> 20) & 7; - switch (op) { - case 0: gen_sxth(tmp); break; - case 1: gen_uxth(tmp); break; - case 2: gen_sxtb16(tmp); break; - case 3: gen_uxtb16(tmp); break; - case 4: gen_sxtb(tmp); break; - case 5: gen_uxtb(tmp); break; - default: - g_assert_not_reached(); - } - if (rn != 15) { - tmp2 = load_reg(s, rn); - if ((op >> 1) == 1) { - gen_add16(tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - } - store_reg(s, rd, tmp); - break; + case 1: /* Sign/zero extend, in decodetree */ case 2: /* SIMD add/subtract, in decodetree */ + case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 3: /* Other data processing. */ - op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7); - if (op < 4) { - /* Saturating add/subtract. */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - switch (op) { - case 0x0a: /* rbit */ - case 0x08: /* rev */ - case 0x09: /* rev16 */ - case 0x0b: /* revsh */ - break; - case 0x10: /* sel */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - case 0x18: /* clz, in decodetree */ - case 0x20: /* crc32/crc32c, in decodetree */ - case 0x21: - case 0x22: - case 0x28: - case 0x29: - case 0x2a: - goto illegal_op; - default: - goto illegal_op; - } - tmp = load_reg(s, rn); - switch (op) { - case 0x0a: /* rbit */ - gen_helper_rbit(tmp, tmp); - break; - case 0x08: /* rev */ - tcg_gen_bswap32_i32(tmp, tmp); - break; - case 0x09: /* rev16 */ - gen_rev16(tmp); - break; - case 0x0b: /* revsh */ - gen_revsh(tmp); - break; - case 0x10: /* sel */ - tmp2 = load_reg(s, rm); - tmp3 = tcg_temp_new_i32(); - tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE)); - gen_helper_sel_flags(tmp, tmp3, tmp, tmp2); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); - break; - default: - g_assert_not_reached(); - } - } - store_reg(s, rd, tmp); - break; case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ switch ((insn >> 20) & 7) { case 0: /* 32 x 32 -> 32 */ @@ -10820,61 +10787,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) * - Data-processing (plain binary immediate) */ if (insn & (1 << 24)) { - if (insn & (1 << 20)) - goto illegal_op; - /* Bitfield/Saturate. */ - op = (insn >> 21) & 7; - imm = insn & 0x1f; - shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c); - if (rn == 15) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else { - tmp = load_reg(s, rn); - } - switch (op) { - case 2: /* Signed bitfield extract, in decodetree */ - case 6: /* Unsigned bitfield extract, in decodetree */ - case 3: /* Bitfield insert/clear, in decodetree */ - case 7: - goto illegal_op; - default: /* Saturate. */ - if (shift) { - if (op & 1) - tcg_gen_sari_i32(tmp, tmp, shift); - else - tcg_gen_shli_i32(tmp, tmp, shift); - } - tmp2 = tcg_const_i32(imm); - if (op & 4) { - /* Unsigned. */ - if ((op & 1) && shift == 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_usat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_usat(tmp, cpu_env, tmp, tmp2); - } - } else { - /* Signed. */ - if ((op & 1) && shift == 0) { - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - gen_helper_ssat16(tmp, cpu_env, tmp, tmp2); - } else { - gen_helper_ssat(tmp, cpu_env, tmp, tmp2); - } - } - tcg_temp_free_i32(tmp2); - break; - } - store_reg(s, rd, tmp); + /* Bitfield/Saturate, in decodetree */ + goto illegal_op; } else { imm = ((insn & 0x04000000) >> 15) | ((insn & 0x7000) >> 4) | (insn & 0xff); @@ -11568,8 +11482,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) tmp = load_reg(s, rn); switch (op1) { case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp); break; - case 3: gen_revsh(tmp); break; + case 1: gen_rev16(tmp, tmp); break; + case 3: gen_revsh(tmp, tmp); break; default: g_assert_not_reached(); } diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 2e0f74044f..725e627796 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -28,6 +28,7 @@ &s_rri_rot s rn rd imm rot &s_rrrr s rd rn rm ra &rrrr rd rn rm ra +&rrr_rot rd rn rm rot &rrr rd rn rm &rr rd rm &ri rd imm @@ -43,6 +44,8 @@ &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 &bfi rd rn lsb msb +&sat rd rn satimm imm sh +&pkh rd rn rm imm tb # Data-processing (register) @@ -454,3 +457,32 @@ UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm + +# Packing, unpacking, saturation, and reversal + +PKH ---- 0110 1000 rn:4 rd:4 imm:5 tb:1 01 rm:4 &pkh + +@sat ---- .... ... satimm:5 rd:4 imm:5 sh:1 .. rn:4 &sat +@sat16 ---- .... .... satimm:4 rd:4 .... .... rn:4 \ + &sat imm=0 sh=0 + +SSAT .... 0110 101. .... .... .... ..01 .... @sat +USAT .... 0110 111. .... .... .... ..01 .... @sat + +SSAT16 .... 0110 1010 .... .... 1111 0011 .... @sat16 +USAT16 .... 0110 1110 .... .... 1111 0011 .... @sat16 + +@rrr_rot ---- .... .... rn:4 rd:4 rot:2 ...... rm:4 &rrr_rot + +SXTAB16 .... 0110 1000 .... .... ..00 0111 .... @rrr_rot +SXTAB .... 0110 1010 .... .... ..00 0111 .... @rrr_rot +SXTAH .... 0110 1011 .... .... ..00 0111 .... @rrr_rot +UXTAB16 .... 0110 1100 .... .... ..00 0111 .... @rrr_rot +UXTAB .... 0110 1110 .... .... ..00 0111 .... @rrr_rot +UXTAH .... 0110 1111 .... .... ..00 0111 .... @rrr_rot + +SEL .... 0110 1000 .... .... 1111 1011 .... @rndm +REV .... 0110 1011 1111 .... 1111 0011 .... @rdm +REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm +REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm +RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 99673929c0..ea147e5348 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -25,6 +25,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra +&rrr_rot !extern rd rn rm rot &rrr !extern rd rn rm &rr !extern rd rm &ri !extern rd imm @@ -40,6 +41,8 @@ &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 &bfi !extern rd rn lsb msb +&sat !extern rd rn satimm imm sh +&pkh !extern rd rn rm imm tb # Data-processing (register-shifted register) @@ -74,7 +77,8 @@ BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi TEQ_rrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi } -# PKHBT, PKHTB at opc1 = 0110 +PKH 1110101 0110 0 rn:4 0 ... rd:4 .. tb:1 0 rm:4 \ + &pkh imm=%imm5_12_6 { CMN_rrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi @@ -148,6 +152,20 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot # Saturate, bitfield +@sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ + &sat imm=%imm5_12_6 +@sat16 .... .... .. . . rn:4 . ... rd:4 .. . satimm:5 \ + &sat sh=0 imm=0 + +{ + SSAT16 1111 0011 001 0 .... 0 000 .... 00 0 ..... @sat16 + SSAT 1111 0011 00. 0 .... 0 ... .... .. 0 ..... @sat +} +{ + USAT16 1111 0011 101 0 .... 0 000 .... 00 0 ..... @sat16 + USAT 1111 0011 10. 0 .... 0 ... .... .. 0 ..... @sat +} + @bfx .... .... ... . rn:4 . ... rd:4 .. . widthm1:5 \ &bfx lsb=%imm5_12_6 @bfi .... .... ... . rn:4 . ... rd:4 .. . msb:5 \ @@ -224,8 +242,14 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm +SEL 1111 1010 1010 .... 1111 .... 1000 .... @rndm + # Ignore Rn, as allowed by constrained unpredictable. # This matches the behaviour of the legacy decoder. +REV 1111 1010 1001 ---- 1111 .... 1000 .... @rdm +REV16 1111 1010 1001 ---- 1111 .... 1001 .... @rdm +RBIT 1111 1010 1001 ---- 1111 .... 1010 .... @rdm +REVSH 1111 1010 1001 ---- 1111 .... 1011 .... @rdm CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm # Branches and miscellaneous control @@ -501,3 +525,14 @@ SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm + +# Register extends + +@rrr_rot .... .... .... rn:4 .... rd:4 .. rot:2 rm:4 &rrr_rot + +SXTAH 1111 1010 0000 .... 1111 .... 10.. .... @rrr_rot +UXTAH 1111 1010 0001 .... 1111 .... 10.. .... @rrr_rot +SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot +UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot +SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot +UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot From patchwork Fri Jul 26 17:49:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169895 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp359914ilk; Fri, 26 Jul 2019 10:57:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqw0KNEuvxMMfYdh3M+EymWvH56JKQADxdNQtjpEFMr48foit+qjIGFJMTZYgGjD0ofH1ei3 X-Received: by 2002:a50:92cd:: with SMTP id l13mr81826137eda.136.1564163867350; Fri, 26 Jul 2019 10:57:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163867; cv=none; d=google.com; s=arc-20160816; b=adroabEFbgN/c5H0XWGRGLL1S3ALibB7eQJCkOUXsea+mwItfINWEgFFeoy8j+f/by q+btnKy7exXVx6BOVGNXB4eGEbW2q9JJOE3lEcewacDr5HilVRd1O5kdwlFbRV7zAAwo xKwC9cVzcdOmavCBKa2Gn8fL2QqbtqXsWvY/FzAcaBvqjNIvhv8C9Z3IXNXXdsydXJG/ 5p3xGVllMVi/L6g5Z1z7zZN/kyFfGr+/zxr6AF3YE6LmZXQpnQoLOgFx4NkoANeUKBI1 Pu96wvHt6hUMvbVn79A8yu97ZSxph4mYo/IKblutNO97mj9XgVKd1M2Btv+wNr3qM/FO RmzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=G+QSnEYqXF/oTE+I+ALJbsZ2r4R3OZGRCeVr3t2ySsk=; b=Zkq4SA3C/xX9fyE0hxcGTd7OrHwDqVT1FEOgrR3bgCtssFRaOG4QrK9rZ96v5yn3mI /4cjRPouvxKsftxVZl+mcNTGrU+4eT+4jCFgePjQeCXBADuR8qefbXNSGoRcMM6oQRCq 5njlRR+zvIRxI6JmvewzhIZ/UUL+y8MLxR//KlBK5wbn7N2a2bYG8vdzF+zi0loS6AJG Xnir8Y6FgpkEmWFYRq1AF8LptgWb9YrwJvmIMfUjfgNzFpBcf3rQpsk1bvtZPbgdFsC7 qHZivw8RSQyjqvvO9gfAI+Qh3rOuChRNy8FTZRAYhF2yXcCpufV3qgIpJmRVzGQQP1yM tuyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kISlNp5n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id rl21si11263769ejb.20.2019.07.26.10.57.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:57:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kISlNp5n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42446 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4TR-0005D0-Pp for patch@linaro.org; Fri, 26 Jul 2019 13:57:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58163) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4N6-0003nL-I0 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4N2-0008Tr-4x for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:11 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:34141) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4N1-0008RK-Mv for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:08 -0400 Received: by mail-pf1-x442.google.com with SMTP id b13so24857463pfo.1 for ; Fri, 26 Jul 2019 10:51:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=G+QSnEYqXF/oTE+I+ALJbsZ2r4R3OZGRCeVr3t2ySsk=; b=kISlNp5nE8I749I4oLIKQckvP5KwoKV4u5lFjFNZsgCw/ptdlVvoWE4ef5IS1npxFF vaoULYbwEDhQK4EKdTJs74/nlh0kxPGP90Px1BsYpuBdv0fJJ3UD7+LBB6cW4uYhaoKh rfDP1nk/MsMfD7xzt5fmEIPXbNDU15fFKu+7gL7552x6mLnOqfZbcjeSxWC3T6YE8CM8 FofFOzeWbZHUbPMuadl3euCmym1DJFh1QzZuMxZOnsNHESGhQhjkmI+rppZhu9U/c5jL z313rgCDJWweNELovc2Wbf8CwGattOFWivvhf+/8IFGk8szaa4cRuQQIU90oaE2BSJ6D S5ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=G+QSnEYqXF/oTE+I+ALJbsZ2r4R3OZGRCeVr3t2ySsk=; b=r0oUAWuwY8w5ymyJ7lLYP9Si6X5lI7sflpHO1f9PAj2wWRd/41ZcOWH3J9a9D4PhUv 0XV7QIll3Ii6h3DpGdW4XKZAC9Pt0cNxi2BNs62pC6baO/fkQOi9Np6UCtBJAGT00Bd2 QxrLhtL8DU67Bge1CwFui6AG6znbvdgUBxQ0vAIaaXGtw8jYk/YtNbQMzj6BhXISjj+e e+pVXwvrfy1ELymkzWr5poGNrsp9XToLVoPAMV34Nh6TDDa6xyQp2ypjz6eZzCWfM9t1 k1OjNLPc7SF2r1ZMT+yntPMOE+rXBZTZw/3OQ/cDqVWanitsRmPQqBgtR8NXo8gdTeaS JiEQ== X-Gm-Message-State: APjAAAXoRZVszj4lcDMfOd/WfYYNsbUCz1rspY0MvPVU03R9xRTGg9fS O+JHMP4RGBubQgP2qkBIK4is9yPa1c0= X-Received: by 2002:a65:5082:: with SMTP id r2mr66449305pgp.170.1564163466096; Fri, 26 Jul 2019 10:51:06 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.05 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:52 -0700 Message-Id: <20190726175032.6769-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 27/67] target/arm: Convert Signed multiply, signed and unsigned divide X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 471 ++++++++++++++++++----------------------- target/arm/a32.decode | 22 ++ target/arm/t32.decode | 18 ++ 3 files changed, 248 insertions(+), 263 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 11e74135fd..5bdec27265 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9512,17 +9512,218 @@ static bool trans_RBIT(DisasContext *s, arg_rr *a) return op_rr(s, a, gen_helper_rbit); } +/* + * Signed multiply, signed and unsigned divide + */ + +static bool op_smlad(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + if (sub) { + /* This subtraction cannot overflow. */ + tcg_gen_sub_i32(t1, t1, t2); + } else { + /* + * This addition cannot overflow 32 bits; however it may + * overflow considered as a signed operation, in which case + * we must set the Q flag. + */ + gen_helper_add_setq(t1, cpu_env, t1, t2); + } + tcg_temp_free_i32(t2); + + if (a->ra != 15) { + t2 = load_reg(s, a->ra); + gen_helper_add_setq(t1, cpu_env, t1, t2); + tcg_temp_free_i32(t2); + } + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMLAD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, false); +} + +static bool trans_SMLADX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, false); +} + +static bool trans_SMLSD(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, false, true); +} + +static bool trans_SMLSDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlad(s, a, true, true); +} + +static bool op_smlald(DisasContext *s, arg_rrrr *a, bool m_swap, bool sub) +{ + TCGv_i32 t1, t2; + TCGv_i64 l1, l2; + + if (!ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + if (m_swap) { + gen_swap_half(t2); + } + gen_smul_dual(t1, t2); + + l1 = tcg_temp_new_i64(); + l2 = tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(l1, t1); + tcg_gen_ext_i32_i64(l2, t2); + tcg_temp_free_i32(t1); + tcg_temp_free_i32(t2); + + if (sub) { + tcg_gen_sub_i64(l1, l1, l2); + } else { + tcg_gen_add_i64(l1, l1, l2); + } + tcg_temp_free_i64(l2); + + gen_addq(s, l1, a->ra, a->rd); + gen_storeq_reg(s, a->ra, a->rd, l1); + tcg_temp_free_i64(l1); + return true; +} + +static bool trans_SMLALD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, false); +} + +static bool trans_SMLALDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, false); +} + +static bool trans_SMLSLD(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, false, true); +} + +static bool trans_SMLSLDX(DisasContext *s, arg_rrrr *a) +{ + return op_smlald(s, a, true, true); +} + +static bool op_smmla(DisasContext *s, arg_rrrr *a, bool round, bool sub) +{ + TCGv_i32 t1, t2; + TCGv_i64 tmp64; + + if (s->thumb + ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP) + : !ENABLE_ARCH_6) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + tmp64 = gen_muls_i64_i32(t1, t2); + + if (a->ra != 15) { + t1 = load_reg(s, a->ra); + if (sub) { + tmp64 = gen_subq_msw(tmp64, t1); + } else { + tmp64 = gen_addq_msw(tmp64, t1); + } + } + if (round) { + tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); + } + t1 = tcg_temp_new_i32(); + tcg_gen_extrh_i64_i32(t1, tmp64); + tcg_temp_free_i64(tmp64); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SMMLA(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, false); +} + +static bool trans_SMMLAR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, false); +} + +static bool trans_SMMLS(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, false, true); +} + +static bool trans_SMMLSR(DisasContext *s, arg_rrrr *a) +{ + return op_smmla(s, a, true, true); +} + +static bool op_div(DisasContext *s, arg_rrr *a, bool u) +{ + TCGv_i32 t1, t2; + + if (s->thumb + ? !dc_isar_feature(thumb_div, s) + : !dc_isar_feature(arm_div, s)) { + return false; + } + + t1 = load_reg(s, a->rn); + t2 = load_reg(s, a->rm); + if (u) { + gen_helper_udiv(t1, t1, t2); + } else { + gen_helper_sdiv(t1, t1, t2); + } + tcg_temp_free_i32(t2); + store_reg(s, a->rd, t1); + return true; +} + +static bool trans_SDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, false); +} + +static bool trans_UDIV(DisasContext *s, arg_rrr *a) +{ + return op_div(s, a, true); +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rm, rs, rn, rd; + unsigned int cond, val, op1, i, rn, rd; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; - TCGv_i64 tmp64; /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -9802,144 +10003,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) switch(op1) { case 0x0: case 0x1: - /* multiplies, extra load/stores */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - break; case 0x4: case 0x5: - goto do_ldst; case 0x6: case 0x7: - if (insn & (1 << 4)) { - ARCH(6); - /* Armv6 Media instructions. */ - rm = insn & 0xf; - rn = (insn >> 16) & 0xf; - rd = (insn >> 12) & 0xf; - rs = (insn >> 8) & 0xf; - switch ((insn >> 23) & 3) { - case 0: /* Parallel add/subtract. */ - /* Done by decodetree */ - goto illegal_op; - case 1: - /* Halfword pack, [US]SAT, [US]SAT16, SEL, REV et al */ - /* Done by decodetree */ - goto illegal_op; - case 2: /* Multiplies (Type 3). */ - switch ((insn >> 20) & 0x7) { - case 5: - if (((insn >> 6) ^ (insn >> 7)) & 1) { - /* op2 not 00x or 11x : UNDEF */ - goto illegal_op; - } - /* Signed multiply most significant [accumulate]. - (SMMUL, SMMLA, SMMLS) */ - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - tmp64 = gen_muls_i64_i32(tmp, tmp2); - - if (rd != 15) { - tmp = load_reg(s, rd); - if (insn & (1 << 6)) { - tmp64 = gen_subq_msw(tmp64, tmp); - } else { - tmp64 = gen_addq_msw(tmp64, tmp); - } - } - if (insn & (1 << 5)) { - tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); - } - tcg_gen_shri_i64(tmp64, tmp64, 32); - tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - store_reg(s, rn, tmp); - break; - case 0: - case 4: - /* SMLAD, SMUAD, SMLSD, SMUSD, SMLALD, SMLSLD */ - if (insn & (1 << 7)) { - goto illegal_op; - } - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - if (insn & (1 << 5)) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* smlald, smlsld */ - TCGv_i64 tmp64_2; - - tmp64 = tcg_temp_new_i64(); - tmp64_2 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_gen_ext_i32_i64(tmp64_2, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - if (insn & (1 << 6)) { - tcg_gen_sub_i64(tmp64, tmp64, tmp64_2); - } else { - tcg_gen_add_i64(tmp64, tmp64, tmp64_2); - } - tcg_temp_free_i64(tmp64_2); - gen_addq(s, tmp64, rd, rn); - gen_storeq_reg(s, rd, rn, tmp64); - tcg_temp_free_i64(tmp64); - } else { - /* smuad, smusd, smlad, smlsd */ - if (insn & (1 << 6)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a - * signed operation, in which case we must set - * the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - if (rd != 15) - { - tmp2 = load_reg(s, rd); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - store_reg(s, rn, tmp); - } - break; - case 1: - case 3: - /* SDIV, UDIV */ - if (!dc_isar_feature(arm_div, s)) { - goto illegal_op; - } - if (((insn >> 5) & 7) || (rd != 15)) { - goto illegal_op; - } - tmp = load_reg(s, rm); - tmp2 = load_reg(s, rs); - if (insn & (1 << 21)) { - gen_helper_udiv(tmp, tmp, tmp2); - } else { - gen_helper_sdiv(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rn, tmp); - break; - default: - goto illegal_op; - } - break; - case 3: - /* USAD, BFI, BFC, SBFX, UBFX */ - /* Done by decodetree */ - goto illegal_op; - } - break; - } - do_ldst: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0x08: @@ -10163,7 +10230,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; - TCGv_i64 tmp64; int op; /* @@ -10429,132 +10495,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 2: /* SIMD add/subtract, in decodetree */ case 3: /* Other data processing, in decodetree */ goto illegal_op; - case 4: case 5: /* 32-bit multiply. Sum of absolute differences. */ - switch ((insn >> 20) & 7) { - case 0: /* 32 x 32 -> 32 */ - case 1: /* 16 x 16 -> 32 */ - case 3: /* 32 * 16 -> 32msb */ - case 7: /* Unsigned sum of absolute differences. */ - /* in decodetree */ - goto illegal_op; - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - goto illegal_op; - } - break; - } - op = (insn >> 4) & 0xf; - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - switch ((insn >> 20) & 7) { - case 2: /* Dual multiply add. */ - case 4: /* Dual multiply subtract. */ - if (op) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (insn & (1 << 22)) { - /* This subtraction cannot overflow. */ - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - /* This addition cannot overflow 32 bits; - * however it may overflow considered as a signed - * operation, in which case we must set the Q flag. - */ - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - if (rs != 15) - { - tmp2 = load_reg(s, rs); - gen_helper_add_setq(tmp, cpu_env, tmp, tmp2); - tcg_temp_free_i32(tmp2); - } - break; - case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */ - tmp64 = gen_muls_i64_i32(tmp, tmp2); - if (rs != 15) { - tmp = load_reg(s, rs); - if (insn & (1 << 20)) { - tmp64 = gen_addq_msw(tmp64, tmp); - } else { - tmp64 = gen_subq_msw(tmp64, tmp); - } - } - if (insn & (1 << 4)) { - tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u); - } - tcg_gen_shri_i64(tmp64, tmp64, 32); - tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, tmp64); - tcg_temp_free_i64(tmp64); - break; - } - store_reg(s, rd, tmp); - break; - case 6: case 7: /* 64-bit multiply, Divide. */ - op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70); - tmp = load_reg(s, rn); - tmp2 = load_reg(s, rm); - if ((op & 0x50) == 0x10) { - /* sdiv, udiv */ - if (!dc_isar_feature(thumb_div, s)) { - goto illegal_op; - } - if (op & 0x20) - gen_helper_udiv(tmp, tmp, tmp2); - else - gen_helper_sdiv(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - } else if ((op & 0xe) == 0xc) { - /* Dual multiply accumulate long. */ - if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - goto illegal_op; - } - if (op & 1) - gen_swap_half(tmp2); - gen_smul_dual(tmp, tmp2); - if (op & 0x10) { - tcg_gen_sub_i32(tmp, tmp, tmp2); - } else { - tcg_gen_add_i32(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - /* BUGFIX */ - tmp64 = tcg_temp_new_i64(); - tcg_gen_ext_i32_i64(tmp64, tmp); - tcg_temp_free_i32(tmp); - gen_addq(s, tmp64, rs, rd); - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); - } else { - if (op & 0x20) { - /* Unsigned 64-bit multiply */ - tmp64 = gen_mulu_i64_i32(tmp, tmp2); - } else { - if (op & 8) { - /* smlalxy, in decodetree */ - goto illegal_op; - } else { - /* Signed 64-bit multiply */ - tmp64 = gen_muls_i64_i32(tmp, tmp2); - } - } - if (op & 4) { - /* umaal, in decodetree */ - goto illegal_op; - } else if (op & 0x40) { - /* 64-bit accumulate. */ - gen_addq(s, tmp64, rs, rd); - } - gen_storeq_reg(s, rs, rd, tmp64); - tcg_temp_free_i64(tmp64); - } - break; + case 4: case 5: + /* 32-bit multiply. Sum of absolute differences, in decodetree */ + goto illegal_op; + case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ + goto illegal_op; } break; case 6: case 7: case 14: case 15: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 725e627796..c5af685585 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -486,3 +486,25 @@ REV .... 0110 1011 1111 .... 1111 0011 .... @rdm REV16 .... 0110 1011 1111 .... 1111 1011 .... @rdm REVSH .... 0110 1111 1111 .... 1111 1011 .... @rdm RBIT .... 0110 1111 1111 .... 1111 0011 .... @rdm + +# Signed multiply, signed and unsigned divide + +@rdmn ---- .... .... rd:4 .... rm:4 .... rn:4 &rrr + +SMLAD .... 0111 0000 .... .... .... 0001 .... @rdamn +SMLADX .... 0111 0000 .... .... .... 0011 .... @rdamn +SMLSD .... 0111 0000 .... .... .... 0101 .... @rdamn +SMLSDX .... 0111 0000 .... .... .... 0111 .... @rdamn + +SDIV .... 0111 0001 .... 1111 .... 0001 .... @rdmn +UDIV .... 0111 0011 .... 1111 .... 0001 .... @rdmn + +SMLALD .... 0111 0100 .... .... .... 0001 .... @rdamn +SMLALDX .... 0111 0100 .... .... .... 0011 .... @rdamn +SMLSLD .... 0111 0100 .... .... .... 0101 .... @rdamn +SMLSLDX .... 0111 0100 .... .... .... 0111 .... @rdamn + +SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn +SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn +SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn +SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ea147e5348..68203e3704 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -228,6 +228,24 @@ SMLALTT 1111 1011 1100 .... .... .... 1011 .... @rnadm # usad8 is usada8 w/ ra=15 USADA8 1111 1011 0111 .... .... .... 0000 .... @rnadm +SMLAD 1111 1011 0010 .... .... .... 0000 .... @rnadm +SMLADX 1111 1011 0010 .... .... .... 0001 .... @rnadm +SMLSD 1111 1011 0100 .... .... .... 0000 .... @rnadm +SMLSDX 1111 1011 0100 .... .... .... 0001 .... @rnadm + +SMLALD 1111 1011 1100 .... .... .... 1100 .... @rnadm +SMLALDX 1111 1011 1100 .... .... .... 1101 .... @rnadm +SMLSLD 1111 1011 1101 .... .... .... 1100 .... @rnadm +SMLSLDX 1111 1011 1101 .... .... .... 1101 .... @rnadm + +SMMLA 1111 1011 0101 .... .... .... 0000 .... @rnadm +SMMLAR 1111 1011 0101 .... .... .... 0001 .... @rnadm +SMMLS 1111 1011 0110 .... .... .... 0000 .... @rnadm +SMMLSR 1111 1011 0110 .... .... .... 0001 .... @rnadm + +SDIV 1111 1011 1001 .... 1111 .... 1111 .... @rndm +UDIV 1111 1011 1011 .... 1111 .... 1111 .... @rndm + # Data-processing (two source registers) QADD 1111 1010 1000 .... 1111 .... 1000 .... @rndm From patchwork Fri Jul 26 17:49:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169894 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp359764ilk; Fri, 26 Jul 2019 10:57:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqxKN6bSxCrQS9TBKdKqv0Ahz0zs+dfkHjXZ3tyOzbaI4zUY+rZICDrQvKDFvEXq8ddHw49t X-Received: by 2002:a50:f98a:: with SMTP id q10mr83762819edn.267.1564163857921; Fri, 26 Jul 2019 10:57:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163857; cv=none; d=google.com; s=arc-20160816; b=kRjzrj3RXYaV6R3ifSOoCKq2wD+o35dGH3TK2dUewJZ6RJAC1npwSopPVW6czeOhBK Frzs9wUXW/VnzwlaWj5wcLGlUDDdfP26+cs8J1S6BETwUS5LTleDW8hXn6sGw43lUylf faVCBvGJKg0EljXUgXAJnu1c7ndADZoRXvrvLK/kOXJNoCb87XXLd+BLdZPse5BgxFMp yYVdE/W9oZsbINu23+EbXXsxVPji9p1yw0iuQQw2q8rS/dAqJRbOdIfcJI5cdVTcJwor LgmPi6TdKLno6a1VMFWrcclVGpFZjrfYUp+/zBvhkTtBAHRA1iWmCSkpNdCLGXnIZNA2 mmIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=S4Q7S2OdhUkyh4FYS2Teg9nr51SAo2OgSkvWrjYq2oc=; b=sv3HLSlTxH2PxKbFfGyq2nG9IDB2qHTZl23Ku04aHgC6eythEyl/vbkIzxSotZ3jGt RjrCyfy3YuMs0QaqrvqQWTvPe04i7dK8kJZ/zIPpeRkGIO+FxEoIHCJQ7KBzOgIgVyLo yx4XnTulJVzI3wqyQPNPPwUWgVAc8F6lBW1xPWKnLB1AkTB1hzCzzSODRPesi/R9+Idb oN/TYARSFwmvy5WM5U6vpWykO6ORj1ndoMJC7s50HNT/u+/KJZr85yVLr4RG2UMHfd+j YqW9hDwLzL9omxdjrtyZZ9XCq1uSnL5MJGnat8Tnvm69ABXulSVrupKH0iW6NLqIgs6m TeiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yAlfUCLG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jp7si11184189ejb.38.2019.07.26.10.57.37 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:57:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yAlfUCLG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4TG-0005Xe-AP for patch@linaro.org; Fri, 26 Jul 2019 13:57:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58282) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NB-0004DZ-K4 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4N7-0000Em-Ve for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:15 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:46601) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4N5-0008UB-Tf for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:12 -0400 Received: by mail-pl1-x629.google.com with SMTP id c2so24992782plz.13 for ; Fri, 26 Jul 2019 10:51:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=S4Q7S2OdhUkyh4FYS2Teg9nr51SAo2OgSkvWrjYq2oc=; b=yAlfUCLGaE+K/ycrFuqkUrax+2KjApxCrDsxWgJP8krVVSNuMV0OY129PFHRt7NUfb MZ+pO47e+xOb6q4dwfQb8dDryP+hGi9T7iK4rnsztrOBVEfpt1vinn7xTEpp+TqT6oYw VRpWunzO/rNOE7ItF3wc8O8+loGldHc9q4kFTXpP0VetRFtAIcrkZZkLt/wLGboalAO9 UQPfxBKLEgmaUIA3qj2AflhCfcID6o2bFDn3uUMzBhQIK6oa6s8J+MgBleEqoAAC/QmQ T0amOkHxIaGi//H61V7UqQ1UpWTJPZs7Vo2R3OzSgg7crrASDUKzs9CMCH62y0nNr0Fw yeGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=S4Q7S2OdhUkyh4FYS2Teg9nr51SAo2OgSkvWrjYq2oc=; b=qnkFTt8BdRNyeKym4wIGeBJjPNLiMzuQohQBhQwFKehaTy0tHe8a3whxQH3ukempeF 5WcOBhNc+WQTIUMg7r0tVwIXyzEVNYzR6NrPVzgmHJM7BSJt7AG9+28v3Z2gV/Q1t/qH VXRlJvfBl9b+6Cgi0TtBC/ZvNLL0aOa+hGKt7qrRjocsQVjTkggLDn/tAlfjo94NpfDm C5MlXZWPGnZi97Ch50seKB/bb4ehJOntrvDm0XTsolKDVuJ2ON6WNtY7UQFbIwxo3UGq Yb0bhZAYg6uvEBasJLQ9bCNYDcm6xyPFehuhduuDwiunYMigdeygMZMD443thX/hMMmP agXQ== X-Gm-Message-State: APjAAAXVDeNyloSrH0QnMMPUE04ldqFRq0URbi1cSPWj90QOb7Yov3dO zVZeyHo27VUeanqMvi9pCV1upTAt160= X-Received: by 2002:a17:902:d70a:: with SMTP id w10mr92326794ply.251.1564163467636; Fri, 26 Jul 2019 10:51:07 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.06 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:53 -0700 Message-Id: <20190726175032.6769-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::629 Subject: [Qemu-devel] [PATCH 28/67] target/arm: Convert MOVW, MOVT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 89 ++++++++++++++++-------------------------- target/arm/a32.decode | 6 +++ target/arm/t32.decode | 9 +++++ 3 files changed, 48 insertions(+), 56 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5bdec27265..ee97a0ccdd 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7919,6 +7919,34 @@ static bool trans_ADR(DisasContext *s, arg_ri *a) return true; } +static bool trans_MOVW(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp = tcg_const_i32(a->imm); + store_reg(s, a->rd, tmp); + return true; +} + +static bool trans_MOVT(DisasContext *s, arg_MOVW *a) +{ + TCGv_i32 tmp; + + if (!ENABLE_ARCH_6T2) { + return false; + } + + tmp = load_reg(s, a->rd); + tcg_gen_ext16u_i32(tmp, tmp); + tcg_gen_ori_i32(tmp, tmp, a->imm << 16); + store_reg(s, a->rd, tmp); + return true; +} + /* * Multiply and multiply accumulate */ @@ -9720,7 +9748,7 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn, rd; + unsigned int cond, val, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -9966,26 +9994,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) /* fall back to legacy decoder */ if ((insn & 0x0f900000) == 0x03000000) { - if ((insn & (1 << 21)) == 0) { - ARCH(6T2); - rd = (insn >> 12) & 0xf; - val = ((insn >> 4) & 0xf000) | (insn & 0xfff); - if ((insn & (1 << 22)) == 0) { - /* MOVW */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, val); - } else { - /* MOVT */ - tmp = load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, val << 16); - } - store_reg(s, rd, tmp); - } else { - /* MSR (immediate) and hints */ - /* All done in decodetree. Illegal ops already signalled. */ - g_assert_not_reached(); - } + /* All done in decodetree. Illegal ops reach here. */ + goto illegal_op; } else if ((insn & 0x0f900000) == 0x01000000 && (insn & 0x00000090) != 0x00000090) { /* miscellaneous instructions */ @@ -10725,42 +10735,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx * - Data-processing (modified immediate, plain binary immediate) + * All in decodetree. */ - if (insn & (1 << 25)) { - /* - * 0b1111_0x1x_xxxx_0xxx_xxxx_xxxx - * - Data-processing (plain binary immediate) - */ - if (insn & (1 << 24)) { - /* Bitfield/Saturate, in decodetree */ - goto illegal_op; - } else { - imm = ((insn & 0x04000000) >> 15) - | ((insn & 0x7000) >> 4) | (insn & 0xff); - if (insn & (1 << 22)) { - /* 16-bit immediate. */ - imm |= (insn >> 4) & 0xf000; - if (insn & (1 << 23)) { - /* movt */ - tmp = load_reg(s, rd); - tcg_gen_ext16u_i32(tmp, tmp); - tcg_gen_ori_i32(tmp, tmp, imm << 16); - } else { - /* movw */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, imm); - } - store_reg(s, rd, tmp); - } else { - /* Add/sub 12-bit immediate, in decodetree */ - goto illegal_op; - } - } - } else { - /* Data-processing (modified immediate) */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } + goto illegal_op; } break; case 12: diff --git a/target/arm/a32.decode b/target/arm/a32.decode index c5af685585..02d7e5b202 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -73,6 +73,12 @@ MOV_rrri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi MVN_rrri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi +%imm16 16:4 0:12 +@mov16 ---- .... .... .... rd:4 ............ &ri imm=%imm16 + +MOVW .... 0011 0000 .... .... ............ @mov16 +MOVT .... 0011 0100 .... .... ............ @mov16 + # Data-processing (register-shifted register) @s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \ diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 68203e3704..fdcfb60cc5 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -150,6 +150,15 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12 } +# Move Wide + +%imm16_26_16_12_0 16:4 26:1 12:3 0:8 +@mov16 .... .... .... .... .... rd:4 .... .... \ + &ri imm=%imm16_26_16_12_0 + +MOVW 1111 0.10 0100 .... 0 ... .... ........ @mov16 +MOVT 1111 0.10 1100 .... 0 ... .... ........ @mov16 + # Saturate, bitfield @sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \ From patchwork Fri Jul 26 17:49:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169900 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp360905ilk; Fri, 26 Jul 2019 10:58:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqxr27GBM+kwnjIvJeV0pc6QUxwQhG3fJ1q2dTeT5ZedwqsHSNevED4dzEptimDFYdSVlkts X-Received: by 2002:ac8:333d:: with SMTP id t58mr69049605qta.167.1564163934705; Fri, 26 Jul 2019 10:58:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163934; cv=none; d=google.com; s=arc-20160816; b=Z8C8QlNwR8eoLCJjRUzq4zXYQ+sJYOBu2rwT/Mw9uGmYWhGT1y+MY65AShc8JUO8Vo A+IYfqCXu5xBIUNwjFRCUEmbWASWlDUxVm6Z0MM5+uJhCOlFLgrxQZGzcFmqYOthqW+V Jmm/QZHfYoLck2IMSnLk720wq8FYODf74ZCwsAdszCESiFiwHp4q+U1ix5lwQym9pVRi WEL1EnYmNqdiIs65qbrLxvJpmFIaufUzlny/rnXbnkKbMPLo+n4zUxOMhTlzfzijWKYj ddY1oTc3gW7bNkNZCFAba6SsG7nmtvyJfUtiF1B7U9kJNBoHenKaoz3eUyvocTyss09D kx6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=7tTsGJIDF0bTmlDGx9oqoy4yU2XiArhYoVylWwae3nM=; b=jLs6llww8B8h1y2nwaZwAMq3Qee+hVjZaM7+CwagKg6ns0i4Lq2pzN+0yTzl5F1CiQ MT6EIutyJ0yG9bbiz3MpQ4SoT9pAX7jKygWlLBYHfQJWYsxBQaqDet3c0AhMqs34I1sV xEGlUpSjLXVAX4oBBmoSYE349ZNLIdPD1PkKesJDo1+5ENmvl/h8tVuqfTp/VnzA/90C /IEUuNvMbnTthAnvkPOwR60gJtUWo2xf/y9CamPVY6quYgE7zO9D5CQbfP7sMfuuLK7H Yi5/7hYFQ7dNq+fignCUhzKTkYG4FFlU8gcLvBzA7HTFOiTfRaM+i6jW2mfm3FYGAlJL zODg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gRKxzn4P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g1si31458918qki.181.2019.07.26.10.58.54 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:58:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=gRKxzn4P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4UW-0002c3-R2 for patch@linaro.org; Fri, 26 Jul 2019 13:58:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58373) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NF-0004WT-Uf for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4N9-0000H1-PM for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:19 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:40196) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4N6-00005e-CC for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:13 -0400 Received: by mail-pl1-x634.google.com with SMTP id a93so24972511pla.7 for ; Fri, 26 Jul 2019 10:51:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7tTsGJIDF0bTmlDGx9oqoy4yU2XiArhYoVylWwae3nM=; b=gRKxzn4PotW6Bf7coh2phGb7sGYj4rkpoLQYg5zKo8a62PIMbO7oAPUn2SOiiwmlSE k1t+dM6oahegAlf4uvCSUMkcZYVcjEvDpoKvlWoa6eXWF2elkK36bZZDI3dCXf86aqti BiGArORg9BQSU6K7e9ZZOyTKCYaEp8bVpbt8gLVCoq9t5/MvgtGqp0sagpVC4HN9F0fR dWexDkblloOfCyAQZJD3sIkJweSaibe1cZi1L+c6qI2aqh9o7FWSOz/QAQCYu0cQHr+2 gCRXO+GUt9cdcSGP5f3mSjyg503qKQ9P2ejhYugQUPYgfi8z0pwxBRbhSE5QJzAYljNZ PFaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7tTsGJIDF0bTmlDGx9oqoy4yU2XiArhYoVylWwae3nM=; b=EQEiG2RARXwzOx8Tusr8VDcvnU2iA+Mz+j65VitpjHgYHNeG2kFMwxccJwWzVM+4cE fcpeEHWS3tE7MMfFvOWz8soTXMZNsR2vRyHZkBmYm9xHJNomlEcFWNnn2lpwrFzFM2rX OTTILLCiS8svS7uMd4htUnuSDSaPRO98c8Qs5gDVf7GOMwhK789o2xWFi6FAINgz3kRs EdlfR2LZq15aRRi2MhvdIbzrPf+yBDvjTe/uuFuO0kiL2EcNxdGnbOB4bFZhvFdNmAhN I1WUdyClF2QPWHq93sN22CniW6KZV3owjOq8bCDrpH1dwvN53giCgt8Iukm8OnxESFir WJmg== X-Gm-Message-State: APjAAAVb1fs4uf7Yh9h7eQJBtow5UfA4nqPSfEOxbgo8gel+xo++jMe/ C5dCtHzxSwOKjXKSA9Kgt5DOsXlyXCw= X-Received: by 2002:a17:902:7791:: with SMTP id o17mr98752380pll.27.1564163468781; Fri, 26 Jul 2019 10:51:08 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.07 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:54 -0700 Message-Id: <20190726175032.6769-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::634 Subject: [Qemu-devel] [PATCH 29/67] target/arm: Convert LDM, STM X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While unifying all of these paths, remove the constrained unpredictable test for "wback && registers == 1" from the T2 encoding that isn't constrained unpredictable for the A1 encoding. The A1 behaviour is allowed for the T2 behaviour. Signed-off-by: Richard Henderson --- target/arm/translate.c | 388 ++++++++++++++++++++--------------------- target/arm/a32.decode | 6 + target/arm/t32.decode | 10 ++ 3 files changed, 206 insertions(+), 198 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index ee97a0ccdd..33daf70d5d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9742,6 +9742,192 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a) return op_div(s, a, true); } +/* + * Block data transfer + */ + +static TCGv_i32 op_addr_block_pre(DisasContext *s, arg_ldst_block *a, int n) +{ + TCGv_i32 addr = load_reg(s, a->rn); + + if (a->b) { + if (a->i) { + /* pre increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n != 1) { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + + if (s->v8m_stackcheck && a->rn == 13 && a->w) { + /* + * If the writeback is incrementing SP rather than + * decrementing it, and the initial SP is below the + * stack limit but the final written-back SP would + * be above, then then we must not perform any memory + * accesses, but it is IMPDEF whether we generate + * an exception. We choose to do so in this case. + * At this point 'addr' is the lowest address, so + * either the original SP (if incrementing) or our + * final SP (if decrementing), so that's what we check. + */ + gen_helper_v8m_stackcheck(cpu_env, addr); + } + + return addr; +} + +static void op_addr_block_post(DisasContext *s, arg_ldst_block *a, + TCGv_i32 addr, int n) +{ + if (a->w) { + /* write back */ + if (!a->b) { + if (a->i) { + /* post increment */ + tcg_gen_addi_i32(addr, addr, 4); + } else { + /* post decrement */ + tcg_gen_addi_i32(addr, addr, -(n * 4)); + } + } else if (!a->i && n != 1) { + /* pre decrement */ + tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } +} + +static bool trans_STM(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, list, mem_idx; + TCGv_i32 addr, tmp, tmp2; + bool user = a->u; + + if (user) { + /* STM (user) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + return false; + } + } + + /* compute total size */ + list = a->list; + n = ctpop16(list); + mem_idx = get_mem_index(s); + + addr = op_addr_block_pre(s, a, n); + for (i = j = 0; i < 16; i++) { + if (((list >> i) & 1) == 0) { + continue; + } + if (user && i != 15) { + tmp = tcg_temp_new_i32(); + tmp2 = tcg_const_i32(i); + gen_helper_get_user_reg(tmp, cpu_env, tmp2); + tcg_temp_free_i32(tmp2); + } else { + tmp = load_reg(s, i); + } + gen_aa32_st32(s, tmp, addr, mem_idx); + tcg_temp_free_i32(tmp); + /* No need to add after the last transfer. */ + if (++j != n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + return true; +} + +static bool trans_LDM(DisasContext *s, arg_ldst_block *a) +{ + int i, j, n, mem_idx, loaded_base; + int list = a->list; + bool user = a->u; + bool exc_return = false; + TCGv_i32 addr, tmp, tmp2, loaded_var; + + if (user) { + /* LDM (user), LDM (exception return) */ + if (IS_USER(s)) { + /* Only usable in supervisor mode. */ + return false; + } + if (extract32(a->list, 15, 1)) { + exc_return = true; + user = false; + } else { + /* LDM (User) does not allow W set. */ + if (a->w) { + return false; + } + } + } + + /* compute total size */ + loaded_base = 0; + loaded_var = NULL; + n = ctpop16(list); + mem_idx = get_mem_index(s); + + addr = op_addr_block_pre(s, a, n); + for (i = j = 0; i < 16; i++) { + if (((list >> i) & 1) == 0) { + continue; + } + tmp = tcg_temp_new_i32(); + gen_aa32_ld32u(s, tmp, addr, mem_idx); + if (user) { + tmp2 = tcg_const_i32(i); + gen_helper_set_user_reg(cpu_env, tmp2, tmp); + tcg_temp_free_i32(tmp2); + tcg_temp_free_i32(tmp); + } else if (i == a->rn) { + loaded_var = tmp; + loaded_base = 1; + } else if (i == 15 && exc_return) { + store_pc_exc_ret(s, tmp); + } else { + store_reg_from_load(s, i, tmp); + } + /* No need to add after the last transfer. */ + if (++j != n) { + tcg_gen_addi_i32(addr, addr, 4); + } + } + + op_addr_block_post(s, a, addr, n); + + if (loaded_base) { + store_reg(s, a->rn, loaded_var); + } + + if (exc_return) { + /* Restore CPSR from SPSR. */ + tmp = load_cpu_field(spsr); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); + } + gen_helper_cpsr_write_eret(cpu_env, tmp); + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + gen_io_end(); + } + tcg_temp_free_i32(tmp); + /* Must exit loop to check un-masked IRQs */ + s->base.is_jmp = DISAS_EXIT; + } + return true; +} + /* * Legacy decoder. */ @@ -10017,139 +10203,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x5: case 0x6: case 0x7: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0x08: case 0x09: - { - int j, n, loaded_base; - bool exc_return = false; - bool is_load = extract32(insn, 20, 1); - bool user = false; - TCGv_i32 loaded_var; - /* load/store multiple words */ - /* XXX: store correct base if write back */ - if (insn & (1 << 22)) { - /* LDM (user), LDM (exception return) and STM (user) */ - if (IS_USER(s)) - goto illegal_op; /* only usable in supervisor mode */ - - if (is_load && extract32(insn, 15, 1)) { - exc_return = true; - } else { - user = true; - } - } - rn = (insn >> 16) & 0xf; - addr = load_reg(s, rn); - - /* compute total size */ - loaded_base = 0; - loaded_var = NULL; - n = 0; - for (i = 0; i < 16; i++) { - if (insn & (1 << i)) - n++; - } - /* XXX: test invalid n == 0 case ? */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - tcg_gen_addi_i32(addr, addr, 4); - } else { - /* post increment */ - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } else { - /* post decrement */ - if (n != 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); - } - } - j = 0; - for (i = 0; i < 16; i++) { - if (insn & (1 << i)) { - if (is_load) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (user) { - tmp2 = tcg_const_i32(i); - gen_helper_set_user_reg(cpu_env, tmp2, tmp); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - } else if (i == rn) { - loaded_var = tmp; - loaded_base = 1; - } else if (i == 15 && exc_return) { - store_pc_exc_ret(s, tmp); - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* store */ - if (user && i != 15) { - tmp = tcg_temp_new_i32(); - tmp2 = tcg_const_i32(i); - gen_helper_get_user_reg(tmp, cpu_env, tmp2); - tcg_temp_free_i32(tmp2); - } else { - tmp = load_reg(s, i); - } - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - j++; - /* no need to add after the last transfer */ - if (j != n) - tcg_gen_addi_i32(addr, addr, 4); - } - } - if (insn & (1 << 21)) { - /* write back */ - if (insn & (1 << 23)) { - if (insn & (1 << 24)) { - /* pre increment */ - } else { - /* post increment */ - tcg_gen_addi_i32(addr, addr, 4); - } - } else { - if (insn & (1 << 24)) { - /* pre decrement */ - if (n != 1) - tcg_gen_addi_i32(addr, addr, -((n - 1) * 4)); - } else { - /* post decrement */ - tcg_gen_addi_i32(addr, addr, -(n * 4)); - } - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (exc_return) { - /* Restore CPSR from SPSR. */ - tmp = load_cpu_field(spsr); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_cpsr_write_eret(cpu_env, tmp); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_end(); - } - tcg_temp_free_i32(tmp); - /* Must exit loop to check un-masked IRQs */ - s->base.is_jmp = DISAS_EXIT; - } - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xa: case 0xb: { @@ -10422,73 +10479,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) insn & (1 << 21)); } } else { - int i, loaded_base = 0; - TCGv_i32 loaded_var; - bool wback = extract32(insn, 21, 1); - /* Load/store multiple. */ - addr = load_reg(s, rn); - offset = 0; - for (i = 0; i < 16; i++) { - if (insn & (1 << i)) - offset += 4; - } - - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck && rn == 13 && wback) { - /* - * If the writeback is incrementing SP rather than - * decrementing it, and the initial SP is below the - * stack limit but the final written-back SP would - * be above, then then we must not perform any memory - * accesses, but it is IMPDEF whether we generate - * an exception. We choose to do so in this case. - * At this point 'addr' is the lowest address, so - * either the original SP (if incrementing) or our - * final SP (if decrementing), so that's what we check. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - loaded_var = NULL; - for (i = 0; i < 16; i++) { - if ((insn & (1 << i)) == 0) - continue; - if (insn & (1 << 20)) { - /* Load. */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == rn) { - loaded_var = tmp; - loaded_base = 1; - } else { - store_reg_from_load(s, i, tmp); - } - } else { - /* Store. */ - tmp = load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if (loaded_base) { - store_reg(s, rn, loaded_var); - } - if (wback) { - /* Base register writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* Fault if writeback register is in register list. */ - if (insn & (1 << rn)) - goto illegal_op; - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } + /* Load/store multiple, in decodetree */ + goto illegal_op; } } break; diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 02d7e5b202..96c47aaf2a 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -40,6 +40,7 @@ &mrs_bank rd r sysm &ldst_rr p w u rn rt rm shimm shtype &ldst_ri p w u rn rt imm +&ldst_block rn i b u w list &strex rn rd rt rt2 imm &ldrex rn rt rt2 imm &bfx rd rn lsb widthm1 @@ -514,3 +515,8 @@ SMMLA .... 0111 0101 .... .... .... 0001 .... @rdamn SMMLAR .... 0111 0101 .... .... .... 0011 .... @rdamn SMMLS .... 0111 0101 .... .... .... 1101 .... @rdamn SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn + +# Block data transfer + +STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block +LDM ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block diff --git a/target/arm/t32.decode b/target/arm/t32.decode index fdcfb60cc5..3ab82c0962 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -37,6 +37,7 @@ &mrs_bank !extern rd r sysm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list &strex !extern rn rd rt rt2 imm &ldrex !extern rn rt rt2 imm &bfx !extern rd rn lsb widthm1 @@ -563,3 +564,12 @@ SXTAB16 1111 1010 0010 .... 1111 .... 10.. .... @rrr_rot UXTAB16 1111 1010 0011 .... 1111 .... 10.. .... @rrr_rot SXTAB 1111 1010 0100 .... 1111 .... 10.. .... @rrr_rot UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot + +# Load/store multiple + +@ldstm .... .... .. w:1 . rn:4 list:16 &ldst_block u=0 + +STM 1110 1000 10.0 .... ................ @ldstm i=1 b=0 +STM 1110 1001 00.0 .... ................ @ldstm i=0 b=1 +LDM 1110 1000 10.1 .... ................ @ldstm i=1 b=0 +LDM 1110 1001 00.1 .... ................ @ldstm i=0 b=1 From patchwork Fri Jul 26 17:49:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169898 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp360470ilk; Fri, 26 Jul 2019 10:58:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqw46us0XN5HPeyVOaFxg16kNK5PZG1VpKzuu8jPwEJnXAyA7Z3K89WNSL2b/kNu1EOlTbSp X-Received: by 2002:ae9:dcc1:: with SMTP id q184mr62221983qkf.61.1564163904099; Fri, 26 Jul 2019 10:58:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163904; cv=none; d=google.com; s=arc-20160816; b=ATgS5bdH9d8uQnhZGu5zTC1PHVfDjJu7xZK5MgAYj+ETXgv+pxnXJY5vgfZYFLHaO/ UiO6DzHTN6cCrgy4iUQHkxunmT1/y1u9IYPrRideTUyYEuXKbDexvrUyDWbhaVfqKbFE jFTiBGAWMVapApqhB7fBIvUw+ezqYcyOVt0oTdMdK14BrBtvOol2lWfayKso1i7Oo4Ns OhIdhHVjpW3K4N29CghzVKCATZgY1iVBPB9euuqrjE09lvPkaknet79XYIbf0GZ9BpIZ h90UYYYxQ99o05FeqBxnDF7WIn1M+yX4Lse6csM9lY+cc5QT789Jy7mcDQs3+4Kcp2Yc 6nFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=7sC4AygPV0WiIiwW7lCQ39zt4aUcLjG0l/PxVVeDVwI=; b=dvJHsyDFDWkONzxLp3nMFn3UEisOL0JOsCxYxozd2LgvfTUc4mUDDYEdZLMkQyh8jr 7Dw0W/E7czVn51/DCUoiRtGC75PWOOpwDd31c2W7c8DgxSUVqHIFHnBodv1BpIb+787O jc2hiyEA/M8X62srkwasrw98IkWvKK6IGWUYRWhSUiZBzViC/l9//RWJHS5R681RSbsg eWVgLqjbPPwHu1GaqinyXosRHO/PdjOM2Y6hTBh/HCPpBBg4eSTDTp6HBa2YSqrmpHQK 6HPjXZr1NoWe0Wl8w2HndPJGRB/6GuUS4082dGjwhC1EBIzDL4wo+QD3Eon0vseAYSYN GoKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="stx/yXoy"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q19si32928963qtk.211.2019.07.26.10.58.23 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:58:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="stx/yXoy"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4U1-0000LL-1u for patch@linaro.org; Fri, 26 Jul 2019 13:58:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58336) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NE-0004S9-P6 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4N9-0000Gm-P2 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:19 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:35370) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4N6-00009K-KD for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:13 -0400 Received: by mail-pl1-x62d.google.com with SMTP id w24so25024574plp.2 for ; Fri, 26 Jul 2019 10:51:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7sC4AygPV0WiIiwW7lCQ39zt4aUcLjG0l/PxVVeDVwI=; b=stx/yXoyHZ3qDZvCGIPUin9oj3MOK/oGTPWca+rQBpB0cNtFHgXl68TGZR7fjyDJFB S5CJkeG8u+Pklt1yK4igGZeOU67cohmKyAvb5SUS9SBLj5Du23soFupaLJlGcvw2r7v5 X9ZXxUexHTvaMv8MNyf8GCwLmHASuKHmDam2WbJimRoaMIOgxq8rjcDqRgoA8Xmk/kOH 4Wk1HV0ZGbRQENsL3i1pze0Je4Nq95jswr4eryZMzkTj8ZRbCnJvvsKhcbGj9hVnz49i U7330NdIHkPkrlbRp4VJfswIlA9MRtoNV5YZc6U4RT8RQ1zyHzwtTN767H5fEmz3p/9Q pgOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7sC4AygPV0WiIiwW7lCQ39zt4aUcLjG0l/PxVVeDVwI=; b=FMNxglvU3RScUtzEOfkV/WM4VxFWWNZG+UjXrGW6NAbrpTBPqCjbPKCRbFFdeJ+Xj5 d7MGCYiUpc7j89R7aCJ93InxvlNr8UvIa2oodUfpSd22FJRRRf+DEJ3p+1qGnyqspjG9 vNveTFtPB9NVA9q0H8ZupTSXpoBTNDBvZqhuDfk+Z8F/x4fFZCDY0rX9BKpeBw4OHuQ6 qGUdDX94E8iyzUsRb5NxxmVBmo27+RQPZw/cESpOQd1D26VAQ7RNq4skyGyWKVCav5ur wVzuWA0NcJE27zwhu8uc5NC7fi1rbhAR/EXYBcz0cG+p2urLXWRvxZ8l2u8iicqaZDQE 5/Aw== X-Gm-Message-State: APjAAAVYWCviVtiyTaH3jbJRn0cvVQPFc1PceVTEYQlmWbFeBDwf021r JQqD1fgA3aALEh+R+KUDangn39TKL+g= X-Received: by 2002:a17:902:100a:: with SMTP id b10mr56845250pla.338.1564163470135; Fri, 26 Jul 2019 10:51:10 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.08 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:55 -0700 Message-Id: <20190726175032.6769-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PATCH 30/67] target/arm: Convert B, BL, BLX (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 134 +++++++++++++++-------------------- target/arm/a32-uncond.decode | 8 +++ target/arm/a32.decode | 8 +++ target/arm/t32.decode | 79 +++++++++++++-------- 4 files changed, 122 insertions(+), 107 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 33daf70d5d..3f14e5c7f3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7582,6 +7582,14 @@ static int t32_expandimm_imm(DisasContext *s, int x) return imm; } +static int t32_branch24(DisasContext *s, int x) +{ + /* Convert J1:J2 at x[22:21] to I2:I1, which involves I=J^~S. */ + x ^= !(x < 0) * (3 << 21); + /* Append the final zero. */ + return x << 1; +} + /* * Include the generated decoders. * Note that the T32 decoder reuses some of the trans_* functions @@ -9928,13 +9936,56 @@ static bool trans_LDM(DisasContext *s, arg_ldst_block *a) return true; } +/* + * Branch, branch with link + */ + +static bool trans_B(DisasContext *s, arg_i *a) +{ + gen_jmp(s, s->pc_read + a->imm); + return true; +} + +static bool trans_B_cond_thumb(DisasContext *s, arg_ci *a) +{ + /* This has cond from encoding, required to be outside IT block. */ + if (a->cond >= 0xe) { + return false; + } + if (s->condexec_mask) { + gen_illegal_op(s); + return true; + } + arm_skip_unless(s, a->cond); + gen_jmp(s, s->pc_read + a->imm); + return true; +} + +static bool trans_BL(DisasContext *s, arg_i *a) +{ + tcg_gen_movi_i32(cpu_R[14], s->pc | s->thumb); + gen_jmp(s, s->pc_read + a->imm); + return true; +} + +static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) +{ + /* For A32, ARCH(5) is checked near the start of the uncond block. */ + if (s->thumb && (a->imm & 2)) { + return false; + } + tcg_gen_movi_i32(cpu_R[14], s->pc | s->thumb); + gen_bx_im(s, (s->pc_read & ~3) + a->imm + !s->thumb); + return true; +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, val, op1, i, rn; + unsigned int cond, op1, i, rn; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10102,21 +10153,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } gen_rfe(s, tmp, tmp2); return; - } else if ((insn & 0x0e000000) == 0x0a000000) { - /* branch link and change to thumb (blx ) */ - int32_t offset; - - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->pc); - store_reg(s, 14, tmp); - /* Sign-extend the 24-bit offset */ - offset = (((int32_t)insn) << 8) >> 8; - val = s->pc_read; - /* offset * 4 + bit24 * 2 + (thumb bit) */ - val += (offset << 2) | ((insn >> 23) & 2) | 1; - /* protected by ARCH(5); above, near the start of uncond block */ - gen_bx_im(s, val); - return; } else if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10205,24 +10241,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x7: case 0x08: case 0x09: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; case 0xa: case 0xb: - { - int32_t offset; - - /* branch (and link) */ - if (insn & (1 << 24)) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, s->pc); - store_reg(s, 14, tmp); - } - offset = sextract32(insn << 2, 0, 26); - val = s->pc_read + offset; - gen_jmp(s, val); - } - break; + /* All done in decodetree. Reach here for illegal ops. */ + goto illegal_op; case 0xc: case 0xd: case 0xe: @@ -10594,32 +10616,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) if (insn & (1 << 15)) { /* Branches, misc control. */ if (insn & 0x5000) { - /* Unconditional branch. */ - /* signextend(hw1[10:0]) -> offset[:12]. */ - offset = ((int32_t)insn << 5) >> 9 & ~(int32_t)0xfff; - /* hw1[10:0] -> offset[11:1]. */ - offset |= (insn & 0x7ff) << 1; - /* (~hw2[13, 11] ^ offset[24]) -> offset[23,22] - offset[24:22] already have the same value because of the - sign extension above. */ - offset ^= ((~insn) & (1 << 13)) << 10; - offset ^= ((~insn) & (1 << 11)) << 11; - - if (insn & (1 << 14)) { - /* Branch and link. */ - tcg_gen_movi_i32(cpu_R[14], s->pc | 1); - } - - offset += s->pc_read; - if (insn & (1 << 12)) { - /* b/bl */ - gen_jmp(s, offset); - } else { - /* blx */ - offset &= ~(uint32_t)2; - /* thumb2 bx, no need to check */ - gen_bx_im(s, offset); - } + /* Unconditional branch, in decodetree */ + goto illegal_op; } else if (((insn >> 23) & 7) == 7) { /* Misc control */ if (insn & (1 << 13)) @@ -10704,24 +10702,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } } else { - /* Conditional branch. */ - op = (insn >> 22) & 0xf; - /* Generate a conditional jump to next instruction. */ - arm_skip_unless(s, op); - - /* offset[11:1] = insn[10:0] */ - offset = (insn & 0x7ff) << 1; - /* offset[17:12] = insn[21:16]. */ - offset |= (insn & 0x003f0000) >> 4; - /* offset[31:20] = insn[26]. */ - offset |= ((int32_t)((insn << 5) & 0x80000000)) >> 11; - /* offset[18] = insn[13]. */ - offset |= (insn & (1 << 13)) << 5; - /* offset[19] = insn[11]. */ - offset |= (insn & (1 << 11)) << 8; - - /* jump to the offset */ - gen_jmp(s, s->pc_read + offset); + /* Conditional branch, in decodetree */ + goto illegal_op; } } else { /* diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 8dee26d3b6..573ac2cf8e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -21,3 +21,11 @@ # All insns that have 0xf in insn[31:28] are decoded here. # All of those that have a COND field in insn[31:28] are in a32.decode # + +&i !extern imm + +# Branch with Link and Exchange + +%imm24h 0:s24 24:1 !function=times_2 + +BLX_i 1111 101 . ........................ &i imm=%imm24h diff --git a/target/arm/a32.decode b/target/arm/a32.decode index 96c47aaf2a..f0f0f50c4e 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -520,3 +520,11 @@ SMMLSR .... 0111 0101 .... .... .... 1111 .... @rdamn STM ---- 100 b:1 i:1 u:1 w:1 0 rn:4 list:16 &ldst_block LDM ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block + +# Branch, branch with link + +%imm26 0:s24 !function=times_4 +@branch ---- .... ........................ &i imm=%imm26 + +B .... 1010 ........................ @branch +BL .... 1011 ........................ @branch diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 3ab82c0962..ab7d7ba100 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -285,46 +285,54 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm %msr_sysm 4:1 8:4 %mrs_sysm 4:1 16:4 %imm16_16_0 16:4 0:12 +%imm21 26:s1 11:1 13:1 16:6 0:11 !function=times_2 +&ci cond imm { + # Group insn[25:23] = 111, which is cond=111x for the branch below, + # or unconditional, which would be illegal for the branch. { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + # Hints + { + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 - # The canonical nop ends in 0000 0000, but the whole rest - # of the space is "reserved hint, behaves as nop". - NOP 1111 0011 1010 1111 1000 0000 ---- ---- - } - # Note that the v7m insn overlaps both the normal and banked insn. - { - MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ + # The canonical nop ends in 0000 0000, but the whole rest + # of the space is "reserved hint, behaves as nop". + NOP 1111 0011 1010 1111 1000 0000 ---- ---- + } + # Note that the v7m insn overlaps both the normal and banked insn. + { + MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ &mrs_bank sysm=%mrs_sysm - MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg - MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 - } - { - MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ + MRS_reg 1111 0011 111 r:1 1111 1000 rd:4 0000 0000 &mrs_reg + MRS_v7m 1111 0011 111 0 1111 1000 rd:4 sysm:8 + } + { + MSR_bank 1111 0011 100 r:1 rn:4 1000 .... 001. 0000 \ &msr_bank sysm=%msr_sysm - MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg - MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 - } - BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r - { - # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for - # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET. - ERET 1111 0011 1101 1110 1000 1111 0000 0000 - SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ + MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg + MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 + } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r + { + # At v6T2, this is the T5 encoding of SUBS PC, LR, #IMM, and works as for + # every other encoding of SUBS. With v7VE, IMM=0 is redefined as ERET. + ERET 1111 0011 1101 1110 1000 1111 0000 0000 + SUB_rri 1111 0011 1101 1110 1000 1111 imm:8 \ &s_rri_rot rot=0 s=1 rd=15 rn=14 - } - SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i - HVC 1111 0111 1110 .... 1000 .... .... .... \ + } + SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i + HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 - UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + UDF 1111 0111 1111 ---- 1010 ---- ---- ---- + } + B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21 } # Load/store (register, immediate, literal) @@ -573,3 +581,12 @@ STM 1110 1000 10.0 .... ................ @ldstm i=1 b=0 STM 1110 1001 00.0 .... ................ @ldstm i=0 b=1 LDM 1110 1000 10.1 .... ................ @ldstm i=1 b=0 LDM 1110 1001 00.1 .... ................ @ldstm i=0 b=1 + +# Branches + +%imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24 +@branch24 ................................ &i imm=%imm24 + +B 1111 0. .......... 10.1 ............ @branch24 +BL 1111 0. .......... 11.1 ............ @branch24 +BLX_i 1111 0. .......... 11.0 ............ @branch24 From patchwork Fri Jul 26 17:49:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169908 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp363164ilk; Fri, 26 Jul 2019 11:00:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqxx2JR3DR5bp7iy7SfFFwcEE89+4ZDqXmNMrCTVQ8ZZ1bs8d/hwAy8uFwcI6GnwcjzIxVXi X-Received: by 2002:a37:a389:: with SMTP id m131mr65817462qke.168.1564164057309; Fri, 26 Jul 2019 11:00:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164057; cv=none; d=google.com; s=arc-20160816; b=mQSt8f8rLw1E/w+HuffVA6B6v760AS3bYYSlUimPJspogYdvzqypGl1t5qki07w2LG aju4EZkF7vtjwWOeYWNfeKVNhozWKqLGMiIqFM+ggv9MBFrxhEgQz640cKBBJfO0qM5j qHdQdJyl6vX1Ug7Ts5Yv8ffDLJcqsf2s9sBIhIPdfYl3m1Y9CHFhraNcvFQWytaHwcIF kwQ4Cjou7cRJ5c/wBmiUQPO1c5iINN5xsyW7eq1CjXT93151JnmmRMZYlFytYVx4RRB4 pK+ITxIy1oS65ZJxLesHQKDVhU9+p7fcqoy+kfBy//hTpnbAsUVZgLLg6rXR3IK1JWWl KGgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=BMsZb1YBUEkHFwRh2YB1z1GO0sYcNt67hSkjhh9u9CQ=; b=qlUyaS03VB+z0cx/+hIVJm5novUmoXJPnD5/aF7QTyh0TIxZL09vwlPbPY8GLOydY5 d9f4Pofa85kqPUmjvkUxUnluYU2V5nh/HVyoUD2YkXu5Jac/UXcW3soGeZUm/fkiczkJ BnfKYHScxipIcCZoGGM6spcKwxQOaUkZZJb2yqfoqaKmS2BxxPsMtwJWEtCmXmpiQOtM tLEfI22SGCPAtwHkmUE5dl04gj8QzwPmTPTOndJdUdVGbgnCSR3zOeeDn7MZn9hyZyJ8 UmV57BhlmRZZDVsOhCNatGpDC69Kq+npXG5XveC5xibU/OZfmhUZZmY8UaP23sHqUSz1 wc2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mi5iMrWG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a193si10819726qkc.324.2019.07.26.11.00.57 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:00:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=mi5iMrWG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4WV-0001Rk-1p for patch@linaro.org; Fri, 26 Jul 2019 14:00:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58413) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NH-0004ZC-Kb for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NF-0000Ni-Ez for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:22 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:35672) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NE-0000CC-Fw for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:20 -0400 Received: by mail-pf1-x434.google.com with SMTP id u14so24877954pfn.2 for ; Fri, 26 Jul 2019 10:51:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BMsZb1YBUEkHFwRh2YB1z1GO0sYcNt67hSkjhh9u9CQ=; b=mi5iMrWGCckm2qAJEelgKpFU5RQeFtlvjRdAG3uF/g8cPqEcYsYMp6Ewb2jnN9DITj dplcSyTTrSSmw8PjN76+0yBAlDaB36wTCEU8vkdWu3Gh5C0QLEHkbg0Y0ThX9GhW72Vc zvVnrhS17n6ZhckRCeolIIacRX56xk0gSJ2H7iaQYz94ET+CBR3heLseAD1tfhvgCzDe vgI1IOm6GLwuKwKN+Kuab0Vt27U+/VhFzsb9SOInNoLGbLePpbRVduT1rfBterlpqTPT /js+TS3eM/OBIf/CVTXOggaIdlBNV5C5QCvUscDp57FEw5wCKpsDD3HDvbcEA3w/zX6d zFNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BMsZb1YBUEkHFwRh2YB1z1GO0sYcNt67hSkjhh9u9CQ=; b=LL7lZgGF8+hzCLgvwCH1TXYlRx9WaRWdGCC1unkDBJ74hx5MrNuSrN14Pstt5Lps5h +7GuoIBfLn6ggJjuuiGbrrzcZ6DQmUqvEk8MOlvNI08rqTtiW3Kkf5TLjZCyp5GLI/hh Eil2yW9ayiyUCaW0CEjO1tQYI24e/F93K0V00yTHiZFhRMReVOe6O5rfG88j8XDoiSNF 2wwcccy6Qhr/aZAw2HrdILw/2ce+0y8PBaKxr6/PI90yC6wbNzlHU0yuZijStvg+C9eD HBtnL9OF3JDfesHdSNzJrNxfF2SFsbmXN8um8FayojCLzkc1VwuApcMxoa/83fY+60M3 RlbA== X-Gm-Message-State: APjAAAVofr5Lsv8nsciRerwfGbgvj0duWULZ7f3yFYdfFIhuPQpM7Hik YByQcs0BQ5hzr1bFYsfX7hWLMok737c= X-Received: by 2002:a62:2f06:: with SMTP id v6mr23655611pfv.195.1564163471371; Fri, 26 Jul 2019 10:51:11 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.10 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:56 -0700 Message-Id: <20190726175032.6769-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::434 Subject: [Qemu-devel] [PATCH 31/67] target/arm: Convert SVC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 19 +++++++++++++------ target/arm/a32.decode | 4 ++++ 2 files changed, 17 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 3f14e5c7f3..7ea118a795 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9979,6 +9979,18 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) return true; } +/* + * Supervisor call + */ + +static bool trans_SVC(DisasContext *s, arg_SVC *a) +{ + gen_set_pc_im(s, s->pc); + s->svc_imm = a->imm; + s->base.is_jmp = DISAS_SWI; + return true; +} + /* * Legacy decoder. */ @@ -10243,6 +10255,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) case 0x09: case 0xa: case 0xb: + case 0xf: /* All done in decodetree. Reach here for illegal ops. */ goto illegal_op; case 0xc: @@ -10258,12 +10271,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) goto illegal_op; } break; - case 0xf: - /* swi */ - gen_set_pc_im(s, s->pc); - s->svc_imm = extract32(insn, 0, 24); - s->base.is_jmp = DISAS_SWI; - break; default: illegal_op: gen_illegal_op(s); diff --git a/target/arm/a32.decode b/target/arm/a32.decode index f0f0f50c4e..c2fb28f235 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -528,3 +528,7 @@ LDM ---- 100 b:1 i:1 u:1 w:1 1 rn:4 list:16 &ldst_block B .... 1010 ........................ @branch BL .... 1011 ........................ @branch + +# Supervisor call + +SVC ---- 1111 imm:24 &i From patchwork Fri Jul 26 17:49:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169903 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp361635ilk; Fri, 26 Jul 2019 10:59:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqwEbt/6tjiMz1w8CgXTTm2W+7Kv+BJyCLLsP+rs8ClPBOz/TZZWO1wicI/tsgJlelPzfH3A X-Received: by 2002:a50:a4ad:: with SMTP id w42mr81856949edb.230.1564163983515; Fri, 26 Jul 2019 10:59:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163983; cv=none; d=google.com; s=arc-20160816; b=iXYoRqHFjhaIA2H1aUhLde9iZduI1Ltbk7eskbNsGXhmF99reG17IzTdEIERtG5oR9 e3/V1hI61ifY5qwRlgntaVrK/U/WPlZpN/l/b2Z5hYpYShL4R6JuvShV0TW9t+beyC57 CIrUdI4NpdeGOLOZYUpBMQtDWi1+feR7eduEPOQ9y+HRm0DBzJLq/6XX8TQBH8aD0YRk uapLCXsZJuPqHPFj3gjzMw++JwHab0HBlR1B5s3erkbP4IfUMkdiUFZm2kdNpQweOC9S lWIlvGHF4GlZK+TgD+LOTxSp6lCbJhW+rncSKcDl6R0mnwhuc3dnNZSrMugJwjUbK3o9 GZeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=9vUZl6rgWeXH1YY9hBMz+TVXEkH2e7x0hrOM8enxV9o=; b=WgXFtmo20bUBe7wolX05QGjP81AbLotEQtbbwlUTm+sYALyw4PRjQrRKJ94koyj7i8 D57lhzdDCt8kjOD3RuLiUyjZb0++Wkr4di/sK0lXnuvpUNj//pWBcWvuRii673ddcvEI zBJFgq3miV0bQQBIDAoZ+FfRlFCd6DZEfdPo9OPP8Wrzl7GG9Gt9dN8YD3kbPudyiZJe GZesf5s7aT7utprNZWw0HX6m4mEVPz1j/KzZ43mdbBAPUP14HKupmSHL41Bl3Vvsxsl2 YHQ1H6ikJ53S9M6tPSUvpUijF8OzsyalXlLIGomV+Kl8P3UuOphHreicgJuTwqaoAizP zinQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uUD8jLH2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l11si12991361edb.116.2019.07.26.10.59.43 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:59:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=uUD8jLH2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4VI-000635-U8 for patch@linaro.org; Fri, 26 Jul 2019 13:59:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58360) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NF-0004VW-OC for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4ND-0000LR-LZ for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:21 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:38423) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NB-0000Cu-FI for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:17 -0400 Received: by mail-pf1-x430.google.com with SMTP id y15so24860770pfn.5 for ; Fri, 26 Jul 2019 10:51:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=9vUZl6rgWeXH1YY9hBMz+TVXEkH2e7x0hrOM8enxV9o=; b=uUD8jLH2uTXEyAQE2vjg5gcofjHMYcFoOZOQlE3d3QNnTxp9M2lHr6Q9AqEEwEU/WU DcUStg+cB+EOQElxrpyqPCzYOPOdKYygIf6012cyxZ/BNe+yyrM8IUo1u0Tt9cp/NGxy qN6ffZrS5mGRR1libC/Xfn0JQut6I/CI2bNdZZkaI8W700q5uVjS3g/ehCcHsa5EBGpR OCLfR8VKPJWqwTIJwLXdBsMFSwXeB884Z+hLge8OMaQ4nJh6ubrH+43R51mdPVl6SpW0 CWC7Om8iJi/PoGJRIhJEkadFNM30DEfzSAol/YHGKVACqOS9cSetZXk839MtKMS/rKxt R9Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=9vUZl6rgWeXH1YY9hBMz+TVXEkH2e7x0hrOM8enxV9o=; b=pr2F9zlv6xeAfqDnddo+6eNqzoNpQpgsNTDjx6RFVroRUKEJiCqQNN1jdh9xX+8EOC SP9vJKs3x1e3NOWjz0dCu++3TaiHuX/XiasxUBGEdex2y51TXAPTN+g0W0S8OTbWV+8R z9tGwq08JIFvi8ktlwzoahttL/USDHbk6Lqt7Ri+xNjWJSehoNQCh1wMfoPNbRJcZUyL LreMTAk23ovkufoRvW+cmcMgqpbizH+FuvsZQjTU9IkNOTYatV2ooZ+oIJaRracCSTm4 KvMYDG+zEcNlWUF1CYvLIx4pmVlGI43xfd73W7ymS+7O1mn/UNBEXN6jaB7+USkbWijG HLTA== X-Gm-Message-State: APjAAAXA/fCQGn3rhojq00rCFe+bQH4pffH1ogk4p54BmnHaeTcAuDMD twcGkwhWxXHYblYZJuFUx8pMAs+c8NA= X-Received: by 2002:aa7:9298:: with SMTP id j24mr22747609pfa.58.1564163472492; Fri, 26 Jul 2019 10:51:12 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.11 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:57 -0700 Message-Id: <20190726175032.6769-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::430 Subject: [Qemu-devel] [PATCH 32/67] target/arm: Convert RFE and SRS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 150 ++++++++++++++--------------------- target/arm/a32-uncond.decode | 8 ++ target/arm/t32.decode | 12 +++ 3 files changed, 81 insertions(+), 89 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 7ea118a795..b43b344f96 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9991,16 +9991,71 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a) return true; } +/* + * Unconditional system instructions + */ + +static bool trans_RFE(DisasContext *s, arg_RFE *a) +{ + int32_t offset; + TCGv_i32 addr, t1, t2; + + if (IS_USER(s) || !ENABLE_ARCH_6) { + return false; + } + + addr = load_reg(s, a->rn); + + switch (a->pu) { + case 0: offset = -4; break; /* DA */ + case 1: offset = 0; break; /* IA */ + case 2: offset = -8; break; /* DB */ + case 3: offset = 4; break; /* IB */ + default: + g_assert_not_reached(); + } + tcg_gen_addi_i32(addr, addr, offset); + + /* Load PC into tmp and CPSR into tmp2. */ + t1 = tcg_temp_new_i32(); + gen_aa32_ld32u(s, t1, addr, get_mem_index(s)); + tcg_gen_addi_i32(addr, addr, 4); + t2 = tcg_temp_new_i32(); + gen_aa32_ld32u(s, t2, addr, get_mem_index(s)); + + if (a->w) { + /* Base writeback. */ + switch (a->pu) { + case 0: offset = -8; break; + case 1: offset = 4; break; + case 2: offset = -4; break; + case 3: offset = 0; break; + } + tcg_gen_addi_i32(addr, addr, offset); + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + gen_rfe(s, t1, t2); + return true; +} + +static bool trans_SRS(DisasContext *s, arg_SRS *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + gen_srs(s, a->mode, a->pu, a->w); + return true; +} + /* * Legacy decoder. */ static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1, i, rn; - TCGv_i32 tmp; - TCGv_i32 tmp2; - TCGv_i32 addr; + unsigned int cond, op1; /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10119,52 +10174,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) default: goto illegal_op; } - } else if ((insn & 0x0e5fffe0) == 0x084d0500) { - /* srs */ - ARCH(6); - gen_srs(s, (insn & 0x1f), (insn >> 23) & 3, insn & (1 << 21)); - return; - } else if ((insn & 0x0e50ffe0) == 0x08100a00) { - /* rfe */ - int32_t offset; - if (IS_USER(s)) - goto illegal_op; - ARCH(6); - rn = (insn >> 16) & 0xf; - addr = load_reg(s, rn); - i = (insn >> 23) & 3; - switch (i) { - case 0: offset = -4; break; /* DA */ - case 1: offset = 0; break; /* IA */ - case 2: offset = -8; break; /* DB */ - case 3: offset = 4; break; /* IB */ - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - /* Load PC into tmp and CPSR into tmp2. */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - switch (i) { - case 0: offset = -8; break; - case 1: offset = 4; break; - case 2: offset = -4; break; - case 3: offset = 0; break; - default: abort(); - } - if (offset) - tcg_gen_addi_i32(addr, addr, offset); - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - return; } else if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10324,7 +10333,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; - TCGv_i32 tmp2; TCGv_i32 addr; int op; @@ -10473,44 +10481,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) goto illegal_op; } } else { - /* Load/store multiple, RFE, SRS. */ - if (((insn >> 23) & 1) == ((insn >> 24) & 1)) { - /* RFE, SRS: not available in user mode or on M profile */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - if (insn & (1 << 20)) { - /* rfe */ - addr = load_reg(s, rn); - if ((insn & (1 << 24)) == 0) - tcg_gen_addi_i32(addr, addr, -8); - /* Load PC into tmp and CPSR into tmp2. */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - tcg_gen_addi_i32(addr, addr, 4); - tmp2 = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s)); - if (insn & (1 << 21)) { - /* Base writeback. */ - if (insn & (1 << 24)) { - tcg_gen_addi_i32(addr, addr, 4); - } else { - tcg_gen_addi_i32(addr, addr, -4); - } - store_reg(s, rn, addr); - } else { - tcg_temp_free_i32(addr); - } - gen_rfe(s, tmp, tmp2); - } else { - /* srs */ - gen_srs(s, (insn & 0x1f), (insn & (1 << 24)) ? 1 : 2, - insn & (1 << 21)); - } - } else { - /* Load/store multiple, in decodetree */ - goto illegal_op; - } + /* Load/store multiple, RFE, SRS, in decodetree */ + goto illegal_op; } break; case 5: diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 573ac2cf8e..3b961233e5 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -29,3 +29,11 @@ %imm24h 0:s24 24:1 !function=times_2 BLX_i 1111 101 . ........................ &i imm=%imm24h + +# System Instructions + +&rfe rn w pu +&srs mode w pu + +RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe +SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs diff --git a/target/arm/t32.decode b/target/arm/t32.decode index ab7d7ba100..26b51c3bb2 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -582,6 +582,18 @@ STM 1110 1001 00.0 .... ................ @ldstm i=0 b=1 LDM 1110 1000 10.1 .... ................ @ldstm i=1 b=0 LDM 1110 1001 00.1 .... ................ @ldstm i=0 b=1 +&rfe !extern rn w pu +@rfe .... .... .. w:1 . rn:4 ................ &rfe + +RFE 1110 1000 00.1 .... 1100000000000000 @rfe pu=2 +RFE 1110 1001 10.1 .... 1100000000000000 @rfe pu=1 + +&srs !extern mode w pu +@srs .... .... .. w:1 . .... ........... mode:5 &srs + +SRS 1110 1000 00.0 1101 1100 0000 000. .... @srs pu=2 +SRS 1110 1001 10.0 1101 1100 0000 000. .... @srs pu=1 + # Branches %imm24 26:s1 13:1 11:1 16:10 0:11 !function=t32_branch24 From patchwork Fri Jul 26 17:49:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169901 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp361160ilk; Fri, 26 Jul 2019 10:59:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqwKGuyfLlL0oLAGFPQaFVqwKpsqLtrFaqIJV69tLjgdrKSwiZdozNIVE7LnUMW8M7x3vpQx X-Received: by 2002:a37:9c94:: with SMTP id f142mr57365173qke.427.1564163951297; Fri, 26 Jul 2019 10:59:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163951; cv=none; d=google.com; s=arc-20160816; b=MTALTF7VICoy1YsmPZG9KDnnS4Y0mDIhiHQ++kTAT8Ptqd9ucC8GV4PqOh8aC+rVoD KvCupSAKc9tkXR8KszViIPGOb4rf6B6q/VywMwATLnW8CIyPWXTGvbiIYet2Aghzp8xv jbPdUmx3cM3fUy+DwYVY/Zn9O8mYoCpgZOLAr/+uupKKAd3u8rhXdrL9kC0H4Zq4zLPU UVeR2BnNVr1EhG2tV+hhO9VJuW4PGT/enXR+5/dbLrG2eO0+79Rr/MG9NDgMCO6qXYSh 2fTHrSqv8fUS0aRP5ft+s+e++TyLeQ57MVEGOT/QkHjEgGD74pmP1YARSZ1pWEgQksMB BenA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=VzkvUsUZh9EVbOcurylb0EvE0t9ji9eIajoY1fu0OlU=; b=pshfqFh7/+G7b7j36hn1YRnsqAviskp9JTURS2TyNIb8hMOOzEH1/GnEDVX7+YsyqY JOVxhaNN+cFx3D9l2Oz0Y+W8ijve4Tg1NgB/pMh1u/IAL0EghwxoTeVg6ET8pr8si5Tr Gtn+e6rWHDLQo555kT7jp4TT0wjBovSU77nN5GDpRv9EFS5rXJx5/WhzFPuZQn9ilYW3 mqaySzJ3naxzBs15ucbb27j7yivqgr5kXvpB+MDDO+VgokBAxNijoiXer/ZAC4lsm8pT QEdZJzLSjHsTkW56SbEFx12vBr9/r2Oyh8RkaQ0JIPDVPjWijdTDWcCUVEyExgQyREhR uY9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JTiaH8qg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i7si30642970qkl.262.2019.07.26.10.59.11 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:59:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=JTiaH8qg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Uk-0003Ys-Ax for patch@linaro.org; Fri, 26 Jul 2019 13:59:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58513) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NJ-0004ht-ED for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NF-0000P8-P1 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:24 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:33288) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NF-0000Fa-EK for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:21 -0400 Received: by mail-pl1-x633.google.com with SMTP id c14so24959377plo.0 for ; Fri, 26 Jul 2019 10:51:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VzkvUsUZh9EVbOcurylb0EvE0t9ji9eIajoY1fu0OlU=; b=JTiaH8qg13W5L7ZBXSUJXBfgCem9ARL1uiQFgjSz3GSsuW+K63GFGoVMb1eXI/kHqS j5hIjUWGgN1EPPkz2rr1n64pKilRQCsxioGELbw3wawI+4wddJNXnP1nhoWD8pNmyV+C mNdpGdJaP81pZoxCI7PxFV7p6yVbbTITfQIw2go7rFoCe9x7xUaeBIACssl/3OzYWVCu ZY+9QXhV0w6pPtg4I9FY8QkZLOQp4g2sbKK8TBKlGAtn5myrOZEnDGIg/POrKhl92QWA 8lj0WeCyZz+FbWjo0mJ9pL4EKimeh8qPjin+JDCX8JxUhY/7WK2QK+16mujg8FbpX1GH n4lA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VzkvUsUZh9EVbOcurylb0EvE0t9ji9eIajoY1fu0OlU=; b=gxUILojchfA4QTkL5IoKzKIYUB9Z9AgrWExrmVNdHBgvTdHTGzZRW9UfcOHGtALPIy Jbbs7TyUmp8TtU9ogHOrIh0YPcWOlYCG5tlITIfIr6gM2j7pa44Jxrh1loxx3yh8gfkk LJ7Wv2fRLMb2dmwEKdEC4kEMleLblM92oPUDZFgDoa8b7wnNSsUkjGb4b2HM8OudE2hy JKy4/DS/0BD9GhBn2rqxOhGlPCzC9teFVWD4LplzVBstohx5xBDOUZEPuFinDLf7kUji 6NzWp0LUF9VTB33ztJTu0p3Yhln1waqrtYVlwTkpIOdly2LEQWJ7RD2w12+rJXl36qQQ HeRQ== X-Gm-Message-State: APjAAAUlzJkIcwHKfKOSAABC5Z88Fz7zHTdhpiU+QKsPB7Ez1IlcNsQZ F/YXys8mHQEGZ8AXrY7wtA2idnrn7w8= X-Received: by 2002:a17:902:aa83:: with SMTP id d3mr94715985plr.74.1564163473666; Fri, 26 Jul 2019 10:51:13 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.12 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:58 -0700 Message-Id: <20190726175032.6769-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::633 Subject: [Qemu-devel] [PATCH 33/67] target/arm: Convert Clear-Exclusive, Barriers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 122 +++++++++++++++-------------------- target/arm/a32-uncond.decode | 10 +++ target/arm/t32.decode | 10 +++ 3 files changed, 73 insertions(+), 69 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index b43b344f96..797e8f7344 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10049,6 +10049,58 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } +/* + * Clear-Exclusive, Barriers + */ + +static bool trans_CLREX(DisasContext *s, arg_CLREX *a) +{ + if (!ENABLE_ARCH_6K) { + return false; + } + gen_clrex(s); + return true; +} + +static bool trans_DSB(DisasContext *s, arg_DSB *a) +{ + if (!s->thumb && !ENABLE_ARCH_7) { + return false; + } + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + return true; +} + +static bool trans_DMB(DisasContext *s, arg_DMB *a) +{ + return trans_DSB(s, NULL); +} + +static bool trans_ISB(DisasContext *s, arg_ISB *a) +{ + /* + * We need to break the TB after this insn to execute + * self-modifying code correctly and also to take + * any pending interrupts immediately. + */ + gen_goto_tb(s, 0, s->pc & ~1); + return true; +} + +static bool trans_SB(DisasContext *s, arg_SB *a) +{ + if (!dc_isar_feature(aa32_sb, s)) { + return false; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc & ~1); + return true; +} + /* * Legacy decoder. */ @@ -10142,38 +10194,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) s->base.is_jmp = DISAS_UPDATE; } return; - } else if ((insn & 0x0fffff00) == 0x057ff000) { - switch ((insn >> 4) & 0xf) { - case 1: /* clrex */ - ARCH(6K); - gen_clrex(s); - return; - case 4: /* dsb */ - case 5: /* dmb */ - ARCH(7); - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - return; - case 6: /* isb */ - /* We need to break the TB after this insn to execute - * self-modifying code correctly and also to take - * any pending interrupts immediately. - */ - gen_goto_tb(s, 0, s->pc & ~1); - return; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->pc & ~1); - return; - default: - goto illegal_op; - } } else if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10636,43 +10656,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) gen_set_psr_im(s, offset, 0, imm); } break; - case 3: /* Special control operations. */ - if (!arm_dc_feature(s, ARM_FEATURE_V7) && - !arm_dc_feature(s, ARM_FEATURE_M)) { - goto illegal_op; - } - op = (insn >> 4) & 0xf; - switch (op) { - case 2: /* clrex */ - gen_clrex(s); - break; - case 4: /* dsb */ - case 5: /* dmb */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - break; - case 6: /* isb */ - /* We need to break the TB after this insn - * to execute self-modifying code correctly - * and also to take any pending interrupts - * immediately. - */ - gen_goto_tb(s, 0, s->pc & ~1); - break; - case 7: /* sb */ - if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { - goto illegal_op; - } - /* - * TODO: There is no speculation barrier opcode - * for TCG; MB and end the TB instead. - */ - tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); - gen_goto_tb(s, 0, s->pc & ~1); - break; - default: - goto illegal_op; - } - break; + case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ case 5: /* eret, in decodetree */ case 6: /* MRS, in decodetree */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index 3b961233e5..b077958cec 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -22,6 +22,7 @@ # All of those that have a COND field in insn[31:28] are in a32.decode # +&empty !extern &i !extern imm # Branch with Link and Exchange @@ -37,3 +38,12 @@ BLX_i 1111 101 . ........................ &i imm=%imm24h RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs + +# Clear-Exclusive, Barriers + +# QEMU does not require the option field for the barriers. +CLREX 1111 0101 0111 1111 1111 0000 0001 1111 +DSB 1111 0101 0111 1111 1111 0000 0100 ---- +DMB 1111 0101 0111 1111 1111 0000 0101 ---- +ISB 1111 0101 0111 1111 1111 0000 0110 ---- +SB 1111 0101 0111 1111 1111 0000 0111 0000 diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 26b51c3bb2..9fe1500fe0 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -306,6 +306,16 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm # of the space is "reserved hint, behaves as nop". NOP 1111 0011 1010 1111 1000 0000 ---- ---- } + + # Miscelaneous control + { + CLREX 1111 0011 1011 1111 1000 1111 0010 1111 + DSB 1111 0011 1011 1111 1000 1111 0100 ---- + DMB 1111 0011 1011 1111 1000 1111 0101 ---- + ISB 1111 0011 1011 1111 1000 1111 0110 ---- + SB 1111 0011 1011 1111 1000 1111 0111 0000 + } + # Note that the v7m insn overlaps both the normal and banked insn. { MRS_bank 1111 0011 111 r:1 .... 1000 rd:4 001. 0000 \ From patchwork Fri Jul 26 17:49:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169904 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp362122ilk; Fri, 26 Jul 2019 11:00:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqxR37bRpDWWpDxqur70igZSbFZRs9fjCCRHitQ7Bgh0uB4u7gUn+MyJPbfqCI6w4x/oV6Q/ X-Received: by 2002:a05:6402:134c:: with SMTP id y12mr82949556edw.96.1564164012726; Fri, 26 Jul 2019 11:00:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164012; cv=none; d=google.com; s=arc-20160816; b=Zzhm+Lyk7SoZB0uDZJlOgFMVBU29iDAcN5GT6Em0YVBR4ab6QeUvneXvSbo7olxaT6 2pBgz2wuOO+9YTA83FGagK0+Ty3e/7KSQExugzGawCoWgcmXTSnSq5hVQHkz1AJYkv2G Scn8VaDArHI1s3/vT4W76pan12m/5psPiSJVMI4mxcO6wYJe7STYAozjsn+uDsum45Pj /FIx6GX17eRRPVXTcwBe2QtN6hKbPmpu1gwqt77RI8RfVLrLkl4in48kDGak6TzVWYah 42h4WDMgqu7/5sUn2/9UPYI4diemRwpXu4KkdboXcKuZfW1miDGTqTNKlw66JIxUIDw4 qv1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=V+9sEjvD/MeB+TtFs8ZOx130uH8wMAavrP8D396SPq0=; b=HUYfL3n+gmJetn4oBDjL7f7eQXK8Y9ZCgRutYtODUr/E86wPCuJMjsXxCEOsGrNAyN gcDscncxTMgA5T66pscjLxfTZOcw+Q1SWS8G6a9uSWWisbe3OmivzIjm/vKud6ftZ3hr D8CqKZtXkY376yJhoyQ+gGl+688EFSh/ET98EXxIiROmeLpiGHgdzdjPQ7A6yOX+AyAc ucJmEROw/du58YgTkELUFt2e0jj8jgEwL0Mn89d6M+2YRPWeE3uIbxoYFGPyiEXdO5YD EkzSoOvInfBaUTiuBEvsd2BO245tLEN63/9bTFETJBz67fDxjMoeeDJSy9aKfNOeLaLW bkTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="f/SL5nhg"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w33si14625110eda.399.2019.07.26.11.00.12 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:00:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="f/SL5nhg"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Vm-0007F8-7U for patch@linaro.org; Fri, 26 Jul 2019 14:00:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58470) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NJ-0004dq-Le for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NF-0000PC-P2 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:23 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:38747) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NF-0000Ik-Fo for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:21 -0400 Received: by mail-pl1-x62a.google.com with SMTP id az7so25001957plb.5 for ; Fri, 26 Jul 2019 10:51:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=V+9sEjvD/MeB+TtFs8ZOx130uH8wMAavrP8D396SPq0=; b=f/SL5nhg6EpaND6So2WRj2YgErez5hqgIJwID9peBtD1SXLkj/xgmGHbHMRBRWwtbw RXSDPacY9aDCUPgz+ZPoHHyB1WQ1nSpguwemwoaVm0YpppCWDB/uyCnvT16ivzwZAXrg 0F+weck/PPdUkDvSwiYlEmDj+NOgeODZEF35YXUXjta9WU0/2h1RKhu63jWfcrr187oT UdKB3U7F/G0wuNIoqX5Gs0tORHs3Y0l9X1s0su4mUvM9/Ru6Lr2Lz0MEM64vTaS3d7TR ccL6ftirSUdGNfpvi3+cJAoLeMJIckHd4zyVB61VkqyAdLWIqcVvSp+9xyMAOYKmAJRK HgWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=V+9sEjvD/MeB+TtFs8ZOx130uH8wMAavrP8D396SPq0=; b=VAYDUtRP14FpabVPUmPMj+OLYOwGcfqECODdrRMmAOnMAiPhhJFXq0zK24bbc3BPdh CGliNabA+yXLN50oAnriO0LG0jo7RwmJv74AsqtmRf8VfJYneCLD6Keh3F1PPFqnuIJl aYF61DdaUfh7fVKbo4OZzQZzPoRPVSWQbzBK/L5jAYsaSPFXdMJmZ6zfqIBwlR98pVqJ soj0RtmsFVjeJKH5Yl2mhFAShc3jYjns1g8JjEeIAeG442KW9sYxalxX9uF7vZLj6ogo k1XFlJtrtfBcWxjuubYOYcwgQz/E8a4x0RaMaFnB+gUvN01a68zaVX7kdzJbz2HmDkzK clXA== X-Gm-Message-State: APjAAAVvjpNK0C2UGjT6Qt9NtNKJkxR1e5sd0OWxw8AZ9f1fricWhicC RiVT8M3xF6gGX5MUQBsU4oOZrsuAicM= X-Received: by 2002:a17:902:7781:: with SMTP id o1mr97579752pll.205.1564163474983; Fri, 26 Jul 2019 10:51:14 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.13 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:49:59 -0700 Message-Id: <20190726175032.6769-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62a Subject: [Qemu-devel] [PATCH 34/67] target/arm: Convert CPS (privileged) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 87 +++++++++++++++--------------------- target/arm/a32-uncond.decode | 3 ++ target/arm/t32.decode | 3 ++ 3 files changed, 42 insertions(+), 51 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 797e8f7344..8dbe189df7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10049,6 +10049,40 @@ static bool trans_SRS(DisasContext *s, arg_SRS *a) return true; } +static bool trans_CPS(DisasContext *s, arg_CPS *a) +{ + uint32_t mask, val; + + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + + mask = val = 0; + if (a->imod & 2) { + if (a->A) { + mask |= CPSR_A; + } + if (a->I) { + mask |= CPSR_I; + } + if (a->F) { + mask |= CPSR_F; + } + if (a->imod & 1) { + val |= mask; + } + } + if (a->M) { + mask |= CPSR_M; + val |= a->mode; + } + if (mask) { + gen_set_psr_im(s, mask, 0, val); + } + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10220,31 +10254,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) ARCH(5TE); } else if ((insn & 0x0f000010) == 0x0e000010) { /* Additional coprocessor register transfer. */ - } else if ((insn & 0x0ff10020) == 0x01000000) { - uint32_t mask; - uint32_t val; - /* cps (privileged) */ - if (IS_USER(s)) - return; - mask = val = 0; - if (insn & (1 << 19)) { - if (insn & (1 << 8)) - mask |= CPSR_A; - if (insn & (1 << 7)) - mask |= CPSR_I; - if (insn & (1 << 6)) - mask |= CPSR_F; - if (insn & (1 << 18)) - val |= mask; - } - if (insn & (1 << 17)) { - mask |= CPSR_M; - val |= (insn & 0x1f); - } - if (mask) { - gen_set_psr_im(s, mask, 0, val); - } - return; } goto illegal_op; } @@ -10350,7 +10359,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t imm, offset; uint32_t rd, rn, rm, rs; TCGv_i32 tmp; TCGv_i32 addr; @@ -10631,31 +10639,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) case 0: /* msr cpsr, in decodetree */ case 1: /* msr spsr, in decodetree */ goto illegal_op; - case 2: /* cps, nop-hint. */ - /* nop hints in decodetree */ - /* Implemented as NOP in user mode. */ - if (IS_USER(s)) - break; - offset = 0; - imm = 0; - if (insn & (1 << 10)) { - if (insn & (1 << 7)) - offset |= CPSR_A; - if (insn & (1 << 6)) - offset |= CPSR_I; - if (insn & (1 << 5)) - offset |= CPSR_F; - if (insn & (1 << 9)) - imm = CPSR_A | CPSR_I | CPSR_F; - } - if (insn & (1 << 8)) { - offset |= 0x1f; - imm |= (insn & 0x1f); - } - if (offset) { - gen_set_psr_im(s, offset, 0, imm); - } - break; + case 2: /* cps, nop-hint, in decodetree */ + goto illegal_op; case 3: /* Special control operations, in decodetree */ case 4: /* bxj, in decodetree */ case 5: /* eret, in decodetree */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index b077958cec..eb1c55b330 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -35,9 +35,12 @@ BLX_i 1111 101 . ........................ &i imm=%imm24h &rfe rn w pu &srs mode w pu +&cps mode imod M A I F RFE 1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000 &rfe SRS 1111 110 pu:2 1 w:1 0 1101 0000 0101 000 mode:5 &srs +CPS 1111 0001 0000 imod:2 M:1 0 0000 000 A:1 I:1 F:1 0 mode:5 \ + &cps # Clear-Exclusive, Barriers diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 9fe1500fe0..f8d8660466 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -44,6 +44,7 @@ &bfi !extern rd rn lsb msb &sat !extern rd rn satimm imm sh &pkh !extern rd rn rm imm tb +&cps !extern mode imod M A I F # Data-processing (register-shifted register) @@ -340,6 +341,8 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm SMC 1111 0111 1111 imm:4 1000 0000 0000 0000 &i HVC 1111 0111 1110 .... 1000 .... .... .... \ &i imm=%imm16_16_0 + CPS 1111 0011 1010 1111 1000 0 imod:2 M:1 A:1 I:1 F:1 mode:5 \ + &cps UDF 1111 0111 1111 ---- 1010 ---- ---- ---- } B_cond_thumb 1111 0. cond:4 ...... 10.0 ............ &ci imm=%imm21 From patchwork Fri Jul 26 17:50:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169879 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp356872ilk; Fri, 26 Jul 2019 10:54:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqwGO09gUtsk0a/n9UwKoAnzyWLH0v6+nP6ooaletqFmcKRfdW0brObMWYPJkVCgKsoC34tN X-Received: by 2002:a17:907:374:: with SMTP id rs20mr53045114ejb.36.1564163670667; Fri, 26 Jul 2019 10:54:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163670; cv=none; d=google.com; s=arc-20160816; b=DfJXiNPmv1kAvske0illrqltWooOjFlwa95RbLBxV3QgGv+Q4C19jNP2U0B4iATPMY hVgJSaOS/65sEu33uoUhHCNB7YxJtxfXvNl/aZ6zBXA/8DHaEd1/77otbfDnKKQBfLBE YN3yWpOjc3IIGlEN9L3Z6Zl8B+FjEo+Y7kmhkupbT6pwoJmpcrtH2kvEH1ZkHc9+Akyv vytsvcJiYhJjn4V4YZPtZnHoURuITxQu23mBdfo3o9r42T+bZDQkvAhDrBQKsAZmZA6i EHONc9PtElOcs3sVStIvp9qDl+VNxxyJpPRqjQB1xbkladWuB/xftCRAodS/bJDf7RO3 V8sA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=CWeGp5OQUiIGgb4lAKmE1/GSBVlKuVNMscwa0w65aPo=; b=cFSAAsSa8TiehHR+h12lH8PSBRQsQixz1pCZPp6DIEeuiMb+qfc2c9JQjeB4cCw6tz 46sIbzU91NeYe26vjbn+dCQ4JqqTZr/utpZ5vLKeEb+BZ1HkPibQLXdafaCknIXrWwxI UaWlu3TWUpE4vkAIu1pEw6vmgHRZLnyHd2i/bsQIqlXDc5mL5gqoY0UOhQ1xtkxrDldU pHnyDaoDLMdJLQHzGgdGwqq05DvZeQxZVqTFAGAS14rUszqX259rDwW6w5uDCzT1GgS7 7nyKPmsYqeaAEvSKoVOnXDlp1fYtyDUhlX3+UZofwHOnhkhnQeE45fog6QVxk+ZYWvPZ sCZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xTfBpe1r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k42si12438586eda.162.2019.07.26.10.54.30 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:54:30 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xTfBpe1r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4QG-0000io-A8 for patch@linaro.org; Fri, 26 Jul 2019 13:54:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58481) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NH-0004ef-UJ for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NG-0000SC-LP for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:23 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:34268) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NG-0000Ie-EK for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:22 -0400 Received: by mail-pf1-x434.google.com with SMTP id b13so24857640pfo.1 for ; Fri, 26 Jul 2019 10:51:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CWeGp5OQUiIGgb4lAKmE1/GSBVlKuVNMscwa0w65aPo=; b=xTfBpe1rZ6GuS2QfdzU8bs9Re1n0GUAJM1+XQA1ASnIsbzridR8mOS00jnSQAHk9mo DuD/zuGaytI5sUDsuMxjZODVhnUnBWh2p1uNBMWfCk+PWctmmLmQwqiZHXL1o5lwzhP4 Cre6HEt86GyL7IjgR4mV02t4nIRKOM9ZZbOEdSuNwXZRpSQFYThyOL7MBQpDj07GReGq ZWWNr9phIylsPRitJvVShLev9Bz+1K1pzlKaQ57EFYAQOMGIRowrl+7bs1IwrNtk7PiB cxJ12yg+4VmtZx1acuPL87KJ0O7k48YWTfNy3HB16IwyGw3RataNFNezXKMFF2xQhSRP CgNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CWeGp5OQUiIGgb4lAKmE1/GSBVlKuVNMscwa0w65aPo=; b=AL1+70L9gsv8jXWV0Iw5NgSTT/zvIxEwny3u9SX7Oh/1eCHKOSQcSawolHd5nmih6J VAdUoZUAWU2c8rhVQQy2Twy0Tpaupej6GMrBFYvwoMqqMdYSY+OngTfIw2f1vjNe9lch 42WTJFaxffEC8MqdBwZdhNaNtT/8D5/BKP/QU0UxBcgWsb23lzBb5v//1HbPYZztZ9Vp cU0XC8lKP+9rq+CBMHi7YamOmf8W7HfjT+CAwf3G8F1kaGFDuvZg5fPsMgOIqe85Pp9+ cFNlmUd2qeNi//oO59COQjceOmhVlmjJ7yC6/OSzZz//aOrqFdlIGbtKSTgSTPA3+g0p n/NA== X-Gm-Message-State: APjAAAVN4e7vojwCGHGqNFRpQo0X0JKkVpM2Wcaj6qwi9vxwQBWGCeP+ wRkanI5icYYx0RWgoOB13yxPFdM3FtI= X-Received: by 2002:a62:1c5:: with SMTP id 188mr22560468pfb.26.1564163475850; Fri, 26 Jul 2019 10:51:15 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.15 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:00 -0700 Message-Id: <20190726175032.6769-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::434 Subject: [Qemu-devel] [PATCH 35/67] target/arm: Convert SETEND X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 22 +++++++++++++--------- target/arm/a32-uncond.decode | 4 ++++ 2 files changed, 17 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 8dbe189df7..1d07caa62a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10135,6 +10135,18 @@ static bool trans_SB(DisasContext *s, arg_SB *a) return true; } +static bool trans_SETEND(DisasContext *s, arg_SETEND *a) +{ + if (!ENABLE_ARCH_6) { + return false; + } + if (a->E != (s->be_data == MO_BE)) { + gen_helper_setend(cpu_env); + s->base.is_jmp = DISAS_UPDATE; + } + return true; +} + /* * Legacy decoder. */ @@ -10220,15 +10232,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) return; /* v7MP: Unallocated memory hint: must NOP */ } - if ((insn & 0x0ffffdff) == 0x01010000) { - ARCH(6); - /* setend */ - if (((insn >> 9) & 1) != !!(s->be_data == MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp = DISAS_UPDATE; - } - return; - } else if ((insn & 0x0e000f00) == 0x0c000100) { + if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ if (extract32(s->c15_cpar, 1, 1)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index eb1c55b330..d5ed48f0fd 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -24,6 +24,7 @@ &empty !extern &i !extern imm +&setend E # Branch with Link and Exchange @@ -50,3 +51,6 @@ DSB 1111 0101 0111 1111 1111 0000 0100 ---- DMB 1111 0101 0111 1111 1111 0000 0101 ---- ISB 1111 0101 0111 1111 1111 0000 0110 ---- SB 1111 0101 0111 1111 1111 0000 0111 0000 + +# Set Endianness +SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend From patchwork Fri Jul 26 17:50:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169891 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp358904ilk; Fri, 26 Jul 2019 10:56:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqyZnlaKCgaBvnVjCjad2fegfhBu0z/zApf29M29NJmwk6tTrLh9ZEmEeVdNwFEFyF7DggLu X-Received: by 2002:a17:906:1292:: with SMTP id k18mr74944756ejb.146.1564163806536; Fri, 26 Jul 2019 10:56:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163806; cv=none; d=google.com; s=arc-20160816; b=Vf3rUe73jPTt70ywNr/PpD177vLAYZFBSYvT80btFN38UUfdeyiLozpFLyqJ1nZiUd 8ebubsrLDoNS2R60eOB3aQRxv+1OFJRFhtl8cJtn3SJrDn3JCSXVtCR94F2GkaxT0jlf 7d9Ggd6mhVPVoyBms84xRAOyaV5K19oeKThUGJGsYmTnlBm2rvIUTQ6LsafLATzwq3UA c5ZxDDxf+vRr84mrW5N1CHSg/Gn8AB+G8WZFiSwZokmy6vRwHlaK9SyPoHCXQexw9VqZ JqQ8n2MmHySBwv3f8KZ3CbGUAoW7Ee4fvpE1afba5K0ZfibaFN5TC7GnVY0VmqkLK0cd 7IbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=BzmSmsqkudBY73N0i3QRkWoRxzKdjm/eJVgoMLfj3Sc=; b=C9j2x/IG8M3E5nWp+RhBki5Sy6u5fPl4KQwsMvLZSvYOyvj5V5V+c+wlMYJT9MCOBC APtQ0mCIdrScRD6M5CTiJMmEuhr0Iwm/VWOPXCXmmDfo4IXbcIiW2V+efqGsomjarVo1 CO1Gb4wozeMsSCjLjQrDwLjgaQVxfVb/S4eZAA1RUHw8ahx5Ove9v45AVW+rMUHfVqFY wnyQbtYLcKG/rPAp5chuIEx/6BMhx/FJaN5nD4mnvQQ1C2WrFshHjRSRYakcKVIb6gNk nl7XNT317Ay5qtqnRHZO6VW3YyjYE3or0vKlYUHwti6GS7AUVLNXlWMYiMmdabd/MHpo URfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=x8oCBcnW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q25si11159770ejt.301.2019.07.26.10.56.46 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:56:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=x8oCBcnW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42408 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4ST-00025m-7z for patch@linaro.org; Fri, 26 Jul 2019 13:56:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58884) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NT-0005Hw-Vc for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NO-0000ks-Qd for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:32 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:43351) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NH-0000Jy-Jj for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:30 -0400 Received: by mail-pf1-x444.google.com with SMTP id i189so24859263pfg.10 for ; Fri, 26 Jul 2019 10:51:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BzmSmsqkudBY73N0i3QRkWoRxzKdjm/eJVgoMLfj3Sc=; b=x8oCBcnWbkKY7zCfEztHeVfrYPzRfIa3WgR5nfpNI1fmX4DNoyWWLNSE6eleo3P68z cOmnQhdQREWFxj2tZfxMlK8dsssaACi19p+kdF2IGY8XZoErdV/4C6xYs1ZCeod9cSyE Z0wttuNKaRAyWDYv7n18vI5RJ1nKX1ml6tPtRk/FCx8wqC3DBeIw0x8bRznMTyZSn8Av Kbz9JKt1dma195s6P8MAY151vyhmAL2Vzf8vlVXzxNGZ9Nfxc5WiGUiT5rWe0Nqj9GNM tb9xo4GnQi/YQHz22xxCRwbzWNGMEFelk51hZEW1DmuLsN3mSAhzcdDzjjnSsexnJzJu F6Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BzmSmsqkudBY73N0i3QRkWoRxzKdjm/eJVgoMLfj3Sc=; b=Owe4Cc7YGr3ysfKOisv4CTaTIoJvkPDdyx1TeQu/7LcyZeLE7UqondYdLOmmKXRSKI zfCFlf6CuxcbEi1iZHZJyqJ8m1apB7vpaokTkPdfxeCQ4d60PnLdMvMLV1eg22RD4gCQ Za/t68vpcZjMBl6jxpWc0WCmshJvUfQxq/gc4V8cCBZxk/9h5k+lf3NlBHfsPeDHuH+D 8eXEV2HnTeQnZUpq4Uju4HeDzES+Oc65VNz7gnoSdv77D0V8SgaAbsyHUr4Lmi1xdS9j VbSlzVREHKDjPC/saY+xzCp+8JgrW0Mlb1AhCZQ0bn3H5UaXQTgAnOoKW8NqEoYbwwwU D4dQ== X-Gm-Message-State: APjAAAURv98ni3Vk6uY3rDb+sRb7wH6B/b0bbg/0yh5x+pTxoD2OyQ/W AWVGDIypgZWmp9uDsb+wok4VwlOUxIw= X-Received: by 2002:aa7:989a:: with SMTP id r26mr11675570pfl.232.1564163477012; Fri, 26 Jul 2019 10:51:17 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.15 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:01 -0700 Message-Id: <20190726175032.6769-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 36/67] target/arm: Convert PLI, PLD, PLDW X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 37 +++++++++++++++++++----------------- target/arm/a32-uncond.decode | 10 ++++++++++ 2 files changed, 30 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 1d07caa62a..5366741d7b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10147,6 +10147,26 @@ static bool trans_SETEND(DisasContext *s, arg_SETEND *a) return true; } +/* + * Preload instructions + * All are nops, contingent on the appropriate arch level. + */ + +static bool trans_PLD(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_5TE; +} + +static bool trans_PLDW(DisasContext *s, arg_PLD *a) +{ + return arm_dc_feature(s, ARM_FEATURE_V7MP); +} + +static bool trans_PLI(DisasContext *s, arg_PLD *a) +{ + return ENABLE_ARCH_7; +} + /* * Legacy decoder. */ @@ -10207,23 +10227,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } return; } - if (((insn & 0x0f30f000) == 0x0510f000) || - ((insn & 0x0f30f010) == 0x0710f000)) { - if ((insn & (1 << 22)) == 0) { - /* PLDW; v7MP */ - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - } - /* Otherwise PLD; v5TE+ */ - ARCH(5TE); - return; - } - if (((insn & 0x0f70f000) == 0x0450f000) || - ((insn & 0x0f70f010) == 0x0650f000)) { - ARCH(7); - return; /* PLI; V7 */ - } if (((insn & 0x0f700000) == 0x04100000) || ((insn & 0x0f700010) == 0x06100000)) { if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index d5ed48f0fd..aed381cb8e 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -54,3 +54,13 @@ SB 1111 0101 0111 1111 1111 0000 0111 0000 # Set Endianness SETEND 1111 0001 0000 0001 0000 00 E:1 0 0000 0000 &setend + +# Preload instructions + +PLD 1111 0101 -101 ---- 1111 ---- ---- ---- # (imm, lit) 5te +PLDW 1111 0101 -001 ---- 1111 ---- ---- ---- # (imm, lit) 7mp +PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 + +PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te +PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp +PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 From patchwork Fri Jul 26 17:50:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169886 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp357896ilk; Fri, 26 Jul 2019 10:55:35 -0700 (PDT) X-Google-Smtp-Source: APXvYqywe8pCQWdXDj99x776ncX89dXEF2NDb+XLm0mZcr9ojl5J5N1HtPaDKW0USA1USOn21cur X-Received: by 2002:a50:b6ce:: with SMTP id f14mr80151849ede.236.1564163735544; Fri, 26 Jul 2019 10:55:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163735; cv=none; d=google.com; s=arc-20160816; b=yh/gxO0eqxkv5Vh1O+8n3hV9jatUOeab0mR0YOuNnPFN03PeiMWBtgwfeSP7fd9ZBJ PZFVHEqUFLoZnpExT8uDPiI2V3pPRmGgoizlEuMxe7Mit1L8qMMiaV1NrHLqKg/RBuXa Iwgij3/B6VPkLu8tW38ygLX/YjFfrHa4fPTEkXto/kOxztgp8sjoCAOnFNj61rCPNAg2 ZAgFkOKbbM7HwbLT1PMDS3DQh4+E/YiZ7mB+dc6mmONlB5C8OiTTUixYQ775SjkZqEjF MhB07eF4sb0aVB7voLab2w/6+2g31Wq1qnmvpINEn+u3qCA02GTT4lGZYOGfcbbM35CI flHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=hWnZNwWI4tI65PwmLTIEUSuYbSd9btmA82x5Eaqyf6M=; b=AFSkB4GsZrnDeodLhhecuqfBd+ToDOLKAYQDq8LQCCY0ou0KQWQuyhcaUZQR76T2EQ Dm3YAVEzCefQJixdflZcNbQWmj/sFyJnYBjQnRJIq6zEgn4so88ITjiKXFW3/j5zpeIM m7sWzo/m9uoU7TFL+5P03AAVhRB9Bl7F8duzGbWkQGMFpy/f3zkwNMGmbZICPjL23YJ/ JtLSomXDaptNFxnsO52tHRpu/vXGBmnUpvdd80poow5vpmZ2Cm11ejxRltYOe2bEM8P0 rZLYxoXsyMJIBMATG3zR9sLe+uqqWIGJxiY7ovhkK7wVl/9lb1jOwj5zGW8cgBBU7FeW 9ESw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=biC6MyaV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id rv6si12190457ejb.320.2019.07.26.10.55.35 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:55:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=biC6MyaV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42368 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4RI-0004UD-1X for patch@linaro.org; Fri, 26 Jul 2019 13:55:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58768) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NP-000571-VT for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NM-0000ge-UY for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:29 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:39536) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NF-0000Km-OS for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:28 -0400 Received: by mail-pl1-x641.google.com with SMTP id b7so25061209pls.6 for ; Fri, 26 Jul 2019 10:51:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hWnZNwWI4tI65PwmLTIEUSuYbSd9btmA82x5Eaqyf6M=; b=biC6MyaVGYFUU+cB3fOZf2CH56rijwNd+mbIDwMD/XMxGqHlYgByj4Xxk0GTWLZGkk C8vjr7X8hcWBwDmMYCPejSm1uI3kVaitNj3XhzKz6bPydefsq9J7Ih54rvv3rubBE+QM 86np2g8e+Dy3H1875Gs/DddVboAbbaL7FsPI5gM/2zqQPbXmsvr0ToaYymCxFjkPL1ag I6dNr4ipNEpDbDlVwa79TTrvB8gURN3C0DIbZiBWGcocBwO2Eie+I5Kklnoyg4X9p1pA NeOPc/Ya1lLfInbFUL37f1cZfALcblvODxlEGoIGuyOOjQdLxfa2c2VfelqdLBFp29Nf tofw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hWnZNwWI4tI65PwmLTIEUSuYbSd9btmA82x5Eaqyf6M=; b=KUaOr1/Tb5kERN+F7454wPyTiYeeCx+rQKa5N24pWN6N3W1M1fHpaqtl0qx3CQtK4Y H7UkmTFyieFiWfujmsTxuLETlupysmDQm6I6+KVjKUUA4Ti2uidsRtaUxIdOyrkTlHUp jBhzeiVjaSmJmifvju2hDJ/tFcNy1cj008O3JLMuPMuzh7ciltIYYDUQLD9dJ0+jqr+Q BuGQ8ZF2dxioeXfiHNPsXBCbbUidkL/3sS/deYkg1X8kgNxBmGSMT84YI/sb5KdWtjLt INQj5renwrHSRlVKCJVP1jMDKkItpHA6BdgbU7jZAEWog2PJDyx9VD5E3v/Vh8RIlGm5 rSQw== X-Gm-Message-State: APjAAAVPXHE3U8ML1XUFPXz4Zt8VioJSqoW0ObrJALUwfMBbmQmwQECb c+WkfDTEB/a02BtW/LrBcFtr+pgW1Kc= X-Received: by 2002:a17:902:8207:: with SMTP id x7mr97754983pln.63.1564163478040; Fri, 26 Jul 2019 10:51:18 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.17 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:02 -0700 Message-Id: <20190726175032.6769-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 37/67] target/arm: Convert Unallocated memory hint X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 -------- target/arm/a32-uncond.decode | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5366741d7b..87cbadc6cb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10227,14 +10227,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } return; } - if (((insn & 0x0f700000) == 0x04100000) || - ((insn & 0x0f700010) == 0x06100000)) { - if (!arm_dc_feature(s, ARM_FEATURE_V7MP)) { - goto illegal_op; - } - return; /* v7MP: Unallocated memory hint: must NOP */ - } - if ((insn & 0x0e000f00) == 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ diff --git a/target/arm/a32-uncond.decode b/target/arm/a32-uncond.decode index aed381cb8e..afa95bf7aa 100644 --- a/target/arm/a32-uncond.decode +++ b/target/arm/a32-uncond.decode @@ -64,3 +64,11 @@ PLI 1111 0100 -101 ---- 1111 ---- ---- ---- # (imm, lit) 7 PLD 1111 0111 -101 ---- 1111 ----- -- 0 ---- # (register) 5te PLDW 1111 0111 -001 ---- 1111 ----- -- 0 ---- # (register) 7mp PLI 1111 0110 -101 ---- 1111 ----- -- 0 ---- # (register) 7 + +# Unallocated memory hints +# +# Since these are v7MP nops, and PLDW is v7MP and implemented as nop, +# (ab)use the PLDW helper. + +PLDW 1111 0100 -001 ---- ---- ---- ---- ---- +PLDW 1111 0110 -001 ---- ---- ---- ---0 ---- From patchwork Fri Jul 26 17:50:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169911 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp364208ilk; Fri, 26 Jul 2019 11:01:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqxK53lNLn/2im3PO7cj5VtqYbuNBRU+3ObvfXiHFQZQVVkwW3mgqcIjC9sIgUWTkWyY2vkj X-Received: by 2002:a17:906:2544:: with SMTP id j4mr36776001ejb.221.1564164103269; Fri, 26 Jul 2019 11:01:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164103; cv=none; d=google.com; s=arc-20160816; b=Xm2aw/diASaSnRWwOTZTt2xcxnhy9J9Lu6wdHi0eKUlRYAuCvCk1lYo9CsIazzU8cN mEA9bwJecuvp0R3GnBl2jmA2m9GuqWN9DuN6TJV7e6M+0uaPIJ5T9lUNSIkmHOPGWdd4 fbbfY6UYw++SBURwjxcepCaPjt+0qrQwmdZ1mdpRB6jDG+FhurGPnucs7CGN+BwxlN3f PtRLRipcF7TDKHgT3kfMYvX/tclFISk2KpFwaTs/bW0G+iGNSZvKKJqbCdUCuMzp8VRL NNJuBWeMuZeoFNQXIfWlpVcbZipYoo7EHirp4kQHpscYYNYb+yfHmZXzBD0Vvh9JNlOL ObxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Sh9+ZbJZjCNeBfWv5489FRe5+z+odNhGeCbGO+HiiUM=; b=Nge4zhXXyhp75yTzDEtYDbEWKyxgbdmRCKmGCZ7J3rBcB9yncDasTbhoqbinWhXK0O IG0GqID/9zfU14xYtgqurHsTI5o67EyuA41kyauFxcz962o29QxAH8c3ctHP7twj42Tv jLHQvBH3/KP3lDMQZejLISagBRjExoctJnZNqP9aaA8+45Li1Gi1+mRCQpf3kAuBrNW+ yT9slw16UHzU3VUeDWyuzPqCofBc0at2gvIK1YU2hT4JfB4eXexjjEJAzwLnDK+xn7rl xGdQlPTglS1EXYX0ANz2hFM7MwXAoaQNbvoFE183t3fqFpHWKEmG38/pH9CFTS5986bN nflQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nHWanicV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a17si12764415edd.199.2019.07.26.11.01.43 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:01:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nHWanicV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42609 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4XA-0004yv-Jc for patch@linaro.org; Fri, 26 Jul 2019 14:01:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58576) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NJ-0004mR-G3 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NG-0000T7-V4 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:25 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:43562) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NG-0000Le-PY for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:22 -0400 Received: by mail-pl1-x62d.google.com with SMTP id 4so18030666pld.10 for ; Fri, 26 Jul 2019 10:51:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Sh9+ZbJZjCNeBfWv5489FRe5+z+odNhGeCbGO+HiiUM=; b=nHWanicVGZ+qNGihaHKG85M750QwrldYoN11uKvwbnjDBGSisIypWdoJ8JzDCR1u8b KoI3yYYEHzlQenCMcv8EathuGgc1N6OyaNpRpZaOZ3IQwcC07IZv1yZIO3ZuNO3KqlG9 OVQpMgFzohzX/SDfTeEylpQoxoRVzecAnZL31DbEugHVwn8QZO+K0J9j1f5JfbaTk+4V npXHQhVC8tU7092et4/ZyCSr5+cwCli+L5yBk+f6FBBq3xPk9S2PzPKviS3oZBW2dx80 MrVj6hlxh/0AafF9knjwQ1qenR1yijqamnUl2bOZtul8DTo0HVf3mfxv7StYGfihh9su MaJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Sh9+ZbJZjCNeBfWv5489FRe5+z+odNhGeCbGO+HiiUM=; b=UeSoj+YHJTGr5XU+hBG522E/XOPg48a7KP1bLUtTpC50tX5z+Xa+sgYsY7TkbFbtSs vl3rICTExVmf8FXVCvItlVXUgeCeWoUvQi+9L96JH91lWlseXxA09GNTfVezJkL3upOW eXzSSJlt/T4W+iJxb0Q0c23CriAJinSvlwBzI2R9DXeWuPp0sZTsF58VN9+/67372KyZ YCovWDsPtWegDl6x8PHyRQmQKeN6k+uoO7QWGnxiFyQqmuPyjCozpqMatmIzYXwloUqg /rIbY+fQFWD3m5jqwFAZbozOsD+X/nkOThDQc9UiAbLVSadFldQ9Z6g2kLuJAm7mwrUD 7dog== X-Gm-Message-State: APjAAAV8tOxqV6YuczMza0Makmqrne+X5s+Roo7hey8OulEG/iXSZsGr VixGGoxgLQTaUgOTS48X7haJRFlX8M0= X-Received: by 2002:a17:902:704a:: with SMTP id h10mr95313561plt.337.1564163478965; Fri, 26 Jul 2019 10:51:18 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.18 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:03 -0700 Message-Id: <20190726175032.6769-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62d Subject: [Qemu-devel] [PATCH 38/67] target/arm: Convert Table Branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 62 +++++++++++++++++++++++------------------- target/arm/t32.decode | 8 +++++- 2 files changed, 41 insertions(+), 29 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 87cbadc6cb..9c6623fb6b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9979,6 +9979,37 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) return true; } +static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) +{ + TCGv_i32 addr, tmp; + + tmp = load_reg(s, a->rm); + if (half) { + tcg_gen_add_i32(tmp, tmp, tmp); + } + addr = load_reg(s, a->rn); + tcg_gen_add_i32(addr, addr, tmp); + + gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), + half ? MO_UW | s->be_data : MO_UB); + tcg_temp_free_i32(addr); + + tcg_gen_add_i32(tmp, tmp, tmp); + tcg_gen_addi_i32(tmp, tmp, s->pc_read); + store_reg(s, 15, tmp); + return true; +} + +static bool trans_TBB(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, false); +} + +static bool trans_TBH(DisasContext *s, arg_tbranch *a) +{ + return op_tbranch(s, a, true); +} + /* * Supervisor call */ @@ -10358,9 +10389,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rm, rs; - TCGv_i32 tmp; - TCGv_i32 addr; + uint32_t rd, rn, rs; int op; /* @@ -10406,7 +10435,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) rn = (insn >> 16) & 0xf; rs = (insn >> 12) & 0xf; rd = (insn >> 8) & 0xf; - rm = insn & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ @@ -10479,30 +10507,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Load/store exclusive, in decodetree */ goto illegal_op; } else if ((insn & (7 << 5)) == 0) { - /* Table Branch. */ - if (rn == 15) { - addr = tcg_temp_new_i32(); - tcg_gen_movi_i32(addr, s->pc_read); - } else { - addr = load_reg(s, rn); - } - tmp = load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - if (insn & (1 << 4)) { - /* tbh */ - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - tmp = tcg_temp_new_i32(); - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - } else { /* tbb */ - tcg_temp_free_i32(tmp); - tmp = tcg_temp_new_i32(); - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - } - tcg_temp_free_i32(addr); - tcg_gen_shli_i32(tmp, tmp, 1); - tcg_gen_addi_i32(tmp, tmp, s->pc_read); - store_reg(s, 15, tmp); + /* Table Branch, in decodetree */ + goto illegal_op; } else { /* Load/store exclusive, load-acq/store-rel, in decodetree */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index f8d8660466..17e6dae688 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -487,7 +487,7 @@ LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 -# Load/Store Exclusive and Load-Acquire/Store-Release +# Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch @strex_i .... .... .... rn:4 rt:4 rd:4 .... .... \ &strex rt2=15 imm=%imm8x4 @@ -531,6 +531,12 @@ LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0 LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0 LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0 +&tbranch rn rm +@tbranch .... .... .... rn:4 .... .... .... rm:4 &tbranch + +TBB 1110 1000 1101 .... 1111 0000 0000 .... @tbranch +TBH 1110 1000 1101 .... 1111 0000 0001 .... @tbranch + # Parallel addition and subtraction SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm From patchwork Fri Jul 26 17:50:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169902 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp361437ilk; Fri, 26 Jul 2019 10:59:29 -0700 (PDT) X-Google-Smtp-Source: APXvYqzvvwLZq6EKZFd9XhLMgW8JaJApa564Xjic5NdSo1vIcSficSsRcfVDrdkqMN/Mhn364YlJ X-Received: by 2002:a50:b155:: with SMTP id l21mr83968585edd.186.1564163969293; Fri, 26 Jul 2019 10:59:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163969; cv=none; d=google.com; s=arc-20160816; b=bUAstoA4MTmVyeNbpiaJ8Cwx8hBbdEZTiO2nVq4S051UKV9BfL3BpdAZwOU2Evc/8R tFvPdzzLW7l3+VfkfPJG8V9mXMl4qRFPfzt6pfjGWB1s06voi1FsDB8Az1gXQG2u9Sbt JV5efdvBVmJbbkha9csJAcTLZILJaqQ8ncgt/DFRtgTvLKwpKO2avoSkL+OI65yCNm3N HITkl0vXKFxon08NPJbQ2SwA3/+a9VjBNI9m9TKyx1P/sow59kcZJwxmddsqNJgEX1H/ 48lEULaQ9r5JMGObVnuRjqgi/8yiwoDvanD9E7LOLbyBdMIL6QnmXu1Zj5FSXfIkFqyt Bk7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Nxa/cuCHMs3HeU9P7ofD/RBscm9ah4Tq+3WaXVFVTi8=; b=aWeo6p5nm8XlHdZIbT1lN6FDeGD7EY9oTqrvOIeAN5CjNYXJ/kHHDX7EiBAHihBKu/ vSYXzK1c0ASX0SxNn5ux1i85IriIQFBI4wOaFLVuCYJnJWA4UktxqauOGnlkBc1fw1Ig OH8SVXxboS+fqGHArzeH4u+3RuEQgtcf4MNqOvzT3QEOpE9jJaBCZkl5ZZZo3zP+HUHJ hb9z7gtj9929+61p7HRWRYula0gSiK9Va1d5Bs8vzkk1dJswXmQKm4Hwu2rORojIjuhC Er1SOkEcRWu7i7OZoNChtCyyuUE++wzntywIG3Zp3bsn4Hfi0Zv38i6lRbXpQUPO985+ +3VA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=khOm4Ns3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m38si13382401edd.215.2019.07.26.10.59.29 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:59:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=khOm4Ns3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4V5-0004KA-S6 for patch@linaro.org; Fri, 26 Jul 2019 13:59:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58630) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NL-0004ql-EV for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NI-0000WJ-1W for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:26 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:37883) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NH-0000Mz-QC for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:23 -0400 Received: by mail-pg1-x542.google.com with SMTP id i70so14371649pgd.4 for ; Fri, 26 Jul 2019 10:51:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Nxa/cuCHMs3HeU9P7ofD/RBscm9ah4Tq+3WaXVFVTi8=; b=khOm4Ns3aOhzviXJxUgm0+U2fW4iOx0h/eq74+vKDGl0DyGQuc4eDWoSE4OzDkBOhs xvQkkAtF7ajTyt1lFY9jhcACRUSCCCDesn7Z8XZRKDVbT9u2Bu0vxFscV8ZP9pW5KEMG l9h6BJYyqh2qF5Ja1rZSe2610pr8qQ9XFeIevU4Uct4VWbPIGWM9sz0+H7EjRqxpUf9D 9KGs23yt1JJ0Rh6hbhxoJtd06zf8yR6wBM0l8NwGyQFAbDARrKuJ+FgNXa8QOy0ShCPb 2DX392DuNA0ktSa9h9kw5BboG6n04lCwB5hg6IH0q5eXUe3Ku8N2fwgGZMd+N3pVhJiP IlKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Nxa/cuCHMs3HeU9P7ofD/RBscm9ah4Tq+3WaXVFVTi8=; b=jgAX7rLjK0xh8v+wxTcppyt+50tGpkufECZnDqAen+kViOG96fyDD/GOsDx5UnaKSu +LRRopIPhORlaHQBCVBWl/zJXn517HpwGyr0l+gij6zPU0MnxguxVwn188mMpzHHvH+4 xL5uGUhmBSNCqbKfQcSljbnYLjkE+qAISJEK5dhXqQu1IJMIC+VUkUh20Kc3udpb7Jv2 ZHEqvbj5YDuLJRTcy/SWZ8Lc6MP75D4ktW2rjPAuwhTZ0rRnIeEoY0NtsiBPl31Rinc4 RQ5n4SmGyVXx+qDmpD/TQyVU1dsxVIy8pHIK6u8ZLCK6tlXY69zrxKA7yxFyTi6EhC8D ZNBA== X-Gm-Message-State: APjAAAUdnXAv+6EHy6YJZyV3qudmWMy4sx6qVQN9eSh2EyOgLLBIkJ2n zZ5+Q3xsMyyAq8mLBkTBt7X4Ovxo9m0= X-Received: by 2002:a17:90a:ac11:: with SMTP id o17mr100549798pjq.134.1564163480128; Fri, 26 Jul 2019 10:51:20 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.18 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:04 -0700 Message-Id: <20190726175032.6769-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 39/67] target/arm: Convert SG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++++++++++++++++++++++++------------------ target/arm/t32.decode | 5 ++++- 2 files changed, 33 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9c6623fb6b..df515e9341 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8497,6 +8497,34 @@ static bool trans_SMC(DisasContext *s, arg_SMC *a) return true; } +static bool trans_SG(DisasContext *s, arg_SG *a) +{ + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + /* + * SG (v8M only) + * The bulk of the behaviour for this instruction is implemented + * in v7m_handle_execute_nsc(), which deals with the insn when + * it is executed by a CPU in non-secure state from memory + * which is Secure & NonSecure-Callable. + * Here we only need to handle the remaining cases: + * * in NS memory (including the "security extension not + * implemented" case) : NOP + * * in S memory but CPU already secure (clear IT bits) + * We know that the attribute for the memory this insn is + * in must match the current CPU state, because otherwise + * get_phys_addr_pmsav8 would have generated an exception. + */ + if (s->v8m_secure) { + /* Like the IT insn, we don't need to generate any code */ + s->condexec_cond = 0; + s->condexec_mask = 0; + } + return true; +} + /* * Load/store register index */ @@ -10445,28 +10473,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) * - load/store doubleword, load/store exclusive, ldacq/strel, * table branch, TT. */ - if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_M) && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1001_0111_1111_1110_1001_0111_111 - * - SG (v8M only) - * The bulk of the behaviour for this instruction is implemented - * in v7m_handle_execute_nsc(), which deals with the insn when - * it is executed by a CPU in non-secure state from memory - * which is Secure & NonSecure-Callable. - * Here we only need to handle the remaining cases: - * * in NS memory (including the "security extension not - * implemented" case) : NOP - * * in S memory but CPU already secure (clear IT bits) - * We know that the attribute for the memory this insn is - * in must match the current CPU state, because otherwise - * get_phys_addr_pmsav8 would have generated an exception. - */ - if (s->v8m_secure) { - /* Like the IT insn, we don't need to generate any code */ - s->condexec_cond = 0; - s->condexec_mask = 0; - } - } else if (insn & 0x01200000) { + if (insn & 0x01200000) { /* load/store dual, in decodetree */ goto illegal_op; } else if ((insn & (1 << 23)) == 0) { diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 17e6dae688..c0b962479b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -485,7 +485,10 @@ STRD_ri_t32 1110 1001 .100 .... .... .... ........ @ldstd_ri8 w=0 p=1 LDRD_ri_t32 1110 1001 .101 .... .... .... ........ @ldstd_ri8 w=0 p=1 STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 -LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 +{ + SG 1110 1001 0111 1111 1110 1001 01111111 + LDRD_ri_t32 1110 1001 .111 .... .... .... ........ @ldstd_ri8 w=1 p=1 +} # Load/Store Exclusive, Load-Acquire/Store-Release, and Table Branch From patchwork Fri Jul 26 17:50:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169907 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp363134ilk; Fri, 26 Jul 2019 11:00:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqzNmBsWLpALyFciCphmEloEXUxXgU0WAEiXB+2LcY54DGQUI53jBeITJ8NHsBQvn+92Immv X-Received: by 2002:ac8:670f:: with SMTP id e15mr64767527qtp.191.1564164055794; Fri, 26 Jul 2019 11:00:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164055; cv=none; d=google.com; s=arc-20160816; b=jZISBhpn/Q9VzOp6BvUclBSblcJzn7frdkL1+uKnTjHBdXKD7CfEvXaRKGW9CvTjRL 5B5FmtJM3Vw8lAUKZeu5lNSjSfpRp3QrxEYPZMZG0fiSN8vgvyYrF/0/xao9ewSyeRBW 4Q7SuXpXYjAwSNtn7Hql0a0bGNhm+TA4POWEaZ4rjhBrBGAmfSSl6VKF/ABbujWWoaRl kGq3ljhUtDfQJ2R55azILaJW4Q2FVgHJQ/Wak725qis+yT7Vfwrey1e5b7J9U95nRLde 4Lw8HTAm/bWgLhtjLfzVlw0tiAt6yXlICAn3qgqEHb0xZIP4CswOqLX6Pt5PQrC9tfOe SWXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=8jS7+sK+VOWigPY1q5W77YMTHCuDnHzgvWGfuf+9BAA=; b=PqPwSvyGXrx14SFe5ANxcKsdYfiShkVL9Uw/EkpATOPg7lZm8ZYJLBaXhGsPvSe2b1 zjKof2bxax1uWDPZ47ergZ0xRg71jNgnnzwop2reutBZEYafQHd7S9cOFO4pnNyWjn5z MxOyTHw7tVxDEFMe0uneynIttsALuKhQoWm4A35deEYrb1LyAPNg652d5eJMbinrczId GAgtzGfpDkDkb8CJGrHRxwA1GonZOyX3UvZ2wdMiP7phnvjmECwuUybA4Wfwpi4O0ntI gTp9OlJFYHAyAAzO6eYwvB4oq11tFc4amtkfhGa2ghCrueYKGCIRcLiGmLgT+eUYfh2+ vy6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=azOLCzTt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l26si29541421qkg.62.2019.07.26.11.00.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:00:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=azOLCzTt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42586 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4WS-0002DH-Ba for patch@linaro.org; Fri, 26 Jul 2019 14:00:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58650) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NM-0004uS-94 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NI-0000Y2-Sj for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:27 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:39453) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NI-0000Q4-I3 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:24 -0400 Received: by mail-pf1-x431.google.com with SMTP id f17so20864100pfn.6 for ; Fri, 26 Jul 2019 10:51:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8jS7+sK+VOWigPY1q5W77YMTHCuDnHzgvWGfuf+9BAA=; b=azOLCzTt87mhEvZFoPs2GqxB8az68wv1L3gzdeqQyminX1GfMMN/y2NhMugWSWXLTh paPKGB/xNH6LmwFw5tPCnouRsT/gUWKbiJ2aA4wbDDAZ+e5f00WE6DOBjcPw86sAXB23 z+l2WRBmT6CLb5DRxMdRoUfoIqWPfrXqS9UXeqfstMCH9b4pbEtRiyHuMRlKXbqEQXdk kGggh7bdixhrz8OLp+a1yYKX+a7zdHoPvE0ATHWcxOMTOv9kM0mkCpPM4ksBcMEaXIXQ uHgkKqTwI2rjqk9McXYXLwyNEKAiE8Py5tUsiG7eKaQpb+YReNN6cChZUt9yU02MZ5eG lmcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8jS7+sK+VOWigPY1q5W77YMTHCuDnHzgvWGfuf+9BAA=; b=TgsnhOBIXzI1PndDgpaitPfwQYnlM9LDwcE6b2MHEKn0+NZzVpXhv93hNexFXYllBt kLzWFIkpnBmhBFBtk6XJIPM0TNwFZI/stve42b1IiI5Se6iTrnq48us2ZOcTjDB06kW6 uBy7OhP7B0m6JUG1EwXzAxk3kpM8fA17XJ32GwHBiZylak4Bshtip8Sjg1EpM92WBUTW R8PN/HPlH+YipS4x4P7AlB6OeLxztG64wIo8XMbW7kCR63EG+PvymjfIzes1BPYAp+rI spPEwreCCeosa8mBs43vHHtY0hiKWoUp1IEQ3HfAOmkICBAZ7ZUAzCHivDF3PYANQc5d dDNQ== X-Gm-Message-State: APjAAAUn7hqMHjgng/SeGMSifUhb03aHTyDqryGSSkF0ALJGYa672wJo nJd1dqvqZI9BLe/7Z7kJKVa3W/wtXLU= X-Received: by 2002:a62:2d3:: with SMTP id 202mr23840798pfc.131.1564163481243; Fri, 26 Jul 2019 10:51:21 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.20 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:05 -0700 Message-Id: <20190726175032.6769-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::431 Subject: [Qemu-devel] [PATCH 40/67] target/arm: Convert TT X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 88 ++++++++++++++---------------------------- target/arm/t32.decode | 5 ++- 2 files changed, 32 insertions(+), 61 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index df515e9341..a750a2c092 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8525,6 +8525,31 @@ static bool trans_SG(DisasContext *s, arg_SG *a) return true; } +static bool trans_TT(DisasContext *s, arg_TT *a) +{ + TCGv_i32 addr, tmp; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + if (a->rd == 13 || a->rd == 15 || a->rn == 15) { + /* We UNDEF for these UNPREDICTABLE cases */ + return false; + } + if (a->A && !s->v8m_secure) { + gen_illegal_op(s); + return true; + } + + addr = load_reg(s, a->rn); + tmp = tcg_const_i32((a->A << 1) | a->T); + gen_helper_v7m_tt(tmp, cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + store_reg(s, a->rd, tmp); + return true; +} + /* * Load/store register index */ @@ -10417,7 +10442,7 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rd, rn, rs; + uint32_t rn; int op; /* @@ -10461,70 +10486,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* fall back to legacy decoder */ rn = (insn >> 16) & 0xf; - rs = (insn >> 12) & 0xf; - rd = (insn >> 8) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); case 4: - if (insn & (1 << 22)) { - /* 0b1110_100x_x1xx_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store doubleword, load/store exclusive, ldacq/strel, - * table branch, TT. - */ - if (insn & 0x01200000) { - /* load/store dual, in decodetree */ - goto illegal_op; - } else if ((insn & (1 << 23)) == 0) { - /* 0b1110_1000_010x_xxxx_xxxx_xxxx_xxxx_xxxx - * - load/store exclusive word - * - TT (v8M only) - */ - if (rs == 15) { - if (!(insn & (1 << 20)) && - arm_dc_feature(s, ARM_FEATURE_M) && - arm_dc_feature(s, ARM_FEATURE_V8)) { - /* 0b1110_1000_0100_xxxx_1111_xxxx_xxxx_xxxx - * - TT (v8M only) - */ - bool alt = insn & (1 << 7); - TCGv_i32 addr, op, ttresp; - - if ((insn & 0x3f) || rd == 13 || rd == 15 || rn == 15) { - /* we UNDEF for these UNPREDICTABLE cases */ - goto illegal_op; - } - - if (alt && !s->v8m_secure) { - goto illegal_op; - } - - addr = load_reg(s, rn); - op = tcg_const_i32(extract32(insn, 6, 2)); - ttresp = tcg_temp_new_i32(); - gen_helper_v7m_tt(ttresp, cpu_env, addr, op); - tcg_temp_free_i32(addr); - tcg_temp_free_i32(op); - store_reg(s, rd, ttresp); - break; - } - goto illegal_op; - } - /* Load/store exclusive, in decodetree */ - goto illegal_op; - } else if ((insn & (7 << 5)) == 0) { - /* Table Branch, in decodetree */ - goto illegal_op; - } else { - /* Load/store exclusive, load-acq/store-rel, in decodetree */ - goto illegal_op; - } - } else { - /* Load/store multiple, RFE, SRS, in decodetree */ - goto illegal_op; - } - break; + /* All in decodetree */ + goto illegal_op; case 5: /* All in decodetree */ goto illegal_op; diff --git a/target/arm/t32.decode b/target/arm/t32.decode index c0b962479b..90db05dab6 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -506,7 +506,10 @@ STRD_ri_t32 1110 1001 .110 .... .... .... ........ @ldstd_ri8 w=1 p=1 @ldrex_d .... .... .... rn:4 rt:4 rt2:4 .... .... \ &ldrex imm=0 -STREX 1110 1000 0100 .... .... .... .... .... @strex_i +{ + TT 1110 1000 0100 rn:4 1111 rd:4 A:1 T:1 000000 + STREX 1110 1000 0100 .... .... .... .... .... @strex_i +} STREXB 1110 1000 1100 .... .... 1111 0100 .... @strex_0 STREXH 1110 1000 1100 .... .... 1111 0101 .... @strex_0 STREXD_t32 1110 1000 1100 .... .... .... 0111 .... @strex_d From patchwork Fri Jul 26 17:50:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169909 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp363610ilk; Fri, 26 Jul 2019 11:01:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqy2LFvcHSOVRZ8VKw4uboujQJNEuHBobVyURdkceegxs7B/IahiRsrmBTr7zMyq8fR9dy9N X-Received: by 2002:a05:620a:1393:: with SMTP id k19mr61614849qki.67.1564164077749; Fri, 26 Jul 2019 11:01:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164077; cv=none; d=google.com; s=arc-20160816; b=AmmhyaQnC2GcAkrNvJk5LYcbmWJ/bY1Hf2mVHb1vyIdFbV2X4hsHargqjI+oQHUm5+ sszHR0cib7OWoZtuA3GFIqiTYpX7rSFcCNRms128dlq35JOVDbUNU9RKrSgsN0fcNms+ 5MDFKCW16qQkexOqxJTRePf43h1l/0s+1T1BZMfREHQm3EVvk1+yedVLDZ0j6QNzQelK lzv7FqcKIXJHyecvIE9jJoHCR/lTz7jItkFXM+xDatlzOJH+FdDanDIOxhx9T75dj1MR DxFGplA+J1SQmKNi7O8lFQYaDcQs45/ZFK3LVIpqcHIErRMVsScqJQvPt7htlswunaoX hfOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=j/Y5KQrISdOhV+y6GL73HUL9WgurT5sljbcK6vWGUPQ=; b=cklTZWEomHvIV2uBBrVWTmujJTj7eTpVEB4rIrjyp06rGfKcx/41kM7j/334Cx33mH vtPyCg7Y2cJaVFxL8bZwdqtvyvzlyzyjqrjZAtG0iA5fITyDNN9fM5Jk3tQOeklRKEeh TnU9NlZmnpKaLdebTnRvRssa9mOhCo89roqcMSqtblLcOY4MLIrOlF1NGGWbBu3KWJzR 4evAxbpGvspaAL3XfRFbm49u5XJz28jvBBOoYAx/9mBFO5In3IjW8kStWJOlKeBAtfSf AUFW+ljuHWALFOnaMPfigmtzBpeWRrvkbT3fETSPDhy70gUwj5LEi2rppiVFZGgnTxzi ByUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DqavtkYf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l33si35526607qtc.281.2019.07.26.11.01.17 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:01:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DqavtkYf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Wo-0003VL-Oe for patch@linaro.org; Fri, 26 Jul 2019 14:01:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59232) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nj-0006SG-6o for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Na-000133-GA for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:46 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:35148) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NK-0000Zw-4h for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:41 -0400 Received: by mail-pg1-x543.google.com with SMTP id s1so18806272pgr.2 for ; Fri, 26 Jul 2019 10:51:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j/Y5KQrISdOhV+y6GL73HUL9WgurT5sljbcK6vWGUPQ=; b=DqavtkYf6IoaO0cuL4mNyqfvDRLI7vMm1q5C6uakUbdR1LJVwBUK/A2/zSn7JYdFIb JmuV2mTZz/QPX5By/YKKcQKnFqY3PjyOTmI5seSXG6bqSEgDCc4o9W1A/plSu+LFK30X 9Py9W/i1te/HU0WXoOWP4ld3bcytoz+Zki97kJvPSivIb7aYPZDSJYP7Jm3SqRjtEo5m KJM1qmBiC9XJG96QyNea+d98JS0jgGzaebqJA2gUR7Vxen9LlMfgULsw7Mmv+jT5pJff PF4SvbnedhlcXh2MXHiaZ53KbsHcggYXBb7XfPAFyiaG18nbmLisYo1Hymbw1mokXu4z ZZ/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j/Y5KQrISdOhV+y6GL73HUL9WgurT5sljbcK6vWGUPQ=; b=qvs4/xU8tGk2rFh8CPX3LQfEQrZVWlfyX2+qz8waiEu+NUEOd12zDEFUPK/37nesol va9Gt1J3lG4uEFnEPZxN6CcPxwBlKsTn29rVv89uT21ac2gw11/Y8cx2F+rjk8IhLWFC BIEMuxo8vXU11jRcNohrsvytMAaLOSx9q8+JQY8R6klQMXruR9NpOr/f4hODsnzyWj0H ZAueEq9nko1+otlPqwoCmBybvN3MDG1xzM02ZTdplO2+D2vSKVzlNehfU07F0sIocwhd DLOi/Df9tDQ/pb/qdq45kfCZMGmFh2Rr4/kcs683qk6l1Pihn9/LJp4Fc6qMKZaH8Ymf FRjA== X-Gm-Message-State: APjAAAVfVL2PPZAku7ecUkHj7wGe0dweq6iKVUGqE6ecsgNJjjtnHosv 3GiGZDEDPKJ41klv/sqvSdAcg3iYR9g= X-Received: by 2002:a63:2c8:: with SMTP id 191mr91127952pgc.139.1564163482963; Fri, 26 Jul 2019 10:51:22 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.21 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:06 -0700 Message-Id: <20190726175032.6769-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 41/67] target/arm: Simplify disas_thumb2_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Signed-off-by: Richard Henderson --- target/arm/translate.c | 78 ++---------------------------------------- 1 file changed, 3 insertions(+), 75 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index a750a2c092..836b3752f7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10442,9 +10442,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn) /* Translate a 32-bit thumb instruction. */ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) { - uint32_t rn; - int op; - /* * ARMv6-M supports a limited subset of Thumb2 instructions. * Other Thumb1 architectures allow only 32-bit @@ -10485,34 +10482,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } /* fall back to legacy decoder */ - rn = (insn >> 16) & 0xf; switch ((insn >> 25) & 0xf) { case 0: case 1: case 2: case 3: /* 16-bit instructions. Should never happen. */ abort(); - case 4: - /* All in decodetree */ - goto illegal_op; - case 5: - /* All in decodetree */ - goto illegal_op; - case 13: /* Misc data processing. */ - op = ((insn >> 22) & 6) | ((insn >> 7) & 1); - if (op < 4 && (insn & 0xf000) != 0xf000) - goto illegal_op; - switch (op) { - case 0: /* Register controlled shift, in decodetree */ - case 1: /* Sign/zero extend, in decodetree */ - case 2: /* SIMD add/subtract, in decodetree */ - case 3: /* Other data processing, in decodetree */ - goto illegal_op; - case 4: case 5: - /* 32-bit multiply. Sum of absolute differences, in decodetree */ - goto illegal_op; - case 6: case 7: /* 64-bit multiply, Divide, in decodetree */ - goto illegal_op; - } - break; case 6: case 7: case 14: case 15: /* Coprocessor. */ if (arm_dc_feature(s, ARM_FEATURE_M)) { @@ -10541,6 +10514,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } if (arm_dc_feature(s, ARM_FEATURE_VFP)) { + uint32_t rn = (insn >> 16) & 0xf; TCGv_i32 fptr = load_reg(s, rn); if (extract32(insn, 20, 1)) { @@ -10599,49 +10573,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } } break; - case 8: case 9: case 10: case 11: - if (insn & (1 << 15)) { - /* Branches, misc control. */ - if (insn & 0x5000) { - /* Unconditional branch, in decodetree */ - goto illegal_op; - } else if (((insn >> 23) & 7) == 7) { - /* Misc control */ - if (insn & (1 << 13)) - goto illegal_op; - - if (insn & (1 << 26)) { - /* hvc, smc, in decodetree */ - goto illegal_op; - } else { - op = (insn >> 20) & 7; - switch (op) { - case 0: /* msr cpsr, in decodetree */ - case 1: /* msr spsr, in decodetree */ - goto illegal_op; - case 2: /* cps, nop-hint, in decodetree */ - goto illegal_op; - case 3: /* Special control operations, in decodetree */ - case 4: /* bxj, in decodetree */ - case 5: /* eret, in decodetree */ - case 6: /* MRS, in decodetree */ - case 7: /* MSR, in decodetree */ - goto illegal_op; - } - } - } else { - /* Conditional branch, in decodetree */ - goto illegal_op; - } - } else { - /* - * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx - * - Data-processing (modified immediate, plain binary immediate) - * All in decodetree. - */ - goto illegal_op; - } - break; case 12: if ((insn & 0x01100000) == 0x01000000) { if (disas_neon_ls_insn(s, insn)) { @@ -10649,14 +10580,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) } break; } - /* Load/store single data item, in decodetree */ goto illegal_op; default: - goto illegal_op; + illegal_op: + gen_illegal_op(s); } - return; -illegal_op: - gen_illegal_op(s); } static void disas_thumb_insn(DisasContext *s, uint32_t insn) From patchwork Fri Jul 26 17:50:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169932 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp386948ilk; Fri, 26 Jul 2019 11:22:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqwqYBl9wgBl6gouysOtcXbYhYJ9yjx1BFqmGS/2zcexPcXcwbevO3RYscM8GgrJsctsZGhB X-Received: by 2002:ac8:23c5:: with SMTP id r5mr69368855qtr.319.1564165327211; Fri, 26 Jul 2019 11:22:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564165327; cv=none; d=google.com; s=arc-20160816; b=B/yKfJ/Lp34PwpIj8tcG1Fh/J/RBFN6mqUedfe3d8V6vXv3485mH6D0+/s5YxgM3Tr hnxc3OTNRfF2WNpuLLoyfMRetzzeb9N1+vGXEjc5aCJ2pyCklxdu01QHEpCtTXhLRB9u v2BuSc3bbG/JKv1nJ0/VV2q6yE7asjjUJA+h2ooz8GOhJFLvAJ3VAblDTsFZ6rF8tNuW ATQKLVcdwk2AlvlTddrAGX1Vu34JV3G4y7LBf76+vnP/Dtc83yaShsl/YFoNPX/Dkmwo j/AP1+pD7lPDw5/ERHbOz/TwcvNz8vH2ZZpYeqx9Xo2+LcyJ1GRup4jj/XZBJQoEI9MT X06A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=W3BPBGeDUmZyQaUuLRW8yTB0WQP3Hy+VMnlWae7mNLI=; b=wwwGs47/nAXXLviC/g4QxAfXtlCl9sgw0B3XQRtwDs4XH1xdTdrVbtFbchWNmqNheL FfvUp2/ns6q/fcOxiFTmt06YfeJ6Bi98T8NkAI0pu5C10J46xDKp5n20C4Gl0CMBsLHp A57x4rrE+yyEbMrW39QQoWfWtfGhNmweWes4ptlpO2GohUlyOzsjiYAjNHZDMVkJTDAX sRRb8KBT7eA5JRn3cWpOQpw0RVHRC7hrSGaSC0vac228okAJf7M5fnhOqNSY946X7BEP zTHOfRP1BQkLoP826Npy6nvGBzvlZ94Mj3Ftsj1tT6PHbojt2x457gldB3ka7EjNgvBN V+Yw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e2fvHXQI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w64si31715392qkb.254.2019.07.26.11.22.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:22:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=e2fvHXQI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42648 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4YB-0008R0-Dw for patch@linaro.org; Fri, 26 Jul 2019 14:02:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58755) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NO-00055R-K2 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NL-0000dg-Au for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:29 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:41331) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NL-0000c6-4p for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:27 -0400 Received: by mail-pg1-x542.google.com with SMTP id x15so14765467pgg.8 for ; Fri, 26 Jul 2019 10:51:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=W3BPBGeDUmZyQaUuLRW8yTB0WQP3Hy+VMnlWae7mNLI=; b=e2fvHXQIMl+wPOnNu8W2rqNL50WX5PTNxKgxp9oViVF2Nim5/j+AP4LFKxtn9xE34Z csnLdnCeetCKbD/GthGFGI7aiYowxav48QoktypnxNu2IpK0O4VJRbwMtXyMvXcV1f9F 4ANePOseex7d16MGcl6GK3oeebjVVya2f/tw2VQ4kkKBLtskwxQUNPJAmBDpWSbq/Jb3 DIllizJ9tLPPW9YGyS0WMHIUG6mad/nEkCHSAdb1btmILxccoFGQ1p5ukr2mwQa873dV b/+wX7xUQFNBhsP6NMRCL/dWbM3/2NvHOyflAINZ0UtZL8rf7jpBk+VP3lcn1kfpSf9j nBsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=W3BPBGeDUmZyQaUuLRW8yTB0WQP3Hy+VMnlWae7mNLI=; b=MPr0VNTaHMMETRMK7xK6/UHsz30BjY6bes9zeZvYDTQFgyOKvmH6zndEXfh7zW2OPY BguiCyRqACKFssSuWo/afDP1b0k+4ySP8y3WGb887L7TFWFZHtJl+imINB9Lv4PcPpX3 TqCXlzbK/YASfBPI5E6MqV3b1ZqqHVK3JuJOACr4RKS8s/NEPsTiEgZ+DujOxL5AAr7c 7VNoC7/Sl5AjuXn6b0bkc6Qns3sOb05mixJyAtC7BKB3QWt/YZZYRnnpCnHekPr99sY5 nxkxiBAu6a4RFd0xrJNtvfbQi5TDOejfp9F+aXyFmzG1gDkTozPgZJM6VLweVMYdnmvt NK8g== X-Gm-Message-State: APjAAAVx59t3iATr2hVEc0l1oR/JiV0nXPiRei/kkwfERGdYpKyflc9N SJkSQDhz6MrWBVHeS121GyFEHoYaHuA= X-Received: by 2002:a17:90a:c68c:: with SMTP id n12mr100875680pjt.29.1564163485938; Fri, 26 Jul 2019 10:51:25 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.24 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:07 -0700 Message-Id: <20190726175032.6769-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 Subject: [Qemu-devel] [PATCH 42/67] target/arm: Simplify disas_arm_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fold away all of the cases that now just goto illegal_op, because all of their internal bits are now in decodetree. Signed-off-by: Richard Henderson --- target/arm/translate.c | 69 ++++++++++-------------------------------- 1 file changed, 16 insertions(+), 53 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 836b3752f7..65a74a963b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10257,7 +10257,7 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) static void disas_arm_insn(DisasContext *s, unsigned int insn) { - unsigned int cond, op1; + unsigned int cond = insn >> 28; /* M variants do not implement ARM mode; this must raise the INVSTATE * UsageFault exception. @@ -10267,7 +10267,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) default_exception_el(s)); return; } - cond = insn >> 28; if (cond == 0xf) { /* In ARMv3 and v4 the NV condition is UNPREDICTABLE; we @@ -10332,11 +10331,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) goto illegal_op; } return; - } else if ((insn & 0x0fe00000) == 0x0c400000) { - /* Coprocessor double register transfer. */ - ARCH(5TE); - } else if ((insn & 0x0f000010) == 0x0e000010) { - /* Additional coprocessor register transfer. */ } goto illegal_op; } @@ -10348,55 +10342,24 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } /* fall back to legacy decoder */ - if ((insn & 0x0f900000) == 0x03000000) { - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if ((insn & 0x0f900000) == 0x01000000 - && (insn & 0x00000090) != 0x00000090) { - /* miscellaneous instructions */ - /* All done in decodetree. Illegal ops reach here. */ - goto illegal_op; - } else if (((insn & 0x0e000000) == 0 && - (insn & 0x00000090) != 0x90) || - ((insn & 0x0e000000) == (1 << 25))) { - /* Data-processing (reg, reg-shift-reg, imm). */ - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - } else { - /* other instructions */ - op1 = (insn >> 24) & 0xf; - switch(op1) { - case 0x0: - case 0x1: - case 0x4: - case 0x5: - case 0x6: - case 0x7: - case 0x08: - case 0x09: - case 0xa: - case 0xb: - case 0xf: - /* All done in decodetree. Reach here for illegal ops. */ - goto illegal_op; - case 0xc: - case 0xd: - case 0xe: - if (((insn >> 8) & 0xe) == 10) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - } else if (disas_coproc_insn(s, insn)) { - /* Coprocessor. */ + switch ((insn >> 24) & 0xf) { + case 0xc: + case 0xd: + case 0xe: + if (((insn >> 8) & 0xe) == 10) { + /* VFP. */ + if (disas_vfp_insn(s, insn)) { goto illegal_op; } - break; - default: - illegal_op: - gen_illegal_op(s); - break; + } else if (disas_coproc_insn(s, insn)) { + /* Coprocessor. */ + goto illegal_op; } + break; + default: + illegal_op: + gen_illegal_op(s); + break; } } From patchwork Fri Jul 26 17:50:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169913 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp364632ilk; Fri, 26 Jul 2019 11:02:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqyS0LzTHK5+ogqopUXniQue3sIVB7MrKBGzwO1x8DhpMVy++yLUvZ2Wbb3Yj6pZCv2Qp0sK X-Received: by 2002:a05:6402:129a:: with SMTP id w26mr83253708edv.167.1564164121104; Fri, 26 Jul 2019 11:02:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164121; cv=none; d=google.com; s=arc-20160816; b=FLrtcjs1kAREx9eJREA8PML+Z1ENrGuFA7CDa668h8peoHull1HdU4FY38dBGwjVLe DRI+a5bz/xva2WqLhMQ/c8EdOAroEKZUHNivyoYs7mGHCVFlBbW7JzRxAgvSv5YSUt9K S46rvwW3iKeKNOQmURVUW0kArCqeWp8nHYkAGBFBobt9mgprGUed+TQNdc8yf3PzQ1sV TGc5hg50PyEG13lsSrMPRwXfcwMAuSo127Tm9RdqTtN4jra0qk2k0BFpSOPxawKhy27H JrkdvSuZpvi+0nl1xpW+4VSgm62pq9467KleGzV34GlLR3egCNu7vmfpjxCE+Plzf6rx i0vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=BeJ+pb6ctnzLHVd1R33fd022stp222LK5CW6SHtredI=; b=J4mIkxiDRxF6QYhNH4CJYNPU9/WoerXxbbZxQHIPTgy/RrKVgAu5xEHhCqJOlxV5Kj G3gUFGbu9nlPNkfF0xpbiB2GZQskeJWHQfEqPSgV2VDlgUaDpKvfgOsesTh+5AJTbtjl 1yo0Hf0R6Z7MMUCsMo1cLNwlItLBwyCCdgz9E/ZWNX/EbJRjzLFIuw6cBSqOB4+1VLH1 5MYdvWJAHTL9TgpZ6qpfBp1C8hgmNo5+nXM8xzwSM2vgviu6YwaTSSlzWMblzJb6XZLT IMtPenbIk3rZJHyGQxa2o8uj1FN8ipQNJbt08WszKC3dXfzuSOwscjC8fT2+AaDyVosQ tpUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pZqwVVtH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u12si11445981ejz.73.2019.07.26.11.02.00 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:02:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=pZqwVVtH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4XX-0006Vv-4A for patch@linaro.org; Fri, 26 Jul 2019 14:01:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58836) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NS-0005Cv-Jy for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NO-0000jk-Cf for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:31 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:41596) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NO-0000e4-5r for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:30 -0400 Received: by mail-pf1-x441.google.com with SMTP id m30so24865980pff.8 for ; Fri, 26 Jul 2019 10:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BeJ+pb6ctnzLHVd1R33fd022stp222LK5CW6SHtredI=; b=pZqwVVtHLxWhL94AkDYYgYTXk1sGL8fnfLESWlIPloluyfnCXCrXrlQok3gH3Hod8O 2DN/m31BMtPDGnBdhJnjasfsVoc1IaApeEhwh1gauPzgOg1nOlUkhOAb5YQ6cMKc/uuI xTXO7w0KqHU9ePwl25vFJ9t3j7lZhhIm7LfaLB8VS09mSmvVza6OBAZSlvZVjEfNO3YV WXcJJWCrCyq9Qgp0PpBCC62jmn4n3hhYfoJdDWrERwKza+p4pLDjfCeSPRmNW11iy9o9 5FqdDPpou1NF9S7wRRJGkdWOIZVsgWB6ygCM6m1oF75PJucJWmwWIY3scZSG3DpS5Wkg NReg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BeJ+pb6ctnzLHVd1R33fd022stp222LK5CW6SHtredI=; b=Rltmb1lQvSv9YFSg7QNyed+asvXNd5Pyfg3U9nUdwGocgraRf7xc7RSsNiqZxNw30W hTg8TkuAp1yxSq+fEmHiqmIGIukp4axFwGmUKPs5nVC92P4LUC/zQJ+2qSjHkvSZANK7 +qyhODLoHSDViDAbhU6U9hD2TsJC/qHS9ZCI1OsBCKvsabPccCGlgqLC2tKuXr3RYPGc 2qhpnVCO1gSz5laok6NZpPZIOmUM5MDVPDYK5TMonnGHoV8dS//Xhtz/E9s+U6AF6vDa VYvuS9DaUtBgECZUcXUXRYU66abP+CewIBdZXm00Y4HLTz1GOz965tpMzAA85y4N/Tn9 pUiw== X-Gm-Message-State: APjAAAVjnkffmdh07P9euE3Qno1QZp3SyCKYgaKQsiBZalDvbOR3eNe3 BxEP58hSX9OVRZuYsCCDcXr677uXweQ= X-Received: by 2002:a17:90a:d814:: with SMTP id a20mr99531064pjv.48.1564163486971; Fri, 26 Jul 2019 10:51:26 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.25 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:08 -0700 Message-Id: <20190726175032.6769-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 43/67] target/arm: Add skeleton for T16 decodetree X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 6 ++++++ target/arm/Makefile.objs | 6 ++++++ target/arm/t16.decode | 20 ++++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 target/arm/t16.decode -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 65a74a963b..db93b12608 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7608,6 +7608,7 @@ static int t32_branch24(DisasContext *s, int x) #include "decode-a32.inc.c" #include "decode-a32-uncond.inc.c" #include "decode-t32.inc.c" +#include "decode-t16.inc.c" #ifdef CONFIG_PRAGMA_DIAGNOSTIC_AVAILABLE # pragma GCC diagnostic pop @@ -10559,6 +10560,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) TCGv_i32 tmp2; TCGv_i32 addr; + if (disas_t16(s, insn)) { + return; + } + /* fall back to legacy decoder */ + switch (insn >> 12) { case 0: case 1: diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 7806b4dac0..cf26c16f5f 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -43,12 +43,18 @@ target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE) $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\ "GEN", $(TARGET_DIR)$@) +target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + target/arm/translate-sve.o: target/arm/decode-sve.inc.c target/arm/translate.o: target/arm/decode-vfp.inc.c target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c target/arm/translate.o: target/arm/decode-a32.inc.c target/arm/translate.o: target/arm/decode-a32-uncond.inc.c target/arm/translate.o: target/arm/decode-t32.inc.c +target/arm/translate.o: target/arm/decode-t16.inc.c obj-y += tlb_helper.o debug_helper.o obj-y += translate.o op_helper.o diff --git a/target/arm/t16.decode b/target/arm/t16.decode new file mode 100644 index 0000000000..e954f61fe4 --- /dev/null +++ b/target/arm/t16.decode @@ -0,0 +1,20 @@ +# Thumb1 instructions +# +# Copyright (c) 2019 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# From patchwork Fri Jul 26 17:50:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169931 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp385156ilk; Fri, 26 Jul 2019 11:20:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqxZRcB6CqMdGKlq266h1EqFHLCea9aT7TJK6gKHB6ASn6Gd4vYbL/7KoTB9zyFfefcGt5Xe X-Received: by 2002:a37:dc1:: with SMTP id 184mr63985480qkn.10.1564165219406; Fri, 26 Jul 2019 11:20:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564165219; cv=none; d=google.com; s=arc-20160816; b=v2MpcZxsfZM1LuKgkctPw7aLNfh8m/snJ/wWo2NNw+0uHAhzMqw9GzQ+xvVta2DRKY XZzoE3tRmO76hrEB/8bxUVxTNX5gSXJmOYFT/mUumZx5TZBmFk2Tp/a97Fcto4Cr+an6 iZ6Le8TeCf8u39fxfe5NjjhroWK0XzQN0gOGDzi9NRQP7calyLPd84GK4SwaqgFhLwvB Opmcw9rp3hjnAiMGENRhYNjTslu0187Kw6jBoX4l3OFA7wNGU12DfOd7E3vt8RxvUKvn 2/wRkJAC5dzeU837lghdl61pEYcg+PIwfRZHZdQ4oJW4gnvjOM19fQFpuXDwasLIR8iC uziQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=08mhmhwkN3rkpLTk3jFBP+0Hu2kGOWCoL5BouMwfU6w=; b=ei89CNzjTdorjQzsnnnkdh68rEYFx5h2taiQfBYMTyn/U5hwwkk5YFxovWD7HIuFgC QmrMWqrL8Ts8YJ3rgf4Nbt/Gxr+3VMsMpSqabBrU/XgK8fnWofqrvlfSYwiJ0vJCact0 uLK7anrsl/8vbOgPYxs6YhV+nbCa1bGQUnPwi+1N504+MQ8eM/d4Dbo5UMpfM10ld0q2 H3iM47omo5I78n9XWFsKn8hEP64qHOf9OXbUngS4IGYP3mJn8CdFODuf5SsvPIPKEs5k oIkZfjZBl7uBE6yTMmca6w7Zv3l8HXeuLyPsO3zIB+N0dK4UhOqgauYFANoCJlFpJgl1 GhCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CKWa8HfR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f11si30733931qkb.182.2019.07.26.11.20.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:20:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CKWa8HfR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Z0-0002YS-06 for patch@linaro.org; Fri, 26 Jul 2019 14:03:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58802) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NP-0005AH-Ps for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NN-0000hK-CP for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:30 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:36405) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NN-0000fy-5Y for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:29 -0400 Received: by mail-pl1-x644.google.com with SMTP id k8so25034775plt.3 for ; Fri, 26 Jul 2019 10:51:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=08mhmhwkN3rkpLTk3jFBP+0Hu2kGOWCoL5BouMwfU6w=; b=CKWa8HfR9M4ax+fBilew63DupBxNirusUrVU6GEhWank7AMnsG3Xuar5LKv6kNOdH+ xI09ZqoB1Cx2kGMKjLHImp7O9yc6hZ6vJuTqwn7WN6WBMfHGMsQBjPLgjqOHy0QpjKVE 1ClNKVRpnkeo8boNTDDIe6h+wUd/t/OQSjZBc3VP478Mf4SsKZ7xnsiSZQl3oBb+P+zR On7vlSVWwNjO/g/RA6v5uKwLxLbiI1pttIh7uPJ1Zjgm+v9poP8UUqiv5wFvNPbkWdMb B8upzMzojx19NB0/TxFOcsMVx+awy/PXDScybyuwIjk3PieWyv9CYZpKUWRegF6ZF+Ft EIlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=08mhmhwkN3rkpLTk3jFBP+0Hu2kGOWCoL5BouMwfU6w=; b=kUU0HN6dmJNkzdxeM6gzhAN2eXDB6A3AEEj6XXiCTVvZt77ZIbBilAd+vKwmsrBJAY M8la+oN2N1KVyC6nXOHjcqMgdnE+6lvX85TZ0FLD+eOeZf6fJc4SoL/sn841uANuZagt nTlcH0fu2ad4wHzWKV/6cKCG4hRD1aerhR6O327h6WjP4b/HIKHLPMJQsNBpZKFoHjak eo5/H/BKShuUhcmyK5D3PerOReipybSSEI5wrqsnpnF9rgcPTlP8PQpsVKzXjXb6bDwU BkdrRz5W3sIeXLIUe3+NxlnQE1PLI1pmwetdH0XVz6JeVscySBTe82cdeDI7Qrd2FmXs rvKw== X-Gm-Message-State: APjAAAVhJFHYB7Tj2wRa0reiOCoKeDzw8kZ12ix+DVhcIOh5fFHw591Z zSkTxS5YbijuH//4qzDmBnYOGoOVPYQ= X-Received: by 2002:a17:902:934a:: with SMTP id g10mr99350967plp.18.1564163487973; Fri, 26 Jul 2019 10:51:27 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.26 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:09 -0700 Message-Id: <20190726175032.6769-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 44/67] target/arm: Convert T16 data-processing (two low regs) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 152 ++--------------------------------------- target/arm/t16.decode | 36 ++++++++++ 2 files changed, 43 insertions(+), 145 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index db93b12608..17a0eea425 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -486,13 +486,6 @@ static inline void gen_logic_CC(TCGv_i32 var) tcg_gen_mov_i32(cpu_ZF, var); } -/* T0 += T1 + CF. */ -static void gen_adc(TCGv_i32 t0, TCGv_i32 t1) -{ - tcg_gen_add_i32(t0, t0, t1); - tcg_gen_add_i32(t0, t0, cpu_CF); -} - /* dest = T0 + T1 + CF. */ static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { @@ -7590,6 +7583,11 @@ static int t32_branch24(DisasContext *s, int x) return x << 1; } +static int t16_setflags(DisasContext *s, int x) +{ + return s->condexec_mask == 0; +} + /* * Include the generated decoders. * Note that the T32 decoder reuses some of the trans_* functions @@ -10751,145 +10749,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers) + * - Data-processing (two low registers), in decodetree */ - rd = insn & 7; - rm = (insn >> 3) & 7; - op = (insn >> 6) & 0xf; - if (op == 2 || op == 3 || op == 4 || op == 7) { - /* the shift/rotate ops want the operands backwards */ - val = rm; - rm = rd; - rd = val; - val = 1; - } else { - val = 0; - } - - if (op == 9) { /* neg */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - } else if (op != 0xf) { /* mvn doesn't read its first operand */ - tmp = load_reg(s, rd); - } else { - tmp = NULL; - } - - tmp2 = load_reg(s, rm); - switch (op) { - case 0x0: /* and */ - tcg_gen_and_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x1: /* eor */ - tcg_gen_xor_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0x2: /* lsl */ - if (s->condexec_mask) { - gen_shl(tmp2, tmp2, tmp); - } else { - gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x3: /* lsr */ - if (s->condexec_mask) { - gen_shr(tmp2, tmp2, tmp); - } else { - gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x4: /* asr */ - if (s->condexec_mask) { - gen_sar(tmp2, tmp2, tmp); - } else { - gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x5: /* adc */ - if (s->condexec_mask) { - gen_adc(tmp, tmp2); - } else { - gen_adc_CC(tmp, tmp, tmp2); - } - break; - case 0x6: /* sbc */ - if (s->condexec_mask) { - gen_sub_carry(tmp, tmp, tmp2); - } else { - gen_sbc_CC(tmp, tmp, tmp2); - } - break; - case 0x7: /* ror */ - if (s->condexec_mask) { - tcg_gen_andi_i32(tmp, tmp, 0x1f); - tcg_gen_rotr_i32(tmp2, tmp2, tmp); - } else { - gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp); - gen_logic_CC(tmp2); - } - break; - case 0x8: /* tst */ - tcg_gen_and_i32(tmp, tmp, tmp2); - gen_logic_CC(tmp); - rd = 16; - break; - case 0x9: /* neg */ - if (s->condexec_mask) - tcg_gen_neg_i32(tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - break; - case 0xa: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - rd = 16; - break; - case 0xb: /* cmn */ - gen_add_CC(tmp, tmp, tmp2); - rd = 16; - break; - case 0xc: /* orr */ - tcg_gen_or_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xd: /* mul */ - tcg_gen_mul_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xe: /* bic */ - tcg_gen_andc_i32(tmp, tmp, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp); - break; - case 0xf: /* mvn */ - tcg_gen_not_i32(tmp2, tmp2); - if (!s->condexec_mask) - gen_logic_CC(tmp2); - val = 1; - rm = rd; - break; - } - if (rd != 16) { - if (val) { - store_reg(s, rm, tmp2); - if (op != 0xf) - tcg_temp_free_i32(tmp); - } else { - store_reg(s, rd, tmp); - tcg_temp_free_i32(tmp2); - } - } else { - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - } - break; + goto illegal_op; case 5: /* load/store register offset. */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index e954f61fe4..9833fc97e7 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -18,3 +18,39 @@ # # This file is processed by scripts/decodetree.py # + +&s_rrr_shi !extern s rd rn rm shim shty +&s_rrr_shr !extern s rn rd rm rs shty +&s_rri_rot !extern s rn rd imm rot +&s_rrrr !extern s rd rn rm ra + +# Set S if the instruction is outside of an IT block. +%s !function=t16_setflags + +# Data-processing (two low registers) + +%reg_0 0:3 + +@lll_noshr ...... .... rm:3 rd:3 \ + &s_rrr_shi %s rn=%reg_0 shim=0 shty=0 +@xll_noshr ...... .... rm:3 rn:3 \ + &s_rrr_shi s=1 rd=0 shim=0 shty=0 +@lxl_shr ...... .... rs:3 rd:3 \ + &s_rrr_shr %s rm=%reg_0 rn=0 + +AND_rrri 010000 0000 ... ... @lll_noshr +EOR_rrri 010000 0001 ... ... @lll_noshr +MOV_rrrr 010000 0010 ... ... @lxl_shr shty=0 # LSL +MOV_rrrr 010000 0011 ... ... @lxl_shr shty=1 # LSR +MOV_rrrr 010000 0100 ... ... @lxl_shr shty=2 # ASR +ADC_rrri 010000 0101 ... ... @lll_noshr +SBC_rrri 010000 0110 ... ... @lll_noshr +MOV_rrrr 010000 0111 ... ... @lxl_shr shty=3 # ROR +TST_rrri 010000 1000 ... ... @xll_noshr +RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0 +CMP_rrri 010000 1010 ... ... @xll_noshr +CMN_rrri 010000 1011 ... ... @xll_noshr +ORR_rrri 010000 1100 ... ... @lll_noshr +MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0 +BIC_rrri 010000 1110 ... ... @lll_noshr +MVN_rrri 010000 1111 ... ... @lll_noshr From patchwork Fri Jul 26 17:50:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169887 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp358394ilk; Fri, 26 Jul 2019 10:56:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqwh8v6XQ/NaLssjqjYeNFxvUlqow4cwVATofBVFQeHL4aQn4c48xW1WYWgNdr0VeYhaEzK9 X-Received: by 2002:aa7:d68e:: with SMTP id d14mr83679324edr.253.1564163768090; Fri, 26 Jul 2019 10:56:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163768; cv=none; d=google.com; s=arc-20160816; b=ydHwLDRm++LAgxzyQcQHuGyZ0a9UWy9xTFZd7FIiNloWfcRkyIJptXBWVcSklREmZf 9V4UheQG7/ArisCSc2HkV8zRvAl89Fddn3XLpQVzbIJOovs5s8nvGlQYVAYDN4REDP9/ tfh2ewMTABzsUC79BKKu+Wf+hQRa9J6ysHf4p/43U3f+RgtMjdcZwAX9ltPzdLa2hvjt ZQfqD//WkwE1oAJe7GPLTbu8z0ylS4X+PfqQOWXvXHQO32HDdz7ivKUEDhsc0Z8XVrnf 4w0yIl/+XNQVQmtxpQT4nHOoC0bh0gTcrVTApyaf0j8m2RGbDyw8SoEmkPw1qBfojyux 7ptA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=DJdrX3hGPWd+nibN4wc0pBIHsM6KUMw+bIbJb3gnsWg=; b=U9fjiLh9qWYA2DtYp/E9BmakOwqGtPXK8B9ea9KkY5wiMqMlMmaDnxYE2ljZox8ZIC Ehp96z+JV8lnCgxiU32UmonJGtQc6RT3XcSb0LXkGy9SzygiHBntQjxo9PxbVqb/s7QJ 2446b5QP7bCrGBomMX+KAESBlxjd7UzgrsVpOQgbtyB2TZk0hPqDxw954fCzO7X3HPc8 1te6yaW38ZvD0kQs7EV6jeolNCMV2VFXWT076m+MM31px+HRs7JfkfeOA7IRbnfSBB/E Fs8WMWL7VBj112i9JYOyk2sjaMXAWzJUksffHBki1NXaV9HvJ9LUEZnyJilSjn5Vjj/S WUuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SMX8tfFk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h10si14357433ede.349.2019.07.26.10.56.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:56:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SMX8tfFk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Rn-0007W0-EV for patch@linaro.org; Fri, 26 Jul 2019 13:56:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58917) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NR-0005Lb-Nm for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NQ-0000p1-I4 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:33 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:33410) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NQ-0000if-CO for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:32 -0400 Received: by mail-pg1-x544.google.com with SMTP id f20so15878106pgj.0 for ; Fri, 26 Jul 2019 10:51:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DJdrX3hGPWd+nibN4wc0pBIHsM6KUMw+bIbJb3gnsWg=; b=SMX8tfFkoYwIcv28vMhG4MahozdMyw8XYZvQYpm8lIsJRiHb2YmyH0RHZXRjuDqG8h aNaPPkmq5W0/5pVAmjCWfTw3wz9bM+uMD8/wWAd7UTVSZcmT3E1EswqaoFFdThQENjXW m6/AdnpmZt44SLMTqMHuS/1Ygct9wrRViSSX1T/N16/h31A7MIrgfc+3VctsYstZwYBF binQlAKZEC9FHXAt+6B1htgh6+w9laFYIrPMfNyZu/up+pEGglfJE8rnNYlPcS1VZbOD Tb+UqKL8bN/1z/8zfK4TddcX6zacp/nRkYa/T+205DTcD+r2xOL0uRy/6kbL+3xOLaUi +eSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DJdrX3hGPWd+nibN4wc0pBIHsM6KUMw+bIbJb3gnsWg=; b=FA2fHL1YvejWdllZ2nh8lcPtWMf0iiD2GX74OkmgzkrRa6eKE+vdRF5lr8zlGEy1Af cSZOigovVA4ATU59zKLa1whbLXCPDNk2UbN1VkNMkacfMZOVquiclyqo6htuzoJZOySU BQIBXRhsBsO5EaYFXVs825Gs8xUE8pe+mDeebD1tNEK1444pzyyuDHffMeBYDMia1hca eScGN6GXYbsdDbo+dmnx2LnmLRH8KJx0UjkGEHrX4x5OLTOAeZM/5XEEL8S94L14WzPj X/3MqVcl35IzBUldglo83n47TR2s6ktv2PalHeSJGZqwWTlBy/YzTe+933+9zgwcHARO 7dlA== X-Gm-Message-State: APjAAAVs3hwH7U1DJjCCxNanArryV7kUEi6wCGmeBhBwm9GWKzbZ6ItX TFUcaEiH2szJE8ZVn+sWgQeEpbNgthc= X-Received: by 2002:a63:5823:: with SMTP id m35mr93897621pgb.329.1564163489154; Fri, 26 Jul 2019 10:51:29 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.28 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:10 -0700 Message-Id: <20190726175032.6769-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 45/67] target/arm: Convert T16 load/store (register offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 51 ++---------------------------------------- target/arm/t16.decode | 15 +++++++++++++ 2 files changed, 17 insertions(+), 49 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 17a0eea425..7b87621315 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10754,55 +10754,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) goto illegal_op; case 5: - /* load/store register offset. */ - rd = insn & 7; - rn = (insn >> 3) & 7; - rm = (insn >> 6) & 7; - op = (insn >> 9) & 7; - addr = load_reg(s, rn); - tmp = load_reg(s, rm); - tcg_gen_add_i32(addr, addr, tmp); - tcg_temp_free_i32(tmp); - - if (op < 3) { /* store */ - tmp = load_reg(s, rd); - } else { - tmp = tcg_temp_new_i32(); - } - - switch (op) { - case 0: /* str */ - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 1: /* strh */ - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 2: /* strb */ - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 3: /* ldrsb */ - gen_aa32_ld8s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 4: /* ldr */ - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 5: /* ldrh */ - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 6: /* ldrb */ - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - case 7: /* ldrsh */ - gen_aa32_ld16s_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - break; - } - if (op >= 3) { /* load */ - store_reg(s, rd, tmp); - } else { - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; + /* load/store register offset, in decodetree */ + goto illegal_op; case 6: /* load/store word immediate offset */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 9833fc97e7..567c5005d6 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ldst_rr !extern p w u rn rt rm shimm shtype # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -54,3 +55,17 @@ ORR_rrri 010000 1100 ... ... @lll_noshr MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0 BIC_rrri 010000 1110 ... ... @lll_noshr MVN_rrri 010000 1111 ... ... @lll_noshr + +# Load/store (register offset) + +@ldst_rr ....... rm:3 rn:3 rt:3 \ + &ldst_rr p=1 w=0 u=1 shimm=0 shtype=0 + +STR_rr 0101 000 ... ... ... @ldst_rr +STRH_rr 0101 001 ... ... ... @ldst_rr +STRB_rr 0101 010 ... ... ... @ldst_rr +LDRSB_rr 0101 011 ... ... ... @ldst_rr +LDR_rr 0101 100 ... ... ... @ldst_rr +LDRH_rr 0101 101 ... ... ... @ldst_rr +LDRB_rr 0101 110 ... ... ... @ldst_rr +LDRSH_rr 0101 111 ... ... ... @ldst_rr From patchwork Fri Jul 26 17:50:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169893 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp359611ilk; Fri, 26 Jul 2019 10:57:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqwwV4vt6JAJRK47XCzvyaE9T2BC66IeU4fOx6IENas5lU3vVJGBpUqLnIghG9i8AHL+nLnJ X-Received: by 2002:a50:eb0b:: with SMTP id y11mr83840193edp.224.1564163848358; Fri, 26 Jul 2019 10:57:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163848; cv=none; d=google.com; s=arc-20160816; b=gPom2JHqcY5RvCXVUr5qphmVNGbsdqCHxuDsdzNNxOZfWkSWIGlRy9ouSd3juomefW +ugcuqWq1Xr+a5AB7F0zP+riVVJa8CR1BAVJbS0v/vXaL7mb2axyYqe47er50qbARBCL nQbC7Iix4BMqD6gE8m6vjxXbiWQ8EIuEy5hFj7AcH6CA47te8nzSW2AMaSnlUYvHGUaI cKWS5yrz3ZT5Po8CEHhq9Kp9EgZu3nNuSfRpYfKhKEwd3jehy9nW7dI5zTBronSA+jFu +q+6XvNQpLqQmvgQmH+mQtGdW/kEzN82v/1T1xKBx5umD+i9gw2GrEr+cnNylbTkRN+E oG/w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=rYLqZpflL8enArleH0yr8+1WjHV+ohzdNCLhPhFauU8=; b=O7vaXOFNfJKPRKa/soRaYihQ/UJx0SaltoZRPl86DdiIFhoXn3ET8oX4dqHejDRrx8 3Z4fFV5HWDPoDaXfabz6JVig1Fzu4+DiganFBO6NMaJ3NEtvu3113sePeNDskIzX8oXj 3laanILXIRVlpgtvkVvh++x8tdI/Ei2uT/yDdUZV9KUcuctKRNzi6ee7SQoE87DcSwd7 URJK6lz9lH8clvbZaQGL1A/MOZqhffIb1NkjAxYUk7x8LYzY0cF9g960kKdqxoqV6fPL grzVRckYTm9OHUZdrP5PEEAICCKcY8qq7RYMKArLHaE8FFFBoiyqYJtB5BUoI/tD0TuF ou8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vUuFxnGZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d24si11658479ejt.166.2019.07.26.10.57.28 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:57:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=vUuFxnGZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4T7-0004xb-U7 for patch@linaro.org; Fri, 26 Jul 2019 13:57:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59049) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NW-0005fG-Bq for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NR-0000sI-SQ for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:36 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:39973) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NR-0000lc-Js for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:33 -0400 Received: by mail-pg1-x541.google.com with SMTP id w10so25118876pgj.7 for ; Fri, 26 Jul 2019 10:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rYLqZpflL8enArleH0yr8+1WjHV+ohzdNCLhPhFauU8=; b=vUuFxnGZfQO+eydHDnu89G4IdZjWb7HlKZY0QaHpGWE2BItOyaXMRIyVdYMQ5FlbEM Yim3sn4LSJI+5S27aQP1J2C2gp1832rmmjn9LZEPvvc6vHBj15SNzxQnSTccj6It2Qu6 cS6QTKFPWIY1IProfCj0G52h3yThcb54AOYaoXea967IO0U7De6pKTx3WjHAbiwNNoQW Pv2eBFF0vGE0C8m5ue1r55cJDh1mazO5ejuFcwKyH0XSM6zu9//T4NI/KhOvRakQY0bv LIsUPxvbl/VsMzZRVQY/gHNa2DNFyrVkYn/6y36PZCjMoYP7ouD3kNNyjtf9KLKQhUlg STGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rYLqZpflL8enArleH0yr8+1WjHV+ohzdNCLhPhFauU8=; b=t6eSJVZ9WBeYqG7QFh0GjW0PLsjEM/XSlrM0IQY9O6nq5ax8WOX5M+vRPtg+IgWOht T8jBV0KaAd4fHIXU2lG4NClBacLqIi982PDlS1gQqn+b4h3kh8fYONmCRT6tL1a6ZNH+ zqPSxXjYoIKh0y9Q44d/L/DpLR2kbH7MNGiSEYFrk/n0zukDRtllJhI5EMmxaWGud60r pJKfjntUMnyXCZoZrTboDxJzeGl/51avPhUSsSYSaKWSLBhSr5Ox8K2dSiU9cehym3gq BxqmfFvVKlNT5xm9b+Xp7yGxff2JH4MXjNDoQp/vj+6r3bsEsxyZdZyxiCVvbDRHZ6hu uuRw== X-Gm-Message-State: APjAAAVqb4Z28vN79tdSyBlW8YvusFMpAIQ9KdNyPsvYyKbQ5HbFGmqA 3MUnlbXDPlVe/13BnqHDIHXntFmXbQI= X-Received: by 2002:a63:7e1d:: with SMTP id z29mr92318259pgc.346.1564163490363; Fri, 26 Jul 2019 10:51:30 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.29 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:11 -0700 Message-Id: <20190726175032.6769-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 46/67] target/arm: Convert T16 load/store (immediate offset) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 94 +++--------------------------------------- target/arm/t16.decode | 33 +++++++++++++++ 2 files changed, 38 insertions(+), 89 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 7b87621315..28f274ca7c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10753,97 +10753,13 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) */ goto illegal_op; - case 5: - /* load/store register offset, in decodetree */ + case 5: /* load/store register offset, in decodetree */ + case 6: /* load/store word immediate offset, in decodetree */ + case 7: /* load/store byte immediate offset, in decodetree */ + case 8: /* load/store halfword immediate offset, in decodetree */ + case 9: /* load/store from stack, in decodetree */ goto illegal_op; - case 6: - /* load/store word immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 4) & 0x7c; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 7: - /* load/store byte immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 6) & 0x1f; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld8u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st8_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 8: - /* load/store halfword immediate offset */ - rd = insn & 7; - rn = (insn >> 3) & 7; - addr = load_reg(s, rn); - val = (insn >> 5) & 0x3e; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld16u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st16_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - - case 9: - /* load/store from stack */ - rd = (insn >> 8) & 7; - addr = load_reg(s, 13); - val = (insn & 0xff) * 4; - tcg_gen_addi_i32(addr, addr, val); - - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - store_reg(s, rd, tmp); - } else { - /* store */ - tmp = load_reg(s, rd); - gen_aa32_st32_iss(s, tmp, addr, get_mem_index(s), rd | ISSIs16Bit); - tcg_temp_free_i32(tmp); - } - tcg_temp_free_i32(addr); - break; - case 10: /* * 0b1010_xxxx_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 567c5005d6..797e4e7068 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ldst_rr !extern p w u rn rt rm shimm shtype +&ldst_ri !extern p w u rn rt imm # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -69,3 +70,35 @@ LDR_rr 0101 100 ... ... ... @ldst_rr LDRH_rr 0101 101 ... ... ... @ldst_rr LDRB_rr 0101 110 ... ... ... @ldst_rr LDRSH_rr 0101 111 ... ... ... @ldst_rr + +# Load/store word/byte (immediate offset) + +%imm5_6x4 6:5 !function=times_4 + +@ldst_ri_1 ..... imm:5 rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 +@ldst_ri_4 ..... ..... rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 imm=%imm5_6x4 + +STR_ri 01100 ..... ... ... @ldst_ri_4 +LDR_ri 01101 ..... ... ... @ldst_ri_4 +STRB_ri 01110 ..... ... ... @ldst_ri_1 +LDRB_ri 01111 ..... ... ... @ldst_ri_1 + +# Load/store halfword (immediate offset) + +%imm5_6x2 6:5 !function=times_2 +@ldst_ri_2 ..... ..... rn:3 rt:3 \ + &ldst_ri p=1 w=0 u=1 imm=%imm5_6x2 + +STRH_ri 10000 ..... ... ... @ldst_ri_2 +LDRH_ri 10001 ..... ... ... @ldst_ri_2 + +# Load/store (SP-relative) + +%imm8_0x4 0:8 !function=times_4 +@ldst_spec_i ..... rt:3 ........ \ + &ldst_ri p=1 w=0 u=1 imm=%imm8_0x4 + +STR_ri 10010 ... ........ @ldst_spec_i rn=13 +LDR_ri 10011 ... ........ @ldst_spec_i rn=13 From patchwork Fri Jul 26 17:50:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169915 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp365689ilk; Fri, 26 Jul 2019 11:02:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqzSKWexcVGvuBWTQVj9ZdchmKv74vHlFJ2lfSEfPS4r0sBR0knCNFL93pJxSKs1MdhYtXzg X-Received: by 2002:aed:3f47:: with SMTP id q7mr68455128qtf.209.1564164168237; Fri, 26 Jul 2019 11:02:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164168; cv=none; d=google.com; s=arc-20160816; b=YkywXDoNiAHpp8E8fVwS/4C8/11hVahXPF7OY7I02sUwQxe6uMxOvrHkp+3YccA5kI 2zp35PZNqEWE0XxoVbVZBDeQ/l7igtAuaQ4K+rcPOhfLEkvlSVyJvhG9rs+9pyVcPYvd R51RWWKgrjzO4NmNjwF8TJofth6IOLNKXVruRRGSU1CjeiyJD8aIN9mXy7B/tcJu3fa8 uy7nyYKshBlqCeApywaRq7gF4A6VfDPDeEZ1DhDcBBR8T9Nv0rZemSTtVS/joJEcDjuV WKwKjEGOsXvEl2kvQ1EwR7/amMUGuzXhINafltPRBJ47eIyistrdK+ntXIe41C9MVKiO rpTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=wDt/gxXOEruKJVqZkyq92uFSMEbVcSh409biqimT4es=; b=VEcj0FQN3laZyrRn+1QYUAnWQKk/uYfC0FFx/w8J7/8DvokVaPVVy3q2tRyOho81Kj EgAAGrLo6Ercy0Iua1aZfudJKyw/KQ1G34sIBKvVJnE5zFn4oIKVW/4M+lG7V16V2833 aRNsOHy9+4ZtPcPxLcSUeG22k9xOigCOTjmXHgCqCfHpQL7lvEurBO1DYqRe6YB2LqWU ieCwuWhMc6K+pyH6ZhJ7VsJTTrHIgEK73m2UwttU1bwJpAi4UldqAmhz+qmnwfg7S2pW cubczq3Ht0IEg9FsRtMQ67USEcpWIYhp4kwk7IRyCkRzWlVyDj/7QRDNr/v7SRrMbq+Z Q+hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=l2uVYsyC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j96si32634280qtb.125.2019.07.26.11.02.48 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:02:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=l2uVYsyC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4YH-00007n-P4 for patch@linaro.org; Fri, 26 Jul 2019 14:02:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59015) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4NV-0005Wz-Bc for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NS-0000sh-0f for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:36 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:35667) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NR-0000oE-Nu for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:33 -0400 Received: by mail-pf1-x42e.google.com with SMTP id u14so24878344pfn.2 for ; Fri, 26 Jul 2019 10:51:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wDt/gxXOEruKJVqZkyq92uFSMEbVcSh409biqimT4es=; b=l2uVYsyChcSlp0SE+aT5EmxpknN6lP8vdMTXyOHaOGtOP3IPv5s0hGhJ6fer3Yjtir CYMcjPuWSPL4/wiznTn2JlwZTedJHqywSb5VzPcfPzF80R23aoySf4wYC7L9xcfjZw4E C5xFPl7y+htqkPEKndGiu5Nr/gJNrm2HAuHM8ULNYzAlfmn7knmZhKFfs3t1YkEhXSzA t56/NTjFzKtl8/bel1g0TCPFZ145TchN6kJKVv9sJwq+FJoNv9/KrYJ3I1IQ5qU+2JnN n/vDamCocGRuScJGVsvYQ7EFh6d1YhRDR0v4AuOHGB7/foJhz+YwKJYgzhYcrMMTFGgW bDXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wDt/gxXOEruKJVqZkyq92uFSMEbVcSh409biqimT4es=; b=iSO0kMundiFqzqY/8Y1rK2GJm/O1ukvlPSdfBsLwqP2cpFg+/0dLsOjdau+XWoBUc8 ggBN6dF7MNknQl6LORrDAcWyAZyPy+/rGYcRwUIKBdlDojsjTj3vCx4oEUUUDqbW8H4m jkivzZ2b5m/1gElxdm9/hvzth8d8qC4kK0klXFsOUMywz/SFinQneNqJQqdMT20FBa0G TIsdzjI25Mr7nqgL2GAFemCrTQt3u90R/Oxncj5Hz9VZKdxg9MxogOxdvc7Wd0AOrTxt T8C9q5xAcTvZfN04vKtREAlPW7lsAAbldd9M+KU+OKDSmssyI0HGHBwWB1ij/2LkDfFw /mZQ== X-Gm-Message-State: APjAAAWi2EmNz+sXCfevuTSRjl9vdinFEldONvkvjwire6drjQTQ6O/r 6KZaKWdkrfeDF4JruTV808rPMr8n094= X-Received: by 2002:a63:b904:: with SMTP id z4mr90750276pge.388.1564163491483; Fri, 26 Jul 2019 10:51:31 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.30 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:12 -0700 Message-Id: <20190726175032.6769-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42e Subject: [Qemu-devel] [PATCH 47/67] target/arm: Convert T16 add pc/sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 12 +----------- target/arm/t16.decode | 7 +++++++ 2 files changed, 8 insertions(+), 11 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 28f274ca7c..525276ed13 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10758,19 +10758,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 7: /* load/store byte immediate offset, in decodetree */ case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ + case 10: /* add PC/SP (immediate), in decodetree */ goto illegal_op; - case 10: - /* - * 0b1010_xxxx_xxxx_xxxx - * - Add PC/SP (immediate) - */ - rd = (insn >> 8) & 7; - val = (insn & 0xff) * 4; - tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val); - store_reg(s, rd, tmp); - break; - case 11: /* misc */ op = (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 797e4e7068..568656ecd6 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm @@ -102,3 +103,9 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2 STR_ri 10010 ... ........ @ldst_spec_i rn=13 LDR_ri 10011 ... ........ @ldst_spec_i rn=13 + +# Add PC/SP (immediate) + +ADR 10100 rd:3 ........ imm=%imm8_0x4 +ADD_rri 10101 rd:3 ........ \ + &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP From patchwork Fri Jul 26 17:50:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169897 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp360220ilk; Fri, 26 Jul 2019 10:58:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqxM2l4EJE9qvUTI6mSciXkFAhCnAOqX2q3WCB7XxokCSQbmFkMzRRwnkGL4m1QQ/bgnrwZA X-Received: by 2002:a0c:9332:: with SMTP id d47mr67714910qvd.222.1564163888829; Fri, 26 Jul 2019 10:58:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163888; cv=none; d=google.com; s=arc-20160816; b=goqnLWJLe2/omeauUE31cyQdqZO2KihAIIHtyL/vv/cbITYEXJCiFW6LAbRr1D/wNB uYtTfNuhDSX24x/fCOnGfY2AeDsrETi43QtzGLgp+a6V9ccPAdIW24i4CWmjsPE1IXh3 LW0XqM1LgjgyFJTkjixebDAuSRAo9KqdnmAivfy1VRXAD8V3Ck75nyEj2W3EyhT42yct y/7yHlpL6hMeSlNO4QOviaYsXSDRhSHBr+1AYlV1X/POLU+X+4sWryrgm1K1tuirSJEb kEKTwAKhJI5mIiljO005AdRm7mXWLSsLne5WgfQdSS8be1toktF+yd5k6IKYjMeSWcuN 9FCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=BTtAZNtC5LEslFth4SXf60p+WzB9yMjQ3jwBVq1HIi4=; b=FymxdagqPQwMAYEet8vHU0q5TqgiICVXf1nuaF6D1V9A94fjJ1KKkNRFqdepUhNIK/ rKldQrkAJrecCMZfo+7cjU9x8s4hL5R6QGBkM7sdqcMR98OwG8uICoZTvJcP0dr0lucZ OOpgLt8isutQbJPAJxl3OZXkT38bVD3nxtHANBd//EyBVK4souA5hBeONaj9oQKV2HTb 2TigJGEtsaMYzqwCc3JTi1IwUkw0e5XbmBryJGrwfsKtXGVLsAMz6sX+0zLycP3R46Kf +m5VdZCaibW8UzmrZWjOEv0gQKKlgxraX5St1xZmyDUwKDZ5AVae+grKGogeYSHfLmuc hoOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=P9xCZVJS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a38si34432991qvd.50.2019.07.26.10.58.08 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:58:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=P9xCZVJS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Tm-0007nJ-2I for patch@linaro.org; Fri, 26 Jul 2019 13:58:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59095) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nb-0005oT-Dn for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NT-0000v4-7M for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:38 -0400 Received: from mail-pl1-x643.google.com ([2607:f8b0:4864:20::643]:39540) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NR-0000qm-Vh for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:35 -0400 Received: by mail-pl1-x643.google.com with SMTP id b7so25061441pls.6 for ; Fri, 26 Jul 2019 10:51:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BTtAZNtC5LEslFth4SXf60p+WzB9yMjQ3jwBVq1HIi4=; b=P9xCZVJSzzPbFwt0skLMTpo8XnRqYGuhw2eh9OeVGkUmwz70l2P48a8hNEpssL939P cD+1uSa2ZfLb+9AUrt85qbbGF3dQk06EazdGaBc0ekb9rnlyvujhFs157VEQceB7ijdT w8cuD4WpDWzftv3dtWezARrsm04RKbDv94SfS9dEVdgkLGnyuBlb2Xp5TKVLy4SEO0if a+igRl3ht4NxL1Wo2vopl7KFJaYW1cZEakz2h6t0QprPt/uqs802fXE1Qq8RD2kDPkw1 cs35MLeu7axsUcn43OUGOSb8wvwiv2G8zjTpTt8oD1HF8pvClicJx8JJrrP4x3Rr9lhY AjKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BTtAZNtC5LEslFth4SXf60p+WzB9yMjQ3jwBVq1HIi4=; b=NT8CtqEDA+4dt2STkzCo6mCQ4LxbgrtscadHsB7LVOJnUY4+cnaf8RNnXH1OSrEE/S +6Ve/qIzLV1V0HGekn1L2gi36A0MSWmM6tSwivffMjmn2r3Aj5e/vNhDXO7kWMlG5Oge j41LzXPQNfJeLn57rmmPDhs/Y02Aa6eSWPCzcIF7lR3p7CQKv0xi6F7br0L39wingA2o og15NYwNEzZ6yIOW0wyOx+w4O/11fIfp/yMHp8vwO+Kg81s11Ve9MSTJgyrIfz4vr7EU CaqZB2sADXErglNNQc1btMRX5rzbOzox62N5GDvRP0pUHNXrvP+qT2fndIKEQRpwMQxV gp3Q== X-Gm-Message-State: APjAAAW3FLg4Ok6lMKvR2U+hP1WN9nrHX3LqD7lCfHQRY6y4UVdTQv5x zMnjw36s2wBxytCjkwTDkFBqAY9Mnsk= X-Received: by 2002:a17:902:424:: with SMTP id 33mr17653195ple.151.1564163492748; Fri, 26 Jul 2019 10:51:32 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.31 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:13 -0700 Message-Id: <20190726175032.6769-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 48/67] target/arm: Convert T16 load/store multiple X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 47 +++++++----------------------------------- target/arm/t16.decode | 8 +++++++ 2 files changed, 16 insertions(+), 39 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 525276ed13..f551fde3db 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9988,6 +9988,13 @@ static bool trans_LDM(DisasContext *s, arg_ldst_block *a) return true; } +static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) +{ + /* Writeback is conditional on the base register not being loaded. */ + a->w = !(a->list & (1 << a->rn)); + return trans_LDM(s, a); +} + /* * Branch, branch with link */ @@ -10759,6 +10766,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 12: /* load/store multiple, in decodetree */ goto illegal_op; case 11: @@ -10984,45 +10992,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; - case 12: - { - /* load/store multiple */ - TCGv_i32 loaded_var = NULL; - rn = (insn >> 8) & 0x7; - addr = load_reg(s, rn); - for (i = 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* load */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == rn) { - loaded_var = tmp; - } else { - store_reg(s, i, tmp); - } - } else { - /* store */ - tmp = load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - if ((insn & (1 << rn)) == 0) { - /* base reg not in list: base register writeback */ - store_reg(s, rn, addr); - } else { - /* base reg in list: if load, complete it now */ - if (insn & (1 << 11)) { - store_reg(s, rn, loaded_var); - } - tcg_temp_free_i32(addr); - } - break; - } case 13: /* conditional branch or swi */ cond = (insn >> 8) & 0xf; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 568656ecd6..67476b30dc 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -26,6 +26,7 @@ &ri !extern rd imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm +&ldst_block !extern rn i b u w list # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -109,3 +110,10 @@ LDR_ri 10011 ... ........ @ldst_spec_i rn=13 ADR 10100 rd:3 ........ imm=%imm8_0x4 ADD_rri 10101 rd:3 ........ \ &s_rri_rot rn=13 s=0 rot=0 imm=%imm8_0x4 # SP + +# Load/store multiple + +@ldstm ..... rn:3 list:8 &ldst_block i=1 b=0 u=0 w=1 + +STM 11000 ... ........ @ldstm +LDM_t16 11001 ... ........ @ldstm From patchwork Fri Jul 26 17:50:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169906 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp362695ilk; Fri, 26 Jul 2019 11:00:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqzhvPYvlIn5fcieIgqMBuEDrZmkuUFalg9OWeMuEpy+Bq1BI1Q7FFzIWFANUppLsXRq2uZA X-Received: by 2002:a50:90c5:: with SMTP id d5mr85436842eda.28.1564164036146; Fri, 26 Jul 2019 11:00:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164036; cv=none; d=google.com; s=arc-20160816; b=zDmJ5mTJzyo3VEAYYK0WE+VN7VjR2qgbfILVDy92FkABTB1vCjCOiOT+dQmJSvLNQc FxWGQvFk+/P1ceBHMGKQvf1npCnocjwQGs8D0Bg9DLrjv1tOl5aSDie7T4Jx8bbnCom7 9AtPvon4oUnsUwfHw3uZKYL4cdcB5/VdnXILJmmlzcu9Tl8eeJDgMpFg8LbhJ8gZry8Z HsHNPijL2fmh9LoYp3xcuAbGfLtrYmn3Vx3O37lYma3TV7gZqpkOwwVLHCxxHk9aGCKX qRqQulofOh1Qix+trxRpAfGF10t31LoRji7GrZ0cBvk/Ytj7TgKNPWINEY+O5eX/Yyvu Rlpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=7nWDfS+LdH5ciQPlK6I4CJ7o4VfuIN/4vlkt7Y4d8wE=; b=Ua+DAOWP1gaASW6Ah64BkEs85uK0CA6AzWXf8F27HRTlmPWExjEmwbwsZSrDloti7o o/jL4h4yCMEOK+YQ/GD5gUVABAXZvDFCqOzX/v1zY0s2wdwOYHXdDmOyQ101Tb5ee87Q wiw5+MxZr6y+1+9gSGzAnYQNolgIWvnyyC7LmFcL+Kz0id2XUe2kyA8znHeQTOj13zEX 6IyMuicn4PaLzKAkSkuVny0oE7ySXjciTr4IcwBERUqj/OR0jw4Hkg8VsKZRRj8IBdRI bVQV36lwx6ruLy317vLI+I6gPrVLzE/LmaMhFIT1SKxWFqHTDVA6vC2N6riQ6LweEIqS Q5RA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KT+IyBJ0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a24si13332567edd.382.2019.07.26.11.00.35 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:00:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=KT+IyBJ0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42570 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4WA-0008Bn-Gm for patch@linaro.org; Fri, 26 Jul 2019 14:00:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59160) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nc-00064d-0h for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NY-00010n-Cw for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:42 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:39541) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NV-0000th-SK for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:38 -0400 Received: by mail-pl1-x644.google.com with SMTP id b7so25061451pls.6 for ; Fri, 26 Jul 2019 10:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7nWDfS+LdH5ciQPlK6I4CJ7o4VfuIN/4vlkt7Y4d8wE=; b=KT+IyBJ0sQ4gxsqcoF8Y9qFThtAqsqt8oEfZeIROZyIyzZKUae7CJfu664N7GDnRJR VNus7Haphr8QjZ3VWoiWV3y2OeZc2h/t4Nd592i/embtWuZOMiQ0+BWEi/4Dbd8lXvzK yI9e/vposoNleYJFWqVHuJr97CXVfhIy6Yu0gVwJ0LPgLgqpq/9QBp51adkG0U3TdsH6 oEqfZuZ1C7FDV1Xw86XCdgfp9WbzIORxENAtj7NoUvNdoDkmGunOrJI17d19HiDr7Fu9 QBW4vaqZQoY4cN0L+YjKLuFlBhqfkhM84usqbV/wM4KqFazgP/E0RLv54W2vB5O9yQhI O3/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7nWDfS+LdH5ciQPlK6I4CJ7o4VfuIN/4vlkt7Y4d8wE=; b=PsyCsJlb00NyPSo6vDpi9kizU/tT/kN7DT/fgPIuV3Q1W5VMl85jOfv1sh0QFQy/QM 0z5XmC1jQP71+r5IK/a5mgoH71jC09L7RXSqSHDfv2VyjZCDW54kbEllWudDPmAjr1sa Ndm5n/x3VZc6ng28jq9vUCa5byPc6bihQX3g/y0T4kJYa9Wni9+8vXVK9uW7II/G/hrN ZkbJ1vGxGGUCVA/LR7prMF1HlOsDd9xUTZe1KR9YJJWq4TBLosKSZGnoGodiK+VvgOhk wD//8NX5FT4HHJL86B/THoy1tzceSXS83QHd16enQSP3aNLzrCa1Cm1uc5FsJcfaUxMj dBag== X-Gm-Message-State: APjAAAWM6nfm8oVnHG6SgKe0pWtBg7zNTwHDpYZwUWixPgMlVOShMcO2 m2R5vipDcXphUO4RYpu5S+ITkB0d/Y0= X-Received: by 2002:a17:902:b48f:: with SMTP id y15mr99334283plr.268.1564163493700; Fri, 26 Jul 2019 10:51:33 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.32 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:14 -0700 Message-Id: <20190726175032.6769-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 49/67] target/arm: Convert T16 add/sub (3 low, 2 low and imm) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 16 ++++++++++++++++ 2 files changed, 18 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index f551fde3db..692891dbe0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10580,31 +10580,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) * 0b0001_1xxx_xxxx_xxxx * - Add, subtract (three low registers) * - Add, subtract (two low registers and immediate) + * In decodetree. */ - rn = (insn >> 3) & 7; - tmp = load_reg(s, rn); - if (insn & (1 << 10)) { - /* immediate */ - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, (insn >> 6) & 7); - } else { - /* reg */ - rm = (insn >> 6) & 7; - tmp2 = load_reg(s, rm); - } - if (insn & (1 << 9)) { - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - } else { - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - } - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); + goto illegal_op; } else { /* shift immediate */ rm = (insn >> 3) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 67476b30dc..965fb1bf6e 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -117,3 +117,19 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm + +# Add/subtract (three low registers) + +@addsub_3 ....... rm:3 rn:3 rd:3 \ + &s_rrr_shi %s shim=0 shty=0 + +ADD_rrri 0001100 ... ... ... @addsub_3 +SUB_rrri 0001101 ... ... ... @addsub_3 + +# Add/subtract (two low registers and immediate) + +@addsub_2i ....... imm:3 rn:3 rd:3 \ + &s_rri_rot %s rot=0 + +ADD_rri 0001 110 ... ... ... @addsub_2i +SUB_rri 0001 111 ... ... ... @addsub_2i From patchwork Fri Jul 26 17:50:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169899 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp360811ilk; Fri, 26 Jul 2019 10:58:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqypXin4F0C/8n8Z3AJFXY+NHMfNRkT6dY8L7jGSpykYjRoRwvoEPoDT4iEQbewNmbc4y5uh X-Received: by 2002:a0c:89b7:: with SMTP id 52mr70088057qvr.199.1564163927941; Fri, 26 Jul 2019 10:58:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564163927; cv=none; d=google.com; s=arc-20160816; b=kKj48j3Rp6cDanGmjk1upBt5uLuP0zz7fYE4SEKsgbxMevILpNcDXeSmO/+eam2H04 zZZXh10Gi2nL72zDHhP77osGcJF+xuJFesNv7Bk9kDSMxPHz6/fqSKPujP3kY9295CIR pF9BJ0/IocBEKV8J/2BcLzql7X48sJWTRK2hMW2+k1+SdycnWSiB90O4CTk1vyWQxSOl R9XdQ3jDw4TO7JJy+6smHW8m53sVn62RSgRaHRJMW2GQsuyg2jLzpogW5+ejhuKNjmzj 3Nlqeyp4SGzvAdefYPxH0hrZkL3//D4L5v62K9wU60/QTFmaxW42x3Bszd0RdP2nmlD9 mV8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=8uDpXmk2fu+tSj6HfWWHlssj2XKXCMWZi0tyb4tGXOc=; b=LXwi/hdQQzQ9muL4ibahuDWD11kpBcuGQ7imx+gKT/m2GrnqyYfXxwD8qZL2e8a3Ze rtaNCTyMJhviAL+JTtNfcsuOJXYiVUhfie2vWM90+DTZ1JmHLoF9fktiXQ/8pJpRZfiG 99LYCD8ZrLUuY/EoG2AJAhUcJ1O8uxKVLFpmx9nXPPH+YeHRC6hOMDCsaons2ftmd9JG mWY8jrg6KuAuhFcKQnQVygLTVSmWsAfR5MmzlTWjCxTgzQyKtqXZQPeK9z8FpvQQ372m i8umpFaut2Unt4JG6ROQanR7gLGO0UiZ1nJ87obosuu4tYAFozqP7HYWpR1IB6UTZ9e/ rSUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=atpvhmyD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x190si5820095qke.175.2019.07.26.10.58.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 10:58:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=atpvhmyD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4UQ-0002Ca-Vd for patch@linaro.org; Fri, 26 Jul 2019 13:58:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59162) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nb-00064j-Vr for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4NY-00011O-I6 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:42 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:34339) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NX-0000wX-Di for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:40 -0400 Received: by mail-pl1-x644.google.com with SMTP id i2so25048116plt.1 for ; Fri, 26 Jul 2019 10:51:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8uDpXmk2fu+tSj6HfWWHlssj2XKXCMWZi0tyb4tGXOc=; b=atpvhmyDtUy1RYtrvBv8oBntVn6bXSSR/tqasJqEeDKCXAJtNA4QXtSDtVERLdpQic HlIgcmBOi3sFqG2kOMXxGD5lX0bd8ZOGOnYO38RRda5KT3rv/wxfKu0a139NyIYhb9NZ WNUPWW/H7XT2HRnJ3zv9oqSj1+eJVT9Z4byUzp6fomtXJWWG10wPgEq0OCugjjjUffgE uT460ehbKiJPf33AqhO4dpUVDx6v5MEkQmRCk9yWq33tbPJL45WvYCAalHYbgC0LCOZq qJ7XtBiG3epLuMHsX9v/1S5GDzLiUxSKViQqLaMwrdUgBP4YUOe01a5XTYzt+/e6goCJ ZQGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8uDpXmk2fu+tSj6HfWWHlssj2XKXCMWZi0tyb4tGXOc=; b=kO1bJ+qTIUrL5Icg7/GRABBneNyzJBxG91PptXKS3f8SYdW5PDs1PQNnn3C1GbXpXu B0hDc8tfi4ph7QYCnj/A1Pm0w/wiaepsoeSK7h+9TT+4fZjrrEeAZ31iz8A5c7ximHh3 /2HUS/0V9bcFyV9aMQEHZEeaosqzMq/eN3HAx0sU9jxKsE7RgWaD5kwsLeq+2vVepyii w/wxNn+48tQw0W5mRc5oa7pXIrzJdDecEnlV+rYkXGwxVHjCGOKAGmiLqRE6aW6oPXGR NoMFqlp4ogYExaB+yUeRm/V/L8Y2/U5qlqEQhQ6Idg+Rja9FHEtbjxNGUI6WLfMLiUh7 5vwA== X-Gm-Message-State: APjAAAXap3dazlRX5wxloCq6/O+ieFBznz2I2wYI19U+BohnHNwkSf6I Qne0mHglUpn3SlhMjmYI6pdVedmsuCw= X-Received: by 2002:a17:902:d70a:: with SMTP id w10mr92328491ply.251.1564163495029; Fri, 26 Jul 2019 10:51:35 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.33 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:15 -0700 Message-Id: <20190726175032.6769-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 50/67] target/arm: Convert T16 one low register and immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 44 ++---------------------------------------- target/arm/t16.decode | 11 +++++++++++ 2 files changed, 13 insertions(+), 42 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 692891dbe0..9bdcb91537 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10594,48 +10594,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); } break; - case 2: case 3: - /* - * 0b001x_xxxx_xxxx_xxxx - * - Add, subtract, compare, move (one low register and immediate) - */ - op = (insn >> 11) & 3; - rd = (insn >> 8) & 0x7; - if (op == 0) { /* mov */ - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, insn & 0xff); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } else { - tmp = load_reg(s, rd); - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, insn & 0xff); - switch (op) { - case 1: /* cmp */ - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - break; - case 2: /* add */ - if (s->condexec_mask) - tcg_gen_add_i32(tmp, tmp, tmp2); - else - gen_add_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - case 3: /* sub */ - if (s->condexec_mask) - tcg_gen_sub_i32(tmp, tmp, tmp2); - else - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - store_reg(s, rd, tmp); - break; - } - } - break; + case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ + goto illegal_op; case 4: if (insn & (1 << 11)) { rd = (insn >> 8) & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 965fb1bf6e..edb67a3896 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -133,3 +133,14 @@ SUB_rrri 0001101 ... ... ... @addsub_3 ADD_rri 0001 110 ... ... ... @addsub_2i SUB_rri 0001 111 ... ... ... @addsub_2i + +# Add, subtract, compare, move (one low register and immediate) + +%reg_8 8:3 +@arith_1i ..... rd:3 imm:8 \ + &s_rri_rot rot=0 rn=%reg_8 + +MOV_rri 00100 ... ........ @arith_1i %s +CMP_rri 00101 ... ........ @arith_1i s=1 +ADD_rri 00110 ... ........ @arith_1i %s +SUB_rri 00111 ... ........ @arith_1i %s From patchwork Fri Jul 26 17:50:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169905 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp362194ilk; Fri, 26 Jul 2019 11:00:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqzqey0PnXvAKGT7+1/2AVFjcxuy7BXGHaVqNiAZr5guPLpuncMV8GLEcbacdnuIfr4la/0M X-Received: by 2002:a50:ad0c:: with SMTP id y12mr82281456edc.25.1564164015605; Fri, 26 Jul 2019 11:00:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164015; cv=none; d=google.com; s=arc-20160816; b=A5Udd+fm0wWNcJP6S403rJ9ui9YOtgVZ6glEVsJdy243DiEul+T900DruLcC7jYw3C hRj4AtVK5NlSazLFKjcmt8R6wZOViySlXs6exg40h888v4FZSm7plBHEvctgci5xtV7M GArqs65M5ue41cG+l77uTB4WjjMiCiu6ancsxrLjQTG5zsXIw7vK6FxHvfPNUJ7XRxUB zIFJ48uXGT15AXHXvJRGDDDiclRBW6RuXdz0WWXVnRp9FMnHid7uKR/jsMviItr3Rypy l5i6gzdRHV6MAmXcum7RWpE5/2yaCjZ17sA7vvEF+l0PnYTWAFG2DSkyt8Czhg6o1qOh fApQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=IrOBDo+AXilRW3wlJP2NZAtzPEtyDf6q+uMfRAEA/NI=; b=OHrmgKUborQnEGhAxv4ZGsNj/PfdXGXb7J7BTarzkaZTZ99k1YcgeDH/u7RHgmW3qU F5RL2Jllbbi9YpwPZ4NFcYuiNXMRJUf1kdFUWXKijubYOHWlnDo+JYN4PRIitAH4if+V eNnpw8c8iomNdKgkOP60Wuo/S0gkGbjlpN9NryYrycdjrhCPHmRvQzR0DIXxuHNRSHuA M4CKVwNVT806bCWXqXAmq6MH8Vxeye2/FRgUMeDpEdXfX1Aed/ByzGSzOtm0RiwewljN joru8C6An3lA763tffrIARlY9olnJ2bDGAlElnJ150VKvtv91uFO28EdmuGF47HcFAZd cKQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HoMVKWu0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z20si12499307edd.286.2019.07.26.11.00.15 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:00:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=HoMVKWu0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Vo-0007Nf-Lz for patch@linaro.org; Fri, 26 Jul 2019 14:00:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59195) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nd-0006Bv-Ku for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Na-00012q-Fa for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:43 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:43567) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4NY-0000yQ-Ck for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:40 -0400 Received: by mail-pl1-x632.google.com with SMTP id 4so18030903pld.10 for ; Fri, 26 Jul 2019 10:51:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IrOBDo+AXilRW3wlJP2NZAtzPEtyDf6q+uMfRAEA/NI=; b=HoMVKWu0oOTa7UKx7ED5TontqAfti1JQ7VEe/rbHXTE6oXK41FnB8koKNRRa71pN5u syIBAu0/b9SOUGSx0Rt0Aua2n+KjsSgFnKGnT2pW8vHEQDBl2WSeNV1/vFeNAxwa/v4Q Tu8M3VjQY9QW9pS3aQUVEy+u/cDRtctHyw0WkzFqdQKVEEA5yS5A+eTtBw4IFUFgvZAe mJAh7sDsN9fZqnxRg3H1UQbVJ4POiLKiVdqubDzV+40lC5E6eS4/JUKDpqKAf++KtyN1 hFrKhaVAfdwaPhF7KXln3gcXZEvMmT8h7ghX3OaKtOhRQw4s1ui45XsKGiLU29CFuqCQ re0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IrOBDo+AXilRW3wlJP2NZAtzPEtyDf6q+uMfRAEA/NI=; b=ILMuPDD6ZeRiWh50yztHS6f1hqlr43FDXw6XgUzbVPhSckdmESrbbBafry63yp91e6 j/mHliN5V/Z50gmLyeCw8vnAo7Rg8U+Bq5DqBZR0wq9VUtyXCVtul3S4MdBXHK//6ZUW F8znxFCzRD6LoyR6Hp5kXTX7/6GLMIqRTS9z8JT0TpK0jnx2gNsXZMOqkhtm90XpqBIF NjDGq9qEuYwjH3abCYFhxBDCXw/A0y7PIRHcNK/OvejYLfFWmXlVvh2XyQgjZlZ/LQMo iZ4vlgmDKi41WcPNgrfUmaplLVKt9SVHWNsxUIYnmalFMqBFZfKh3xtddjB5EMSxGMOV Jt2Q== X-Gm-Message-State: APjAAAVfsj1gbKMI1fdhT9aADFleC091SJfIFCwsVkjsFyDovPMM4Uhd Fz3vA9eiVk7fDdy5CS0rRrWrrKjtps8= X-Received: by 2002:a17:902:e210:: with SMTP id ce16mr98753140plb.335.1564163496015; Fri, 26 Jul 2019 10:51:36 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.35 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:16 -0700 Message-Id: <20190726175032.6769-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::632 Subject: [Qemu-devel] [PATCH 51/67] target/arm: Convert T16 branch and exchange X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 64 +++++++++++++++--------------------------- target/arm/t16.decode | 10 +++++++ 2 files changed, 33 insertions(+), 41 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9bdcb91537..e2183eb543 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8406,7 +8406,7 @@ static bool trans_BX(DisasContext *s, arg_BX *a) if (!ENABLE_ARCH_4T) { return false; } - gen_bx(s, load_reg(s, a->rm)); + gen_bx_excret(s, load_reg(s, a->rm)); return true; } @@ -8433,6 +8433,26 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a) return true; } +static bool trans_BXNS(DisasContext *s, arg_BXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + gen_illegal_op(s); + } else { + gen_bxns(s, a->rm); + } + return true; +} + +static bool trans_BLXNS(DisasContext *s, arg_BLXNS *a) +{ + if (!s->v8m_secure || IS_USER_ONLY) { + gen_illegal_op(s); + } else { + gen_blxns(s, a->rm); + } + return true; +} + static bool trans_CLZ(DisasContext *s, arg_CLZ *a) { TCGv_i32 tmp; @@ -10645,49 +10665,11 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; case 3: - { /* 0b0100_0111_xxxx_xxxx * - branch [and link] exchange thumb register + * In decodetree */ - bool link = insn & (1 << 7); - - if (insn & 3) { - goto undef; - } - if (link) { - ARCH(5); - } - if ((insn & 4)) { - /* BXNS/BLXNS: only exists for v8M with the - * security extensions, and always UNDEF if NonSecure. - * We don't implement these in the user-only mode - * either (in theory you can use them from Secure User - * mode but they are too tied in to system emulation.) - */ - if (!s->v8m_secure || IS_USER_ONLY) { - goto undef; - } - if (link) { - gen_blxns(s, rm); - } else { - gen_bxns(s, rm); - } - break; - } - /* BLX/BX */ - tmp = load_reg(s, rm); - if (link) { - val = (uint32_t)s->pc | 1; - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, val); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* Only BX works as exception-return, not BLX */ - gen_bx_excret(s, tmp); - } - break; - } + goto illegal_op; } break; } diff --git a/target/arm/t16.decode b/target/arm/t16.decode index edb67a3896..4701f72357 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &ri !extern rd imm +&r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list @@ -144,3 +145,12 @@ MOV_rri 00100 ... ........ @arith_1i %s CMP_rri 00101 ... ........ @arith_1i s=1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s + +# Branch and exchange + +@branchr .... .... . rm:4 ... &r + +BX 0100 0111 0 .... 000 @branchr +BLX_r 0100 0111 1 .... 000 @branchr +BXNS 0100 0111 0 .... 100 @branchr +BLXNS 0100 0111 1 .... 100 @branchr From patchwork Fri Jul 26 17:50:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169926 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp369895ilk; Fri, 26 Jul 2019 11:06:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqzdUHkLqCJO7/+WzDN3O5ti1ZevMeUHIIOWlF8wymEiSR/RFTSDOJ0pYNoBw5E720kplurH X-Received: by 2002:ac8:2bf1:: with SMTP id n46mr66794552qtn.372.1564164367576; Fri, 26 Jul 2019 11:06:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164367; cv=none; d=google.com; s=arc-20160816; b=ZFugbEUHn8wd9ja9P6g6n+4Wy67EI8A38e6XogdbjgVLVqH7A8tUf96vuFw+GKhaS8 IP6eOU5kXTLQ4D7jdSnMmJNFh1w1PPTofcOk2BjG3htF0RSyWbYIClCbp9t2A4SOlaW7 roVnWW2Yl8oEKQKxOBU4/5Y6QzhXYp4WMQeRf5HqEszkB8CfIPZy6uFkhhNLzK1gxsY2 WAAS9qU4gcJP828aek9Gq5t9Qc5IGU6quMoDdW4BHy9NsyRxuYfLliS+FYfdjmsJzaJ4 mvYwSaQGD9TfmmlL0H74xwvIiPqrxUbxuwzdiuRWYZKTKmTBnVVrV4o3lqJANy9QEVqO GsPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=+4XfaDCTfyuI+ugQIIzBK6MHDxWWrmnHUnH0Hltgmbo=; b=u8DdJLnm/i9Q1Q32ptm8eTiKrXTuAJrqZGoYaMKwyZzUKKCnSQXpMxQ/JgR3zWdaoc JZiHOi8lgn2hwAARr3snwq+KU4Ec4bfTF+wicR8eChcPTxnL+4h3tpLYmagfM5Ujqeuu pF8F6NUYf7Lxtg3FANQA3LHJHmlb83jrIIzCBo4FymId0IAZJUe0wUTIgtpNN7PlgvIu Uj1mFydLog2yaK7af74pFvbJVVWFEHQtJh08vUvz32RO9OIaDSs17wezpjB95y33Lry9 ou4oOI/g5QcxlWbom3qZXreyMRxFowigz/wNRwFAlQ9zVunVvDBYxRTPj1PQNN52iDTn oLew== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=socwDXsH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r21si15491789qvr.188.2019.07.26.11.06.07 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:06:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=socwDXsH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42808 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4bW-0003UI-34 for patch@linaro.org; Fri, 26 Jul 2019 14:06:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59737) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nw-0007Wy-Nc for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nu-0001PG-3K for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:03 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:38257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Ns-0000zB-Oa for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:01 -0400 Received: by mail-pf1-x443.google.com with SMTP id y15so24861200pfn.5 for ; Fri, 26 Jul 2019 10:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=+4XfaDCTfyuI+ugQIIzBK6MHDxWWrmnHUnH0Hltgmbo=; b=socwDXsHqY7yZXUSpb45ST5QixBbzT62HHOJE0nIj3BKMkNL+Fd/ljjQXsGqYj0d9U 2x0aGRFsn78hjoqjMD9kLH7I/VFO17xuInQU4fT1TSHxmh/Wju1VvLCemgIraxVDW5JU Ij3gYHaEOaFqN8EbOSNK8SRPCVf30pWyawBsqlfl5CPZjU3kN8eAMJCwC0b7aEeNCyYr g5XyGZj7jhh3Ygsfncq8K3iT0ZSH8Ptn3H4CFrlYvF+09H9O64rPysxgzDnF1N6kLcL5 hfR5mt2E9+Fp7C0gw2oNsKzxRJCNsLl5BLuLipH8Y8TuU2vwD5VLPoRa49+TqV563Wa9 Fs2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=+4XfaDCTfyuI+ugQIIzBK6MHDxWWrmnHUnH0Hltgmbo=; b=bu0HgrdAJn0uMXpYe7aolKlp8TkNthurIYKayBytKS125oRrqT/Nj3P4LkyGB/82k+ 2FK6TXpcjCGsrEIvlJhkjCsB0BsCEQxt7fh87l0scyA/W3ONacCTF4QHriNPJabpfnEw SHpNEk/V2tOcZaRlp+D5jicuyvbIkKCUift/ngD7/tYC83k3O7/KtH4Y6pTfJntFPiFK JrQOXPE83py08uve9gz8uo8Lu4d+k+yhBI+dZj5EXoc3MZiL8eA+k25bz54afEBe7qFe AFYcMwxQTAp6dlmE3dkz0+8Orus8DN4QJk3FURCguuYT//NWTNn9K/MG8NB005LvEieZ CA/A== X-Gm-Message-State: APjAAAVDIjzUrnMRcg4x17kabo9LGms65riWf/pNx53A8Pln1uOBv/Ns dqBcbXKI17MPWrIQ5eaRgkoSqhfz0yk= X-Received: by 2002:a63:7b18:: with SMTP id w24mr91960531pgc.328.1564163497124; Fri, 26 Jul 2019 10:51:37 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.36 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:17 -0700 Message-Id: <20190726175032.6769-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 52/67] target/arm: Convert T16 add, compare, move (two high registers) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 49 ++---------------------------------------- target/arm/t16.decode | 10 +++++++++ 2 files changed, 12 insertions(+), 47 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index e2183eb543..23f5f982f5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10628,55 +10628,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); break; } - if (insn & (1 << 10)) { - /* 0b0100_01xx_xxxx_xxxx - * - data processing extended, branch and exchange - */ - rd = (insn & 7) | ((insn >> 4) & 8); - rm = (insn >> 3) & 0xf; - op = (insn >> 8) & 3; - switch (op) { - case 0: /* add */ - tmp = load_reg(s, rd); - tmp2 = load_reg(s, rm); - tcg_gen_add_i32(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - if (rd == 13) { - /* ADD SP, SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 1: /* cmp */ - tmp = load_reg(s, rd); - tmp2 = load_reg(s, rm); - gen_sub_CC(tmp, tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - break; - case 2: /* mov/cpy */ - tmp = load_reg(s, rm); - if (rd == 13) { - /* MOV SP, reg */ - store_sp_checked(s, tmp); - } else { - store_reg(s, rd, tmp); - } - break; - case 3: - /* 0b0100_0111_xxxx_xxxx - * - branch [and link] exchange thumb register - * In decodetree - */ - goto illegal_op; - } - break; - } /* - * 0b0100_00xx_xxxx_xxxx - * - Data-processing (two low registers), in decodetree + * - Data-processing (two low registers), in decodetree + * - data processing extended, branch and exchange, in decodetree */ goto illegal_op; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 4701f72357..69d3894ba7 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -146,6 +146,16 @@ CMP_rri 00101 ... ........ @arith_1i s=1 ADD_rri 00110 ... ........ @arith_1i %s SUB_rri 00111 ... ........ @arith_1i %s +# Add, compare, move (two high registers) + +%reg_0_7 7:1 0:3 +@addsub_2h .... .... . rm:4 ... \ + &s_rrr_shi rd=%reg_0_7 rn=%reg_0_7 shim=0 shty=0 + +ADD_rrri 0100 0100 . .... ... @addsub_2h s=0 +CMP_rrri 0100 0101 . .... ... @addsub_2h s=1 +MOV_rrri 0100 0110 . .... ... @addsub_2h s=0 + # Branch and exchange @branchr .... .... . rm:4 ... &r From patchwork Fri Jul 26 17:50:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169914 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp364892ilk; Fri, 26 Jul 2019 11:02:12 -0700 (PDT) X-Google-Smtp-Source: APXvYqw7vUVw/fBBS4iNvHyYstsxZGJHfmS4sZDUSMtGzmqywJ2N7GKK1uO9AGjyfkW0Mo3NZuSQ X-Received: by 2002:a17:906:af86:: with SMTP id mj6mr28681089ejb.157.1564164131966; Fri, 26 Jul 2019 11:02:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164131; cv=none; d=google.com; s=arc-20160816; b=FsW9kNVhWTiEJhGd7WDzMCRWpXiAl6G9plqo50IOldTYsOEnYo3IoJSi2ktjGhJUFk QwIj0ucl1CPKGoLJc+LN2pFcuK1afVVivG3C69SqNEK6SEcGN3GU2Ts16BQGkhYsxP2D kU7dkgLPskQczVV7e+GvldtsK+AAT/+XdEUe6DwB153kh4pBATKqyUHBcaBeTSgK9Hg5 4OSHjfWttTJmb+HA8rqcHnP2lJjflgTcjLI/oiJpFZ0ScZZrbnV0n0Yzl+268RM274m1 4DwkyM0JPGeXN0idNvJ/PAYqixXwmfUI8geN2TVRUqdT9SIAzz1GQU6sxPq0BxscOeQ9 pw4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4oQFd4eolp/sR05iPY07hrdPVedFpqTSb74q9tevE6Q=; b=qSZm0BrVsiEJe/nrAJNLHA/0eOoTShVIQTDlB3Kh8pAeTW8PpCpn5VyeC0VDJSZE8S Fj0DNHV3c27g3FuqYrAoSsc8h+gidIk/3dpldQ1HDfcYaMAlFCuQ52zGqVrq/ia9f9z8 gmhQjNV3ndv5H0StgFqfkzjkTR3lddxrMyAJYqnrB61m9bP/nHF/dJlB9c0Hwy+ybz5K Tlp5UUUofkcZy1WnHmAQ7pt/pIInFdk7wgzClLchL3frkDt3ZjUQAqjkd/DFXUm4+uYp GkzwMst8ZPSDXahS24cXLsA8fB69kLpFJtdjRbvX80HpZo3+Vah8yHjbGziCsQ45BGfT pbkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sebaT5Ca; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i3si12286207eda.107.2019.07.26.11.02.11 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:02:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=sebaT5Ca; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Xh-000715-8A for patch@linaro.org; Fri, 26 Jul 2019 14:02:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59399) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4No-00072A-UA for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nl-0001C9-CI for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:55 -0400 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:39977) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nl-000104-3L for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:53 -0400 Received: by mail-pg1-x544.google.com with SMTP id w10so25119004pgj.7 for ; Fri, 26 Jul 2019 10:51:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4oQFd4eolp/sR05iPY07hrdPVedFpqTSb74q9tevE6Q=; b=sebaT5CasiTw2aM3248r1KuO5rtFcs1xBcJSCI0q1O9VXVe8TaJ5Jd4Xof3DPSkguy SdwPX+1iUc6OEXijV+TlXieOtSH9CiMnH1cGu8E6VElNAFU3DJEYnFwmcTj4gWP9mmUK /wPf2JdJDkvHEmeOaTfp+7hzDOgFzA/rI4rVIP6vSTsOnuaRjvABIpedUTv8GtfLknum oHRT/y2drBf5b/EDjQld8UII+U8bZ1Kbn/SQkkAPoe4cwsg5wFLzJpvvDBeONpw1ohv9 85Klm4DDg8PXU7dbUnp8pnDjroZ3PAPrhHCZY9+1N0/7tnJA7b4VtDlNkYd9c+OuztrL Acag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4oQFd4eolp/sR05iPY07hrdPVedFpqTSb74q9tevE6Q=; b=DEs1nBHbmqVrESg3rs7bnP+O1Cyo757KEy+t7vVQPX/KFIO/25j4TvSt//NmnMjJ2B r9wPZH+uYwJGCqBoM+zN4GHoQEzSk6VhhT/tyG0M/bCLj7/6e9olFW+u2KvUDTik/6qo cuaTatRSBXJAmdFkz84o1URYOQlNWQkJuvL/MBHCdEAF7RYKynrir+veBLFqLxcSwVnz Xrk7YBQX4B9mVGgCjykw67cfgVDLuSXvB5w1qx76WwBEWkNpZMM58O/XMvlg36bVTgJi yOFDg6Beh4agwqIaVkCUlAaAI7MvAakWiYpVqYyQ8PzmyJf7PqVfvIW1TqPAPLAcsT0+ UpUQ== X-Gm-Message-State: APjAAAVMUbDH/56Sk5Ifcxd+DIKzv4yBpHq3v9fRlHjO8ypZ/96eQn53 +yuoD98xxkgIlvG1F1XfCiJTY09mRgI= X-Received: by 2002:a17:90a:d996:: with SMTP id d22mr99375160pjv.86.1564163498255; Fri, 26 Jul 2019 10:51:38 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.37 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:18 -0700 Message-Id: <20190726175032.6769-54-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 53/67] target/arm: Convert T16 adjust sp (immediate) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 ++------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 23f5f982f5..8dd88419fe 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10648,19 +10648,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* misc */ op = (insn >> 8) & 0xf; switch (op) { - case 0: - /* - * 0b1011_0000_xxxx_xxxx - * - ADD (SP plus immediate) - * - SUB (SP minus immediate) - */ - tmp = load_reg(s, 13); - val = (insn & 0x7f) * 4; - if (insn & (1 << 7)) - val = -(int32_t)val; - tcg_gen_addi_i32(tmp, tmp, val); - store_sp_checked(s, tmp); - break; + case 0: /* add/sub (sp, immediate), in decodetree */ + goto illegal_op; case 2: /* sign/zero extend. */ ARCH(6); diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 69d3894ba7..ddf12ada11 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -156,6 +156,15 @@ ADD_rrri 0100 0100 . .... ... @addsub_2h s=0 CMP_rrri 0100 0101 . .... ... @addsub_2h s=1 MOV_rrri 0100 0110 . .... ... @addsub_2h s=0 +# Adjust SP (immediate) + +%imm7_0x4 0:7 !function=times_4 +@addsub_sp_i .... .... . ....... \ + &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4 + +ADD_rri 1011 0000 0 ....... @addsub_sp_i +SUB_rri 1011 0000 1 ....... @addsub_sp_i + # Branch and exchange @branchr .... .... . rm:4 ... &r From patchwork Fri Jul 26 17:50:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169925 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp369585ilk; Fri, 26 Jul 2019 11:05:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqwxSMFRmyf+cbiBNSEbsqDMnp6EV4zNvNIIFpnsgXxigeX9soewMv+FrO1pwXkQE7ux++/T X-Received: by 2002:a17:906:cce9:: with SMTP id ot41mr45183612ejb.196.1564164352635; Fri, 26 Jul 2019 11:05:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164352; cv=none; d=google.com; s=arc-20160816; b=bAg8KFm43JmwYFInYO8eDtAEwSwd44W/UX1Tv2VM64c1vQ/wR1FToeoMeGWb453sbA Jhliuq/ooq281mtc4xg8KUM4ejMdODj/UfOx0ZSVET0WnEow1gWreEjT8NluyzEPDCna yd44hQKX0DI5cy95UGVhQ0fri+arZnOF3vHMQzdgdnoXrYvVmJ5zkN1lOWyU5YpP83dw lrJZPjGN+6Tkn2BabmRpgNMTZX4qHVKkSK3fo9Ipo3/BbKY1FYhoFQz4Mvd+4wsPRUbD iCB30MQKWYWFn3lGTPi6IehGcxsSGiaDtsXJx4Dp7jHmJ/OzZtClU3LZQgyulFDbhvF/ LZ5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=zTUDYR2hU4ZALOUVF4vngOslrJ4X/C4rxl23t5JZO3Q=; b=OB73lA/Qom80MF+ypm63uY572WzSsfEIcCS2UHaIwfZmK6aDS5opgWvSdbQZi1wH0O fnPuDnvgbXuVWUqppJurv+8ZM4DhiZPRa/7uuN59DPTuvbqsgcB+QPFzBdjhDP07KEA8 ZLj9wjQe0iUv7vsH32VvU7t9HXR+lrtU0Q2L1AZqypBBd8Zr96NWjutKL0x/4UTo2bLi iSqpu9dF9CMYDeafbnCPZdapNsTZjQ5X45U7xvs9cld9fp/ycB6fLT9nc0wphfw47V3Y qcSqEEAwYJAiK0pzyKpXDes5HFCa0+NoyaOI0G6FdRgPElEfWhQ4aI1vgoAaeqDPU/aO 57nA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IBcpfWh5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w51si13209856edd.246.2019.07.26.11.05.52 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:05:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=IBcpfWh5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4bG-0002V3-Dx for patch@linaro.org; Fri, 26 Jul 2019 14:05:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59725) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nv-0007Vx-G1 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nt-0001Ow-Vy for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:03 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:35150) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nt-00010K-LP for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:01 -0400 Received: by mail-pg1-x543.google.com with SMTP id s1so18806513pgr.2 for ; Fri, 26 Jul 2019 10:51:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zTUDYR2hU4ZALOUVF4vngOslrJ4X/C4rxl23t5JZO3Q=; b=IBcpfWh5F6SICO8ZNgo7HTWDEj65hPbOmjwpHDMPOSCTbQdQto+AG5lDVWE1kScYkY rEsUNeJv4bBFCbT66tWGHDNt+d0xjQ/OB9MQdoTN+F/1CPHGwOBZ3boZbOttYIDTYNsh PTmM0DBzE0+7rqSNGOfyl8V5z6oueULbw4QzVAOk+njVXlGr6WsSRMS16e8bi46V+NgY od0S5QvWjed+z6Qr/bSITXm52QCaEWcF4h1c92XYLvDWqCm8zaDNUmo+kP4TJvAyWXTL wZL411752OUL9vsnDENcfUJhWQ4PLhmiKZxUrZYiGTzCycnozF00YUPxnAXEFN0wttuH 9Ggw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zTUDYR2hU4ZALOUVF4vngOslrJ4X/C4rxl23t5JZO3Q=; b=qWuKciOTBgUp44THfd2OYFQsPHpBsEvPJdNDve0gj3t80YqWIVIGIJ7mqpAKx/YlmV N1WofbG0o7d0sV5oOQGVx0iH8imL1ZafV136cMVeB4Va1jjGLMfp3r1lDkmGlVZ+3Pxp iC51jM60sjgQDtxcEEAROzrusNHjtQ0nnVPuRgz4S7Vp2PlkDzDC9rsDqct8Hgx9bFtE 0Aq1V/yCdc0VeeBWxlUwitp62MiMzhNlEHhTSwEgCgPo3i3pQKf8UjVKz396ZlTMlTlZ ZDB/n5PGlr8yleQhX4fEdXBgeZxD6GZ6j0QWwVuboKPurB0iJEib9i4w7kUj/nNLcIo8 RNug== X-Gm-Message-State: APjAAAXXJzBYU/Uevl0MLP9dK9aiHweyBqpXuysX2gjH66oFmCp5MaOb PJUr4LhaJQkEKszDyVMzcX0FBkmr8kU= X-Received: by 2002:a63:5c7:: with SMTP id 190mr90711195pgf.67.1564163499284; Fri, 26 Jul 2019 10:51:39 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.38 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:19 -0700 Message-Id: <20190726175032.6769-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 54/67] target/arm: Convert T16, extract X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 14 +------------- target/arm/t16.decode | 10 ++++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 8dd88419fe..9c8e11bd3a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10649,21 +10649,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) op = (insn >> 8) & 0xf; switch (op) { case 0: /* add/sub (sp, immediate), in decodetree */ + case 2: /* sign/zero extend, in decodetree */ goto illegal_op; - case 2: /* sign/zero extend. */ - ARCH(6); - rd = insn & 7; - rm = (insn >> 3) & 7; - tmp = load_reg(s, rm); - switch ((insn >> 6) & 3) { - case 0: gen_sxth(tmp); break; - case 1: gen_sxtb(tmp); break; - case 2: gen_uxth(tmp); break; - case 3: gen_uxtb(tmp); break; - } - store_reg(s, rd, tmp); - break; case 4: case 5: case 0xc: case 0xd: /* * 0b1011_x10x_xxxx_xxxx diff --git a/target/arm/t16.decode b/target/arm/t16.decode index ddf12ada11..1b47e804bf 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -23,6 +23,7 @@ &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra +&rrr_rot !extern rd rn rm rot &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -173,3 +174,12 @@ BX 0100 0111 0 .... 000 @branchr BLX_r 0100 0111 1 .... 000 @branchr BXNS 0100 0111 0 .... 100 @branchr BLXNS 0100 0111 1 .... 100 @branchr + +# Extend + +@extend .... .... .. rm:3 rd:3 &rrr_rot rn=15 rot=0 + +SXTAH 1011 0010 00 ... ... @extend +SXTAB 1011 0010 01 ... ... @extend +UXTAH 1011 0010 10 ... ... @extend +UXTAB 1011 0010 11 ... ... @extend From patchwork Fri Jul 26 17:50:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169919 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp367157ilk; Fri, 26 Jul 2019 11:03:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqzsSWxfVb8eKrPspzilI4QirrUdejhPlsC1avv2qQBYUqTo+x/zanlcqGrylvwu8w7LCCWH X-Received: by 2002:aed:2a43:: with SMTP id k3mr68418684qtf.301.1564164233218; Fri, 26 Jul 2019 11:03:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164233; cv=none; d=google.com; s=arc-20160816; b=D6yWVf+6DptZ+UbfPQN8FPm7cieT0TujTJjz3zizm7+hLenz6auOF5hIpN2y/Bstxi ZkN1T10Uj5zSR4moox/I2PurTEOaOGjBhj2Fm1qgFYM5xa+56UjYXVQ02H+/XC2hykvN DXxlX3H4ACZwM2UDDQiFhbv/2sk0i8IatVfVEpsQo9ZRSZncuT9GYYuzJaSDeWr6bIJW Dc3eSddpf4dzmpbusnkmLgkR4x2lWqIekQMt0T4f8OT3SQI2Ou9PET/wel8yR6F+NJM8 NKHboijef+Ixni2cfrTOdabe+LAopdGApQuOQohCoX1DHtlSei8jfN0sGpAWC2i8gV6R jABA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=qeYs/8P06sT88x1fm+VX2RboOfuM1870Y9rpmWOvTNY=; b=APIif95xCxM4BL/PgTMsw+Fx4FSCPUGkzmyMC1/BcVm1c+PNg+4msGdrmCKicnvKhZ B7zLcGDB4ki4j6PYof5TDulgx/BR6JEbl3is/IppPSseyThtTdAMe1kMBFepu8q6SBPx U39O6O7D9SQ6B7X6/EWjwE0tP0c+bwKs6uRvQfhBIgqUwrO6d6l60HBhrfCm+1OkWn7r GJONgVRb3v0pOmSDrzkd59T9eDoVSDS6oIQf6xSCmPxWbjY//rGT/bunJFKz4oAEX8e8 CPGYNVyOw3YDQacD2x5uaSRs3cmeu63TKNS65LCgo857b11SUAuX72q0tMdPaaZTZdlY 0qEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yQ3jutNB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s5si12063971qts.160.2019.07.26.11.03.53 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:03:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=yQ3jutNB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4ZM-0003gY-05 for patch@linaro.org; Fri, 26 Jul 2019 14:03:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59456) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nr-0007DA-Hp for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nl-0001CH-Ec for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:57 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:39975) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nk-00011l-1d for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:53 -0400 Received: by mail-pg1-x541.google.com with SMTP id w10so25119044pgj.7 for ; Fri, 26 Jul 2019 10:51:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qeYs/8P06sT88x1fm+VX2RboOfuM1870Y9rpmWOvTNY=; b=yQ3jutNBhJLz4jBCk1TzF98u6da0i8ITj42pLZcF/8tNMCnmPEK/FGue1OrihmFZzA wRMe4XhlTsudTRVI05ErFLXxAz+QvaxTWFX1IXDFdhgYghGQNWS/k1DWBJ3SfGFWIdRj eGEZJuixaTHCGaelA6nYHa3q0VtOyBpgblzUNZ9F0B49DAcTlkOhfvs+cK85hPrrG0xm rDrg/ZlN+CVVN3vD38GbYwA5hxY8dvMb4/gJeEVWeMz79Ifhm/ZHaA1Sg+OjOYAJBluB odItBAJ8OqixFNdVmPKEczhf+HWQ7BcQlF5k9TRB3BWqHztzn6NT8mQglN/kOpVLtg1r H1+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qeYs/8P06sT88x1fm+VX2RboOfuM1870Y9rpmWOvTNY=; b=rcnByn3W3kL+sZCW5TxwO1wRc9LMVIlmZ5yjTs2Rh7/m5jH9NkVN2pAHZwShsQlDuh x6gi3pCQPfOpQdv368loPHCvNhD5B9Z1BCcXcmDOIYLsWJ+Y/gg5dcZz+3M7RWGshzPR fApB/Q2o5Tdn+/mp5xJHlev+QwKK7GeSQfBY+Q5kg9bFozOtybbMrU4+f7P86lBfFIEU MDH7LpJMxr5bS/kujq05mxY4wkN7nYxXOmsKvqOrP7rC9ZHAOTnZCcwtYom/Ct8NYQX8 dUUBqj+AQjMwsKVqH5tON+l6n9hoQWtt+1EUU0ewksdZACstBUBYcSB1c90EsXj5cnG4 IiEA== X-Gm-Message-State: APjAAAXL3rrVd+gcnVP/5GCaGN1o2Y/bwx4hJA5P1CYg8+EvDN+DL6dm JREKVHWS2vPeKmbWcoMA80PTZbDE22Q= X-Received: by 2002:a17:90a:30aa:: with SMTP id h39mr99848190pjb.32.1564163500297; Fri, 26 Jul 2019 10:51:40 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.39 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:20 -0700 Message-Id: <20190726175032.6769-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 55/67] target/arm: Convert T16, Change processor state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 85 ++++++++++++++++++++---------------------- target/arm/t16.decode | 12 ++++++ 2 files changed, 52 insertions(+), 45 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9c8e11bd3a..8f2adbbc7d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7531,6 +7531,11 @@ static int negate(DisasContext *s, int x) return -x; } +static int plus_2(DisasContext *s, int x) +{ + return x + 2; +} + static int times_2(DisasContext *s, int x) { return x * 2; @@ -10163,6 +10168,9 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) { uint32_t mask, val; + if (ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M)) { + return false; + } if (IS_USER(s)) { /* Implemented as NOP in user mode. */ return true; @@ -10193,6 +10201,36 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) return true; } +static bool trans_CPS_v6m(DisasContext *s, arg_CPS_v6m *a) +{ + TCGv_i32 tmp, addr; + + if (!(ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M))) { + return false; + } + if (IS_USER(s)) { + /* Implemented as NOP in user mode. */ + return true; + } + + tmp = tcg_const_i32(a->im); + /* FAULTMASK */ + if (a->F) { + addr = tcg_const_i32(19); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + /* PRIMASK */ + if (a->I) { + addr = tcg_const_i32(16); + gen_helper_v7m_msr(cpu_env, addr, tmp); + tcg_temp_free_i32(addr); + } + tcg_temp_free_i32(tmp); + gen_lookup_tb(s); + return true; +} + /* * Clear-Exclusive, Barriers */ @@ -10793,51 +10831,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) break; } - case 6: - switch ((insn >> 5) & 7) { - case 2: - /* setend */ - ARCH(6); - if (((insn >> 3) & 1) != !!(s->be_data == MO_BE)) { - gen_helper_setend(cpu_env); - s->base.is_jmp = DISAS_UPDATE; - } - break; - case 3: - /* cps */ - ARCH(6); - if (IS_USER(s)) { - break; - } - if (arm_dc_feature(s, ARM_FEATURE_M)) { - tmp = tcg_const_i32((insn & (1 << 4)) != 0); - /* FAULTMASK */ - if (insn & 1) { - addr = tcg_const_i32(19); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - /* PRIMASK */ - if (insn & 2) { - addr = tcg_const_i32(16); - gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); - } - tcg_temp_free_i32(tmp); - gen_lookup_tb(s); - } else { - if (insn & (1 << 4)) { - shift = CPSR_A | CPSR_I | CPSR_F; - } else { - shift = 0; - } - gen_set_psr_im(s, ((insn & 7) << 6), 0, shift); - } - break; - default: - goto undef; - } - break; + case 6: /* setend, cps; in decodetree */ + goto illegal_op; default: goto undef; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 1b47e804bf..f43ea6ce20 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -29,6 +29,8 @@ &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list +&setend !extern E +&cps !extern mode imod M A I F # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -183,3 +185,13 @@ SXTAH 1011 0010 00 ... ... @extend SXTAB 1011 0010 01 ... ... @extend UXTAH 1011 0010 10 ... ... @extend UXTAB 1011 0010 11 ... ... @extend + +# Change processor state + +%imod 4:1 !function=plus_2 + +SETEND 1011 0110 010 1 E:1 000 &setend +{ + CPS_v6m 1011 0110 011 im:1 00 I:1 F:1 + CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod +} From patchwork Fri Jul 26 17:50:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169916 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp366001ilk; Fri, 26 Jul 2019 11:03:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqwGYLmw2bdT/+KcBW+TpsdCrFCxiBV77lsMOHS/+FI8E8olOeEDqIKJeI+jZNWzUDiJhCpp X-Received: by 2002:a50:ed07:: with SMTP id j7mr84863858eds.107.1564164181902; Fri, 26 Jul 2019 11:03:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164181; cv=none; d=google.com; s=arc-20160816; b=cflJxLl64k3NrH8R+FQn534Tuo6pr1zeHTdOjrzKQo7aMZHez2PedfYUWRVWIiJPoA 5Wmj55BzF47OFv03i8DRUA26SDzMrw1JipFGzom0jQzEMrJmbfNB5FoD71VBgB6UiGAH LJLIxINJD6dos/EyT6DrWxp+LP6jaq2HyUOSS+wiEJCfQ2v7rWpVz00QNo/rTz2NimFl 6aO+ALyKMTjy4aPcJgNAszHo2b/BuCq92KlnWTWS2O5XiAHlMvy1OsDSua4K6/QG/pbH LAPObIwa1KUXoW5E4QBL1mkTFcXU2451aewn+fEo8krmmNpRrAXgrfX72lNgm/y4quKj Ig6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ZAbTmn5IF7GueTfMYNm2AkgzbEYkr29V4U+PzJz5VKI=; b=Ui28Li5lG6rfyC2H/3Ok6V/EECJtrBegdqyHH9QX/KnQmCwflb7QDURIl3BgQO/M/3 KAzIvZXDnBygv5enQ633BMvk8/w+R//PYO4+8lcwHiO2w3avsTBeAyktkeREQlnZF7FF Cef9SCUbO0WTtMVTOFTC6hXQ17XhyHzpG8PnoAdRkB6EIce3WIZ3dNpXXSBykvKrENzh X2tKo07ZQ0gMMxb39L9C4bJcZnq63ZvqkKJcXObnxmzI13cktyboUfH/13QNL3t+ZpcH p1evAoKZ5wOT7LJSv+veKN4xDzoUffDj7Ro6HT4rjqm4lbChuwrDIWIafLT7rsCTDfCo FUlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="u1/bN0yv"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g23si11910721eje.302.2019.07.26.11.03.01 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:03:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="u1/bN0yv"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42654 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4YW-00006l-Cj for patch@linaro.org; Fri, 26 Jul 2019 14:03:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59613) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nu-0007Ne-UA for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nr-0001Hp-Ep for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:01 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:40792) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4No-000128-FJ for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:57 -0400 Received: by mail-pg1-x533.google.com with SMTP id w10so25119067pgj.7 for ; Fri, 26 Jul 2019 10:51:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ZAbTmn5IF7GueTfMYNm2AkgzbEYkr29V4U+PzJz5VKI=; b=u1/bN0yvmLzzHZfwmGdJtqVQKUSWEOylJMAksCfq9jC94VNMAvZ3KCxdO1kjRUVRI6 /bTeVsyiywp38B2aiqP//FyAkzUuRl95nOkshxh4D6x5g2A8+TwsmjmD2UM/dhvdWItc cC5txPzMn2csHMyVAQicSWkWb0VBDzdBsMkITEFB83azfPSRORtz/j9G/p48f30RBXGM zCr6V/F8+yN8j5yFjLQdbKntZoClfHfwad7andkRFLGfRiRZEh00ICVTiR39oUpdjfl/ rjaffxT0QJgfGP9sEvNpbUVR4xDtiKs3tyRXi/ZfExQSKUIQPEVy58ZKY73hJsYukebj 5iDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ZAbTmn5IF7GueTfMYNm2AkgzbEYkr29V4U+PzJz5VKI=; b=DafL8n7M81pkrRc+4z5gQ1Gofkcm3DmBFFrEbIiff6MYeETBJn4cvKc4UngdlYOzqa qsMC+BeLFcqNW4lyXG/4j3TO9HygtgqSFB/DFkprcBCQkAY6vHUOKsQQe+JT0u/Ay0rj rfvWwrCYqztyMLj5mFuduZmPPBoMnmsfPFAIp25S1N6VRhnHPGbK5xUPLYj8vgq/xeYJ H2DZeUQoHYkFlyRbjAZGnNPfeCe2Cv2F8f3kyPK++Y/2PVE54yFD3PE8Ow3RQBjUz5ET tnfMaKbnjsBIqj6FowB5kAKH7GhGOZ1vpyjJwWynX5exErGuOaU7WZI++zGSBlA7o8EA +V3w== X-Gm-Message-State: APjAAAUmUDSBFoKsfkhKBRkp5Qd1s7fGXBCXVBf+D4B4LN4gu7R3vSOU hnFH+bjBA7I2i6w0ycAJZX8DaLlpQjA= X-Received: by 2002:a17:90a:ca0f:: with SMTP id x15mr53334493pjt.82.1564163501445; Fri, 26 Jul 2019 10:51:41 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.40 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:21 -0700 Message-Id: <20190726175032.6769-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::533 Subject: [Qemu-devel] [PATCH 56/67] target/arm: Convert T16, Reverse bytes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 18 +++--------------- target/arm/t16.decode | 9 +++++++++ 2 files changed, 12 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 8f2adbbc7d..c9386ceefb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10616,7 +10616,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rn, rd, shift, cond; + uint32_t val, op, rm, rd, shift, cond; int32_t offset; int i; TCGv_i32 tmp; @@ -10815,20 +10815,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) break; } - /* Otherwise this is rev */ - ARCH(6); - rn = (insn >> 3) & 0x7; - rd = insn & 0x7; - tmp = load_reg(s, rn); - switch (op1) { - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp, tmp); break; - case 3: gen_revsh(tmp, tmp); break; - default: - g_assert_not_reached(); - } - store_reg(s, rd, tmp); - break; + /* Otherwise this is rev, in decodetree */ + goto illegal_op; } case 6: /* setend, cps; in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index f43ea6ce20..8864f89a81 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrr_rot !extern rd rn rm rot +&rr !extern rd rm &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -195,3 +196,11 @@ SETEND 1011 0110 010 1 E:1 000 &setend CPS_v6m 1011 0110 011 im:1 00 I:1 F:1 CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod } + +# Reverse bytes + +@rdm .... .... .. rm:3 rd:3 &rr + +REV 1011 1010 00 ... ... @rdm +REV16 1011 1010 01 ... ... @rdm +REVSH 1011 1010 11 ... ... @rdm From patchwork Fri Jul 26 17:50:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169927 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp370130ilk; Fri, 26 Jul 2019 11:06:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqxaZFI7cJaYrmHkaaPWusxNXoKpPY1YO7VakdQTMid7LRv1ugz7NEX7zpPtCFzD2Yo8P6Gg X-Received: by 2002:a0c:b786:: with SMTP id l6mr69360274qve.148.1564164378666; Fri, 26 Jul 2019 11:06:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164378; cv=none; d=google.com; s=arc-20160816; b=sEftmkuWdX9QsX02x42hWbI3da94J03V1PG4lYvG29ueqhogprFm3+j9kzxxtm5Ns1 V0of17smcQ/Db1vrLb3bAsFMYZCZxB6v/Mmalpp/5SNi1hByNCcVTaMR2AttI5YuyjGq 2Tja8EAdqrUWwm2jv3Hug9ypNn2wLHjy7g240DIxRXJN6Zi/s1AqNxLpQw0lH3dsqF+m zCbxxAMb/B/sD2j0UV9UaupHOZw2fEFCOO+3FR62Pl5XHq2umY1Eh8qIX+XkU3jQwGlG jR/a7lY96DDd9MeGk8RoXZpCqOHzm9EkCpFrHqoIkPpOto7WtcNQtlqzksl1tfizc9ba CAqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=jvX6d8XTRW2yINP7UUXQMp5wulYHcQa40IZNorojim4=; b=aObX08u0iarvRNcjo+I+Z8RXstyopCPPVBxsv/om0Yrl/uNRQIPbNmKE7bJfPw67Ih isdETz3FJHz/Fo7ufwYRBUhD/Mr3udd5bKbWkMhJ/mE2eE4JKBA30iWvaLRLE4RfGj2w etUmy5OBEtNPCtxLAZaR7gdr8DvJ6f4GW2WhLymPv9dRHVW/iP3kjk4VFIl9BGsnS/X1 13UrBFUaLyHOneZQyRmQAWYqZ944Se5EMp9Do1ZI52GY6hXFvesYxtttQnDKB25FUOpe CubtuneH2CsE48QTelxyy2q8g10Egbh1Nx0N1ZEbpcqM95xodvryQ14411GBXOX/q5n/ OJTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Wa09kRYm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e11si29014685qkm.49.2019.07.26.11.06.18 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:06:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Wa09kRYm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4bg-0004Le-8w for patch@linaro.org; Fri, 26 Jul 2019 14:06:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59853) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nz-0007fg-4D for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nv-0001SW-8G for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:05 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:38257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nu-00013K-UG for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:03 -0400 Received: by mail-pf1-x442.google.com with SMTP id y15so24861302pfn.5 for ; Fri, 26 Jul 2019 10:51:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jvX6d8XTRW2yINP7UUXQMp5wulYHcQa40IZNorojim4=; b=Wa09kRYm6m3CF3ttivMMv8u/yQKXirGUlAJVWq4s8hIZCc1gyeFdJCRrNob2zTCJWQ lrCwA4+AzRPw+J4AJvZtpquXXt5eFlYD5ol9rVJufp+s+f+oqzyPQkc1kPm0BqF913Vz Bww8YS5g8Wsh/rZaM7NhrWOktQRCJBDtXvML3bTNiRUaepVEiDDW0MAF8Ld7ERVo7Oj9 jrd1+ADjUKBWHNbYP15JpcwL0g1KP7+uH8kVoEAUo15Rn0RAUp3I0+Z8waiX1/DVLkP2 Ei4TmzmUqskYn3FqJ7JFm0BFIfX22UKjw6dTA3dxK78iyUJacKIKi03qFMcpk0H9iD3d eevA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jvX6d8XTRW2yINP7UUXQMp5wulYHcQa40IZNorojim4=; b=pMV2YAywcXWvr543wYMFa7HhCRrGdEkhCpJ4V3X5f4W7/nNT9u6KRGvtBjVvmY/Ytc vX4MxC/FOsNPFta/EAvAxtQHeDYPAWdDcmQ3dlKba1eSm5poNvLCr1BvTa+CSumHykDo KQp4J92jXAL62THXCgb9N/5AUgNr7imrBWQE/qsLdJQd3pP0HRcOxMxpjPfpI5wWkoWK N61OMcqj+w9lR6twSHW9OPnudA1/OaEDQBSVlwHbPjPZNzrvdJTKtFEBGLHWbi7AI/LC h9/HYcRzWmM2oATfwuBZ99otbsLbnZc0RfgXon2Fmfdbsx7cLIrKj+L8HkpvgafnGnwI H2uA== X-Gm-Message-State: APjAAAWn0Xplubd68aR6sqp6enIIUH+na8vkfYQwtLDvnyz2qY5MqGtV 22LzZDj9uMdNwgQgZsRYRpg+T+6CR74= X-Received: by 2002:a65:5188:: with SMTP id h8mr59842315pgq.294.1564163502521; Fri, 26 Jul 2019 10:51:42 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.41 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:22 -0700 Message-Id: <20190726175032.6769-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 57/67] target/arm: Convert T16, nop hints X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 3 +-- target/arm/t16.decode | 17 +++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index c9386ceefb..55404414a2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10779,8 +10779,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 15: /* IT, nop-hint. */ if ((insn & 0xf) == 0) { - gen_nop_hint(s, (insn >> 4) & 0xf); - break; + goto illegal_op; /* nop hint, in decodetree */ } /* * IT (If-Then) diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 8864f89a81..90a4b71a45 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -19,6 +19,7 @@ # This file is processed by scripts/decodetree.py # +&empty !extern &s_rrr_shi !extern s rd rn rm shim shty &s_rrr_shr !extern s rn rd rm rs shty &s_rri_rot !extern s rn rd imm rot @@ -204,3 +205,19 @@ SETEND 1011 0110 010 1 E:1 000 &setend REV 1011 1010 00 ... ... @rdm REV16 1011 1010 01 ... ... @rdm REVSH 1011 1010 11 ... ... @rdm + +# Hints + +{ + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 + + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 + + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 +} From patchwork Fri Jul 26 17:50:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169920 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp367282ilk; Fri, 26 Jul 2019 11:03:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqzVZXHcuc4+K9hvRYdr/aXxZpU4Sa/U41JbTvNRQZVZMqEvk4P9GdJDEUK0reln4GxxtCp0 X-Received: by 2002:ae9:e217:: with SMTP id c23mr21496592qkc.227.1564164239128; Fri, 26 Jul 2019 11:03:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164239; cv=none; d=google.com; s=arc-20160816; b=nqtxTP5KKrRtYdIHqCwHlfxqCCZivMFaC9Dhq+6Zn6kZKMQ4BvDOpR26aHjNMLRIPi m2rQe1Mz9WgHXXKujdPyKnnwwWqrcpI78X/RXAmghMzSjXx+r1CoEhrJisDWEcStEtax lQeOm0hOiidW5DzAGFGQzlUxJQKmFe5vT/Zi6MiF7Cb7Ifa7wK5dIm5yHC9eIRFv//Au Dgk2AyU0b6bE+sez+8xfs0SDFlOtX6eYMt2Dl9gYVUj1W9zFHET9nSy6+KDCeRPyHFWk toRpdS+jBrLK+MtJt6aeKsyeMBp+pthPmprXTWbj06KWKdwOfcxPe0CG8WkfxtZcBGER xmOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=C70Yg+46c/XVZyXVh4QRHDyUG/TqYDz7LEEkFesYi6Q=; b=tf3yA3T2zlIO1Z8TRC6ud4LoBgasj4Bx9y4RpJjxUby6H3V34WXZ2PSp5zrjsOyvIy I61c9Bfh2e1mX6Z1WAjzJzfqxuCTsJXfkDn8et7WQoyqYUP4RLOx+yquX/nBroyIhDw6 pm3gj8YqU6yjyJUw8WJiwirzw007OnRzht9gA90hUt9pLKeMf/nBcOy2HnXpMkG2mN9f vVw5HQyZNGMV3FbxOVkKvjsb/+SZW++i6kKShxsFg8/0pe91s7AZWgEqiwykPLzFQt9H eDAjYiiopRFQnKcpawyuEnIESX4I+PNYZnQ6JD8/VpeiuvLdlnIlcmjeLsFeQZZNwLSR C6cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NzxCzQPw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v22si30872940qta.332.2019.07.26.11.03.59 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:03:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NzxCzQPw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4ZR-00037P-W2 for patch@linaro.org; Fri, 26 Jul 2019 14:03:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59738) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nv-0007X2-Ot for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nt-0001OU-Ri for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:03 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:46825) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nt-00014l-Ge for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:01 -0400 Received: by mail-pf1-x429.google.com with SMTP id c3so1720839pfa.13 for ; Fri, 26 Jul 2019 10:51:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=C70Yg+46c/XVZyXVh4QRHDyUG/TqYDz7LEEkFesYi6Q=; b=NzxCzQPwDL2RHpSKettJLJJ3w8c0BDGTVv1D2coZzWHKoMplL/ZnUe4nh5V15XPe6O 2wvHwYgFDvS5rWbFipEQDZqV3L/elqF1/YwK94JB3inJTWRaic+RNfKB6FtMaGYBh+LY 7ddtzIuW02hHgXU+WObCHgWmrEqaFhWP1/vn+vZ6AoDhdBmcIpwu0YwksdtzqVcjd+ih IxICgFMB4AidU6+tIdQBC5GXSekfcHFMhtegGtvcdsnelu0WW6RYGHkGdWpLxRL11MgW J6xLpCfeMpwGfP/KNsXqU6iaA2poW4fHJR1JRQVrwIQ3DXvx32rxQj6xCrplH0avJlxB Acrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=C70Yg+46c/XVZyXVh4QRHDyUG/TqYDz7LEEkFesYi6Q=; b=AmrI8spPKH3QnbnW+7MQxpZtLc7mTYqg6s3f7SpkkcmgEE92xEG5a0d9WLKe9UI8mk vII89VozCnZmExbnKyVpLFVxEV7sr31GKyouBdqxShBdJu3KE3Z0HlO9KpIdoG0SOFz2 IcZJme0sC12My/XAXFMFvFBhccjp4OnYeZGinIexEa/QKJ/F95g1NRNnHf2o/eNH6y9y hz9RmLQCMSMxWwTc2bJ3OO++k3J671X4v2p9rmnW366oGl2HHz4ZdClS0m4BCq4AJ15J afp5wG6TYrBPeTOevOy8Zd0ZMEabDnnQbSGevWEki72D1KRL8OoF9iwN/gCPGjkMtT4o evnw== X-Gm-Message-State: APjAAAV/PTinB7D7coR/M8HsTBLGa80nlXxtZgn4kokW0kU4TbWadg6e QKpAQAUc5RIiyEBHLSMpAuROS4MkF6I= X-Received: by 2002:a63:ee08:: with SMTP id e8mr38601581pgi.70.1564163503573; Fri, 26 Jul 2019 10:51:43 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.42 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:23 -0700 Message-Id: <20190726175032.6769-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::429 Subject: [Qemu-devel] [PATCH 58/67] target/arm: Convert T16, push and pop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 83 ++++++------------------------------------ target/arm/t16.decode | 10 +++++ 2 files changed, 22 insertions(+), 71 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 55404414a2..5d0d0779c8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7593,6 +7593,16 @@ static int t16_setflags(DisasContext *s, int x) return s->condexec_mask == 0; } +static int t16_push_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (14 - 8); +} + +static int t16_pop_list(DisasContext *s, int x) +{ + return (x & 0xff) | (x & 0x100) << (15 - 8); +} + /* * Include the generated decoders. * Note that the T32 decoder reuses some of the trans_* functions @@ -10618,7 +10628,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) { uint32_t val, op, rm, rd, shift, cond; int32_t offset; - int i; TCGv_i32 tmp; TCGv_i32 tmp2; TCGv_i32 addr; @@ -10691,76 +10700,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) goto illegal_op; case 4: case 5: case 0xc: case 0xd: - /* - * 0b1011_x10x_xxxx_xxxx - * - push/pop - */ - addr = load_reg(s, 13); - if (insn & (1 << 8)) - offset = 4; - else - offset = 0; - for (i = 0; i < 8; i++) { - if (insn & (1 << i)) - offset += 4; - } - if ((insn & (1 << 11)) == 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - - if (s->v8m_stackcheck) { - /* - * Here 'addr' is the lower of "old SP" and "new SP"; - * if this is a pop that starts below the limit and ends - * above it, it is UNKNOWN whether the limit check triggers; - * we choose to trigger. - */ - gen_helper_v8m_stackcheck(cpu_env, addr); - } - - for (i = 0; i < 8; i++) { - if (insn & (1 << i)) { - if (insn & (1 << 11)) { - /* pop */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - store_reg(s, i, tmp); - } else { - /* push */ - tmp = load_reg(s, i); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - /* advance to the next address. */ - tcg_gen_addi_i32(addr, addr, 4); - } - } - tmp = NULL; - if (insn & (1 << 8)) { - if (insn & (1 << 11)) { - /* pop pc */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - /* don't set the pc until the rest of the instruction - has completed */ - } else { - /* push lr */ - tmp = load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - tcg_temp_free_i32(tmp); - } - tcg_gen_addi_i32(addr, addr, 4); - } - if ((insn & (1 << 11)) == 0) { - tcg_gen_addi_i32(addr, addr, -offset); - } - /* write back the new stack pointer */ - store_reg(s, 13, addr); - /* set the new PC value */ - if ((insn & 0x0900) == 0x0900) { - store_reg_from_load(s, 15, tmp); - } - break; + /* push/pop, in decodetree */ + goto illegal_op; case 1: case 3: case 9: case 11: /* czb */ rm = insn & 7; diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 90a4b71a45..10cdca1fbb 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -221,3 +221,13 @@ REVSH 1011 1010 11 ... ... @rdm # rest of the space is a reserved hint, behaves as nop. NOP 1011 1111 ---- 0000 } + +# Push and Pop + +%push_list 0:9 !function=t16_push_list +%pop_list 0:9 !function=t16_pop_list + +STM 1011 010 ......... \ + &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list +LDM 1011 110 ......... \ + &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list From patchwork Fri Jul 26 17:50:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169918 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp366752ilk; Fri, 26 Jul 2019 11:03:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqwo5auAj2w9KJ/8Faf7r88tIcigPxaYXWYThZAQCQ48XTPsw4argHol3INJnhhrqORjF4Gm X-Received: by 2002:a37:a80d:: with SMTP id r13mr56250598qke.209.1564164212259; Fri, 26 Jul 2019 11:03:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164212; cv=none; d=google.com; s=arc-20160816; b=s/xVBOU3B7Uhkx/PEet1valQQ5uaQDmL/dgcgzfVXNxZaXCAy4UKkrGvXnedYwfc1j hVWG+LLTz55VgN7+FBe31d61BOd1vFP/GSl3h/R+cwXgQNV5RVgSb1oeYXY0fl729PBi RYcFW8kqJ/M16Q4LlSVNUUw2P+fBWQJ+n2VAqZXZxDlRqqWwGS62Np6jd8I3iRNK2F6T OL6Un1iNY/CcJBaj+YfK/nmX8DDHkSdA3cqjKLlEhhJ5YTjRjJ/ip4J3AupS0PiDobtq /x300t0CkS00iTZgXE74vTjgqpkBqlrJ8XT0RzJcg3fwsp8bhgzdpbZQtdZExpq49a2n b2YA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=kW5KBD6wPpayXUHizYdiz+TBRbqx6bgCGmxteuVYILs=; b=Io7iS2nuYofEHrVZWWqQPVv5o8wRdOW/icmfzALrFsSSHP9UyULuMLmUen2E8Uwqn/ R5KyuqXsARctRBDhFOLAzFYPr1zY9yZTPsarrfMrZxLpeIZAxB9LxbxhPLmZ/Sclbw21 EO2v+opmDBm2ndbXqAGXp8MwQ7YyfeXYVwNX/zoK8lP79roHX0uW9xN7xsQAFnc9z/IV KHGMZm/b6phckuslEuotLbPwQC54H/l/bFfhz6PKN3LvOYjShIKlzQcgjqyfl+wBGTu8 2k8560B91LoyDawocsp3uROuxwHrKP+tyqTdKEwyh60lyuBB6EVWquQgd3Z2qxalFe20 PF3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="P/NyunXc"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 73si17367268qkf.25.2019.07.26.11.03.32 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:03:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="P/NyunXc"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Yz-0002YZ-C1 for patch@linaro.org; Fri, 26 Jul 2019 14:03:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59733) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nv-0007Wc-Ml for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nu-0001PK-2p for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:03 -0400 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:43351) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nt-00015p-Qg for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:01 -0400 Received: by mail-pf1-x442.google.com with SMTP id i189so24859782pfg.10 for ; Fri, 26 Jul 2019 10:51:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kW5KBD6wPpayXUHizYdiz+TBRbqx6bgCGmxteuVYILs=; b=P/NyunXcP/IxoRd21r8LFlzNsCYrAu6YIymG9KavT2DR7sxxz19uDsHBFb1qt8XIi7 jpvFuIoGGINF0D06C9w/2gEtGWiIowCQxwB7c07LvT6OxWKsK7L4SKmiuHbcPnSkyDLD EqE0WLtr5WEWfxBIs9ZYHX8UhXUCTGubbR8A50e47WmstEN55Ln5Zs+xsELxUcPalCdJ kwkzTuTPnjIxo43G7SCZ0lrjtNv2s8kGe4Aq3fo+hX+4EecyK4nflkk41qrzLyH2PlZP WTLnB451CMQivPVPQaUJqASpW34JWUD6e/b5P3qI/H/CvSzhplNDzOBHEssqkeKj4Zsq DB7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kW5KBD6wPpayXUHizYdiz+TBRbqx6bgCGmxteuVYILs=; b=gAMU02LhD1WJi8RQge+GuvzWSPoAEoNyxnQ37i3fQIbg2kX4sUxvh4Kw9FBsowRcCH m7hr/dWNiCdxAR3PuffC/Bo1LEGE32HlSfLaYmWupA4gDybQwNDr86sd3VhkiVS6O1Pk CMfpoIL11v9SQOa/P613uHepWTspTW16rQxu2RXRiM5CK0n2rR3UpeKttrU7W9w9YXzW 0rsN0a7X03/l7qdgf4og8CVl9Bd1RCdRyZqd/q3T/qOoQAXh/hW5pXtUHiJXJR/nIC6u HhhvPJxEk4H765jjHnsUPlaNxO3U1gGQgQtaON1e4OPZsPTEXezRBqNktZzdPAa/Y8rP DgZw== X-Gm-Message-State: APjAAAUVV/sRvrwaFXGAlio3F9kObaywNVFZ9snJDVoNSdWK5Dds15Cy 9adz023FVxybEb1D0QaxlnFdaBE/BMQ= X-Received: by 2002:a65:5c4b:: with SMTP id v11mr49756112pgr.62.1564163504727; Fri, 26 Jul 2019 10:51:44 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.43 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:24 -0700 Message-Id: <20190726175032.6769-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 59/67] target/arm: Convert T16, Conditional branches, Supervisor call X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 +++----------------------- target/arm/t16.decode | 12 ++++++++++++ 2 files changed, 15 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5d0d0779c8..97c472c8f7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10626,7 +10626,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift, cond; + uint32_t val, op, rm, rd, shift; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10767,28 +10767,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } break; - case 13: - /* conditional branch or swi */ - cond = (insn >> 8) & 0xf; - if (cond == 0xe) - goto undef; - - if (cond == 0xf) { - /* swi */ - gen_set_pc_im(s, s->pc); - s->svc_imm = extract32(insn, 0, 8); - s->base.is_jmp = DISAS_SWI; - break; - } - /* generate a conditional jump to next instruction */ - arm_skip_unless(s, cond); - - /* jump to the offset */ - val = s->pc_read; - offset = ((int32_t)insn << 24) >> 24; - val += offset << 1; - gen_jmp(s, val); - break; + case 13: /* conditional branch or swi, in decodetree */ + goto illegal_op; case 14: if (insn & (1 << 11)) { diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 10cdca1fbb..f4091c812d 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -28,11 +28,13 @@ &rr !extern rd rm &ri !extern rd imm &r !extern rm +&i !extern imm &ldst_rr !extern p w u rn rt rm shimm shtype &ldst_ri !extern p w u rn rt imm &ldst_block !extern rn i b u w list &setend !extern E &cps !extern mode imod M A I F +&ci !extern cond imm # Set S if the instruction is outside of an IT block. %s !function=t16_setflags @@ -231,3 +233,13 @@ STM 1011 010 ......... \ &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list LDM 1011 110 ......... \ &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list + +# Conditional branches, Supervisor call + +%imm8_0x2 0:s8 !function=times_2 + +{ + UDF 1101 1110 ---- ---- + SVC 1101 1111 imm:8 &i + B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2 +} From patchwork Fri Jul 26 17:50:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169928 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp370605ilk; Fri, 26 Jul 2019 11:06:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqyW01y8nDUnL42w2kut2s4xTLLFlzdqD29G8pVOavn9d8P+WEp7OLl8D5bCtNXho3pT7EyD X-Received: by 2002:a50:b388:: with SMTP id s8mr82605590edd.15.1564164398877; Fri, 26 Jul 2019 11:06:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164398; cv=none; d=google.com; s=arc-20160816; b=Imk+LkT/slJUCusSjHCePR2rwSZsydJbUE3vF5hkwU6kRWPgKZsMFgzWbajjK+5wLR ob0UE6/l4EEaAzYroiW70QZ25U0qvJP0rcTqmcr7FpcAQICqZ02ltPo7xai2NGUwdoJH unnE0zVqaoY2/BMssl3lUAM5CB1vqt591om6DBf5PHriedivQSMZgYJiC9I68sT+oESl ENWZ5finYIk5Z5a87IRoAGxxUR4rhOoNjki/CJJUdEhU0CAJUdqKKkbCQx1mw3FMdMGA iww5jTfBrKfNc2W9rF8rP5aieJjCSoO621euE8CWwSJQF/3bIUJffBEmhVueLek0UXaG HMUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4eSnwGdItsZZfZWQU9TzlBCuQSBa1+CtKc/8GLA6ttg=; b=QIa9K7F21zzkJoOvjDpUoH3mTejr4PcNO7jXfTmP/+sJnvp6stEKIBGsTWtQ+Bz2bU vPaTcHed8R6iD9vIcB6d8zzvRh9H1CUJcGH342HLCM4yCStNZzk5mAdYx9GwZ6r81UkA oCLJDY+Cp0kyhIGpT3EtX+9UDmG4MpRGWH6CwCtonOOT5TZwCw+62aRc1wThSMjIDLE7 UZ+gPx4tN77GIq1EKcxI7UiGbc665hX4UXwYrxxMlpgV3PbkBMdkXsN9uZNrYeHVLpbV QY41UdoFpVvO55TM2B0BY7oQfKUau6PDdKOgfpGK7Mh8vu5GqWH5YZ0B2D3c2vAXV2Hd c6eA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BmS4hBPw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f17si12945295eda.220.2019.07.26.11.06.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:06:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BmS4hBPw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42824 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4c1-0005Yt-PG for patch@linaro.org; Fri, 26 Jul 2019 14:06:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59716) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nx-0007Uz-C7 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Ns-0001KN-61 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:03 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:37071) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nr-00016Z-Tl for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:00 -0400 Received: by mail-pg1-x52a.google.com with SMTP id i70so14372154pgd.4 for ; Fri, 26 Jul 2019 10:51:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4eSnwGdItsZZfZWQU9TzlBCuQSBa1+CtKc/8GLA6ttg=; b=BmS4hBPw5lamyrdx8TR9pA8Xo3AbD7c675p6vfH2K29pKeZEf644NVNaGlC35Y9KRG MIwbFQ4dcVm+HaOohT7lc+lQbLY5VLvi+gbJkbze1MeQC7wMdJDmUG981IDBq0LoESIH Bp2IJrbxlAS5acxpInOfBdWkPsG3ZBym/YlsZyylEEEdROFQPG1YADzjjehDY85MEZQg i+JJCAx2TeJjmo0EoSc7QpfGuqOWgevoMhYyofSVNNKUhG/imB7yW4uh+2PX50RgyyzF aGgNKOyG6gkSYOxpS2zghT4RKn4vp8quINMAhExSVY42ktK5purh4GHz23ki7fGX3xci 3gdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4eSnwGdItsZZfZWQU9TzlBCuQSBa1+CtKc/8GLA6ttg=; b=fvPxPvu6yvBEw39A8dRugDEkfDVC3W3oRTgr/5ijvOpRuTXI6DIFQaAVJG9QTzRR+S 0ujfLadluR+3srkBF9dSJRujGtXU9a61ippkWav4+FBGA/RDS82zp61eCMJ0bxuTSZ/5 6be5j5TBjvkpwPhgKQ/eckVFn2BPerESOWDH0PX7FDpA3c3B6aT8N0tPzTRmkjdFGDCQ c5xbkr9i3KAcMnQ3e23npomGFiFiqYBWKjsV0qnxJKJyRAsGG3Cg7pMs0XIRadM9pLSF dtJQWFNVlPB+1zSL7ohYxRwtrFtz1GfJZDbgOMnZda03OgzSenaBveyb+AxxUneROixu fINg== X-Gm-Message-State: APjAAAWuWx+0G3fjpbIiHjs0WNERioOKgTbPw+MlFadYpWLKVU2tNloW MY6DyrtHS0auLuI7wNUzh3Flyh4I0+M= X-Received: by 2002:a63:e54:: with SMTP id 20mr90473834pgo.244.1564163505827; Fri, 26 Jul 2019 10:51:45 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.44 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:25 -0700 Message-Id: <20190726175032.6769-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52a Subject: [Qemu-devel] [PATCH 60/67] target/arm: Convert T16, Miscellaneous 16-bit instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 111 ++++++++++++----------------------------- target/arm/t16.decode | 31 ++++++++---- 2 files changed, 54 insertions(+), 88 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 97c472c8f7..f3a946d8c9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10104,6 +10104,18 @@ static bool trans_TBH(DisasContext *s, arg_tbranch *a) return op_tbranch(s, a, true); } +static bool trans_CBZ(DisasContext *s, arg_CBZ *a) +{ + TCGv_i32 tmp = load_reg(s, a->rn); + + arm_gen_condlabel(s); + tcg_gen_brcondi_i32(a->nz ? TCG_COND_EQ : TCG_COND_NE, + tmp, 0, s->condlabel); + tcg_temp_free_i32(tmp); + gen_jmp(s, s->pc_read + a->imm); + return true; +} + /* * Supervisor call */ @@ -10325,6 +10337,25 @@ static bool trans_PLI(DisasContext *s, arg_PLD *a) return ENABLE_ARCH_7; } +/* + * If-then + */ + +static bool trans_IT(DisasContext *s, arg_IT *a) +{ + /* + * No actual code generated for this insn, just setup state. + * + * Combinations of firstcond and mask which set up an 0b1111 + * condition are UNPREDICTABLE; we take the CONSTRAINED + * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, + * i.e. both meaning "execute always". + */ + s->condexec_cond = a->cond; + s->condexec_mask = a->imm; + return true; +} + /* * Legacy decoder. */ @@ -10688,85 +10719,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 8: /* load/store halfword immediate offset, in decodetree */ case 9: /* load/store from stack, in decodetree */ case 10: /* add PC/SP (immediate), in decodetree */ + case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ - goto illegal_op; - - case 11: - /* misc */ - op = (insn >> 8) & 0xf; - switch (op) { - case 0: /* add/sub (sp, immediate), in decodetree */ - case 2: /* sign/zero extend, in decodetree */ - goto illegal_op; - - case 4: case 5: case 0xc: case 0xd: - /* push/pop, in decodetree */ - goto illegal_op; - - case 1: case 3: case 9: case 11: /* czb */ - rm = insn & 7; - tmp = load_reg(s, rm); - arm_gen_condlabel(s); - if (insn & (1 << 11)) - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 0, s->condlabel); - else - tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel); - tcg_temp_free_i32(tmp); - offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3; - val = s->pc_read; - val += offset; - gen_jmp(s, val); - break; - - case 15: /* IT, nop-hint. */ - if ((insn & 0xf) == 0) { - goto illegal_op; /* nop hint, in decodetree */ - } - /* - * IT (If-Then) - * - * Combinations of firstcond and mask which set up an 0b1111 - * condition are UNPREDICTABLE; we take the CONSTRAINED - * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, - * i.e. both meaning "execute always". - */ - s->condexec_cond = (insn >> 4) & 0xe; - s->condexec_mask = insn & 0x1f; - /* No actual code generated for this insn, just setup state. */ - break; - - case 0xe: /* bkpt */ - { - int imm8 = extract32(insn, 0, 8); - ARCH(5); - gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true)); - break; - } - - case 0xa: /* rev, and hlt */ - { - int op1 = extract32(insn, 6, 2); - - if (op1 == 2) { - /* HLT */ - int imm6 = extract32(insn, 0, 6); - - gen_hlt(s, imm6); - break; - } - - /* Otherwise this is rev, in decodetree */ - goto illegal_op; - } - - case 6: /* setend, cps; in decodetree */ - goto illegal_op; - - default: - goto undef; - } - break; - case 13: /* conditional branch or swi, in decodetree */ goto illegal_op; @@ -10822,7 +10776,6 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) } return; illegal_op: -undef: gen_illegal_op(s); } diff --git a/target/arm/t16.decode b/target/arm/t16.decode index f4091c812d..17297a3032 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -210,20 +210,33 @@ REVSH 1011 1010 11 ... ... @rdm # Hints +%it_cond 5:3 !function=times_2 + { - YIELD 1011 1111 0001 0000 - WFE 1011 1111 0010 0000 - WFI 1011 1111 0011 0000 + { + YIELD 1011 1111 0001 0000 + WFE 1011 1111 0010 0000 + WFI 1011 1111 0011 0000 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1011 1111 0100 0000 - # SEVL 1011 1111 0101 0000 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1011 1111 0100 0000 + # SEVL 1011 1111 0101 0000 - # The canonical nop has the second nibble as 0000, but the whole of the - # rest of the space is a reserved hint, behaves as nop. - NOP 1011 1111 ---- 0000 + # The canonical nop has the second nibble as 0000, but the whole of the + # rest of the space is a reserved hint, behaves as nop. + NOP 1011 1111 ---- 0000 + } + IT 1011 1111 ... imm:5 &ci cond=%it_cond } +# Miscellaneous 16-bit instructions + +%imm6_9_3 9:1 3:5 !function=times_2 + +HLT 1011 1010 10 imm:6 &i +BKPT 1011 1110 imm:8 &i +CBZ 1011 nz:1 0.1 ..... rn:3 imm=%imm6_9_3 + # Push and Pop %push_list 0:9 !function=t16_push_list From patchwork Fri Jul 26 17:50:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169923 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp368373ilk; Fri, 26 Jul 2019 11:04:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqyf4RWAFmRWJXaWXLhzNtkFVVkEV/4a3+dl04Bt4l4dcOAa/8Mi/1JQC9jpYklsOCmOAPTU X-Received: by 2002:a50:f410:: with SMTP id r16mr84478270edm.120.1564164291548; Fri, 26 Jul 2019 11:04:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164291; cv=none; d=google.com; s=arc-20160816; b=jrKN3IFxWzID4cFPnam4QekxXs9NTKWiAlLBOFRfMd4PmcyHUXVOe1OYPaTCEmojWs YwdbO5IVqEm+hs1IiMoCRlEA/dLZf+nAEa3dHVmf4nKq1I7oc0CG3Qef5CV0nY4Pqt0U D/VG43s2OYxwHuZKhxOZVc6yrlvf0y149VA7qfZz39HIEPlzrNEcwEPVR78oEpKK3WiE sMOpSiicpODg79/0Qbx94o2IFzrf/KKupGCah+ewYqxR7IbOH/fssOTBKzTeinA/48kM 0pKjqfivanfSyGJPy0CT6L4ZTY8P6WVZFiCClWNZeTOZJJere3wnhCZF/GRHjzDhgDB/ hPKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=8QVQ4BiqNc7iS0VjGNnUVyPSyENYZan6FBJAYfvLZTc=; b=KuuhhOuLw00rlW0dMw8VGJWJm2ee3RCK4PvuXL5G8nBM9tA/JpmjOaWapAvs8pUHdo D1QIQ/TZfxWRT/iKmRl+t3dwBmK1YmGwDYYsjdxUsTcTuXRADvrU169Jdzlr8GQbIIQq jB7tuTp7YQUYfLqMSf+e3URAMKyBd2ndLGiSKq2/T7qJbBMtzwwdwfMvTJJlwKxg3CON +iLog2ss/kxW0xAY62xIBzI3t0eR0qt//2KssVplLvJ6sTFfrDFtNR8ojWkEwVJA+k1s cPunQSBMVhHFhgTsM1LWcdnyZcvde4JbtqVd4lIcqDlVCEyKJv2IaRM3wIYt/xYpOTCZ NcZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QVe2eF5t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y25si12359324edc.377.2019.07.26.11.04.51 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:04:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QVe2eF5t; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4aF-00077a-UD for patch@linaro.org; Fri, 26 Jul 2019 14:04:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59458) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nr-0007DC-Hp for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nn-0001Eu-Mi for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:57 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:40067) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nl-00016t-GG for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:55 -0400 Received: by mail-pf1-x443.google.com with SMTP id p184so24849389pfp.7 for ; Fri, 26 Jul 2019 10:51:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8QVQ4BiqNc7iS0VjGNnUVyPSyENYZan6FBJAYfvLZTc=; b=QVe2eF5t5OwKctLNlKcL1Cp/S1HuU3u6npmInBLg3MDJTacCR0bML8eN+coRv0pbfv fLSOCeNWiPxy/8AIXOrKPgXvMkKY6Ff7QMEdesGKPqy70QVK5Z16zFslntSDkUbuKJyI oTbSy2oonDD3UwsbvTFlbPR2zK/GQfwyEcAbRMTJrKEi/oe7buRlUPd8tU1nk8KbP6ff S2jI7/EXaec4/SA2OYPJLcu6WhkrgmBh+cS5Vd3hR5GTZuZHV0HTSyEIFZ26YqbJ3rPK 72tOnaeVDwDFU3fO/Ytap2znGT6mIglouuMwHztJHkLStwCWeMvpSLqpsjpufPaNUy+z Wvhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8QVQ4BiqNc7iS0VjGNnUVyPSyENYZan6FBJAYfvLZTc=; b=ZiRmWFRIeRmR+97XSul+Lzs1Yu6QrwTo5TQhelK54T0PKpCYF3F8vq+gj7WIyv718V 4K2qWKJxO465eRQf94PCnlqqQoT3rH9wFYDyM6h9o60rYnD8wPeX+kXH5W52Mlg+dAj7 SlXL4Ii/Scbniq73bWIBDrXNg9Xm1to/SZHD9e/UD4Y/KShUeU6cCQel13wJGgTBILPN PCDHfksBCt9ezwc/ldLv+LS3yxIw3+9R3y3wvSF/zVEhWCP/Q2CMoDJ5/KyUU/MWjh+K VNMGblXGZnzF7nHmaZhqtzWCnuw8/gbW/Tn+JKbvmKIggLL1Ymtoytz6KCVa58628mNv z2JQ== X-Gm-Message-State: APjAAAW4KHxMb1Q4tyh0ept9NxoPm9wZMQsGrltk86RfUhpxPzp2EWE1 PBHVRu94f8XhPBBuA6QdOdhXq4bEww0= X-Received: by 2002:a17:90a:1b4c:: with SMTP id q70mr96449651pjq.69.1564163507269; Fri, 26 Jul 2019 10:51:47 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.46 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:26 -0700 Message-Id: <20190726175032.6769-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 61/67] target/arm: Convert T16, shift immediate X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 26 ++------------------------ target/arm/t16.decode | 8 ++++++++ 2 files changed, 10 insertions(+), 24 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index f3a946d8c9..f9022fe65c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10657,7 +10657,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rd, shift; + uint32_t val, rd; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10669,29 +10669,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* fall back to legacy decoder */ switch (insn >> 12) { - case 0: case 1: - - rd = insn & 7; - op = (insn >> 11) & 3; - if (op == 3) { - /* - * 0b0001_1xxx_xxxx_xxxx - * - Add, subtract (three low registers) - * - Add, subtract (two low registers and immediate) - * In decodetree. - */ - goto illegal_op; - } else { - /* shift immediate */ - rm = (insn >> 3) & 7; - shift = (insn >> 6) & 0x1f; - tmp = load_reg(s, rm); - gen_arm_shift_im(tmp, op, shift, s->condexec_mask == 0); - if (!s->condexec_mask) - gen_logic_CC(tmp); - store_reg(s, rd, tmp); - } - break; + case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ goto illegal_op; case 4: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 17297a3032..ddffd073a2 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -126,6 +126,14 @@ ADD_rri 10101 rd:3 ........ \ STM 11000 ... ........ @ldstm LDM_t16 11001 ... ........ @ldstm +# Shift (immediate) + +@shift_i ..... shim:5 rm:3 rd:3 &s_rrr_shi %s rn=%reg_0 + +MOV_rrri 000 00 ..... ... ... @shift_i shty=0 # LSL +MOV_rrri 000 01 ..... ... ... @shift_i shty=1 # LSR +MOV_rrri 000 10 ..... ... ... @shift_i shty=2 # ASR + # Add/subtract (three low registers) @addsub_3 ....... rm:3 rn:3 rd:3 \ From patchwork Fri Jul 26 17:50:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169921 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp367847ilk; Fri, 26 Jul 2019 11:04:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqzu/5Isfhgf0an3jpiAooGZkmaKcl+EW0sq8IAf/9GO85JUY4oi0Ni41B7dx0yGcZs5PzHR X-Received: by 2002:a37:a9d0:: with SMTP id s199mr64468228qke.32.1564164268449; Fri, 26 Jul 2019 11:04:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164268; cv=none; d=google.com; s=arc-20160816; b=YJuPJBaWl1By+IJWcvnYfnZxii7TgOasvjlIntzEXfYX7P3WzZ8rZUIcF88EfT8eg8 Wsd53DXWAUuBomuIjBchWCK5xeUyFyd5NwKPuggsEUcTGiFLj20piFcfrgubPHh3Llyk 3dAiK8zBLth9cHTlcmc8uHuPZN2ixOQoJSGVMvRw+Vh1lEGB80f5q264SP3sQ3g4WTGN QifW/zNofSwdrdfDxg5K+2Yv7eG8GyuLNZnEhWWxQ0sfjKc7mUjJko0J39nI+rojGC4P BaY0YHjZ8s052aycIHtkSdL5gSIuh7Oo4J57DRW/ThfTtExDniHI+HXhUigfE+cxe0PO /KbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=p0rmZulySAyfFLpagWq7oUqjHQLoiP7mX2YCEOpaKkw=; b=sEKIMHSZ/qRYX97NU3+g8MGPQetslGGBOaZKvv96XjbplA8EFN5QJtg7jUIKPay5Hb s6GQjkS/hEbKia3pjCKoOEfuTZLM+N5BpN1sXv2uvVGkZI3LLtMmsunHyM5pFhysC63A MnP65hbNgXsFrUC6lOm35wQfdhhz4msQcvKnhGJsql/9UiSP1aRwXlrX8EsD22xY2qVi 6tQ6z5XMKkxptJvAOPhmEI/mNFQe+HMh+YeUgTi0upSb9xV690KSXd+ZNmhb4DAenuIh KGZ8sfIF0k5A6dyOnHl17iJMQ2uPUZLzEHVNP4WtC+nrndg83cXw59SxqUlXBb1sffCP XnmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="cQRG/J8w"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d65si3489743qkf.121.2019.07.26.11.04.28 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:04:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="cQRG/J8w"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Zv-0005kJ-2r for patch@linaro.org; Fri, 26 Jul 2019 14:04:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59946) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4O8-0008Do-5O for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nu-0001Pj-88 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:13 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:39246) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nu-00017Y-0H for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:02 -0400 Received: by mail-pf1-x441.google.com with SMTP id f17so20864591pfn.6 for ; Fri, 26 Jul 2019 10:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=p0rmZulySAyfFLpagWq7oUqjHQLoiP7mX2YCEOpaKkw=; b=cQRG/J8wdaeIQa1d78ZU1v82b4g3H1w2EnWaY/CpFqWTbdNYoY4OjkLDuT/d1JKiqD BZO1NxsAwKo7LmfcyZA6zG4QTX75+laq6A0w8/6Ofx1xKfE1HVqh0D6XIN59O7vfEitv 8PUIe5fSiibdNIL4cHZfRJ8LqTCcjdGzi5EmOK+VtPe/1dHgh0Nias4XzXVJ5jOxFCMS TNyYOMuyseQuRppiv8JCvnmus0kwTGNV53LXWryDDtBkkseOtqN+aLskoVfKfenpedoJ hTtFjF4J+UYTQ0LNF834xnFsv+vRsyPzQFp1/D+GJj7WcosPr8cGgY1qAzBrQq/jvdw4 gV/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=p0rmZulySAyfFLpagWq7oUqjHQLoiP7mX2YCEOpaKkw=; b=jjTH76XLHs7aoteGwWJXbd8p8+lfqLQLFLHQcjek8awLSLdz1ELDbWq5vvelj6+DYc KWe00zTPbeKIK6/weIWV0VpkSVD44nxSrglQUIRIyGwLZH9AGMLHMYYTXvblRmAkcB9T ADekhEiWnI7RiIhkqE0t8OgwynIjLOF5m11gt+d//MVGE/+ItHUyEXwSgDZRdcbvg5AK sjBiLIFEngiR8oOlZNmSYQJSLFBuLjy7QfXxP3XhaUkWb3iCoAdhk7P+Kp8ZpqD9ePZc pd/UFUYwYyWDL8lS6bfSjDb7pzrdVDIwbems7sMfs6SoGU/YvL9CKXgMSo04FZvB48iz qjgQ== X-Gm-Message-State: APjAAAWy2WO0tlf2OIVggzDIFTeTDICDPQYfyWYcINonP5gZ2nH1syNh MdfG4iizluMhxbP06iq3jV/TTLHbz6w= X-Received: by 2002:a63:c442:: with SMTP id m2mr93954716pgg.286.1564163508292; Fri, 26 Jul 2019 10:51:48 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.47 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:27 -0700 Message-Id: <20190726175032.6769-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH 62/67] target/arm: Convert T16, load (literal) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 42 ++---------------------------------------- target/arm/t16.decode | 4 ++++ 2 files changed, 6 insertions(+), 40 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index f9022fe65c..f1cab437e0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1011,14 +1011,6 @@ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_ld##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_ld##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo); \ } #define DO_GEN_ST(SUFF, OPC) \ @@ -1026,14 +1018,6 @@ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \ TCGv_i32 a32, int index) \ { \ gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \ -} \ -static inline void gen_aa32_st##SUFF##_iss(DisasContext *s, \ - TCGv_i32 val, \ - TCGv_i32 a32, int index, \ - ISSInfo issinfo) \ -{ \ - gen_aa32_st##SUFF(s, val, a32, index); \ - disas_set_da_iss(s, OPC, issinfo | ISSIsWrite); \ } static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val) @@ -1082,9 +1066,7 @@ static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data); } -DO_GEN_LD(8s, MO_SB) DO_GEN_LD(8u, MO_UB) -DO_GEN_LD(16s, MO_SW) DO_GEN_LD(16u, MO_UW) DO_GEN_LD(32u, MO_UL) DO_GEN_ST(8, MO_UB) @@ -10657,11 +10639,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, rd; + uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; - TCGv_i32 addr; if (disas_t16(s, insn)) { return; @@ -10671,26 +10652,7 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) switch (insn >> 12) { case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */ case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - goto illegal_op; - case 4: - if (insn & (1 << 11)) { - rd = (insn >> 8) & 7; - /* load pc-relative. Bit 1 of PC is ignored. */ - addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4); - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s), - rd | ISSIs16Bit); - tcg_temp_free_i32(addr); - store_reg(s, rd, tmp); - break; - } - - /* - * - Data-processing (two low registers), in decodetree - * - data processing extended, branch and exchange, in decodetree - */ - goto illegal_op; - + case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */ case 5: /* load/store register offset, in decodetree */ case 6: /* load/store word immediate offset, in decodetree */ case 7: /* load/store byte immediate offset, in decodetree */ diff --git a/target/arm/t16.decode b/target/arm/t16.decode index ddffd073a2..c18d146a84 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -113,6 +113,10 @@ LDRH_ri 10001 ..... ... ... @ldst_ri_2 STR_ri 10010 ... ........ @ldst_spec_i rn=13 LDR_ri 10011 ... ........ @ldst_spec_i rn=13 +# Load (PC-relative) + +LDR_ri 01001 ... ........ @ldst_spec_i rn=15 + # Add PC/SP (immediate) ADR 10100 rd:3 ........ imm=%imm8_0x4 From patchwork Fri Jul 26 17:50:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169922 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp368084ilk; Fri, 26 Jul 2019 11:04:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqye1ewrp4/zQwTC47TMNVrAcOXgyNtSsfcmvEb/Q6fc1evd9CSgN3ltrt/WZpUemIK7NIoY X-Received: by 2002:aa7:c486:: with SMTP id m6mr84248611edq.298.1564164278671; Fri, 26 Jul 2019 11:04:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164278; cv=none; d=google.com; s=arc-20160816; b=mAQKUCQFdWV8sxIW9mV7USK4WazGrHbjURqmOQQ8kWIwy9amaxSvFbivTjmDeko8+P ysVMSS9Y0TaEoHOPJPGFsYRcxdAw/itgNEhCsHUCUQ78O/YyEm2Vi4GihFp5HUDk1YTT zBg3T1DUuGFO+jPmzpkwLEElnoEyNuxslmcXkuiAmGKL/xe0dIcDahwa6V9xczqjBWgh LB7ssUVN1TBD5HCvszbudzgyd/8tyq70Z3/jNgyOKqyhNee295JY2Uh0ZhSVTKtZT0Hw upzMymcatvgNAQxkp0cysW8AtNXUq+c2sXS69SZUZ0MA/MPCO3TuUpXGENPW12GfyV8N Oxbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=gABFvmxEEZWzDc6dniX7CF33hz80PTh6Y9giG8B8d38=; b=DaudJsA1IXbu/+Hbuyq5+aKUCxNd8qszvw1C+OW6L6H/FsUJx3Qr6EZp8au1alCcua nY599wLS95cFJ5bhznhIZZwgb1tXt2pvVdzZHcRqMwII2Yijy3ifv5pDpXnVeCTROmPI Zdg5AbzWjvljty2Li0w/cN83MWbJ2iK9loVdyBv9K+PYH0Koq5f+HADSDPmpcrVVtUpb kTvNwfjSZIusSeaHxZlBfwdMdHpOyET/hqg0YDE9QT4XuY8XeDQEOpoBZ1hrAo5jQNGF 4reTVwlM0OQ4y2j4E8s27mk0iMqzK0GJpLwuK8FlgjMra4+Ko/q6eLFB/pTPO1f7vIqN XFPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qWfwn4vf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g53si11915327edc.53.2019.07.26.11.04.38 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:04:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qWfwn4vf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4a5-0006OC-6U for patch@linaro.org; Fri, 26 Jul 2019 14:04:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59750) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nx-0007Xo-0J for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nu-0001PT-4Z for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:03 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:45515) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nt-00018d-T0 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:02 -0400 Received: by mail-pf1-x42c.google.com with SMTP id r1so24850680pfq.12 for ; Fri, 26 Jul 2019 10:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=gABFvmxEEZWzDc6dniX7CF33hz80PTh6Y9giG8B8d38=; b=qWfwn4vfzazKS9Qyhqn1gfCLRpl+xcxrytxChp9uBWzRbPB5/opktJPXVxkR+DovQV +Rbmq5T3LVD8szGFnO2/bLdiim6hk2L6ZEYt9sujp+9dGixaS+12xmyCPzumlrlRz2dO 8qNeiPUzn/1Ufuc/AEi4zeO5YFHcZwn0E6EBFSkmucRNvGr/NY45c8IYLMq+6/RkYiZu iASZPLDLsGBC+/odukewMUBxulL7ShkJ7Cm/aGvI41PeMO7Afhgmc0WlJYygAF+2uxZf /E/vxM8auJYL5LSXWJQ1yA4GP/Gmq45MbwUkMSbOyYcaBCemPgbtUt6gF5xuO/t2pTMT eBPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=gABFvmxEEZWzDc6dniX7CF33hz80PTh6Y9giG8B8d38=; b=SXgzISkKJXw5UvjT/EL22kbBqE/yCu7nlBPE7SnwG1ItptKd61yzxHFQdJqzYbh+K0 IT4MI1NN1vAvZ9lC46hz2R9usiocsGt8sD5r7gcjMMH2G7+JGYPoqE9Hqi/i0gRJzspn hlo9PuVvj+kt1ZkYxLyhwBjGjs7hZ0KxJTZA4+skxKthBoJ1tlxeld+RZn1rA86T505S /PUtHQ5JSmGaS12WcZCfSHBEavIrK08UDzS2OMYoiI9yeXVQn4ehe0shUmUAF/bK/E9h 3CuX9LbEDtOGpOJV2MgRlHaDnjnx2eCHxA7YEOAL+rQi2CL0xm6jGAOgeupqhGcvFx9m zurA== X-Gm-Message-State: APjAAAVn7WyIl/jjk+RRzNu0g23sexN5ZOgyw7TZp9kppj+XdAhy7EsH splz8K6KBjXTeous55kULwqGchamNB4= X-Received: by 2002:a17:90a:cb87:: with SMTP id a7mr102378917pju.130.1564163509596; Fri, 26 Jul 2019 10:51:49 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.48 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:28 -0700 Message-Id: <20190726175032.6769-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42c Subject: [Qemu-devel] [PATCH 63/67] target/arm: Convert T16, Unconditional branch X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 9 ++------- target/arm/t16.decode | 6 ++++++ 2 files changed, 8 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index f1cab437e0..480515a0a9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10639,7 +10639,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val; int32_t offset; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -10683,12 +10682,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) gen_bx(s, tmp); break; } - /* unconditional branch */ - val = s->pc_read; - offset = ((int32_t)insn << 21) >> 21; - val += offset << 1; - gen_jmp(s, val); - break; + /* unconditional branch, in decodetree */ + goto illegal_op; case 15: /* thumb_insn_is_16bit() ensures we can't get here for diff --git a/target/arm/t16.decode b/target/arm/t16.decode index c18d146a84..457f2f4178 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -268,3 +268,9 @@ LDM 1011 110 ......... \ SVC 1101 1111 imm:8 &i B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2 } + +# Unconditional Branch + +%imm11_0x2 0:s11 !function=times_2 + +B 11100 ........... &i imm=%imm11_0x2 From patchwork Fri Jul 26 17:50:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169910 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp363667ilk; Fri, 26 Jul 2019 11:01:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqzK8uyPSWWZmySEejaySM4LiklTa6l9ylxkCuAgRKNZJYwJbYiDs4YlNFhR7nKp7zr38kEq X-Received: by 2002:a37:8081:: with SMTP id b123mr63863797qkd.62.1564164079991; Fri, 26 Jul 2019 11:01:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164079; cv=none; d=google.com; s=arc-20160816; b=VAjFydYpSqNE5bcSWVHVVGbRXxsqr8X92Xvm1KN1jwCTkMrfCxtF3ayxDN0YF3+a/+ M/LxcI4KY0es82S30GId7TatJ2JplriqWFlCuytwRJ5ap44FkRW0Gbvd2n7FVRyih/Le d84yFwHXndvDT703cEwflLp67eHBnfSFrx+ZAcw6zkgpMe8G+L1wuAt5l9eH330XMBk7 Y2/YuF5mzfgcM2+7FdqkkXEaIHcuvz60qWXo3by03rly6AsRH3vaceYKV6OjhRaRLf22 IrW5z2m5rNQRtujZTDAjb/xeHhRjnBGoi7hkKb9mfd9Wtlvk+PVI1tLOKdET31Y+fJ5f DSEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=3dOWwe1vKbsdIWS0nSZCwW1yYPHjDGBihHkemS/ZoSY=; b=w9G42/qt3JkfOTf99jmDkLYrfVsARZshx+lOVhU7J5Olk3UGmR21VwR7Vtl+/8B6Qm N887Pu6UPuI2Yj947xgFVMshVolN6UzKzC5BVo+eanrR7ayEOBqez74whABFXvMSYX+P 9Kz/m3R2vpAcTN4Mz4Dbkd/9ig9eON39XnxV6SNLriwKc+uhRMjLDh4isCUiWXx2Bo4d oFTRmp5y0bESnb5IQJDYy5n5bpB7ZuzDSDgO30imno0pm9Bc7YjylhO3TTKFJ0N41k8p VfXK0U9VhkLO0IOs6PPyqbe/fw07WMqjIshhfevRvG0DM9BN9jNs/Nni5nc9X2B/Q5wg iV/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dyjxBfl6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id z20si34849766qtb.360.2019.07.26.11.01.19 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:01:19 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dyjxBfl6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Wt-0002xm-1K for patch@linaro.org; Fri, 26 Jul 2019 14:01:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59558) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nt-0007K9-3w for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nr-0001IO-IQ for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:00 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]:35665) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nn-00018s-Iu for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:57 -0400 Received: by mail-pf1-x42b.google.com with SMTP id u14so24878698pfn.2 for ; Fri, 26 Jul 2019 10:51:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3dOWwe1vKbsdIWS0nSZCwW1yYPHjDGBihHkemS/ZoSY=; b=dyjxBfl6BToPNY6VUCaToZdn+s3aAJ3ikTyADQR8Az2DKnYBVnzU2dQphCMsyF9HG/ r0Z9VBcJ5us5CMliebrRm1mSwNgv25a+PiwxJD3uostHSQCLPEKqk3SHbX0wGx188awC W4Du//iD6wHfG4KEhfBsK9bijFmA7SYGsG4znsMUEaG0STRCRroeH7ayMz/nD7GQ64Cw 7mmypMsmAQfjwo46JrX8LU6DR3ojdQ+fDiC5P0z7E/Rcl13GQWkKAWue+OK8N4amtoye 4j4V3eIG4ka4mnct1ctgZVybj8rCZ0f0Gsf7DbCNT5xgzjOusEs5SFiy4gQCvMCnglAj cZGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=3dOWwe1vKbsdIWS0nSZCwW1yYPHjDGBihHkemS/ZoSY=; b=ZAxXVh5NFuOlDZt3B8w8EOXTLbA/3Cuql2a8ZySNJZTHkZN0KxatHjq0OA352kKXrU wlPxfceAsmJ4oV5/Vj1Sr+sOiUpdIOFo+bacnFwA2BzMqHMCkNvwef+3kynaieAlBiQe 9Az5LWrms6mXEjthNZHw/3ORCBYizvNFaUQWYlu3veCfopWUSpqSFpCJBLWg9patvoQb Put/IBCYSjtTsYij+YYqRYT9lIsOWUg/cIvBV/iXEoio7teJDBcWxkwuYDscLhvKpNQh iwat5Z/SCdQxdKCD/11LqfRiz/LPJgtrlCty3Xf2aZBJrbL4jd8co1+4wfbn3Z8oNDCh 1+OQ== X-Gm-Message-State: APjAAAUGg1IxNJ43OIlaYYaFMPDXNGDnicUx8GCFfn3lP5orLGcGUmb8 ORvgskz0hv/mHPeHNED+CknRNwKkt10= X-Received: by 2002:a17:90a:37ac:: with SMTP id v41mr94950125pjb.6.1564163510598; Fri, 26 Jul 2019 10:51:50 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.49 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:29 -0700 Message-Id: <20190726175032.6769-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42b Subject: [Qemu-devel] [PATCH 64/67] target/arm: Convert T16, long branches X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 89 +++++++++++++++++++----------------------- target/arm/t16.decode | 3 ++ 2 files changed, 43 insertions(+), 49 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 480515a0a9..a8db6e9280 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10055,6 +10055,44 @@ static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) return true; } +static bool trans_BL_BLX_prefix(DisasContext *s, arg_BL_BLX_prefix *a) +{ + /* + * thumb_insn_is_16bit() ensures we can't get here for + * a Thumb2 CPU, so this must be a thumb1 split BL/BLX. + */ + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_movi_i32(cpu_R[14], s->pc_read + (a->imm << 12)); + return true; +} + +static bool trans_BL_suffix(DisasContext *s, arg_BL_suffix *a) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + tcg_gen_addi_i32(tmp, cpu_R[14], (a->imm << 1) | 1); + tcg_gen_movi_i32(cpu_R[14], s->pc | 1); + gen_bx(s, tmp); + return true; +} + +static bool trans_BLX_suffix(DisasContext *s, arg_BLX_suffix *a) +{ + TCGv_i32 tmp; + + assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); + if (!ENABLE_ARCH_5) { + return false; + } + tmp = tcg_temp_new_i32(); + tcg_gen_addi_i32(tmp, cpu_R[14], a->imm << 1); + tcg_gen_andi_i32(tmp, tmp, -4); + tcg_gen_movi_i32(cpu_R[14], s->pc | 1); + gen_bx(s, tmp); + return true; +} + static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) { TCGv_i32 addr, tmp; @@ -10639,10 +10677,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - int32_t offset; - TCGv_i32 tmp; - TCGv_i32 tmp2; - if (disas_t16(s, insn)) { return; } @@ -10661,53 +10695,10 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) case 11: /* misc, in decodetree */ case 12: /* load/store multiple, in decodetree */ case 13: /* conditional branch or swi, in decodetree */ - goto illegal_op; - case 14: - if (insn & (1 << 11)) { - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX: - * 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF) - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - ARCH(5); - offset = ((insn & 0x7ff) << 1); - tmp = load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); - - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->pc | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - break; - } - /* unconditional branch, in decodetree */ - goto illegal_op; - case 15: - /* thumb_insn_is_16bit() ensures we can't get here for - * a Thumb2 CPU, so this must be a thumb1 split BL/BLX. - */ - assert(!arm_dc_feature(s, ARM_FEATURE_THUMB2)); - - if (insn & (1 << 11)) { - /* 0b1111_1xxx_xxxx_xxxx : BL suffix */ - offset = ((insn & 0x7ff) << 1) | 1; - tmp = load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, offset); - - tmp2 = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp2, s->pc | 1); - store_reg(s, 14, tmp2); - gen_bx(s, tmp); - } else { - /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */ - uint32_t uoffset = ((int32_t)insn << 21) >> 9; - - tcg_gen_movi_i32(cpu_R[14], s->pc_read + uoffset); - } - break; + /* branches, in decodetree */ + goto illegal_op; } return; illegal_op: diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 457f2f4178..105218882a 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -274,3 +274,6 @@ LDM 1011 110 ......... \ %imm11_0x2 0:s11 !function=times_2 B 11100 ........... &i imm=%imm11_0x2 +BLX_suffix 11101 imm:11 &i +BL_BLX_prefix 11110 imm:s11 &i +BL_suffix 11111 imm:11 &i From patchwork Fri Jul 26 17:50:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169912 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp364622ilk; Fri, 26 Jul 2019 11:02:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqyGr17szOPmqwZpwiAV2ccXzoc3PjxdPYAEPt3lfaciK+r98pkJKA/oF8XWTQlWxtGFX5lb X-Received: by 2002:a17:906:e2c2:: with SMTP id gr2mr74249502ejb.284.1564164120884; Fri, 26 Jul 2019 11:02:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164120; cv=none; d=google.com; s=arc-20160816; b=sv8o4wZR4+cbv74ZK/wGFkhOZRMxz0dlX2Q0q5vPx77xSTGUiKGBcqfJl3hWzPkisV KOnUATDMpM5okrI3LYFNuwvyRKXvCDmRFyfgeLvNXoznnEyg90VQr96WIndx6Ys1wWgd arJAu6/NmCTSBbTQs3Qeghf+ckp8ToUe6DX9SSvJqDWaW0sd68m+lBlpxYdqFAapKuo1 7hCRlIR3VCb9p3nzmFsuHu8Wcg2cdPAM3XURjTPMPkUPVngUsHpsb2sN5lNte1yKGly2 8Eg089dmHIt9MfIet4GIhxsPJcdQLXg6Zla3DFc2Z1pNRAJQNu9T0fNpqWmCcLyRq/kU lxNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=GfZoaF1PKj02fL5gI7kwlJOVMtCnQ9O6XVR81E0meI8=; b=TVRBOnSHTzZXGdBGpFYJbk8GonlwsyXuB8tvSZtZyLgkUwY0qEiJhnYL8q5BuqzZTv s0AGymX3Yy4Ooo4sTbHNzSy1CXBkbHsVsK9OCZaUDGMV3/bL0biplzHNY/fi8Ipw46kl e0cWRjSUHdeLuTMjkdFVHdSe+oSumEJ8iaqjtid7AD/8di66J45XM/emAgvm/LMnMKK3 91MOaNS2cKr7Ot29//LPjcRMvaDTrq8wNzmDuuxwtfQb99JOHFDo9PqA3axDocqL8bhu 6iCLWReVMq55ne6+rJHNxfunSbLzQp583/KvdfYF8oNXgP7jSKEAEKmMZlbXpSX5P7Ce x7eg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kcq8eWPV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f15si14063610edf.297.2019.07.26.11.02.00 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:02:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kcq8eWPV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4XW-0006M3-Kh for patch@linaro.org; Fri, 26 Jul 2019 14:01:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59599) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nu-0007Ms-Op for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Nr-0001Hz-HP for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:00 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:34806) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nn-0001AI-IY for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:51:56 -0400 Received: by mail-pg1-x541.google.com with SMTP id n9so18890225pgc.1 for ; Fri, 26 Jul 2019 10:51:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GfZoaF1PKj02fL5gI7kwlJOVMtCnQ9O6XVR81E0meI8=; b=kcq8eWPVuVdKWR6yW1d/KHcSAnOLyfw8o2AyH2g3hGs0sb1lxn1A0JA91+kpnwI0CS qppjr3UV2eo+kWSsTPm3Igg9+XENJRT6omZwXtoPzln8YbZFwhvmXqShJtOs+gWUxCbI HJL5Qwclub7i4zjhVYFcV/RnUvyw7xJ7RNyViifawnoL+u/kaoFsODr9lQYgnxIZr9Ee yGVhmt9i+LHlYGxDHjym7zm4dxuy5Fbnac9Pgng2GmSzyrkwS3bmj3hDq13G9v6VJfFp K49ZJeCEvLowoCCkYWtjZwPgnRGejqDJGD6/7r4MYQgJ/f9VNIQrxVniWbS1iD2tJ7qK MLTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GfZoaF1PKj02fL5gI7kwlJOVMtCnQ9O6XVR81E0meI8=; b=eHDBEObfeFUkmJ5lHLlEIhd2uI88aTn9xDKoGAJ3B9/unYqyITTDCw5W6XNZNpOD9L kAiaoTzJbn/PofZNui7zF1oPBM0Pt0XKELsDzvdulcuGN343EU6NG1GQ7PeFo5N3iDuv cF7CVA/Ftm4kR0eCRySg4BfgjzZbj4vIFdk2Hp8bn6BmBukE8SgoIhjRTJ8tdVcm9sVr nmPAjdcLWWQuVpMl98LRKJq8hMbY49bLDx/3iojpabHMW69VeHz1Tyx8fOhXVFszMvSi wz6+ehVBZIcd5XxQtNMyGxy3nXsZTdFn5y1I78YiIbR1qk/yhktSFCjdk8M7wn46mSUm B++A== X-Gm-Message-State: APjAAAWt1u3eRVuHv3bGPnyuIiJrn8Mydctz0/Q6x69zYBOGS3gGfc1x JG3Mjs3jYF/VoTrfdcy/qOhlvDTZiX0= X-Received: by 2002:aa7:8218:: with SMTP id k24mr22628587pfi.221.1564163511718; Fri, 26 Jul 2019 10:51:51 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.50 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:30 -0700 Message-Id: <20190726175032.6769-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 65/67] target/arm: Clean up disas_thumb_insn X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now that everything is converted, remove the rest of the legacy decode. Signed-off-by: Richard Henderson --- target/arm/translate.c | 27 ++------------------------- 1 file changed, 2 insertions(+), 25 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index a8db6e9280..c2b8b86fd2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10677,32 +10677,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - if (disas_t16(s, insn)) { - return; + if (!disas_t16(s, insn)) { + gen_illegal_op(s); } - /* fall back to legacy decoder */ - - switch (insn >> 12) { - case 0: case 1: /* add/sub (3reg, 2reg imm), shift imm; in decodetree */ - case 2: case 3: /* add, sub, cmp, mov (reg, imm), in decodetree */ - case 4: /* ldr lit, data proc (2reg), data proc ext, bx; in decodetree */ - case 5: /* load/store register offset, in decodetree */ - case 6: /* load/store word immediate offset, in decodetree */ - case 7: /* load/store byte immediate offset, in decodetree */ - case 8: /* load/store halfword immediate offset, in decodetree */ - case 9: /* load/store from stack, in decodetree */ - case 10: /* add PC/SP (immediate), in decodetree */ - case 11: /* misc, in decodetree */ - case 12: /* load/store multiple, in decodetree */ - case 13: /* conditional branch or swi, in decodetree */ - case 14: - case 15: - /* branches, in decodetree */ - goto illegal_op; - } - return; -illegal_op: - gen_illegal_op(s); } static bool insn_crosses_page(CPUARMState *env, DisasContext *s) From patchwork Fri Jul 26 17:50:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169929 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp371042ilk; Fri, 26 Jul 2019 11:06:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqxnahsltMKrgEDal0DPfKiaVwn/qgjAnUabfvP8XPwi4dUA9MAosxVhOBOPtpNgZj7bNFGT X-Received: by 2002:a17:906:838a:: with SMTP id p10mr71713644ejx.237.1564164418577; Fri, 26 Jul 2019 11:06:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164418; cv=none; d=google.com; s=arc-20160816; b=efZVcxo4c8t91HPE4hZcPnPOXqe9+XF2xkNqmO16mK+Xxoc6YhZNXTqtQkCvJu8MaV CKNopht1ao7PzHSH9k7GoGj/l6tbHvrAggqUyOTHYI+11rBtiSzN5B6CfNOwH1fERzAU 8f9ZMcMUjmI/JTuhPwEp9nZAW0Zf9fKSdRbXBBhP4KspAn3yPiC6MnwCatLDVz2ZqdNd /aMq0ASKBc8Ls8X+xruq9az7inrBj/I/iQYwoY0chKz7/BhPmbOseSVOuSILSsQ+sK2a 2VzUVImMaePpjkGPAkAAYJUJQe3wM7FV0uTcmJgVNA11mQFMQETrJkVw0SdnFp+lLWCR 9usQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=CpCg1eLgsmeNBuXSBMKJnkt//MK4VjGPzn8vhxLPYT4=; b=e47TpUSwA1q95W3tdjy1HKWBeQq/CohGTQOeQuul26zB+VPkB2uL7hz0jVVL0/8fWI Yw5fB+B8cRq5TXXtZhld2ssOlQP3+VhBEE9HN/15Rs910PdTYDh1Sqf79YRFAnPXTUqU udunLZcXDHwhExBIyCSgayBxmthqguxxfX4N89Wu9P/jZZdfzMnUww+iki1N7fCGme5b 90jbh57PQvqI8oVSIEM2n7uxxu+FkpYt/JeAT/O58qyTP86nCKTtjcj7KanyWxt3UN0g gtXkz2ES6pGpA3d+0YZhynCfUA5qrjnRf5oZchv9ME8so7GTv8yIxCbzuvXmp49eQMME H5/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QNMjh3w8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o25si11294960ejd.215.2019.07.26.11.06.58 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:06:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=QNMjh3w8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42836 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4cJ-0006nm-8C for patch@linaro.org; Fri, 26 Jul 2019 14:06:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60006) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4OB-0008Rw-60 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4O8-0001hG-35 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:17 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:37885) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nq-0001CM-Hi for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:14 -0400 Received: by mail-pg1-x541.google.com with SMTP id i70so14372259pgd.4 for ; Fri, 26 Jul 2019 10:51:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CpCg1eLgsmeNBuXSBMKJnkt//MK4VjGPzn8vhxLPYT4=; b=QNMjh3w8HR3G0vPDqCVV1OMzSsqKpgoqDpwu/LU8YFxUHa4kQaBqG+uioKMmdFuWTW hUBr+I48dQ/YYVR456EjtWF2zNlNT8VLGcf9QrtuHWcBuF2EbEY4P0nQBeNAdkggrqQq wJWebg3i8Om8Dwz/kvHaNOxP0BTWKXZYrCmoE3yu048+k0r30HiBPgDAijS3cLbOsd3d k+V6qSRB/dw8ouyY2nlW2DWrY7gLnrtd/JcSNmovAib/syRZHuLk0e6/VFcH1vJxDMmX egcROH59F0gd6umRJZGVnBjb+ChYll7z8GlRFmNLM0TnSCVi12YhfPlr9SqizaMv+ZA1 StGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CpCg1eLgsmeNBuXSBMKJnkt//MK4VjGPzn8vhxLPYT4=; b=pleFhxQa9+WIKrkJNLAI6HdllS0ZUvdKarik4fiiiAQa0Eyh4o3J2QZUjl6KEnNRcX cz+VWwFsGzgZOeOQRiHhE4mdnfPbG5SR5osVdihDjfWkd9Ug18g70nE6ke5JfSJd1OaB zjIGsvOssW2HJkpc68P/QeW9NC6En7JW0MjAGO3XQDlFUHjAlaIufDMc2IniEeXki/7Y qpSNcq6FAzkMNfF26k5ZyYyTkeCA12Bj+btozQ81NvlwUg+ey/tic56o+4u2LR+s9n5h vSext6UunTDeUi5Wg4V6nUF3o3CEb+IKRrJhQ6HQEKCbcX4gmjgmexdidaydkV3mI7lp 1LPg== X-Gm-Message-State: APjAAAURK1xe1Sr7qNdM0MBgu/m/zKm7+opkXFB8RhFIM1ZlTmN9T6Rh KtSWp2q9B1U5Ana7WcEd890oRyto0aU= X-Received: by 2002:a17:90a:ac11:: with SMTP id o17mr100551920pjq.134.1564163512683; Fri, 26 Jul 2019 10:51:52 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.51 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:31 -0700 Message-Id: <20190726175032.6769-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH 66/67] target/arm: Move singlestep check from gen_jmp to gen_goto_tb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We miss quite a number of single-step events by having the check in the wrong place. Signed-off-by: Richard Henderson --- target/arm/translate.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index c2b8b86fd2..9ae9b23823 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2740,7 +2740,10 @@ static void gen_goto_ptr(void) */ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) { - if (use_goto_tb(s, dest)) { + if (unlikely(is_singlestepping(s))) { + gen_set_pc_im(s, dest); + gen_singlestep_exception(s); + } else if (use_goto_tb(s, dest)) { tcg_gen_goto_tb(n); gen_set_pc_im(s, dest); tcg_gen_exit_tb(s->base.tb, n); @@ -2751,16 +2754,9 @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest) s->base.is_jmp = DISAS_NORETURN; } -static inline void gen_jmp (DisasContext *s, uint32_t dest) +static inline void gen_jmp(DisasContext *s, uint32_t dest) { - if (unlikely(is_singlestepping(s))) { - /* An indirect jump so that we still trigger the debug exception. */ - if (s->thumb) - dest |= 1; - gen_bx_im(s, dest); - } else { - gen_goto_tb(s, 0, dest); - } + gen_goto_tb(s, 0, dest); } static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y) From patchwork Fri Jul 26 17:50:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 169917 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp366342ilk; Fri, 26 Jul 2019 11:03:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqymrNzCeLKIcTPFNOlianIM/uxS81vChXcqHQVvByq/nA71sFiovorRu80qe0w+kLL5ImaN X-Received: by 2002:a50:f49a:: with SMTP id s26mr84426756edm.191.1564164194529; Fri, 26 Jul 2019 11:03:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564164194; cv=none; d=google.com; s=arc-20160816; b=LWCxXUVZi4jjF5wrou2/tdaf90tsC3SpBmONYVmgwNyITelZSXbwamKHtfmaFpcG5s 6hZlLq7n8bHJVM2a2hJWf8/N5f1kgk7iCAPZFgfePyF8UTW2rhiwTRBnqbvLoD+7QkfF AYTVPm/HUZeIkZ6e7h4brIuxPPeDIE3sdyk2UsqlDmURC5eDdxcOeBRl0GL29NLEMSSR 7sHygW4h6VF3FTwYP1p4FhPQLPBp+BlpC6aYX9opcRKyPz91g2nE/4F6RAuqMAcgWwbh /uuSxuSdSKOkyiE/sbqYni4FcGHlnOvq8HNdM9O5T3hPgKmNKjk0WmY4s/TrohPvSKLf qhTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ggteB4WINk5mb6nMpXwNHzA9GUmr46ovcnkhvcdKD8k=; b=o2XLTbT26OMw8aKyo2LkEYo2ZbBby1QgQ+7Ozv1okibUxCk3dOEH2rex4U9JSRJ+BZ Vyv3twpGxy8Vt5Z1iXwWcV6vhciT725lELvjC1VZ7uvQmeBeqTRR/2cse41qGHdhGShU PRHcxID/7VSnF929d1non/oVXEKg3EY7Unv5gYI2O/A6HS2OuFpIwIqvnWuBal7mvRaG RvH7WUIXPvjTZpbCauXwQVOztmnUWZwb6AwCVqvxLn85He4oo8zfEhm8ozjoLYohGmyR sJCXN5O34qX8BUsZagfvB4OC2DEQ4M94HuoBFRX6v/JssCFsU+NgNuxwbMaQMS/dcBDc biIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Buc8ocpp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p50si909324eda.338.2019.07.26.11.03.14 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 26 Jul 2019 11:03:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Buc8ocpp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Yi-0001Z5-LE for patch@linaro.org; Fri, 26 Jul 2019 14:03:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59713) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hr4Nw-0007Uk-85 for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hr4Ns-0001KU-6G for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:03 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:38145) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hr4Nr-0001DD-UO for qemu-devel@nongnu.org; Fri, 26 Jul 2019 13:52:00 -0400 Received: by mail-pl1-x644.google.com with SMTP id az7so25002530plb.5 for ; Fri, 26 Jul 2019 10:51:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ggteB4WINk5mb6nMpXwNHzA9GUmr46ovcnkhvcdKD8k=; b=Buc8ocppTVZ8/0vu8O9BFAEvpnSUEBT08+KVgqmbrllPtLH1/hU4ckz56I+Esxjxzg ZrY1cZ1dtZy+SNx4EIMeD9lCtj7pi6eEXSm9O+X2OdhOjDeuUhzON26nzdm9Rc6fc95t DzB2/sDs4SW116bRspRHF8ezfsdjhAckAJC222a692ZTS6IFWNGQPra2PNGMlA3oFfrE 5RNSApyaWBqw0+1W4FdTGMB3cFgqvYt4K+E2C/l0Uyc3H8cSgo7tJ0eViMPMpnn02Ads E8jR2HBPTkhA9hF2NJKgf5tUeaIBNEWROJBIjaeVtcaEQblh7lnmyCmiIBbgrcwpUYLY /sow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ggteB4WINk5mb6nMpXwNHzA9GUmr46ovcnkhvcdKD8k=; b=EP6PvzJTwbygR8uGcGtOI01It01iQFPKiNQcprJguYStCtIiI+uAXEKr/Mq4BuBzYr r2vrKExc3lf1sQ/rP7gsV7tUmaxfD0PLiTyLnzJsu8jBUd6ON9Qh30rzc51mvLY0euxC rOSge61jlqTjz/jlB0fapB0+z0bt6dbVv6Rh/wmmp+wbyhUkHqf1gVKeHjMWvjTSihau PxcuWwh9ZBKc8ekKv5npUPnD+pUaSj8SWIgDlKUWMoIWVs7pA3GcwHF3/Nec6gnUH11y d/Q4i/awra12Ry5MZxZ9HMMif/+NSuKK2h7rBEcgwuHag8qmehD9R3t6QqUm6Lntv3dh cMkA== X-Gm-Message-State: APjAAAVrKIwxEn5+5biYy0d8/I7DMtrgX/BUJ3KpChhWpYJOueN2bFrw 3qfoL1q4tEhIoObUVqLcFOySR+L5m2g= X-Received: by 2002:a17:902:bd94:: with SMTP id q20mr87126516pls.307.1564163513826; Fri, 26 Jul 2019 10:51:53 -0700 (PDT) Received: from localhost.localdomain (97-126-117-207.tukw.qwest.net. [97.126.117.207]) by smtp.gmail.com with ESMTPSA id o24sm104287919pfp.135.2019.07.26.10.51.52 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 26 Jul 2019 10:51:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 26 Jul 2019 10:50:32 -0700 Message-Id: <20190726175032.6769-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190726175032.6769-1-richard.henderson@linaro.org> References: <20190726175032.6769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH 67/67] target/arm: Merge gen_bx_im into trans_BLX_i X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the only remaining use of gen_bx_im. Simplify, since we know the destination mode is changing. Use gen_jmp for the actual branch. Signed-off-by: Richard Henderson --- target/arm/translate.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) -- 2.17.1 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9ae9b23823..dc51e1e622 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -813,21 +813,6 @@ static inline void gen_set_pc_im(DisasContext *s, target_ulong val) tcg_gen_movi_i32(cpu_R[15], val); } -/* Set PC and Thumb state from an immediate address. */ -static inline void gen_bx_im(DisasContext *s, uint32_t addr) -{ - TCGv_i32 tmp; - - s->base.is_jmp = DISAS_JUMP; - if (s->thumb != (addr & 1)) { - tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, addr & 1); - tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb)); - tcg_temp_free_i32(tmp); - } - tcg_gen_movi_i32(cpu_R[15], addr & ~1); -} - /* Set PC and Thumb state from var. var is marked as dead. */ static inline void gen_bx(DisasContext *s, TCGv_i32 var) { @@ -10042,12 +10027,18 @@ static bool trans_BL(DisasContext *s, arg_i *a) static bool trans_BLX_i(DisasContext *s, arg_BLX_i *a) { + TCGv_i32 tmp; + /* For A32, ARCH(5) is checked near the start of the uncond block. */ if (s->thumb && (a->imm & 2)) { return false; } tcg_gen_movi_i32(cpu_R[14], s->pc | s->thumb); - gen_bx_im(s, (s->pc_read & ~3) + a->imm + !s->thumb); + tmp = tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, !s->thumb); + tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb)); + tcg_temp_free_i32(tmp); + gen_jmp(s, (s->pc_read & ~3) + a->imm); return true; }