From patchwork Wed Jun 7 21:27:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 103321 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp2140853qgd; Wed, 7 Jun 2017 14:28:26 -0700 (PDT) X-Received: by 10.99.142.201 with SMTP id k192mr19509530pge.161.1496870906463; Wed, 07 Jun 2017 14:28:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496870906; cv=none; d=google.com; s=arc-20160816; b=GHtzuiGOYEYaDkTT3iVqEZ2njgFJMmZyfdCSMF6+sEqbI0q/21HbZpCdDG91hkK61F QzG8ACZW+u90o7djaIjaEsBS8RZsAjLg/1/WIdiGiD/nQIO0W/LmaJlLep6NQKeX9L/U +03ZvqgCot3LfBVeQF5bXRkFEl6hLscAMNZOh+hXE+2dNUmZciQyZTUng9EGhhiuWP5D whaHJimOGNZFqRMaVXyBRt5TkraicSrrlVGO6qSzrtxoWLvPjLx2r9K78vVpa8HVmat7 iIVgSPa71YABt9RIoCtMcA7kZP8cTrVPhY9bKner4sdY6MlKg095Ug84yfaeWSiAo7Df y9Rg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=aVTJ48/u7ZpUT0RTfUXtOlxprJs9Mm8D2JRDBzG+hxw=; b=cdTJtvkmkIeP2pV1Admc+AJdqK6IQLvB5AFGdoBuxnBKlUpBSj4pqg/oEaAyZTWYr6 fSKlBijKzgIRptaOLPQb3vNwtVehBR3u1xnJOpOpYdaOxNvHAHVilZNyCAflpoZuyg3J cCYkuKh6MTRJTGLmmoKiNlQUgUImsp+5UJujZL9PMKs9KzPCkGOo/tm8DEpJaXcvWe0l 2lMy1RYkvJnComs58B9IA4lZ2JAGXh890LzOBmo7ZKyJl/CftlhVHYFO62HcaNfSOicn FQlPebflof9nKSzQ+hL5dx9b160FSBHojk2FEWt2/aak4raLjMLPQ3XYuGngd8BcN9qP PBew== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h29si2737033pfa.290.2017.06.07.14.28.26; Wed, 07 Jun 2017 14:28:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751505AbdFGV2Z (ORCPT + 7 others); Wed, 7 Jun 2017 17:28:25 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:62921 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751460AbdFGV2Y (ORCPT ); Wed, 7 Jun 2017 17:28:24 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v57LRWuR029821; Wed, 7 Jun 2017 16:27:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1496870852; bh=1iCIXb75oKeQRapxphKQviFjYcpH1gUgxoEICpAHD3s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rEt5UBgV5EVYUbb6Vvperr2geoqgGi/gMXYPpa14nMdcN/0U1fS82MCZfahiDkFdz 1CT/em+vC8FmAZl46Wp3TnVMuKmvDBPkigrPrAQ6PRg8XGlVXuXeG/kqq2V1Fp0Yvs r7tB5z4dirGkawvGkBr1U90aV8hBGlzJUJozBwRQ= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRWee010064; Wed, 7 Jun 2017 16:27:32 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 7 Jun 2017 16:27:32 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRWB9017174; Wed, 7 Jun 2017 16:27:32 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v57LRW307102; Wed, 7 Jun 2017 16:27:32 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Tero Kristo , Lokesh Vutla , Subhajit Paul , , , , Suman Anna Subject: [PATCH 1/6] ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:25 -0500 Message-ID: <20170607212730.33002-2-s-anna@ti.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> References: <20170607212730.33002-1-s-anna@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers M4 & M5 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP100 values as defined in the OMAP4430 ES2.x Public TRM vAP, section "3.6.3.8.7 DPLL_IVA Preferred Settings". The DPLL locked frequency is 1862.4 MHz (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap44xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index 9573b37fbaa7..9cb205b87835 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -357,6 +357,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <931200000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { @@ -374,6 +376,8 @@ reg = <0x01b8>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m4x2_ck>; + assigned-clock-rates = <465600000>; }; dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { @@ -385,6 +389,8 @@ reg = <0x01bc>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m5x2_ck>; + assigned-clock-rates = <266100000>; }; dpll_mpu_ck: dpll_mpu_ck@160 { From patchwork Wed Jun 7 21:27:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 103317 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp2140733qgd; Wed, 7 Jun 2017 14:28:04 -0700 (PDT) X-Received: by 10.99.63.140 with SMTP id m134mr29701752pga.170.1496870883891; Wed, 07 Jun 2017 14:28:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496870883; cv=none; d=google.com; s=arc-20160816; b=XQ5MLaDK1yLrUa3T7zKdmM5JXBcthKP/m6suBX8VCaWxyV3T/W9qrbH/8c+DAei8rY 57j4DcWBaRE8w0rbM01UPYPsXuGXbutzKMcFIPPUCdaDjFf7pcpknxieKw8Ao6rFUWHA sFkxYUc5mgukCIyQp80udrIarzxvwrp206UemPXuwbBnYJJYml/NpmAHfviDNChVqovX zt8CN5QJG3akZhFoga6YmWz+iX5Xans9zacSya3/BYtgqr12eTZ/FC6pZygwV6hZpD/j fMDzQwUuAhSg92t2dkpq5o7vtlFb7bFwT6PNEgb0wCZ238v0UQ6U4V4zznW3XpK1T317 prjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=0vhcFLP/WnkN4uMu07Itnwgl2OsgFvv20l6MymtZTQs=; b=xg0rBclPhfgoiHhRl0ZY+za2DNyjZug53Ajky0+uw5L+BrcBkABA05N33KJ7gGZdd0 HEHn+yMqJiU81NsnSOyJ6OpRUxDy3K4GoaSl/1Xvz/MrHy91+Dogb5PxliApEkpaPTPO E1/YPSXCpIWeLg+lyVqpKjpPfFlN9p0B64Tk3897yAKpzPVG5gYnIw1strZgyhwUEb5v b5LEiynwr5elbsQ+fB1UrH+habzot1464BNGIXBQBZKG91t4+VVAAVm01S/t4AOiU8wB ZwN/yvPOEYG7gh5FWIwADr+/7qpDAzgEJvM5kIuAheADaLp9fL8weRj9VjnWY1AcRJu3 r2gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h29si2737033pfa.290.2017.06.07.14.28.03; Wed, 07 Jun 2017 14:28:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751512AbdFGV2B (ORCPT + 7 others); Wed, 7 Jun 2017 17:28:01 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:62916 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751072AbdFGV2A (ORCPT ); Wed, 7 Jun 2017 17:28:00 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v57LRXuE029825; Wed, 7 Jun 2017 16:27:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1496870853; bh=Mp1Ede1L7EwcH5dAdStEhXeB5DKOyp6bywpIUdF/glo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mdtWqcN2hn5FIyDqnJxwblxRtXvWlyqhwB862WeNBd7x3IzcQh2TOTzJEURx+nkR+ s8b7CWJwnlDTc5H2TNmE13Uw9RnJCBL0T+A6Anv8xum2LtWT8cXb0nR55HyKb9NaA0 SVxWKkmRVtsQwyHxhPAfcSqFXGwo3PTNPS0jX+DE= Received: from DLEE70.ent.ti.com (dlemailx.itg.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRXjr010072; Wed, 7 Jun 2017 16:27:33 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Wed, 7 Jun 2017 16:27:32 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRWVx025575; Wed, 7 Jun 2017 16:27:32 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v57LRW307106; Wed, 7 Jun 2017 16:27:32 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Tero Kristo , Lokesh Vutla , Subhajit Paul , , , , Suman Anna Subject: [PATCH 2/6] ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:26 -0500 Message-ID: <20170607212730.33002-3-s-anna@ti.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> References: <20170607212730.33002-1-s-anna@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IVA DPLL is not an essential DPLL for the functionality of a bootloader and is usually not configured (e.g. older u-boots configure it only if CONFIG_SYS_CLOCKS_ENABLE_ALL is enabled and u-boots newer than 2014.01 do not even have an option), and this results in incorrect operating frequencies when trying to use a DSP or IVAHD, whose root clocks are derived from this DPLL. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset values of the dividers H11 & H12 (functional clocks for DSP and IVAHD respectively) are identical to each other, but are different at each OPP. The reset values also do not match a specific OPP. So, the derived output clocks from the IVA DPLL have to be initialized as well to avoid initializing these divider outputs to incorrect frequencies. The clock rates are chosen based on the OPP_NOM values as defined in the OMAP5432 SR2.0 Data Manual Book vK, section 5.2.3.5 "DPLL_IVA Preferred Settings". The recommended maximum DPLL locked frequency is 2330 MHz for OPP_NOM (value for DPLL_IVA_X2_CLK), so the dpll_iva_ck clock rate used is half of this value. The value 465.92 MHz is used instead of 465.9 MHz for dpll_iva_h11x2_ck so that proper divider value can be calculated. Signed-off-by: Suman Anna --- arch/arm/boot/dts/omap54xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 4899c2359d0a..529193442620 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -315,6 +315,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_x2_ck: dpll_iva_x2_ck { @@ -330,6 +332,8 @@ ti,max-div = <63>; reg = <0x01b8>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h11x2_ck>; + assigned-clock-rates = <465920000>; }; dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { @@ -339,6 +343,8 @@ ti,max-div = <63>; reg = <0x01bc>; ti,index-starts-at-one; + assigned-clocks = <&dpll_iva_h12x2_ck>; + assigned-clock-rates = <388300000>; }; mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { From patchwork Wed Jun 7 21:27:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 103322 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp2140899qgd; Wed, 7 Jun 2017 14:28:36 -0700 (PDT) X-Received: by 10.99.168.6 with SMTP id o6mr33638304pgf.104.1496870916368; Wed, 07 Jun 2017 14:28:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496870916; cv=none; d=google.com; s=arc-20160816; b=sqfdXFPS1VSj6qyoNhEtn75qDUKuyGY9KWHiDWpkoAu8CNBPUF/mo1HjNITKFfMdke G1/KLkppXuI3h9imLMaqnX75oQrghy1Jj4Lo3brT2iHhd8t4kcNJeG4SSN5IImsDmMEc KO0SUr1Y2OvXDkgD05EFluyLYcgXWuudMmZSy3Z+jDlUotgiFyTvKVfJp4iVmam66ylO EBTa1u5j02BqyIYQ+3uRzsetFoL59aiAuJ4Y5mDpdupg88rbhxdH7Ut288ZI/N7HeYjn Zm+9wDuGPPOQtwDn7Y4PRkhqOsu2m1fD4aA8DOr9lxARxF+MWhdL0+rvjpUtGkuNpwRV tIUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=haX1+YcAefV6sBkzAThAjPKOCyMO0j1I8De/6xREWvs=; b=N/ZC8PVRcihcgpNLqSmem8NwKkS5EPQvaWvGQoL9/nFZ7WpqnXn2LS8jlXIdiPOPRB VmjLtSCC44ytkzRWnf0LbLnPdThD4b7nT8WK0YgN/JREMEGng9xdK0gQVbml3eyYUxi8 DghriU8lNHAo8+MBnlAHsMAN7MW7GPyjSwYBUZHG3yoD83OxiDGstFArbSDGJVTyV4z4 e5cLzU40fbhIYVO/w+16qYsaGZKeQkF9FLL9iY08x1aDkvGrqYq+SOSY+SU5cYCPdMLX hvdwSeQqYdg7qsWYVomH2FQtSBH4Js4E9dYNGH1mgQn18jYptKRVL8EKPf90qRxj6S9S TO+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h29si2737033pfa.290.2017.06.07.14.28.36; Wed, 07 Jun 2017 14:28:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751541AbdFGV2f (ORCPT + 7 others); Wed, 7 Jun 2017 17:28:35 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:64590 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751469AbdFGV2e (ORCPT ); Wed, 7 Jun 2017 17:28:34 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v57LRcDK007827; Wed, 7 Jun 2017 16:27:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1496870858; bh=/YisFtzfZ/XRMuKJwUSKz97zX3ABEZrh2bBGnTPBgGU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=f6yQ8/KuMO3eAa5votZUkRhiPUT82cHQEKl+KXg0Lgcc2rrk7hVQkSGA3onZTsWji hd7I/OFfINpguhPduDcEmgYzCz9jd8PFKSWuyN1KW1MOk7JQvED8mZzDFrxB6P68a0 Ge1qW77FdC4o+VNP4U8qdnF9eAmh/50MwrPEnWRE= Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRX5M010069; Wed, 7 Jun 2017 16:27:33 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.3.294.0; Wed, 7 Jun 2017 16:27:32 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRWoP014167; Wed, 7 Jun 2017 16:27:32 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v57LRW307110; Wed, 7 Jun 2017 16:27:32 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Tero Kristo , Lokesh Vutla , Subhajit Paul , , , , Suman Anna Subject: [PATCH 3/6] ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL Date: Wed, 7 Jun 2017 16:27:27 -0500 Message-ID: <20170607212730.33002-4-s-anna@ti.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> References: <20170607212730.33002-1-s-anna@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IPU1 functional clock is actually the output of a mux clock, ipu1_gfclk_mux. The mux clock is sourced by default from the DPLL_ABE_X2_CLK, and this results in a rather odd clock frequency (361 MHz) for the IPU1 functional clock on platforms where ABE_DPLL is configured properly. Reconfigure the mux clock to be sourced from CORE_IPU_ISS_BOOST_CLK (dpll_core_h22x2_ck), so that both the IPU1 and IPU2 are running from the same clock and clocked at the same nominal frequency of 425 MHz. This also ensures that IPU1 functional clock is always configured properly and becomes independent of the state of the ABE DPLL on all boards. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 ++ 1 file changed, 2 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3330738e4c6e..cfaf27215901 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -791,6 +791,8 @@ clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; ti,bit-shift = <24>; reg = <0x0520>; + assigned-clocks = <&ipu1_gfclk_mux>; + assigned-clock-parents = <&dpll_core_h22x2_ck>; }; mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 { From patchwork Wed Jun 7 21:27:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 103319 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp2140763qgd; Wed, 7 Jun 2017 14:28:08 -0700 (PDT) X-Received: by 10.84.208.236 with SMTP id c41mr29180497plj.95.1496870888285; Wed, 07 Jun 2017 14:28:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496870888; cv=none; d=google.com; s=arc-20160816; b=xVQ5ubSQN96IluF1ogyNBmHlAevxn6ra+G9fxXlpQAe5zO9Owl0mbeB36twHgvMwOy AwCJDoaYW3TlHYOrR30ETTaglagQHEmOp/1n0ngIkBq1CY017VCnRwGaA4LFFXoewEIe E9CleMVJ/LKk1n5ib/ewnjaXoTekzVpg5NNhOT0z8mkUPxy9g1/NJJd17IFFp1uslelR +xq6JnLzk/CoritJBFG+6R9hITckbAG8XidHSPnOWvdh79DyAcUsbPnp3TzqqmiC6gYw Fnnrt9iP0EFjypajgKVEuIyzD5MHuAkN6RubjfpW7DzwDMJGx8OpzHcQK7GokBwmtscN ICZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=9WH4qwSPdOYPAa3Fn8ZVT2XgGrld0UioADuG5r1KcN0=; b=iQslb9mGVecnrbQTc/hwFUCx2Xemu+xO9gfbOxYXnUccz8MQUgyTOwhZ2VXV0DlPyP ObuhxSM5fBU2GFMZ7uRKeIv1YnEE+++XLi/y0C9KafBNQVxm3O4Pad8OcqZuLcNJrsGj rAaFjkqpjkmhIiviiMUoBJLexfjPAGA8s6U6XeEMqsh0uxwKk6pvnLhycppcvvr8cju3 z3zuVXDtM+p4nCUU/heXLwo1IofvvFPw2TC+fRwVtCMjDJ81zYwOmlAAiXvKIwawDAl9 aH50lL0ojdrGdboJgqksWcCLy9IOsQQEv4vtoTd0Kr3BJqgcXjaeUUnNO7zbRs0Sxx/p fvfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h29si2737033pfa.290.2017.06.07.14.28.08; Wed, 07 Jun 2017 14:28:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751506AbdFGV2G (ORCPT + 7 others); Wed, 7 Jun 2017 17:28:06 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:62917 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751299AbdFGV2A (ORCPT ); Wed, 7 Jun 2017 17:28:00 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v57LRXtK029829; Wed, 7 Jun 2017 16:27:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1496870853; bh=XskRseTFiiumbEDOCRVE9DhX/AJS8JoW7FNcwV+XO2g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Fyvxj2OFWdm/I0mrVqMIRpdCBpcqr0iE0GbUNsat6oZnp/e6q6xVPEv1HeVJ1qOBX Zo44B+DYSKTO/d2+S7GOldUQcXOQ34GTkb/6qENJWsVIZkfclyvEcI5Bxr7Rv9heTk Rukew4vGdXBiY0zLg+pWWi+/cdlfbRMxKwjhuE/4= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRXOa003998; Wed, 7 Jun 2017 16:27:33 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 7 Jun 2017 16:27:32 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRWBL015971; Wed, 7 Jun 2017 16:27:33 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v57LRW307114; Wed, 7 Jun 2017 16:27:32 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Tero Kristo , Lokesh Vutla , Subhajit Paul , , , , Suman Anna Subject: [PATCH 4/6] ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:28 -0500 Message-ID: <20170607212730.33002-5-s-anna@ti.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> References: <20170607212730.33002-1-s-anna@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The DSP DPLL is a new DPLL compared to previous OMAP generations and supplies the root clocks for the DSP processors, as well as a mux input source for EVE sub-system (on applicable SoCs). This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the DSP DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The DSP DPLL provides two output clocks, DSP_GFCLK and EVE_GCLK. The desired rate for DSP_GFCLK is 600 MHz (same as DSP DPLL CLKOUT frequency), and is currently auto set due to the desired M2 divider value being the same as reset value for the locked frequency of 600 MHz. The EVE_GCLK however is required to be 400 MHz, so set the dpll_dsp_m3x2_ck's rate explicitly so that the divider is set properly. The dpll_dsp_m2_ck rate is also set explicitly to not rely on any implicit matching divider reset values to the locked DPLL frequency. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 1200 MHz, so the dpll_dsp_ck clock rate used is half of this value. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index cfaf27215901..8a82490035d9 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -338,6 +338,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; + assigned-clocks = <&dpll_dsp_ck>; + assigned-clock-rates = <600000000>; }; dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { @@ -349,6 +351,8 @@ reg = <0x0244>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m2_ck>; + assigned-clock-rates = <600000000>; }; iva_dpll_hs_clk_div: iva_dpll_hs_clk_div { @@ -659,6 +663,8 @@ reg = <0x0248>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_dsp_m3x2_ck>; + assigned-clock-rates = <400000000>; }; dpll_gmac_x2_ck: dpll_gmac_x2_ck { From patchwork Wed Jun 7 21:27:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 103320 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp2140789qgd; Wed, 7 Jun 2017 14:28:13 -0700 (PDT) X-Received: by 10.99.100.135 with SMTP id y129mr4842199pgb.5.1496870893639; Wed, 07 Jun 2017 14:28:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496870893; cv=none; d=google.com; s=arc-20160816; b=QnPnpl+o23UpewyrL4Kh/ur8JxG6Waktwdl7a/AviPmjS1/gjJce/vs0HyEEh0eP+e W9/EnRbM9qvpZ1+eBDawB2HkjvKZFgtX1eAZtdCW2zOvLcTSuF690Q9GjZaUM8kmnHUB +jllKaooXjqve5dWZBsLzvH4nKPmi4DSBlT7qmqpjkaCxOXrqtLvmOdQJK0PKqavnr88 Qv1Tf6fLLdHGQ7U5AuyjKve1geVrZWpbOjZoM1HikwysyiykERfZZVE9oiMgTBdVz7hS MyGx7QJyXYiZ9FWXvSgCTnhpelBhLnGZrB6l2YwCSLvcocbS6Qle3po6FsO3beCBSGuv jgrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=ayl2iEjQqAzNgd1hJm5MT8rv7i0wLX8bPQknUN0B61I=; b=Km1UrN5I4kIa//jwuBI8JIHXpI9TqeFt1Dv5PG7teJ/qCho5+BIkuXpd8iRchByllI Caw7DvDjOsVS3O/cJArkQKeQfCxhXcrieEzYMVbZ/VTlM8zW8JpYtkbyor7yCcHwbXjz DKWqTSxsh1stQYh7Sz05ccfHPQms7UIueN5GRzoxGZrlbYm83lrXKRmtTWst5HqaYhbH 94gQYMBJEkjUS3GXDgyLyVxfMRKqNNMf6oRGt0DUT7U79rzkdeQunJg1MgpOmihmyWCX QJplzQW4oMfUGqHiJJJv3iqksv3Co8GZ1ufCVX0SClKtVDjnUtbPm5KfTywgWFO2V/Ed NoSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h29si2737033pfa.290.2017.06.07.14.28.13; Wed, 07 Jun 2017 14:28:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751540AbdFGV2M (ORCPT + 7 others); Wed, 7 Jun 2017 17:28:12 -0400 Received: from lelnx193.ext.ti.com ([198.47.27.77]:62918 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751527AbdFGV2L (ORCPT ); Wed, 7 Jun 2017 17:28:11 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v57LRXAU029833; Wed, 7 Jun 2017 16:27:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1496870853; bh=IqmstxIOnBTVQHj36jWgPcSrbwkKzwPPW8moivTOA9I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OE/E0gFyejzxBPPp3Ml2TVCp1rNd1N4oYbGt8O7mQxOes8UNsoNOYtBJVbxCYoUqF QWCMfb60Ou5PCqDHDnFd2AoyxJ0i8lnTZfmf2c/maILDMi0bTjoxJQNBXfgIA+JB1w xh5QvAJAtHDhxgSnxcfyS2akkRKcY0VoJ6tS1swU= Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRXQc004001; Wed, 7 Jun 2017 16:27:33 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.294.0; Wed, 7 Jun 2017 16:27:33 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRXE2025580; Wed, 7 Jun 2017 16:27:33 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v57LRX307118; Wed, 7 Jun 2017 16:27:33 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Tero Kristo , Lokesh Vutla , Subhajit Paul , , , , Suman Anna Subject: [PATCH 5/6] ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates Date: Wed, 7 Jun 2017 16:27:29 -0500 Message-ID: <20170607212730.33002-6-s-anna@ti.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> References: <20170607212730.33002-1-s-anna@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The IVA DPLL in DRA7xx provides the output clocks for only the IVAHD subsystem in DRA7xx as compared to previous OMAP generations when it provided the clocks for both DSP and IVAHD subsystems. This DPLL is currently not configured by older bootloaders. Use the DT standard properties "assigned-clocks" and "assigned-clock-rates" to set the IVA DPLL clock rate and the rates for its derivative clocks at boot time to properly initialize/lock this DPLL and be independent of the bootloader version. Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. The reset value of the divider M2 (that supplies the IVA_GFLCK, the functional clock for the IVAHD subsystem) does not match a specific OPP. So, the derived output clock from this IVA DPLL has to be initialized as well to avoid initializing these divider outputs to an incorrect frequencies. The OPP_NOM clock frequencies are defined in the AM572x SR2.0 Data Sheet vB, section 5.5.2 "Voltage And Core Clock Specifications". The clock rates are chosen based on these OPP_NOM values and defined as per a DRA7xx PLL spec document. The DPLL locked frequency is 2300 MHz, so the dpll_iva_ck clock rate used is half of this value. The value for the divider clock, dpll_iva_m2_ck, has to be set to 388.333334 MHz or more for the divider clk logic to compute the appropriate divider value for OPP_NOM. Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 4 ++++ 1 file changed, 4 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 8a82490035d9..76e2b7478141 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -376,6 +376,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; + assigned-clocks = <&dpll_iva_ck>; + assigned-clock-rates = <1165000000>; }; dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { @@ -387,6 +389,8 @@ reg = <0x01b0>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_iva_m2_ck>; + assigned-clock-rates = <388333334>; }; iva_dclk: iva_dclk { From patchwork Wed Jun 7 21:27:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 103318 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp2140745qgd; Wed, 7 Jun 2017 14:28:05 -0700 (PDT) X-Received: by 10.99.117.81 with SMTP id f17mr21043711pgn.117.1496870885605; Wed, 07 Jun 2017 14:28:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496870885; cv=none; d=google.com; s=arc-20160816; b=Dn/PpHsapmQgGN1SLF85PQ1tpTd4VlUjeZlCV39sRFanADQPlEacng8yq+JVa6SRr9 EhtV+id+Sr57o+tsF3I39+SWh+VQeoR2eLVRXk6NMh+QkuDUaH43vhwxGmzOGAogTt8G 98nenGu9idXQp5wTPYbOxz/NWuoN7wNYIYY3n0N8a1j95HeHy5lIdNcDYk+Za20jMvX5 AHfvADWqDBHje8BUsDxJcURkfYyQWAQrop/zs88wVvWZKAyZwmeuVtTQtTqlUz+JvcXv 6guAr++PgRdmIXsMJup6KYdWrNyS/niGreFxvPqcI8IfdWYkul9W2w1hBDYt+feTWW/M iEBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=tmIgDENf0EKEwc2UjAwfQPQn137kRwx8b8hUjRcO75Y=; b=MTGWHWkNCjtdfyO17fIjyG24xtJjGHfwTMsoM2L7/PrwudNKfv1yRPxFg/UKavBbw/ ghGuwzp2iUeG+HraqVDW5MbFAxndnC9MzhvjI6YWrkvmytiY0187yKIc21G8X0qF4WKL Q+1i8uXBKQQmGHUIK1F4JE7ciyT6PfSpASEIAjv5M9oG5Ph8uu4X9aqN0DpgmLDbLId3 /VbJ79YgKdjLRylIZl8RIG0fGFKlSXmrenTLRSMFytbDyB093d2xhEWYgXAAaL45JSXV N/bebc3a+818GO7lbcHNsbSpLkLK/9O5YqlHS08NBmhNuxZEUGgoCJuOFxgAOlmNr2ml HzMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h29si2737033pfa.290.2017.06.07.14.28.05; Wed, 07 Jun 2017 14:28:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751517AbdFGV2D (ORCPT + 7 others); Wed, 7 Jun 2017 17:28:03 -0400 Received: from fllnx210.ext.ti.com ([198.47.19.17]:11378 "EHLO fllnx210.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751072AbdFGV2C (ORCPT ); Wed, 7 Jun 2017 17:28:02 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v57LRY9V014177; Wed, 7 Jun 2017 16:27:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1496870854; bh=oGDtYc4VfVfF0bI9BdDjpYGT2PF95ch3t7wgBWW0JRE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=w/fQQbpAbDPPqPWfeF39rCK5aCG9EB2Q3rDKv1h1bOPhzVUWWtt3sYnglFW7+wEwx DhJm/4b4UBOxhp5X502PRoRX/BZZEnCw7jpYHphDagY/Gse2U/sNB+2RjeVsCqRl0Y MxnR7SQjqtRxOU2wYgrux7zPW2fOI824OYRu7zrs= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRY30010080; Wed, 7 Jun 2017 16:27:34 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Wed, 7 Jun 2017 16:27:33 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v57LRXxS014170; Wed, 7 Jun 2017 16:27:33 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.167]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id v57LRX307122; Wed, 7 Jun 2017 16:27:33 -0500 (CDT) From: Suman Anna To: Tony Lindgren CC: Tero Kristo , Lokesh Vutla , Subhajit Paul , , , , Suman Anna Subject: [PATCH 6/6] ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocks Date: Wed, 7 Jun 2017 16:27:30 -0500 Message-ID: <20170607212730.33002-7-s-anna@ti.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20170607212730.33002-1-s-anna@ti.com> References: <20170607212730.33002-1-s-anna@ti.com> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Subhajit Paul The GPU has two functional clocks - GPU_CORE_GCLK and GPU_HYD_GCLK. Both of these are mux clocks and are derived from the DPLL_CORE H14 output clock CORE_GPU_CLK by default. These clocks can also be be derived from DPLL_PER or DPLL_GPU. The GPU DPLL provides the output clocks primarily for the GPU. Configuring the GPU for different OPP clock frequencies is easier to achieve when using the DPLL_GPU rather than the other two DPLLs due to: 1. minimal affect on any other output clocks from these DPLLs 2. may require an impossible post-divider values on existing DPLLs without affecting other clocks. So, switch the GPU functional clocks to be sourced from GPU DPLL by default. This is done using the DT standard properties "assigned-clocks" and "assigned-clock-parents". Newer u-boots (from 2017.01 onwards) reuse and can update these properties to choose an appropriate one-time fixed OPP configuration as all the required ABB/AVS setup is performed within the bootloader. Note that there is no DVFS supported for any of the non-MPU domains. The DPLL will automatically transition into a low-power stop mode when the associated output clocks are not utilized or gated automatically. This patch also sets the initial values for the DPLL_GPU outputs. These values are chosen based on the OPP_NOM values defined as per recommendation from design team. The DPLL locked frequency is kept at 1277 MHz, so that the value for the divider clock, dpll_gpu_m2_ck, can be set to 425.67 MHz for OPP_NOM. Signed-off-by: Subhajit Paul [s-anna@ti.com: revise patch description] Signed-off-by: Suman Anna --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.12.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 76e2b7478141..cf229dfabf61 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -414,6 +414,8 @@ compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; + assigned-clocks = <&dpll_gpu_ck>; + assigned-clock-rates = <1277000000>; }; dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { @@ -425,6 +427,8 @@ reg = <0x02e8>; ti,index-starts-at-one; ti,invert-autoidle-bit; + assigned-clocks = <&dpll_gpu_m2_ck>; + assigned-clock-rates = <425666667>; }; dpll_core_m2_ck: dpll_core_m2_ck@130 { @@ -1760,6 +1764,8 @@ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <24>; reg = <0x1220>; + assigned-clocks = <&gpu_core_gclk_mux>; + assigned-clock-parents = <&dpll_gpu_m2_ck>; }; gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { @@ -1768,6 +1774,8 @@ clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; ti,bit-shift = <26>; reg = <0x1220>; + assigned-clocks = <&gpu_hyd_gclk_mux>; + assigned-clock-parents = <&dpll_gpu_m2_ck>; }; l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {