From patchwork Wed Sep 20 22:23:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 725038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4155CD13D3 for ; Wed, 20 Sep 2023 22:24:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229614AbjITWYH (ORCPT ); Wed, 20 Sep 2023 18:24:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229592AbjITWYG (ORCPT ); Wed, 20 Sep 2023 18:24:06 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9054197 for ; Wed, 20 Sep 2023 15:23:52 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-502fd1e1dd8so620064e87.1 for ; Wed, 20 Sep 2023 15:23:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695248631; x=1695853431; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+hF1P02ld7wbeNQyU0l4vMbS0kxuoLz56i7vh22oekU=; b=pekvhvRm2nAeOEhRPpFYIyJ4uauLjaLnSl+6VyFguEG9LU73WAugob/Nwnjr9eU4mi Kb+4neR7ZSduQjneO+iCpmDeX+7R8kaunMq0B//SpeqkMHQ7FI/AQy9EKqY6KBZYR0Iy rYPsVFBUA/ncH2MGsDM2t1L1lb5G0CVhx8akiPOXD5qmZnlUA2y6lsBMVKLcNNte92Yl L55q+XCvFHVceM5GknuF3JuV40o34/wUqQAaK6LgrOfaH/7QeonQxNzf2WG3dChOWug6 EX27V3H9ZdnG2KkL+Pw035cZZLufPf7f2xnIW65m3waky0JlVhxeXsgMakhyzvDslmes /5iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695248631; x=1695853431; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+hF1P02ld7wbeNQyU0l4vMbS0kxuoLz56i7vh22oekU=; b=bwtql+mHgaD6nvm4652sDsIjgOncZrWymH1GviCixOv4Yfu1L2OTEkgswfcStMRG52 hvE2Pa8JrRXFE4jEdSK/OQSa5FkuPW3evmHtPfuZ79cR0EjFrtahtPsUua66u01qqmrV Kat42z4rA7Rt9WqoZaD5oXXsjUAeG17ovm9aiz6JHuQNbnjeimTNihRTP14tYkb0UQnB WBbULmNtJpFQe0l+8JxTr26w7Sc4Id/47JBA9aKx3ZjwSzOKs6puzOrBwwJCrrU5GAme j0iG7w9Y7/zf89sj0XcEd8T+QA4gaRCzgRJsdidu/t4sgKe3+RizufzIccLx6QG4eL0D e2hA== X-Gm-Message-State: AOJu0Yxdi64po/s9uju2stKzcS6NuBwL7xf06RmlnJY8RryM/A/FYLTM aAclAV0ftZPJHyVNP5SWNHE9bw== X-Google-Smtp-Source: AGHT+IEZJGrEPB6Ohe0IImVhtr4rOFsci1rM/dBFgJNHI1rqUiaIuxPUVtgJp9An4uh6Dlh1g2JO4w== X-Received: by 2002:ac2:5e65:0:b0:503:555:4000 with SMTP id a5-20020ac25e65000000b0050305554000mr3150963lfr.25.1695248631051; Wed, 20 Sep 2023 15:23:51 -0700 (PDT) Received: from [192.168.1.2] (c-05d8225c.014-348-6c756e10.bbcust.telenor.se. [92.34.216.5]) by smtp.gmail.com with ESMTPSA id u14-20020ac2518e000000b004fe0fead9e2sm14557lfi.165.2023.09.20.15.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 15:23:50 -0700 (PDT) From: Linus Walleij Date: Thu, 21 Sep 2023 00:23:45 +0200 Subject: [PATCH 1/2] gpio: Rewrite IXP4xx GPIO bindings in schema MIME-Version: 1.0 Message-Id: <20230921-ixp4xx-gpio-clocks-v1-1-574942bf944a@linaro.org> References: <20230921-ixp4xx-gpio-clocks-v1-0-574942bf944a@linaro.org> In-Reply-To: <20230921-ixp4xx-gpio-clocks-v1-0-574942bf944a@linaro.org> To: Linus Walleij , Imre Kaloz , Krzysztof Halasa , Bartosz Golaszewski , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This rewrites the IXP4xx GPIO bindings to use YAML schema, and adds two new properties to enable fixed clock output on pins 14 and 15. Signed-off-by: Linus Walleij --- .../devicetree/bindings/gpio/intel,ixp4xx-gpio.txt | 38 ------------ .../bindings/gpio/intel,ixp4xx-gpio.yaml | 70 ++++++++++++++++++++++ MAINTAINERS | 2 +- 3 files changed, 71 insertions(+), 39 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt deleted file mode 100644 index 8dc41ed99685..000000000000 --- a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt +++ /dev/null @@ -1,38 +0,0 @@ -Intel IXP4xx XScale Networking Processors GPIO - -This GPIO controller is found in the Intel IXP4xx processors. -It supports 16 GPIO lines. - -The interrupt portions of the GPIO controller is hierarchical: -the synchronous edge detector is part of the GPIO block, but the -actual enabling/disabling of the interrupt line is done in the -main IXP4xx interrupt controller which has a 1:1 mapping for -the first 12 GPIO lines to 12 system interrupts. - -The remaining 4 GPIO lines can not be used for receiving -interrupts. - -The interrupt parent of this GPIO controller must be the -IXP4xx interrupt controller. - -Required properties: - -- compatible : Should be - "intel,ixp4xx-gpio" -- reg : Should contain registers location and length -- gpio-controller : marks this as a GPIO controller -- #gpio-cells : Should be 2, see gpio/gpio.txt -- interrupt-controller : marks this as an interrupt controller -- #interrupt-cells : a standard two-cell interrupt, see - interrupt-controller/interrupts.txt - -Example: - -gpio0: gpio@c8004000 { - compatible = "intel,ixp4xx-gpio"; - reg = <0xc8004000 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml new file mode 100644 index 000000000000..bb1fc393bd8c --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/intel,ixp4xx-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel IXP4xx XScale Networking Processors GPIO Controller + +description: This GPIO controller is found in the Intel IXP4xx + processors. It supports 16 GPIO lines. + The interrupt portions of the GPIO controller is hierarchical. + The synchronous edge detector is part of the GPIO block, but the + actual enabling/disabling of the interrupt line is done in the + main IXP4xx interrupt controller which has a 1-to-1 mapping for + the first 12 GPIO lines to 12 system interrupts. + The remaining 4 GPIO lines can not be used for receiving + interrupts. + The interrupt parent of this GPIO controller must be the + IXP4xx interrupt controller. + GPIO 14 and 15 can be used as clock outputs rather than GPIO, + and this can be enabled by a special flag. + +maintainers: + - Linus Walleij + +properties: + compatible: + const: intel,ixp4xx-gpio + + reg: + maxItems: 1 + + gpio-controller: true + "#gpio-cells": + const: 2 + + interrupt-controller: true + "#interrupt-cells": + const: 2 + + intel,ixp4xx-gpio14-clkout: + description: If defined, enables clock output on GPIO 14 + instead of GPIO. + type: boolean + + intel,ixp4xx-gpio15-clkout: + description: If defined, enables clock output on GPIO 15 + instead of GPIO. + type: boolean + +required: + - compatible + - reg + - "#gpio-cells" + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + #include + gpio@c8004000 { + compatible = "intel,ixp4xx-gpio"; + reg = <0xc8004000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 90f13281d297..4e216887eb76 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2215,7 +2215,7 @@ M: Krzysztof Halasa L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml -F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.txt +F: Documentation/devicetree/bindings/gpio/intel,ixp4xx-gpio.yaml F: Documentation/devicetree/bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml F: Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion* F: Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml From patchwork Wed Sep 20 22:23:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 724727 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75A76C2FC0C for ; Wed, 20 Sep 2023 22:24:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229611AbjITWYI (ORCPT ); Wed, 20 Sep 2023 18:24:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229509AbjITWYG (ORCPT ); Wed, 20 Sep 2023 18:24:06 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDA66D8 for ; Wed, 20 Sep 2023 15:23:53 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-50307acd445so634414e87.0 for ; Wed, 20 Sep 2023 15:23:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1695248632; x=1695853432; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vLjkgT3erisd8thNh77YSEgF45UAom1/3ug+bR94eRg=; b=cdxhTM4FOMFbeN1O2M6wuRnVUDnPudDGmykJjGY1R7O8d8nHolmlCgIUpib+oFTPpG HQPtyqzFp/t/mkAGqXrIv+RPTU+VEanlTLyy2oH5fPBjrNx1UnWbHqGcv+XLY75w+wbH uFB/x+78qRbluGVRddOSURw+pDR4VeRgEVrAYYSwwJ3CMLDZ4I730IBwme7Dv5r/+2yd PkKcVJyBEtJg9jgn2GHnNpMsfMAZk6Ngnm8LxYAM1Hv6jhCOJigrKrsjdsrZaks03piy yWgQsJV6DacoN9FLmCV00BS5sztpJ0KyXQYo0TEcYtoZQXR+XRqJ/guxcRnCYhLKTn6L snmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695248632; x=1695853432; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vLjkgT3erisd8thNh77YSEgF45UAom1/3ug+bR94eRg=; b=J5z9UzAWxcseUuQFS18ooPmkLBAAJRsZ5Krw3rW6z0OQhyWzeiOile5+O6u1G19cac d8trFXlbiKVLCS59Ljp6zlfWZBLimJEf3iKGOTRuJIgPZg5BDGpqYdudmZnhXdcsdYi8 g1bpk9T6lipbWRX9fyNC6aHa1ATkBjQY2ID4+kmNH6aIyDXrUuPva7JaGtMHgn6Zt59K lw7//1SRoNP0fjoShNkyy3mF5M7rkABYoaiEXJGE0h8VvLE8Olagjoy3D8rPEKThO3lX KSJdKX5uFJN+AwWGhHeSZhcQFtnac28/tB+U4GNUgLJzTbrvE5w6B4vilwj6EV2/8TDf x8KQ== X-Gm-Message-State: AOJu0YzROF1RZvZtikp1s5qjEq0eFkwobOSsAszEfIloFz+pddkepNeB GuEUQIVB6znAsCZONPY7XOGdGAWfcqp+TI9dhS8= X-Google-Smtp-Source: AGHT+IFH1+VG7sJVN2LpzTzfZwbtQcp/ITUJsCKlrEFwWrMWXLwatBlfdkhi+mqAWOgOpqVxBMjZbQ== X-Received: by 2002:a05:6512:3f03:b0:500:b8a3:1bf1 with SMTP id y3-20020a0565123f0300b00500b8a31bf1mr4205773lfa.43.1695248632103; Wed, 20 Sep 2023 15:23:52 -0700 (PDT) Received: from [192.168.1.2] (c-05d8225c.014-348-6c756e10.bbcust.telenor.se. [92.34.216.5]) by smtp.gmail.com with ESMTPSA id u14-20020ac2518e000000b004fe0fead9e2sm14557lfi.165.2023.09.20.15.23.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 15:23:51 -0700 (PDT) From: Linus Walleij Date: Thu, 21 Sep 2023 00:23:46 +0200 Subject: [PATCH 2/2] gpio: ixp4xx: Handle clock output on pin 14 and 15 MIME-Version: 1.0 Message-Id: <20230921-ixp4xx-gpio-clocks-v1-2-574942bf944a@linaro.org> References: <20230921-ixp4xx-gpio-clocks-v1-0-574942bf944a@linaro.org> In-Reply-To: <20230921-ixp4xx-gpio-clocks-v1-0-574942bf944a@linaro.org> To: Linus Walleij , Imre Kaloz , Krzysztof Halasa , Bartosz Golaszewski , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Linus Walleij X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This makes it possible to provide basic clock output on pins 14 and 15. The clocks are typically used by random electronics, not modeled in the device tree, so they just need to be provided on request. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ixp4xx.c | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c index dde6cf3a5779..6a9d32b4d0d7 100644 --- a/drivers/gpio/gpio-ixp4xx.c +++ b/drivers/gpio/gpio-ixp4xx.c @@ -38,6 +38,18 @@ #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0) #define IXP4XX_GPIO_STYLE_SIZE 3 +/* + * Clock output control register defines. + */ +#define IXP4XX_GPCLK_CLK0DC_SHIFT 0 +#define IXP4XX_GPCLK_CLK0TC_SHIFT 4 +#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0) +#define IXP4XX_GPCLK_MUX14 BIT(8) +#define IXP4XX_GPCLK_CLK1DC_SHIFT 16 +#define IXP4XX_GPCLK_CLK1TC_SHIFT 20 +#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16) +#define IXP4XX_GPCLK_MUX15 BIT(24) + /** * struct ixp4xx_gpio - IXP4 GPIO state container * @dev: containing device for this instance @@ -202,6 +214,7 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) struct ixp4xx_gpio *g; struct gpio_irq_chip *girq; struct device_node *irq_parent; + u32 val; int ret; g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); @@ -225,13 +238,34 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) } g->fwnode = of_node_to_fwnode(np); + val = __raw_readl(g->base + IXP4XX_REG_GPCLK); /* * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on * specific machines. */ if (of_machine_is_compatible("dlink,dsm-g600-a") || of_machine_is_compatible("iom,nas-100d")) - __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK); + val = 0; + + /* + * Enable clock outputs with default timings of requested clock. + * If you need control over TC and DC, add these to the device + * tree bindings and use them here. + */ + if (of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout")) { + val &= ~IXP4XX_GPCLK_CLK0_MASK; + val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT); + val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT); + val |= IXP4XX_GPCLK_MUX14; + } + + if (of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout")) { + val &= ~IXP4XX_GPCLK_CLK1_MASK; + val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT); + val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT); + val |= IXP4XX_GPCLK_MUX15; + } + __raw_writel(val, g->base + IXP4XX_REG_GPCLK); /* * This is a very special big-endian ARM issue: when the IXP4xx is