From patchwork Mon Sep 18 18:06:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 724318 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6F81CD37B0 for ; Mon, 18 Sep 2023 18:07:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229734AbjIRSHK (ORCPT ); Mon, 18 Sep 2023 14:07:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229674AbjIRSHI (ORCPT ); Mon, 18 Sep 2023 14:07:08 -0400 Received: from mail-pl1-x633.google.com (mail-pl1-x633.google.com [IPv6:2607:f8b0:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7D8F121 for ; Mon, 18 Sep 2023 11:07:01 -0700 (PDT) Received: by mail-pl1-x633.google.com with SMTP id d9443c01a7336-1c337aeefbdso45169855ad.0 for ; Mon, 18 Sep 2023 11:07:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695060421; x=1695665221; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/FxLJCDRi2+AhF6FOTSx+aBMLtSpJjy7MQNwR3R94og=; b=EBj53UQwykWiQU8EeKXFnAZED+FFwvyq0XglEGPU04QSCReR2gRhAkrK27I2V+ERON lgRVORA2U19ayHSDeZj/m+w8N8SSwhsgwYuOJOMFxiq1TeUZgpTtZzLFFmmpiTlfB1SB i75nWmPSsLo9mEeh33LB0RfnoZzxfFA0w6M3Lsqq3YzFAvLKc1a41tj73YpjrLVgzcw4 qwpooow5ZexzXW3INHhQOOIQy+ywa3V2gxKPuajEMCzVOsB9A7IoNLZ+Ef9b+y6zMkfg JX2PI1NYgMnxvgZbIUfYFoBjxNZdBAQ7sADttLIlPdjcqRzK+eqU7Y50NKJmhthQ/4MV ADtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695060421; x=1695665221; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/FxLJCDRi2+AhF6FOTSx+aBMLtSpJjy7MQNwR3R94og=; b=iv6smHCmfu92xproH/Nzrga1/6VBxZgGJ71/gTD3g8sgXB1eXFmn7eDKQovi5luxO2 4qu3r5zEoM1SscWlTPizRfmFgIjC9LOxgaLs4/e+0rsoBiNTtnLUwrM8rIO/JuGHyy7I H1lJgNwHLfsnlAbYMXk+jFe+DQgajdy8pkPxZ1Nvbdubr1OCp5Sdl5FBWfoVINFBEuBN ZBTw4OdRLMCnzkBcTSz3OS+WnUJoUhg+xn+5P/gOly20kNKhXt/6TdY0VsAc51SlphoJ hYbyncTHu7vSHFQ3iTBxZeDTVM4Ov/Ypx1pny8eRtp0AcHcU7tA4C6mXcsftZszaXBZN qQfw== X-Gm-Message-State: AOJu0YyXLtd3vwOdTSg/oGGYhF5dSweMGvE04/Hg8in7FEX2ff0KJ8FQ J3+zMf47g0ykhayEDBtKH2yopg== X-Google-Smtp-Source: AGHT+IFDMbQdNhGOLSD6ilndqDb8cXhJ+CzNk5FP+g+eBNqALQDifdWhN3LJ8Nfabjtn2qCQLRxJug== X-Received: by 2002:a17:903:1247:b0:1c1:ecff:a637 with SMTP id u7-20020a170903124700b001c1ecffa637mr11725339plh.15.1695060421024; Mon, 18 Sep 2023 11:07:01 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id h7-20020a170902704700b001aaf2e8b1eesm8556720plt.248.2023.09.18.11.06.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 11:07:00 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Shuah Khan Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 1/4] RISC-V: KVM: Fix KVM_GET_REG_LIST API for ISA_EXT registers Date: Mon, 18 Sep 2023 23:36:43 +0530 Message-Id: <20230918180646.1398384-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230918180646.1398384-1-apatel@ventanamicro.com> References: <20230918180646.1398384-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org The ISA_EXT registers to enabled/disable ISA extensions for VCPU are always available when underlying host has the corresponding ISA extension. The copy_isa_ext_reg_indices() called by the KVM_GET_REG_LIST API does not align with this expectation so let's fix it. Fixes: 031f9efafc08 ("KVM: riscv: Add KVM_GET_REG_LIST API support") Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/kvm/vcpu_onereg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 1b7e9fa265cb..e7e833ced91b 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -842,7 +842,7 @@ static int copy_isa_ext_reg_indices(const struct kvm_vcpu *vcpu, u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_ISA_EXT | i; isa_ext = kvm_isa_ext_arr[i]; - if (!__riscv_isa_extension_available(vcpu->arch.isa, isa_ext)) + if (!__riscv_isa_extension_available(NULL, isa_ext)) continue; if (uindices) { From patchwork Mon Sep 18 18:06:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 724537 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E218CD37B0 for ; Mon, 18 Sep 2023 18:07:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229851AbjIRSHV (ORCPT ); Mon, 18 Sep 2023 14:07:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229664AbjIRSHM (ORCPT ); Mon, 18 Sep 2023 14:07:12 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D499F182 for ; Mon, 18 Sep 2023 11:07:06 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1bf1935f6c2so34303945ad.1 for ; Mon, 18 Sep 2023 11:07:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695060426; x=1695665226; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5i1eIcDaE0yWa5Js2PwK7z4plrujub6N9pwbwUycwvI=; b=n5WgOqxC/sD9AIOObnUBwHjxeweIK+5IApTUFl+PM6jHKTprvdAK++E38m4gimmR7f HZb9ECsoUHD4pu/JKmGM4tQr6ZyuJ23ZjhC/yVmgavAG+g11RqPcOxFBkFgmak+kNrzo JMaPejqa12loIEdKrjzGqSFXyEzYzEvkzR0f/WUcB0RgaE7iXYBxggQK1XeoL2hHMQwE VsXJ4mvPkxFNNfRLeByXWT+lhPeErl+B1gecBeQLlABs4Bc6jbxYpZ1n6tgpnlxusJCP FZAguQ7fgN9ewS96fIBHgUPwjL9xxaWtFXS4JSRXmUBqgwDIJZvFXiuD9mUUcpQCaC09 aOtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695060426; x=1695665226; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5i1eIcDaE0yWa5Js2PwK7z4plrujub6N9pwbwUycwvI=; b=pyEnvM0arng7notcvj1LIaHGquExnoINPGvaHI3jFmjQp0dFU7fwLka2oI7oyVEBeg oMHE6z89coObg6CmKJ9615eZYxFNRU1GETb88fPito7toxzm8D63gFkweQLAD6PgpE4H 1C4coh2u7e62vQXxdzI3hG9xV5nRcXQZlKqHTvihBliJFapDdqoLCHiOyTWIpebMhQNr 8lWZ9OD8ugNs15LV8M/irSGM93iDNRRYNcLFlqnOioOl2TJuSro9JWoXdHEAkkuAu2KI 5uLLpoVN+69M/huDSHc7lmz4ub7EFcAG1GEi7vNIF6J5YtzsCV38zowLqZ9wytkxXdJ7 p0Vw== X-Gm-Message-State: AOJu0YxqVfdhwWpOLVBbC54NgQd5OBrmZupvt5sz2DVvONov5MtjZu1G q74VYoBoSD8PvbqO9+gKBYFC0Q== X-Google-Smtp-Source: AGHT+IETi36u/uUFnqQ3ujRXaYRtNA+dM21DQd6+dA5XB+7tI1/bMH90xqm0GwYq/Oq3VArOSjGyvA== X-Received: by 2002:a17:903:41cb:b0:1bd:d510:78fb with SMTP id u11-20020a17090341cb00b001bdd51078fbmr529431ple.3.1695060426120; Mon, 18 Sep 2023 11:07:06 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id h7-20020a170902704700b001aaf2e8b1eesm8556720plt.248.2023.09.18.11.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 11:07:05 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Shuah Khan Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 2/4] RISC-V: KVM: Fix riscv_vcpu_get_isa_ext_single() for missing extensions Date: Mon, 18 Sep 2023 23:36:44 +0530 Message-Id: <20230918180646.1398384-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230918180646.1398384-1-apatel@ventanamicro.com> References: <20230918180646.1398384-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org The riscv_vcpu_get_isa_ext_single() should fail with -ENOENT error when corresponding ISA extension is not available on the host. Fixes: e98b1085be79 ("RISC-V: KVM: Factor-out ONE_REG related code to its own source file") Signed-off-by: Anup Patel --- arch/riscv/kvm/vcpu_onereg.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index e7e833ced91b..b7e0e03c69b1 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -460,8 +460,11 @@ static int riscv_vcpu_get_isa_ext_single(struct kvm_vcpu *vcpu, reg_num >= ARRAY_SIZE(kvm_isa_ext_arr)) return -ENOENT; - *reg_val = 0; host_isa_ext = kvm_isa_ext_arr[reg_num]; + if (!__riscv_isa_extension_available(NULL, host_isa_ext)) + return -ENOENT; + + *reg_val = 0; if (__riscv_isa_extension_available(vcpu->arch.isa, host_isa_ext)) *reg_val = 1; /* Mark the given extension as available */ From patchwork Mon Sep 18 18:06:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 724317 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D471CD37B0 for ; Mon, 18 Sep 2023 18:07:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229907AbjIRSHa (ORCPT ); Mon, 18 Sep 2023 14:07:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229639AbjIRSHV (ORCPT ); Mon, 18 Sep 2023 14:07:21 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F18E7FB for ; Mon, 18 Sep 2023 11:07:11 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1c1e3a4a06fso37325495ad.3 for ; Mon, 18 Sep 2023 11:07:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1695060431; x=1695665231; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q85pLC4CWOSNTpoPb1PgDLYa3KXzAnUZu4/HImowDuQ=; b=lCRH4Mm93v6Q29ciEEoh+WGOCMHjvH1RwQsfbsXpiI42eLuAq6T/k2LDZZkUswvZPk pVpI0UE2ZQr4CBDW89VEP8xNSGsGD6k2NbtbnI5e1hZen2nga8fmXzTa5SBQvYvxY2QW ZJpyoEJxiLgSvlIQOpM9uzIxgEC7oaLw3pJMi+QLhekRSydJM94P7exxjknZ+T/KmvLa n9QBzX+kHZJZmkdRQOluIv/0WQskAYKTl9hZw8MgBe2p9/BWvErs+Zk4AcWxmqNdZF1S yGxL3WsDyFb42A7pV8xNJ+/RinIkRMmb2m00OQHSUecXtBHTqLrNpWC2khvgkM9O7eQa Qxuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695060431; x=1695665231; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q85pLC4CWOSNTpoPb1PgDLYa3KXzAnUZu4/HImowDuQ=; b=aMDMVCU+kqASk4DkaXUdPuYM51QcBppqT8R5so1dhjZMQiJf1AdsY8Tzn6c8A7as+A cSeGq+hQAmLozBjjL6FPOBvgxPPusDSwul+tReJ91AAlmuNXLqWh7S0BU+aYkWCmEtKD L7kduAxOwAH9/XdQLjwWUjsCkHYr+HsD2I05WE6vFZ/EVa2khhHRHnIorqZGIOdg+pwp SR1gDyau3/lKRqgQsxWBIydV6tv3BZLwape0MHcMOP1FdpOLJUVLdm9bgUMWBlasjSfw 2kig8ndkdZIM4q03e5NXpsl0MOtEv6jra8yeb2dIzTAYg7C4vzsBfVdJoYc0z6r/d8y6 c2Nw== X-Gm-Message-State: AOJu0Yzbxi9/+yTOj1swbeKz2kNTJKAuTj0mNpEJbg0LXrOVqHfMMd0P Uz2souSgteGAoGKnEGdd/6lXsQ== X-Google-Smtp-Source: AGHT+IEbTMHUWCZuGNdKxBd5I66qIPiIr0OhjMBF5c9waakK0d252e8ysU5y9WDuV2qqSoMPyzw6gA== X-Received: by 2002:a17:902:74cc:b0:1bf:78d:5cde with SMTP id f12-20020a17090274cc00b001bf078d5cdemr8797952plt.59.1695060430928; Mon, 18 Sep 2023 11:07:10 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id h7-20020a170902704700b001aaf2e8b1eesm8556720plt.248.2023.09.18.11.07.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Sep 2023 11:07:10 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Shuah Khan Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 3/4] KVM: riscv: selftests: Fix ISA_EXT register handling in get-reg-list Date: Mon, 18 Sep 2023 23:36:45 +0530 Message-Id: <20230918180646.1398384-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230918180646.1398384-1-apatel@ventanamicro.com> References: <20230918180646.1398384-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Same set of ISA_EXT registers are not present on all host because ISA_EXT registers are visible to the KVM user space based on the ISA extensions available on the host. Also, disabling an ISA extension using corresponding ISA_EXT register does not affect the visibility of the ISA_EXT register itself. Based on the above, we should filter-out all ISA_EXT registers. Fixes: 477069398ed6 ("KVM: riscv: selftests: Add get-reg-list test") Signed-off-by: Anup Patel --- .../selftests/kvm/riscv/get-reg-list.c | 35 +++++++++++-------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index d8ecacd03ecf..76c0ad11e423 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -14,17 +14,33 @@ bool filter_reg(__u64 reg) { + switch (reg & ~REG_MASK) { /* - * Some ISA extensions are optional and not present on all host, - * but they can't be disabled through ISA_EXT registers when present. - * So, to make life easy, just filtering out these kind of registers. + * Same set of ISA_EXT registers are not present on all host because + * ISA_EXT registers are visible to the KVM user space based on the + * ISA extensions available on the host. Also, disabling an ISA + * extension using corresponding ISA_EXT register does not affect + * the visibility of the ISA_EXT register itself. + * + * Based on above, we should filter-out all ISA_EXT registers. */ - switch (reg & ~REG_MASK) { + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_D: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_F: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_H: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVPBMT: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBB: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBA: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZBS: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR: @@ -50,12 +66,7 @@ static inline bool vcpu_has_ext(struct kvm_vcpu *vcpu, int ext) unsigned long value; ret = __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(ext), &value); - if (ret) { - printf("Failed to get ext %d", ext); - return false; - } - - return !!value; + return (ret) ? false : !!value; } void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) @@ -506,10 +517,6 @@ static __u64 base_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state), - KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_A, - KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_C, - KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I, - KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI, From patchwork Mon Sep 18 18:06:46 2023 Content-Type: text/plain; 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Mon, 18 Sep 2023 11:07:15 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Shuah Khan Cc: Palmer Dabbelt , Paul Walmsley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH 4/4] KVM: riscv: selftests: Selectively filter-out AIA registers Date: Mon, 18 Sep 2023 23:36:46 +0530 Message-Id: <20230918180646.1398384-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230918180646.1398384-1-apatel@ventanamicro.com> References: <20230918180646.1398384-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org Currently the AIA ONE_REG registers are reported by get-reg-list as new registers for various vcpu_reg_list configs whenever Ssaia is available on the host because Ssaia extension can only be disabled by Smstateen extension which is not always available. To tackle this, we should filter-out AIA ONE_REG registers only when Ssaia can't be disabled for a VCPU. Fixes: 477069398ed6 ("KVM: riscv: selftests: Add get-reg-list test") Signed-off-by: Anup Patel --- .../selftests/kvm/riscv/get-reg-list.c | 23 +++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 76c0ad11e423..85907c86b835 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -12,6 +12,8 @@ #define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK) +static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX]; + bool filter_reg(__u64 reg) { switch (reg & ~REG_MASK) { @@ -48,6 +50,15 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHPM: return true; + /* AIA registers are always available when Ssaia can't be disabled */ + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h): + case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h): + return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA] ? true : false; default: break; } @@ -71,14 +82,22 @@ static inline bool vcpu_has_ext(struct kvm_vcpu *vcpu, int ext) void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c) { + int rc; struct vcpu_reg_sublist *s; + unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 }; + + for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) + __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state[i]); /* * Disable all extensions which were enabled by default * if they were available in the risc-v host. */ - for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) - __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0); + for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) { + rc = __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0); + if (rc && isa_ext_state[i]) + isa_ext_cant_disable[i] = true; + } for_each_sublist(c, s) { if (!s->feature)