From patchwork Thu Jul 25 10:41:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 169693 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp11464440ilk; Thu, 25 Jul 2019 03:42:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqyWGEyPpZjXK5WK+U2SMxTY4Ov82gWZ32s/XpeI20MBo9kkE28vlXcgUBsEdANE+Mh87xg4 X-Received: by 2002:a63:1d2:: with SMTP id 201mr51157866pgb.307.1564051324083; Thu, 25 Jul 2019 03:42:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564051324; cv=none; d=google.com; s=arc-20160816; b=TvWlIdhePUd9+QBfwTfgbQcyN/FWYGs43xROHzokN+y3gSk2C1Q1bSAx9ARw2hv5qg 3Dd2WpF/77mtp2ipBQfAnLh/p2DldFS3TSjjUBdcZJE2VrSmkiJ61c/iRjDn8KwGfV6x 7EvzNvW+DrYgv3iGX85p4sG8zU/iZ4iwNM+pr9yoqTNwaH2yomGPrRjMycjEJk4aXKNH vPBqtIXk36J+JjD09CKBJiZ3GGoeNjMXSrUvwjBtRHYU+6uK8JNmxpAuZvCBUaRzvSia xRHlloaxjgkBLUUfmlrlzWYF59133nJz1XNphRTDPC3U8O+ViAtxdxDAVm+du5hAfBu6 ZBiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OV03WyWjTcjS53n3WcFXDQeGooA4dZBwGcCk2JpHvuY=; b=Xje8y/ylV83QU2Vh/Wh1QWEjAcG0fMbIjjbqIWo1TcxGxLm5lCuBGjredwZ1+/Ko3v BMIAcY8T4bkLIPyELo4bndNj2t4qsLDPwA15ZDtEMe1Mvis/iPA5oCJ2LbwF+Pm1gvmm Is+bIxf9TD6TGhlFiLxh32LLmTrR+299eOeZ7XtuR+UMB5WnX3tckkfQ0Uq3a/eh2afo 0/cZLxZnx/0nDOP0edmvxQ1ZaGKiGplEorStheIswFOfoEzkKFB2ZIqmKQf3qBE4Uze/ UA7TTHFe+H2YKMIjLuoW1A1RW5dMLYtrs9cI5W56jAU49mWKzScAEimh2nWYRfhA4drk HM5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cD7WEF1d; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[83.226.44.230]) by smtp.gmail.com with ESMTPSA id b6sm8268306lfa.54.2019.07.25.03.41.54 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 25 Jul 2019 03:41:55 -0700 (PDT) From: Niklas Cassel To: Viresh Kumar , Nishanth Menon , Stephen Boyd , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Niklas Cassel , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 01/14] opp: Add dev_pm_opp_find_level_exact() Date: Thu, 25 Jul 2019 12:41:29 +0200 Message-Id: <20190725104144.22924-2-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When using performance states, there is usually not any opp-hz property specified, so the dev_pm_opp_find_freq_exact() function cannot be used. Since the performance states in the OPP table are unique, implement a dev_pm_opp_find_level_exact() in order to be able to fetch a specific OPP. Signed-off-by: Niklas Cassel --- drivers/opp/core.c | 48 ++++++++++++++++++++++++++++++++++++++++++ include/linux/pm_opp.h | 8 +++++++ 2 files changed, 56 insertions(+) -- 2.21.0 diff --git a/drivers/opp/core.c b/drivers/opp/core.c index cac3e4005045..3b7ffd0234e9 100644 --- a/drivers/opp/core.c +++ b/drivers/opp/core.c @@ -401,6 +401,54 @@ struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev, } EXPORT_SYMBOL_GPL(dev_pm_opp_find_freq_exact); +/** + * dev_pm_opp_find_level_exact() - search for an exact level + * @dev: device for which we do this operation + * @level: level to search for + * + * Return: Searches for exact match in the opp table and returns pointer to the + * matching opp if found, else returns ERR_PTR in case of error and should + * be handled using IS_ERR. Error return values can be: + * EINVAL: for bad pointer + * ERANGE: no match found for search + * ENODEV: if device not found in list of registered devices + * + * The callers are required to call dev_pm_opp_put() for the returned OPP after + * use. + */ +struct dev_pm_opp *dev_pm_opp_find_level_exact(struct device *dev, + unsigned int level) +{ + struct opp_table *opp_table; + struct dev_pm_opp *temp_opp, *opp = ERR_PTR(-ERANGE); + + opp_table = _find_opp_table(dev); + if (IS_ERR(opp_table)) { + int r = PTR_ERR(opp_table); + + dev_err(dev, "%s: OPP table not found (%d)\n", __func__, r); + return ERR_PTR(r); + } + + mutex_lock(&opp_table->lock); + + list_for_each_entry(temp_opp, &opp_table->opp_list, node) { + if (temp_opp->level == level) { + opp = temp_opp; + + /* Increment the reference count of OPP */ + dev_pm_opp_get(opp); + break; + } + } + + mutex_unlock(&opp_table->lock); + dev_pm_opp_put_opp_table(opp_table); + + return opp; +} +EXPORT_SYMBOL_GPL(dev_pm_opp_find_level_exact); + static noinline struct dev_pm_opp *_find_freq_ceil(struct opp_table *opp_table, unsigned long *freq) { diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h index 5bdceca5125d..b8197ab014f2 100644 --- a/include/linux/pm_opp.h +++ b/include/linux/pm_opp.h @@ -96,6 +96,8 @@ unsigned long dev_pm_opp_get_suspend_opp_freq(struct device *dev); struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev, unsigned long freq, bool available); +struct dev_pm_opp *dev_pm_opp_find_level_exact(struct device *dev, + unsigned int level); struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev, unsigned long *freq); @@ -200,6 +202,12 @@ static inline struct dev_pm_opp *dev_pm_opp_find_freq_exact(struct device *dev, return ERR_PTR(-ENOTSUPP); } +static inline struct dev_pm_opp *dev_pm_opp_find_level_exact(struct device *dev, + unsigned int level) +{ + return ERR_PTR(-ENOTSUPP); +} + static inline struct dev_pm_opp *dev_pm_opp_find_freq_floor(struct device *dev, unsigned long *freq) { From patchwork Thu Jul 25 10:41:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 169696 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp11464764ilk; Thu, 25 Jul 2019 03:42:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqyKAYqW9JuipHK0uenxNrxfmcaDs1K8chWDtNzhSINJZiu5rF/yXhepX34SJo/6fb38J6Pr X-Received: by 2002:a63:1a03:: with SMTP id a3mr81517123pga.397.1564051342849; Thu, 25 Jul 2019 03:42:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564051342; cv=none; d=google.com; s=arc-20160816; b=GOFTIc2hfZd2cd2WeOvGzSQsS74jKm8g7nufPEk2dDW/eGORuZPFFP2ztf4KsdOAs0 Kok8wqSDmQpV1QbIWilAv2bJD2hpyWGZTDqUa0K25FgMF3/mJerGxFyymaZyH5cjuOns qGku6tb2gbYzvY1j9CEOVoIdUuHEMjjHcSFC6QQM/hlC00/1nsHX7eZLBrCxvYB82GFe 8wSqPXYsHOOdsenPsFdAAisqr2P4gf8eT85Tgf3NUqcDjZX+RA2T9wcvbk9fOXnr2sGc 0/uK2dSURjqwMwtSmpkjyvWbAS3L81zHVb8KykjtT0A3TPzPPYR1acvhd8wieAPBkoKe zI6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tAokF928kZrD6BWMktKupW5JgYGkvTy88fsjwuZBb5Q=; b=XAnwQNNPXMWR4wBwD2zDFsCgOay9h0gDkZwp0rpHa8FRKwCMnHfdF+XqDYQywQpfSK d3oEypmAhzT73eq45wW7CNVflHCeHEMJDYr20/0Lhz8Z7vTUaH6/XtJ9HiarRuj2MXxt 2gItu+v4MYnRGMxbvUEKsDepUDPyiOgAeVlekFxOeOjBsobfWpCCqiwRJ69RYvGb3zWv YZYEFYIleOriETTJwRV9E0eV2Qd2EsrpOSJq36RiRuVgVXKsDoZndyaLkXa1UggBlfIu G2wP5RvTfrUzUAE59tgR+N9z6ZtklWK2dR7DGOIUsggEBWUTRn8WMMGiwbmQasxAPHNc L7yQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="pm/lXcLo"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[83.226.44.230]) by smtp.gmail.com with ESMTPSA id h1sm7451290lfj.21.2019.07.25.03.42.12 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 25 Jul 2019 03:42:12 -0700 (PDT) From: Niklas Cassel To: "Rafael J. Wysocki" , Viresh Kumar , Andy Gross , Ilia Lin Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, sboyd@kernel.org, vireshk@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Sricharan R , Niklas Cassel , linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 03/14] cpufreq: qcom: Re-organise kryo cpufreq to use it for other nvmem based qcom socs Date: Thu, 25 Jul 2019 12:41:31 +0200 Message-Id: <20190725104144.22924-4-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Sricharan R The kryo cpufreq driver reads the nvmem cell and uses that data to populate the opps. There are other qcom cpufreq socs like krait which does similar thing. Except for the interpretation of the read data, rest of the driver is same for both the cases. So pull the common things out for reuse. Signed-off-by: Sricharan R [niklas.cassel@linaro.org: split dt-binding into a separate patch and do not rename the compatible string. Update MAINTAINERS file.] Signed-off-by: Niklas Cassel Reviewed-by: Ilia Lin --- Changes since V1: -Picked up tags. -Renamed .driver .name to "qcom-cpufreq-nvmem". MAINTAINERS | 4 +- drivers/cpufreq/Kconfig.arm | 4 +- drivers/cpufreq/Makefile | 2 +- ...om-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} | 122 +++++++++++------- 4 files changed, 78 insertions(+), 54 deletions(-) rename drivers/cpufreq/{qcom-cpufreq-kryo.c => qcom-cpufreq-nvmem.c} (69%) -- 2.21.0 diff --git a/MAINTAINERS b/MAINTAINERS index 711b5d07f73d..d6b42e2413e4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13320,8 +13320,8 @@ QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096 M: Ilia Lin L: linux-pm@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/opp/kryo-cpufreq.txt -F: drivers/cpufreq/qcom-cpufreq-kryo.c +F: Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt +F: drivers/cpufreq/qcom-cpufreq-nvmem.c QUALCOMM EMAC GIGABIT ETHERNET DRIVER M: Timur Tabi diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm index 70c2b4bea55c..a905796f7f85 100644 --- a/drivers/cpufreq/Kconfig.arm +++ b/drivers/cpufreq/Kconfig.arm @@ -132,8 +132,8 @@ config ARM_OMAP2PLUS_CPUFREQ depends on ARCH_OMAP2PLUS default ARCH_OMAP2PLUS -config ARM_QCOM_CPUFREQ_KRYO - tristate "Qualcomm Kryo based CPUFreq" +config ARM_QCOM_CPUFREQ_NVMEM + tristate "Qualcomm nvmem based CPUFreq" depends on ARM64 depends on QCOM_QFPROM depends on QCOM_SMEM diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 7f2d2e1079d4..9a9f5ccd13d9 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -64,7 +64,7 @@ obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW) += qcom-cpufreq-hw.o -obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o +obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM) += qcom-cpufreq-nvmem.o obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) += raspberrypi-cpufreq.o obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c similarity index 69% rename from drivers/cpufreq/qcom-cpufreq-kryo.c rename to drivers/cpufreq/qcom-cpufreq-nvmem.c index dd64dcf89c74..fd08120768af 100644 --- a/drivers/cpufreq/qcom-cpufreq-kryo.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -9,7 +9,7 @@ * based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables * defines the voltage and frequency value based on the msm-id in SMEM * and speedbin blown in the efuse combination. - * The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC + * The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC * to provide the OPP framework with required information. * This is used to determine the voltage and frequency value for each OPP of * operating-points-v2 table when it is parsed by the OPP framework. @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -42,9 +43,9 @@ enum _msm8996_version { NUM_OF_MSM8996_VERSIONS, }; -static struct platform_device *cpufreq_dt_pdev, *kryo_cpufreq_pdev; +static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; -static enum _msm8996_version qcom_cpufreq_kryo_get_msm_id(void) +static enum _msm8996_version qcom_cpufreq_get_msm_id(void) { size_t len; u32 *msm_id; @@ -73,28 +74,62 @@ static enum _msm8996_version qcom_cpufreq_kryo_get_msm_id(void) return version; } -static int qcom_cpufreq_kryo_probe(struct platform_device *pdev) +static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + u32 *versions) { - struct opp_table **opp_tables; + size_t len; + u8 *speedbin; enum _msm8996_version msm8996_version; + + msm8996_version = qcom_cpufreq_get_msm_id(); + if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { + dev_err(cpu_dev, "Not Snapdragon 820/821!"); + return -ENODEV; + } + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + switch (msm8996_version) { + case MSM8996_V3: + *versions = 1 << (unsigned int)(*speedbin); + break; + case MSM8996_SG: + *versions = 1 << ((unsigned int)(*speedbin) + 4); + break; + default: + BUG(); + break; + } + + kfree(speedbin); + return 0; +} + +static int qcom_cpufreq_probe(struct platform_device *pdev) +{ + struct opp_table **opp_tables; + int (*get_version)(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + u32 *versions); struct nvmem_cell *speedbin_nvmem; struct device_node *np; struct device *cpu_dev; unsigned cpu; - u8 *speedbin; u32 versions; - size_t len; + const struct of_device_id *match; int ret; cpu_dev = get_cpu_device(0); if (!cpu_dev) return -ENODEV; - msm8996_version = qcom_cpufreq_kryo_get_msm_id(); - if (NUM_OF_MSM8996_VERSIONS == msm8996_version) { - dev_err(cpu_dev, "Not Snapdragon 820/821!"); + match = pdev->dev.platform_data; + get_version = match->data; + if (!get_version) return -ENODEV; - } np = dev_pm_opp_of_get_opp_desc_node(cpu_dev); if (!np) @@ -115,23 +150,10 @@ static int qcom_cpufreq_kryo_probe(struct platform_device *pdev) return PTR_ERR(speedbin_nvmem); } - speedbin = nvmem_cell_read(speedbin_nvmem, &len); + ret = get_version(cpu_dev, speedbin_nvmem, &versions); nvmem_cell_put(speedbin_nvmem); - if (IS_ERR(speedbin)) - return PTR_ERR(speedbin); - - switch (msm8996_version) { - case MSM8996_V3: - versions = 1 << (unsigned int)(*speedbin); - break; - case MSM8996_SG: - versions = 1 << ((unsigned int)(*speedbin) + 4); - break; - default: - BUG(); - break; - } - kfree(speedbin); + if (ret) + return ret; opp_tables = kcalloc(num_possible_cpus(), sizeof(*opp_tables), GFP_KERNEL); if (!opp_tables) @@ -174,7 +196,7 @@ static int qcom_cpufreq_kryo_probe(struct platform_device *pdev) return ret; } -static int qcom_cpufreq_kryo_remove(struct platform_device *pdev) +static int qcom_cpufreq_remove(struct platform_device *pdev) { struct opp_table **opp_tables = platform_get_drvdata(pdev); unsigned int cpu; @@ -189,18 +211,20 @@ static int qcom_cpufreq_kryo_remove(struct platform_device *pdev) return 0; } -static struct platform_driver qcom_cpufreq_kryo_driver = { - .probe = qcom_cpufreq_kryo_probe, - .remove = qcom_cpufreq_kryo_remove, +static struct platform_driver qcom_cpufreq_driver = { + .probe = qcom_cpufreq_probe, + .remove = qcom_cpufreq_remove, .driver = { - .name = "qcom-cpufreq-kryo", + .name = "qcom-cpufreq-nvmem", }, }; -static const struct of_device_id qcom_cpufreq_kryo_match_list[] __initconst = { - { .compatible = "qcom,apq8096", }, - { .compatible = "qcom,msm8996", }, - {} +static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { + { .compatible = "qcom,apq8096", + .data = qcom_cpufreq_kryo_name_version }, + { .compatible = "qcom,msm8996", + .data = qcom_cpufreq_kryo_name_version }, + {}, }; /* @@ -209,7 +233,7 @@ static const struct of_device_id qcom_cpufreq_kryo_match_list[] __initconst = { * which may be defered as well. The init here is only registering * the driver and the platform device. */ -static int __init qcom_cpufreq_kryo_init(void) +static int __init qcom_cpufreq_init(void) { struct device_node *np = of_find_node_by_path("/"); const struct of_device_id *match; @@ -218,32 +242,32 @@ static int __init qcom_cpufreq_kryo_init(void) if (!np) return -ENODEV; - match = of_match_node(qcom_cpufreq_kryo_match_list, np); + match = of_match_node(qcom_cpufreq_match_list, np); of_node_put(np); if (!match) return -ENODEV; - ret = platform_driver_register(&qcom_cpufreq_kryo_driver); + ret = platform_driver_register(&qcom_cpufreq_driver); if (unlikely(ret < 0)) return ret; - kryo_cpufreq_pdev = platform_device_register_simple( - "qcom-cpufreq-kryo", -1, NULL, 0); - ret = PTR_ERR_OR_ZERO(kryo_cpufreq_pdev); + cpufreq_pdev = platform_device_register_data(NULL, "qcom-cpufreq-nvmem", + -1, match, sizeof(*match)); + ret = PTR_ERR_OR_ZERO(cpufreq_pdev); if (0 == ret) return 0; - platform_driver_unregister(&qcom_cpufreq_kryo_driver); + platform_driver_unregister(&qcom_cpufreq_driver); return ret; } -module_init(qcom_cpufreq_kryo_init); +module_init(qcom_cpufreq_init); -static void __exit qcom_cpufreq_kryo_exit(void) +static void __exit qcom_cpufreq_exit(void) { - platform_device_unregister(kryo_cpufreq_pdev); - platform_driver_unregister(&qcom_cpufreq_kryo_driver); + platform_device_unregister(cpufreq_pdev); + platform_driver_unregister(&qcom_cpufreq_driver); } -module_exit(qcom_cpufreq_kryo_exit); +module_exit(qcom_cpufreq_exit); -MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver"); +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. CPUfreq driver"); MODULE_LICENSE("GPL v2"); From patchwork Thu Jul 25 10:41:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 169701 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp11465281ilk; Thu, 25 Jul 2019 03:42:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqwxx890/FmQSEUp+OAgp5AUkkHvjLlVPdOj95pXiMndYnLp50dB3vhUs7NLvCHX+y3ZrVOl X-Received: by 2002:a17:902:27a8:: with SMTP id d37mr90319643plb.150.1564051376218; Thu, 25 Jul 2019 03:42:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564051376; cv=none; d=google.com; s=arc-20160816; b=k+sr22lRVdC8F4Abu9q/n2Qrl5VNCeFSOBVXiq8Pqg0dW9VxpcGmtSrRpAIBiRxP1+ kvod87Xk7oTHu+BOy2ZGxYo8sgvnRNpihGbfULFV+inwmrGPcMWUT+vv8lgDJcgSOv+F AOchZfp4aNoW64U/ZAUGtaSUzXdcm1jSpubpaLsUDnwtp6DiMOgfwxBrAStg6woT2Mx3 eGRrT31DsW1t+NXSlJa+Upds4SpfLKJN5+LyjwsWEkE2fEP6fk5J0DsnK3TEQpgqh/8Y ZvlCc1XGcAp3wugRQ5dR8j8Yk8w8cq2bteb69CisbzNnZPKlOBFnFpiQ2gsNEUIOubPq xUWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PiCimMlECSuSC3p9Tf5td0HbmG6WHhr2fDE9h4PjuDA=; b=SH+9JsYZefj3QHbPkUbwie9CM8FaYLUiiB/HFDriMCuU/OOh+EZofmYIcC8dkcHCC0 3ucLbL4/hP30hQkuZ3TkpyeKPxfioVbW2BHbvYrC36ChBwoWhGTsfMHYklSSu28FxqD6 TbSAkLeyXWop3tzAAuPGe7BF1g8c0fY42DWeFAekfNPR838FCo95N7GgdGOQDCoAFePD bV7t+ffJrC1CHWk1ppR2RTyc14ccu57jIka/AG/vjWyE8+ciW0uF0uQU3AQ2F5olE/0l 3yPbLFEbyQDtzmJCcrrxcdT0/AP7LDXeaPDUAZICvk96y5Kqflq5prucc7ONAAFpwEpz mnvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xv5Uave8; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[83.226.44.230]) by smtp.gmail.com with ESMTPSA id e62sm9035045ljf.82.2019.07.25.03.42.49 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 25 Jul 2019 03:42:50 -0700 (PDT) From: Niklas Cassel To: Niklas Cassel , Jorge Ramirez-Ortiz Cc: linux-arm-msm@vger.kernel.org, sboyd@kernel.org, vireshk@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Rob Herring , Rob Herring , Mark Rutland , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/14] dt-bindings: power: avs: Add support for CPR (Core Power Reduction) Date: Thu, 25 Jul 2019 12:41:38 +0200 Message-Id: <20190725104144.22924-11-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DT bindings to describe the CPR HW found on certain Qualcomm SoCs. Co-developed-by: Jorge Ramirez-Ortiz Signed-off-by: Jorge Ramirez-Ortiz Signed-off-by: Niklas Cassel Reviewed-by: Rob Herring --- Changes since V1: -Picked up tags. .../bindings/power/avs/qcom,cpr.txt | 193 ++++++++++++++++++ 1 file changed, 193 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/avs/qcom,cpr.txt -- 2.21.0 diff --git a/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt new file mode 100644 index 000000000000..93be67fa8f38 --- /dev/null +++ b/Documentation/devicetree/bindings/power/avs/qcom,cpr.txt @@ -0,0 +1,193 @@ +QCOM CPR (Core Power Reduction) + +CPR (Core Power Reduction) is a technology to reduce core power on a CPU +or other device. Each OPP of a device corresponds to a "corner" that has +a range of valid voltages for a particular frequency. While the device is +running at a particular frequency, CPR monitors dynamic factors such as +temperature, etc. and suggests adjustments to the voltage to save power +and meet silicon characteristic requirements. + +- compatible: + Usage: required + Value type: + Definition: should be "qcom,qcs404-cpr", "qcom,cpr" for qcs404 + +- reg: + Usage: required + Value type: + Definition: base address and size of the rbcpr register region + +- interrupts: + Usage: required + Value type: + Definition: should specify the CPR interrupt + +- clocks: + Usage: required + Value type: + Definition: phandle to the reference clock + +- clock-names: + Usage: required + Value type: + Definition: must be "ref" + +- vdd-apc-supply: + Usage: required + Value type: + Definition: phandle to the vdd-apc-supply regulator + +- #power-domain-cells: + Usage: required + Value type: + Definition: should be 0 + +- operating-points-v2: + Usage: required + Value type: + Definition: A phandle to the OPP table containing the + performance states supported by the CPR + power domain + +- acc-syscon: + Usage: optional + Value type: + Definition: phandle to syscon for writing ACC settings + +- nvmem-cells: + Usage: required + Value type: + Definition: phandle to nvmem cells containing the data + that makes up a fuse corner, for each fuse corner. + As well as the CPR fuse revision. + +- nvmem-cell-names: + Usage: required + Value type: + Definition: should be "cpr_quotient_offset1", "cpr_quotient_offset2", + "cpr_quotient_offset3", "cpr_init_voltage1", + "cpr_init_voltage2", "cpr_init_voltage3", "cpr_quotient1", + "cpr_quotient2", "cpr_quotient3", "cpr_ring_osc1", + "cpr_ring_osc2", "cpr_ring_osc3", "cpr_fuse_revision" + for qcs404. + +- qcom,cpr-timer-delay-us: + Usage: required + Value type: + Definition: delay in uS for the timer interval + +- qcom,cpr-timer-cons-up: + Usage: required + Value type: + Definition: Consecutive number of timer intervals, or units of + qcom,cpr-timer-delay-us, that occur before issuing an up + interrupt + +- qcom,cpr-timer-cons-down: + Usage: required + Value type: + Definition: Consecutive number of timer intervals, or units of + qcom,cpr-timer-delay-us, that occur before issuing a down + interrupt + +- qcom,cpr-up-threshold: + Usage: optional + Value type: + Definition: The threshold for CPR to issue interrupt when error_steps + is greater than it when stepping up + +- qcom,cpr-down-threshold: + Usage: optional + Value type: + Definition: The threshold for CPR to issue interrupt when error_steps + is greater than it when stepping down + +- qcom,cpr-idle-clocks: + Usage: optional + Value type: + Definition: Idle clock cycles ring oscillator can be in + +- qcom,cpr-gcnt-us: + Usage: required + Value type: + Definition: The time for gate count in uS + +- qcom,vdd-apc-step-up-limit: + Usage: required + Value type: + Definition: Limit of number of vdd-apc-supply regulator steps for + scaling up + +- qcom,vdd-apc-step-down-limit: + Usage: required + Value type: + Definition: Limit of number of vdd-apc-supply regulator steps for + scaling down + +Example: + + cpr_opp_table: cpr-opp-table { + compatible = "operating-points-v2-qcom-level"; + + cpr_opp1: opp1 { + opp-level = <1>; + .... + }; + cpr_opp2: opp2 { + opp-level = <2>; + .... + }; + cpr_opp3: opp3 { + opp-level = <3>; + .... + }; + }; + + cpr@b018000 { + compatible = "qcom,qcs404-cpr", "qcom,cpr"; + reg = <0x0b018000 0x1000>; + interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; + clocks = <&xo_board>; + clock-names = "ref"; + vdd-apc-supply = <&pms405_s3>; + #power-domain-cells = <0>; + operating-points-v2 = <&cpr_opp_table>; + acc-syscon = <&tcsr>; + + nvmem-cells = <&cpr_efuse_quot_offset1>, + <&cpr_efuse_quot_offset2>, + <&cpr_efuse_quot_offset3>, + <&cpr_efuse_init_voltage1>, + <&cpr_efuse_init_voltage2>, + <&cpr_efuse_init_voltage3>, + <&cpr_efuse_quot1>, + <&cpr_efuse_quot2>, + <&cpr_efuse_quot3>, + <&cpr_efuse_ring1>, + <&cpr_efuse_ring2>, + <&cpr_efuse_ring3>, + <&cpr_efuse_revision>; + nvmem-cell-names = "cpr_quotient_offset1", + "cpr_quotient_offset2", + "cpr_quotient_offset3", + "cpr_init_voltage1", + "cpr_init_voltage2", + "cpr_init_voltage3", + "cpr_quotient1", + "cpr_quotient2", + "cpr_quotient3", + "cpr_ring_osc1", + "cpr_ring_osc2", + "cpr_ring_osc3", + "cpr_fuse_revision"; + + qcom,cpr-timer-delay-us = <5000>; + qcom,cpr-timer-cons-up = <0>; + qcom,cpr-timer-cons-down = <2>; + qcom,cpr-up-threshold = <1>; + qcom,cpr-down-threshold = <3>; + qcom,cpr-idle-clocks = <15>; + qcom,cpr-gcnt-us = <1>; + qcom,vdd-apc-step-up-limit = <1>; + qcom,vdd-apc-step-down-limit = <1>; + }; From patchwork Thu Jul 25 10:41:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Niklas Cassel X-Patchwork-Id: 169704 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp11465643ilk; Thu, 25 Jul 2019 03:43:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqzIjHHDn8QGi/9fMhqmZX5KcdgNlQ+sJ/dqhxdgfMaNs7PyIWF1pY5lvlUMKwH22b0SdmyH X-Received: by 2002:a63:1d4:: with SMTP id 203mr10783049pgb.441.1564051396869; Thu, 25 Jul 2019 03:43:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1564051396; cv=none; d=google.com; s=arc-20160816; b=i7qYalvrJrKfpiF+adsWptJqW04GEmwpygD0dHfTcKb+1NNO5MJ/xgdm/LhNzPKZ1X Jd0l0k6k81Rs/3WXgsKqQZRn37nn6IXrPo/xOUxmgKjDw0om54uisLlImhbjO2En9IDw nZAaIZpLS9fCujLyTGKP6a2KPL/TUcKtxJ58g926W+Evf9TRCtRVCrEnHmK9FSUyYS7U tUmzCg3MKHZ5vxhqqbK0O8CHh7nJdd8KvEDuvXbsZIFImFbXh/4EoQ0VFaPEKKQH42B/ 3IN2b8Jq6rmiuDkFiAYyDKY44YrKW0mUHEcG5FND5uTWXunU58qZu2r/xdUqJvm10qUP kSFQ== ARC-Message-Signature: i=1; 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[83.226.44.230]) by smtp.gmail.com with ESMTPSA id 63sm9139580ljs.84.2019.07.25.03.43.09 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Thu, 25 Jul 2019 03:43:10 -0700 (PDT) From: Niklas Cassel To: linux-kernel@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org, jorge.ramirez-ortiz@linaro.org, sboyd@kernel.org, vireshk@kernel.org, bjorn.andersson@linaro.org, ulf.hansson@linaro.org, Niklas Cassel , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 14/14] arm64: defconfig: enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM Date: Thu, 25 Jul 2019 12:41:42 +0200 Message-Id: <20190725104144.22924-15-niklas.cassel@linaro.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190725104144.22924-1-niklas.cassel@linaro.org> References: <20190725104144.22924-1-niklas.cassel@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable CONFIG_ARM_QCOM_CPUFREQ_NVMEM. Signed-off-by: Niklas Cassel --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) -- 2.21.0 diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3e7618818250..9b0cc49f5fe8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -84,6 +84,7 @@ CONFIG_ACPI_CPPC_CPUFREQ=m CONFIG_ARM_ARMADA_37XX_CPUFREQ=y CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_IMX_CPUFREQ_DT=m +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y CONFIG_ARM_RASPBERRYPI_CPUFREQ=m CONFIG_ARM_TEGRA186_CPUFREQ=y CONFIG_ARM_SCPI_PROTOCOL=y