From patchwork Tue Sep 12 14:30:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 722086 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25EABCA0EEB for ; Tue, 12 Sep 2023 15:00:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233143AbjILPAD (ORCPT ); Tue, 12 Sep 2023 11:00:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229556AbjILPAC (ORCPT ); Tue, 12 Sep 2023 11:00:02 -0400 X-Greylist: delayed 1748 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 12 Sep 2023 07:59:58 PDT Received: from mx.kernkonzept.com (serv1.kernkonzept.com [IPv6:2a01:4f8:1c1c:b490::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4C699115 for ; Tue, 12 Sep 2023 07:59:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kernkonzept.com; s=mx1; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From: Reply-To:Content-ID:Content-Description; bh=e0RspZwtHY4b6xeF+Vsx+c1salPGf7KUDftS+3xrVTM=; b=D8tMDnO24+Gcj2XS/qcJZVEek4 1iIPIOQy+bYEclNUMc81yKtm0lqpToj0AD/LQp37m33Mk2CtW29mvHO2dd8qrc7/t7qxosfnRZ8R5 GVmBwHjPVyH4xicTvOmSPU2uO2ZEBjOUmAQvrPpds4HP5LJNPpIOdGUS8NsFKGF/T4CW490t2yrVM MLaF2vMCJ9+ZG8V0aaYh4KNLPk8FqKoU2O+H2KbdFse9fpVrb2DBqVjF/lTyQV1PNYFC0gjiOjg9A Ge3ArM4LitLiFZzS8o9V5NY80vIodpUW51EW6QlasO0gcjbK4wjMqE/JkqO9yT/mxuNzF44v9rpQA e/JUTaJg==; Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1qg4Pf-0034i9-2Z; Tue, 12 Sep 2023 16:30:47 +0200 From: Stephan Gerhold Date: Tue, 12 Sep 2023 16:30:36 +0200 Subject: [PATCH 1/4] spi: dt-bindings: qup: Document power-domains and OPP MIME-Version: 1.0 Message-Id: <20230912-spi-qup-dvfs-v1-1-3e38aa09c2bd@kernkonzept.com> References: <20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com> In-Reply-To: <20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com> To: Mark Brown Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephan Gerhold X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Document power-domains and operating-points-v2 to allow making performance state votes for certain clock frequencies of the SPI QUP controller. Signed-off-by: Stephan Gerhold Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml index 93f14dd01afc..1e498a791406 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml @@ -47,6 +47,11 @@ properties: interrupts: maxItems: 1 + operating-points-v2: true + + power-domains: + maxItems: 1 + reg: maxItems: 1 @@ -63,6 +68,7 @@ examples: - | #include #include + #include spi@7575000 { compatible = "qcom,spi-qup-v2.2.1"; @@ -76,6 +82,8 @@ examples: pinctrl-1 = <&blsp1_spi1_sleep>; dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; dma-names = "tx", "rx"; + power-domains = <&rpmpd MSM8996_VDDCX>; + operating-points-v2 = <&spi_opp_table>; #address-cells = <1>; #size-cells = <0>; }; From patchwork Tue Sep 12 14:30:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 722490 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A1EBCA0EF3 for ; Tue, 12 Sep 2023 15:00:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229556AbjILPAJ (ORCPT ); Tue, 12 Sep 2023 11:00:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236090AbjILPAJ (ORCPT ); Tue, 12 Sep 2023 11:00:09 -0400 Received: from mx.kernkonzept.com (serv1.kernkonzept.com [IPv6:2a01:4f8:1c1c:b490::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FC9112E for ; Tue, 12 Sep 2023 08:00:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kernkonzept.com; s=mx1; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From: Reply-To:Content-ID:Content-Description; bh=rEE4gT/tRGbf35OMgrGbj+X9eBd0L0DdayGyn6TPmts=; b=If7ahky9w1DlTHvZVwPjdXaUhG uzw/xgQUkaQFZo0UncDcb1RLsv11cVx86U8n4TZNz44co85KwarmWAo2cgqzWEkA0U6DvPKL5podl PHU2ld2VKUR/ELYnFRD+JPqna6dJbUqpNTEDBGrlPBpTb2HxcpKPbSrz0sXIH4jQswjclmOixwgK+ ahDObNbGf3QnPb09K5t0nYDxgtXMefVWjmEaPcnzz4yzXM8iTJFn0YexibFfkC1+yBbyVPo1R0bh2 yIcaGVH/ypO+kF3rumVvOzpy0ECG2mc05akA88d/BJfHX+SOpHmR6Hp4sZWjqlGn+uNgE6sLPfu2l rD0pT2LA==; Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1qg4Ph-0034i9-1L; Tue, 12 Sep 2023 16:30:49 +0200 From: Stephan Gerhold Date: Tue, 12 Sep 2023 16:30:37 +0200 Subject: [PATCH 2/4] spi: qup: Parse OPP table for DVFS support MIME-Version: 1.0 Message-Id: <20230912-spi-qup-dvfs-v1-2-3e38aa09c2bd@kernkonzept.com> References: <20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com> In-Reply-To: <20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com> To: Mark Brown Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephan Gerhold X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Parse the OPP table from the device tree and use dev_pm_opp_set_rate() instead of clk_set_rate() to allow making performance state for power domains specified in the OPP table. This is needed to guarantee correct behavior of the clock, especially with the higher clock/SPI bus frequencies. Signed-off-by: Stephan Gerhold --- drivers/spi/spi-qup.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 4b6f6b25219b..bf043be3a2a9 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -667,7 +668,7 @@ static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer) return -EIO; } - ret = clk_set_rate(controller->cclk, xfer->speed_hz); + ret = dev_pm_opp_set_rate(controller->dev, xfer->speed_hz); if (ret) { dev_err(controller->dev, "fail to set frequency %d", xfer->speed_hz); @@ -1027,6 +1028,15 @@ static int spi_qup_probe(struct platform_device *pdev) return -ENXIO; } + ret = devm_pm_opp_set_clkname(dev, "core"); + if (ret) + return ret; + + /* OPP table is optional */ + ret = devm_pm_opp_of_add_table(dev); + if (ret && ret != -ENODEV) + return dev_err_probe(dev, ret, "invalid OPP table\n"); + host = spi_alloc_host(dev, sizeof(struct spi_qup)); if (!host) { dev_err(dev, "cannot allocate host\n"); From patchwork Tue Sep 12 14:30:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 722084 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0E74ECA0EF1 for ; Tue, 12 Sep 2023 15:00:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235032AbjILPAM (ORCPT ); Tue, 12 Sep 2023 11:00:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236098AbjILPAL (ORCPT ); Tue, 12 Sep 2023 11:00:11 -0400 Received: from mx.kernkonzept.com (serv1.kernkonzept.com [IPv6:2a01:4f8:1c1c:b490::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8028F115 for ; Tue, 12 Sep 2023 08:00:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kernkonzept.com; s=mx1; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From: Reply-To:Content-ID:Content-Description; bh=rqAqXU+BauAuZhoJ6lkP5DQOkX1bFvCYekVfXB5a7v4=; b=GgHrrHIgtFRan0MheQxCydItfh ekI6z8r3PAlYr1ztBSOqu+VTwuTgU30ollUcc+9On7jCN6lrdTW5t+ufWif2ZMJ8cP6YSTcVoHIsy /KiNRrW5tQm2JWo029WCYDLPBpSXo+Ag3wS+ouooevmNh/CQ47Kdp1YxIaQKjDv9lodJlnrZJOszc K1O9n9nQ38uQTsgi8NcaVIhfE0ow29Yy2nwVqZehpT6rZY3KythGZcAqjjkvtNXnXJD+wWuT9U2Oc VcCmXOgOei5oKnn0NGptbKFMRzjiPeq4+Jxu8rt6v20gYhkcref5r4ORCbXiN0HeeqiRzHMed/dfq 62nNSxxw==; Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1qg4Pj-0034i9-02; Tue, 12 Sep 2023 16:30:51 +0200 From: Stephan Gerhold Date: Tue, 12 Sep 2023 16:30:38 +0200 Subject: [PATCH 3/4] spi: dt-bindings: qup: Document interconnects MIME-Version: 1.0 Message-Id: <20230912-spi-qup-dvfs-v1-3-3e38aa09c2bd@kernkonzept.com> References: <20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com> In-Reply-To: <20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com> To: Mark Brown Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephan Gerhold X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org When the SPI QUP controller is used together with a DMA engine it needs to vote for the interconnect path to the DRAM. Otherwise it may be unable to access the memory quickly enough. Signed-off-by: Stephan Gerhold Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml index 1e498a791406..88be13268962 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml @@ -44,6 +44,9 @@ properties: - const: tx - const: rx + interconnects: + maxItems: 1 + interrupts: maxItems: 1 @@ -67,6 +70,7 @@ unevaluatedProperties: false examples: - | #include + #include #include #include @@ -84,6 +88,7 @@ examples: dma-names = "tx", "rx"; power-domains = <&rpmpd MSM8996_VDDCX>; operating-points-v2 = <&spi_opp_table>; + interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; #address-cells = <1>; #size-cells = <0>; }; From patchwork Tue Sep 12 14:30:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephan Gerhold X-Patchwork-Id: 722491 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A893CA0EF1 for ; Tue, 12 Sep 2023 15:00:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236055AbjILPAE (ORCPT ); Tue, 12 Sep 2023 11:00:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229556AbjILPAE (ORCPT ); Tue, 12 Sep 2023 11:00:04 -0400 Received: from mx.kernkonzept.com (serv1.kernkonzept.com [IPv6:2a01:4f8:1c1c:b490::2]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9974E115 for ; Tue, 12 Sep 2023 08:00:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kernkonzept.com; s=mx1; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From: Reply-To:Content-ID:Content-Description; bh=d8aTXSfXKUiK1Xyz5/399gXFzKYpAJm1Z7s+7n6AgiA=; b=VW2OT9MEsssDRMkwh3Uc/UV/sU ZvJI7PAAq82QQLTuNMbZ4JB2NvSLaDDhCPziIIIXjoZuw5Si5G7cBoMsE6xSHv21w48NpUQnK+0aS xlAPsANfObrC1zT09ttft7W+z3JCpckVRiUodnA48hUGcsuU5GRfWlotgo1sSQ/yewjwa4Ld/fYdl nImSY9IBb27xYyDp8bkpdUjxhq30ecnHdGpf0m7nyf5FLHMUCl0mrXQXGHsMEw7GBj54hLCAAKRa7 hNAcKfTXX6fvIWrmTWQ9wqC2+4JOJBdElsYVcng7iofUJJ6jJIG88oT9CmsDCrBpjht7ereCuItgF jxnItlew==; Received: from [10.22.3.24] (helo=serv1.dd1.int.kernkonzept.com) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_256_GCM:256) (Exim 4.96) id 1qg4Pk-0034i9-1z; Tue, 12 Sep 2023 16:30:52 +0200 From: Stephan Gerhold Date: Tue, 12 Sep 2023 16:30:39 +0200 Subject: [PATCH 4/4] spi: qup: Vote for interconnect bandwidth to DRAM MIME-Version: 1.0 Message-Id: <20230912-spi-qup-dvfs-v1-4-3e38aa09c2bd@kernkonzept.com> References: <20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com> In-Reply-To: <20230912-spi-qup-dvfs-v1-0-3e38aa09c2bd@kernkonzept.com> To: Mark Brown Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stephan Gerhold X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org When the SPI QUP controller is used together with a DMA engine it needs to vote for the interconnect path to the DRAM. Otherwise it may be unable to access the memory quickly enough. The requested peak bandwidth is dependent on the SPI core/bus clock so that the bandwidth scales together with the selected SPI speed. To avoid sending votes too often the bandwidth is always requested when a transfer starts, but dropped only on runtime suspend. Runtime suspend should only happen if no transfer is active. After resumption we can defer the next vote until the first transfer actually happens. Signed-off-by: Stephan Gerhold --- The bandwidth calculation is taken over from Qualcomm's downstream/vendor driver [1]. Due to lack of documentation about the interconnect setup/behavior I cannot say exactly if this is right. Unfortunately, this is not implemented very consistently downstream... [1]: https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/deca0f346089d32941d6d8194ae9605554486413 --- drivers/spi/spi-qup.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index bf043be3a2a9..e9c186bc530c 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -122,11 +123,14 @@ #define SPI_DELAY_THRESHOLD 1 #define SPI_DELAY_RETRY 10 +#define SPI_BUS_WIDTH 8 + struct spi_qup { void __iomem *base; struct device *dev; struct clk *cclk; /* core clock */ struct clk *iclk; /* interface clock */ + struct icc_path *icc_path; /* interconnect to RAM */ int irq; spinlock_t lock; @@ -149,6 +153,8 @@ struct spi_qup { int mode; struct dma_slave_config rx_conf; struct dma_slave_config tx_conf; + + u32 bw_speed_hz; }; static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer); @@ -181,6 +187,23 @@ static inline bool spi_qup_is_valid_state(struct spi_qup *controller) return opstate & QUP_STATE_VALID; } +static int spi_qup_vote_bw(struct spi_qup *controller, u32 speed_hz) +{ + u32 needed_peak_bw; + int ret; + + if (controller->bw_speed_hz == speed_hz) + return 0; + + needed_peak_bw = Bps_to_icc(speed_hz * SPI_BUS_WIDTH); + ret = icc_set_bw(controller->icc_path, 0, needed_peak_bw); + if (ret) + return ret; + + controller->bw_speed_hz = speed_hz; + return 0; +} + static int spi_qup_set_state(struct spi_qup *controller, u32 state) { unsigned long loop; @@ -675,6 +698,12 @@ static int spi_qup_io_prep(struct spi_device *spi, struct spi_transfer *xfer) return -EIO; } + ret = spi_qup_vote_bw(controller, xfer->speed_hz); + if (ret) { + dev_err(controller->dev, "fail to vote for ICC bandwidth: %d\n", ret); + return -EIO; + } + controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); controller->n_words = xfer->len / controller->w_size; @@ -994,6 +1023,7 @@ static void spi_qup_set_cs(struct spi_device *spi, bool val) static int spi_qup_probe(struct platform_device *pdev) { struct spi_controller *host; + struct icc_path *icc_path; struct clk *iclk, *cclk; struct spi_qup *controller; struct resource *res; @@ -1019,6 +1049,11 @@ static int spi_qup_probe(struct platform_device *pdev) if (IS_ERR(iclk)) return PTR_ERR(iclk); + icc_path = devm_of_icc_get(dev, NULL); + if (IS_ERR(icc_path)) + return dev_err_probe(dev, PTR_ERR(icc_path), + "failed to get interconnect path\n"); + /* This is optional parameter */ if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) max_freq = SPI_MAX_RATE; @@ -1070,6 +1105,7 @@ static int spi_qup_probe(struct platform_device *pdev) controller->base = base; controller->iclk = iclk; controller->cclk = cclk; + controller->icc_path = icc_path; controller->irq = irq; ret = spi_qup_init_dma(host, res->start); @@ -1190,6 +1226,7 @@ static int spi_qup_pm_suspend_runtime(struct device *device) writel_relaxed(config, controller->base + QUP_CONFIG); clk_disable_unprepare(controller->cclk); + spi_qup_vote_bw(controller, 0); clk_disable_unprepare(controller->iclk); return 0; @@ -1241,6 +1278,7 @@ static int spi_qup_suspend(struct device *device) return ret; clk_disable_unprepare(controller->cclk); + spi_qup_vote_bw(controller, 0); clk_disable_unprepare(controller->iclk); return 0; }