From patchwork Thu Sep 7 13:16:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 721335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D37D8EC8742 for ; Thu, 7 Sep 2023 17:44:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241868AbjIGRoS (ORCPT ); Thu, 7 Sep 2023 13:44:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243159AbjIGRoS (ORCPT ); Thu, 7 Sep 2023 13:44:18 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DBCC10DF; Thu, 7 Sep 2023 10:43:51 -0700 (PDT) X-UUID: c9f52a1c4d8011eea33bb35ae8d461a2-20230907 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=hJEKGvhmxp8R6c53ojV/bh0zFZPHPL5RolXP5Jg/CXY=; b=Cn53C4OavqoNUN/EvJKfnpUTS+IgZn+jMqYpflh3U5ZK8mGrFezUWEZxRCHwdSY1Df5wUZbkiXApsnVAGgwkZTydFrlpbgaUy+ZwdldfVOOE0e3YFsoj5hFFb/DbYXrbhsqUcn5BZFls+A/Ze7JFXfubfrgYM1mucrrBBcY8tEU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31, REQID:42e74b9e-43b0-4d6a-9231-5ec08d5efeb5, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:0ad78a4, CLOUDID:b23592be-14cc-44ca-b657-2d2783296e72, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: c9f52a1c4d8011eea33bb35ae8d461a2-20230907 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 231074333; Thu, 07 Sep 2023 21:16:43 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 7 Sep 2023 21:16:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 7 Sep 2023 21:16:42 +0800 From: Macpaul Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Macpaul Lin , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , , , , CC: Bear Wang , Pablo Sun , Macpaul Lin Subject: [PATCH v4 1/2] dt-bindings: arm64: dts: mediatek: add mt8395-evk board Date: Thu, 7 Sep 2023 21:16:29 +0800 Message-ID: <20230907131630.28346-1-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 1. Add compatible for MT8395. 2. Add bindings for the MediaTek mt8395-evk board, also known as the "Genio 1200-EVK". The MT8195 and MT8395 belong to the same SoC family, with only minor differences in their physical characteristics. They utilize unique efuse values for differentiation. The booting process and configurations are managed by boot loaders, firmware, and TF-A. Consequently, the part numbers and procurement channels vary. Signed-off-by: Macpaul Lin Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 6 ++++++ 1 file changed, 6 insertions(+) Changes for v2: - add more detail description for mt8395. - add bindings for mt8395, and mt8395-evk. Changes for v3: - add back bindings for mt8195 compatible. Changes for v4: - No change, update Reviewed-by tag only. Thanks. diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index ae12b1cab9fb..2e8ad49c3479 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -248,6 +248,12 @@ properties: - enum: - mediatek,mt8365-evk - const: mediatek,mt8365 + - description: MediaTek Genio 1200 Boards (Genio 1200 EVK) + items: + - enum: + - mediatek,mt8395-evk + - const: mediatek,mt8395 + - const: mediatek,mt8195 - items: - enum: - mediatek,mt8516-pumpkin From patchwork Thu Sep 7 13:16:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 721340 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DAD7EC873E for ; Thu, 7 Sep 2023 16:43:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233693AbjIGQnQ (ORCPT ); Thu, 7 Sep 2023 12:43:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233843AbjIGQmX (ORCPT ); Thu, 7 Sep 2023 12:42:23 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C760268E; Thu, 7 Sep 2023 09:41:00 -0700 (PDT) X-UUID: ca0e93444d8011ee8051498923ad61e6-20230907 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=gPTRKWq4sZHGza1woWmdro+0C8SBd6DIqrSQBS0hP00=; b=GOCPaRNTjd5RNO7kg1UX13m+MkrE121lgfGm7+XgwLF1bkupguV1X4MZ1Q6UH5qz0mVtkc3CUfBFsk2kZTx249RSa+BmFhnpVExI2I1/Y+z/pXxQLyrQ3kO3Hlpltp8jsgF1a5iFdGraiX7Gt6IMsOrs+nNRLz7QpigKy3HZSqk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31, REQID:98829915-f858-4cf5-ae53-01db36d830cd, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:0ad78a4, CLOUDID:535fac13-4929-4845-9571-38c601e9c3c9, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: ca0e93444d8011ee8051498923ad61e6-20230907 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 699500577; Thu, 07 Sep 2023 21:16:43 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 7 Sep 2023 21:16:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 7 Sep 2023 21:16:42 +0800 From: Macpaul Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Macpaul Lin , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= , , , , CC: Bear Wang , Pablo Sun , Macpaul Lin , Ben Lok Subject: [PATCH v4 2/2] arm64: dts: mediatek: add device-tree for Genio 1200 EVK board Date: Thu, 7 Sep 2023 21:16:30 +0800 Message-ID: <20230907131630.28346-2-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230907131630.28346-1-macpaul.lin@mediatek.com> References: <20230907131630.28346-1-macpaul.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add basic device-tree for the Genio 1200 EVK board. The Demo board is made by MediaTek and has a MT8395 SoC (MT8195 family), associated with the MT6359 and MT6360 PMICs, and the MT7921 connectivity chip. The IOs available on that board are: * 1 USB Type-C connector with DP aux mode support * 2 USB Type-A connector with a USB hub * 1 micro-USB port for gadget or OTG support * 1 full size HDMI RX and 1 full size HDMI TX connector * 1 micro SD slot * 40 pins header * SPI interface header * 1 M.2 slot * 1 audio jack * 1 micro-USB port for serial debug * 2 connectors for DSI displays, 1 of the DSI panel is installed * 3 connectors for CSI cameras * 1 connector for a eDP panel * 1 MMC storage * 1 Touch Panel (installed DSI display) * 1 M.2 slot for 5G dongle This commit adds basic support in order to be able to boot. Signed-off-by: Ben Lok Signed-off-by: Macpaul Lin --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8395-genio-1200-evk.dts | 901 ++++++++++++++++++ 2 files changed, 902 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts Changes for v2: - correct SOC binding to "mediatek,mt8395". - Fix a Linux coding style comments for optee node. - Fix wifi fixed 3.3v power's node with "wifi-3v3-regulator". - Fix node name of mt6360 and mt6517 to generic dts name as "pmic". - Remove unecessary blank line. - Reording usb node as the order of "phy" then "host". Changes for v3: - Add back bindings for "mediatek,mt8195". - Fix wifi fixed 3.3v power's node with "regulator-2" Changes for v4: - Fix Makefile and dts file name with prefix "mt8395-". - Re-order all nodes in mt8395-genio-1200-evk.dts by alphabetical order. - Remove unused "DEBUG" node. diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index c99c3372a4b5..10e640c6ae08 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -53,4 +53,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts new file mode 100644 index 000000000000..4e64c2b36885 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -0,0 +1,901 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Ben Lok + * Macpaul Lin + */ +/dts-v1/; + +#include "mt8195.dtsi" +#include "mt6359.dtsi" +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "MediaTek Genio 1200 EVK-P1V2-EMMC"; + compatible = "mediatek,mt8395-evk", "mediatek,mt8395", + "mediatek,mt8195"; + + aliases { + serial0 = &uart0; + ethernet0 = ð + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x2 0x00000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + vpu_mem: memory@53000000 { + compatible = "shared-dma-pool"; + reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_mem: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + snd_dma_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0x1100000>; + no-map; + }; + + apu_mem: memory@62000000 { + compatible = "shared-dma-pool"; + reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ + }; + }; + + backlight_lcd0: backlight-lcd0 { + compatible = "pwm-backlight"; + pwms = <&disp_pwm0 0 500000>; + enable-gpios = <&pio 47 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <576>; + }; + + backlight_lcd1: backlight-lcd1 { + compatible = "pwm-backlight"; + pwms = <&disp_pwm1 0 500000>; + enable-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 1023>; + num-interpolated-steps = <1023>; + default-brightness-level = <576>; + }; + + can_clk: can-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + clock-output-names = "can-clk"; + }; + + edp_panel_fixed_3v3: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "edp_panel_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_3v3_en_pins>; + }; + + edp_panel_fixed_12v: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "edp_backlight_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&pio 96 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_12v_en_pins>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + + button-volume-up { + wakeup-source; + debounce-interval = <100>; + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + }; + }; + + wifi_fixed_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "wifi_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 135 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +}; + +&disp_pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_default_pins>; + status = "okay"; +}; + +&dmic_codec { + wakeup-delay-ms = <200>; +}; + +ð { + phy-mode ="rgmii-rxid"; + phy-handle = <ð_phy0>; + snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 10000 10000>; + mediatek,tx-delay-ps = <2030>; + mediatek,mac-wol; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + eth_phy0: eth-phy0@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; + }; +}; + +&i2c0 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt9271"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts = <132 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&mt6360_ldo1>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupts = <128 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + interrupt-controller; + #interrupt-cells = <1>; + pinctrl-0 = <&mt6360_pins>; + + charger { + compatible = "mediatek,mt6360-chg"; + richtek,vinovp-microvolt = <14500000>; + + otg_vbus_regulator: usb-otg-vbus-regulator { + regulator-name = "usb-otg-vbus"; + regulator-min-microvolt = <4425000>; + regulator-max-microvolt = <5825000>; + }; + }; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN3-supply = <&mt6360_buck2>; + + mt6360_buck1: buck1 { + regulator-name = "emi_vdd2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_buck2: buck2 { + regulator-name = "emi_vddq"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo1: ldo1 { + regulator-name = "tp1_p3v0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo2: ldo2 { + regulator-name = "panel1_p1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo3: ldo3 { + regulator-name = "vmc_pmu"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo5: ldo5 { + regulator-name = "vmch_pmu"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + /* This is a measure point, which name is mt6360_ldo1 on schematic */ + mt6360_ldo6: ldo6 { + regulator-name = "mt6360_ldo1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo7: ldo7 { + regulator-name = "emi_vmddr_en"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + }; + }; +}; + +&mfg0 { + domain-supply = <&mt6315_7_vbuck1>; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x14c11>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + no-sdio; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; + non-removable; +}; + +&mt6359_vaud18_ldo_reg { + regulator-always-on; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* For USB Hub */ +&mt6359_vcamio_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359codec { + mediatek,mic-type-0 = <1>; /* ACC */ + mediatek,mic-type-1 = <3>; /* DCC */ + mediatek,mic-type-2 = <1>; /* ACC */ +}; + +&pcie0 { + pinctrl-names = "default", "idle"; + pinctrl-0 = <&pcie0_default_pins>; + pinctrl-1 = <&pcie0_idle_pins>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_pins>; + status = "disabled"; +}; + +&pciephy { + status = "okay"; +}; + +&pio { + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + disp_pwm1_default_pins: disp-pwm1-default-pins { + pins1 { + pinmux = ; + }; + }; + + edp_panel_12v_en_pins: edp-panel-12v-en-pins { + pins1 { + pinmux = ; + output-high; + }; + }; + + edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { + pins1 { + pinmux = ; + output-high; + }; + }; + + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = , + , + , + ; + drive-strength = ; + }; + + pins-cc { + pinmux = , + , + , + ; + drive-strength = ; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + input-enable; + }; + + pins-power { + pinmux = , + ; + output-high; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = , + , + , + ; + }; + + pins-cc { + pinmux = , + , + , + ; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; + + gpio_key_pins: gpio-keys-pins { + pins { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength = ; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mt6360_pins: mt6360-pins { + pins { + pinmux = , + ; + input-enable; + bias-pull-up; + }; + }; + + pcie0_default_pins: pcie0-default-pins { + pins { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + pcie0_idle_pins: pcie0-idle-pins { + pins { + pinmux = ; + bias-disable; + output-low; + }; + }; + + pcie1_default_pins: pcie1-default-pins { + pins { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + pwm0_default_pins: pwm0-default-pins { + pins-cmd-dat { + pinmux = ; + }; + }; + + spi1_pins: spi1-pins { + pins { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi2_pins: spi-pins { + pins { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + touch_pins: touch-pins { + pins-irq { + pinmux = ; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux = ; + output-high; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + , + , + ; + }; + }; +}; + +&pmic { + interrupt-parent = <&pio>; + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&spi1 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>; + + can0: can@0 { + compatible = "microchip,mcp2518fd"; + reg = <0>; + clocks = <&can_clk>; + spi-max-frequency = <20000000>; + interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + }; +}; + +&spi2 { + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&u3phy3 { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&ufsphy { + status = "disabled"; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315_6: pmic@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315_7: pmic@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-compatible = "vbuck1"; + regulator-name = "Vgpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + }; + }; + }; +}; + +&xhci0 { + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +};