From patchwork Mon Jul 22 20:20:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 169422 Delivered-To: patch@linaro.org Received: by 2002:ac9:2daa:0:0:0:0:0 with SMTP id g42csp668165oce; Mon, 22 Jul 2019 13:20:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqzNXtQbes0GX8It2s7nFRygFQ9koEHHm4gwF1FwV6cQKGTGesaRnIc/DcorRICPiW28vcUF X-Received: by 2002:a17:90a:360b:: with SMTP id s11mr77823412pjb.51.1563826840424; Mon, 22 Jul 2019 13:20:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563826840; cv=none; d=google.com; s=arc-20160816; b=AR5QryVzdgqPItsVAVQAxNwHRyom3J8+8Xfgvv+Pib71MJH6bZ0TzYlQKs7iXxvRae xJsab7+i54KthFIA+rtlBVBSAqhVeZJuqZPt0uLTjMxanbkjzsPgqfMk6rdnrm3YZHwf OCeIPa+QQqA4p+O/PTLVLaN0yzS/PEp9Nng7OaVl9ijHP1ajdMnRUiunxldDI7K0b3UW UFQO0RvszEbBvHeMxpXqkrDy7Lp1ETn9oMaFHnlyklm9KNmWVAujX8fa8JZtNTBmmdOZ q8CZD2dMyOaQ3alNEnI+5Zzat+Q6ghFrNa7Fm7z1+38V0dVuoTcYBli3OZ2cRv5b+Tqc A9sA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8fAjnJ7nDQcPPJxsddFYnZQ7qDq7y2jRlwXHDTMkcB0=; b=iptXDcq77jAZHQ/xZil/LVKtZ7wIM4fM/JioSU+0GdfVO6goIEOb/3bBL966oR3FHk /3HbNWNAcSRUEIObw3VkK3ZYMs12YZaWfsLgnoq5FY2mE+ZSMMyxl9cJX0c9/mcqPlCL WJhhnu/6e7DPwQZKWLKZC6sf4RUnPANi1VQ8NCU13g0b+vJd3JH7Do74HSaKjFgmatLL dS4P5rsP3IyWvVf3mdoYUUqFEWiCMiFOUcoMfYHq7Fn6ZAjVpAt8wcOMT34LbgSzC9UV vP63MbAv3CsmShPMnkBOi5pXJb/72FfmRkGyfj5SWtXwckTZFSDUQs92Mn3XiUudjVRb f7hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dHdoKBzt; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g11si38635670plm.390.2019.07.22.13.20.40; Mon, 22 Jul 2019 13:20:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=dHdoKBzt; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729143AbfGVUUj (ORCPT + 8 others); Mon, 22 Jul 2019 16:20:39 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:46548 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727808AbfGVUUj (ORCPT ); Mon, 22 Jul 2019 16:20:39 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x6MKKZV4024052; Mon, 22 Jul 2019 15:20:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1563826835; bh=8fAjnJ7nDQcPPJxsddFYnZQ7qDq7y2jRlwXHDTMkcB0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dHdoKBztjEdjgDABtRwBRiRcC2EGolKZ0AUhWgSuDLvWsXXT69wUKjTp+VichBuG6 zlnpFxKRwQPsR8r9zORuDi9LC04i4vMisgqqctT60N/4Va+0ACD/PbNPT7cerhY1SR i/WbEWMKY0oLTOAiQ02QU5VWp7SW6C47Q3XTJChE= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x6MKKZQL064877 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Jul 2019 15:20:35 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 22 Jul 2019 15:20:35 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 22 Jul 2019 15:20:35 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6MKKZs2109981; Mon, 22 Jul 2019 15:20:35 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6MKKZZ21504; Mon, 22 Jul 2019 15:20:35 -0500 (CDT) From: Suman Anna To: Tero Kristo , Nishanth Menon CC: , , Suman Anna Subject: [PATCH 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes Date: Mon, 22 Jul 2019 15:20:21 -0500 Message-ID: <20190722202024.14867-2-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190722202024.14867-1-s-anna@ti.com> References: <20190722202024.14867-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The AM65x Main NavSS block contains a Mailbox IP instance with multiple clusters. Each cluster is equivalent to an Mailbox IP instance on OMAP platforms. Add all the Mailbox clusters as their own nodes under the MAIN NavSS cbass_main_navss interconnect node instead of creating an almost empty parent node for the new K3 mailbox IP and the clusters as its child nodes. All these nodes are marked as disabled, and they need to be enabled along with the appropriate child nodes on a need basis. NOTE: The NavSS only has a limited number of interrupts, so all the interrupts generated by a Mailbox IP are not added by default. Only the needed interrupts that are targeted towards the A53 GIC will need to be be added later on when some sub-mailbox child nodes are added. Signed-off-by: Suman Anna --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++ 1 file changed, 108 insertions(+) -- 2.22.0 diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 8413e80f9d3a..0b3ea2a871ee 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -419,6 +419,114 @@ reg = <0x00 0x30e00000 0x00 0x1000>; #hwlock-cells = <1>; }; + + mailbox0_cluster0: mailbox@31f80000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f80000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster1: mailbox@31f81000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f81000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster2: mailbox@31f82000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f82000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster3: mailbox@31f83000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f83000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster4: mailbox@31f84000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f84000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster5: mailbox@31f85000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f85000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster6: mailbox@31f86000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f86000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster7: mailbox@31f87000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f87000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster8: mailbox@31f88000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f88000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster9: mailbox@31f89000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f89000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster10: mailbox@31f8a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster11: mailbox@31f8b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; }; main_gpio0: main_gpio0@600000 { From patchwork Mon Jul 22 20:20:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 169423 Delivered-To: patch@linaro.org Received: by 2002:ac9:2daa:0:0:0:0:0 with SMTP id g42csp668201oce; Mon, 22 Jul 2019 13:20:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqyYTAmWH+gWuJSe1bBgzxwUVVvQhM1K78hhoZE8bOJXxy452vQ2PwmSjpMzc7DEFaqvs+20 X-Received: by 2002:a17:902:1aa:: with SMTP id b39mr28464327plb.333.1563826843530; Mon, 22 Jul 2019 13:20:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563826843; cv=none; d=google.com; s=arc-20160816; b=g47sZhUZdZc6onbueGu/Xged5CDST7EygDeKgJbjLt7JDdiFe2FiinoILC5POVCi3s ZOP7cckcx6jWGfeIbFaJGza+AzL/OJFMzFLTwojOJFbUMnTlZFQBeH+bCR2q9NqNuew8 byD1WezA62S+DXzyd5aySdQW3b/yFdyiKiZEGZjZJTlydMB1U6mA8E5fX+5E8bUlmW1j 9t2L1QZWcMta1B3x5O2dshWHynG73fGwUzikwQC1VfQWQ56Xc4MJjoEWcAygR2yxHWjm ZgklDsXcwGc2Ur7L9tHEVjgtSOuqFT5WdFteie38RqZpk3+bfANRQ8g59BUo/7ieY4vq W9hQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id g11si38635670plm.390.2019.07.22.13.20.43; Mon, 22 Jul 2019 13:20:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vvOKleEY; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727808AbfGVUUn (ORCPT + 8 others); Mon, 22 Jul 2019 16:20:43 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:53358 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729377AbfGVUUm (ORCPT ); Mon, 22 Jul 2019 16:20:42 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x6MKKdoZ107367; Mon, 22 Jul 2019 15:20:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1563826839; bh=xSJYWr6Q8dYY3cdBz2U1xq3NTPqBkr/olNgj1NHVlMI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vvOKleEYyCUM4lW2vCR9ETAa3WjMlaau8FhJ0c+MZyOhIZqfaUaQVMnBnbU1wdT+O vyUuBDWl9TgGx8Sg7RaWQlRavw2pOpR21+76HPhfOE9kLCWD47GnFIb9RbnYo+JlAl fDUeCGp11+tjkwMqgwU0CZ11g8+RX2QNi5gYZQGE= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x6MKKdDG001721 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Jul 2019 15:20:39 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 22 Jul 2019 15:20:38 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 22 Jul 2019 15:20:38 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6MKKcUB099967; Mon, 22 Jul 2019 15:20:38 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6MKKcZ21510; Mon, 22 Jul 2019 15:20:38 -0500 (CDT) From: Suman Anna To: Tero Kristo , Nishanth Menon CC: , , Suman Anna Subject: [PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs Date: Mon, 22 Jul 2019 15:20:22 -0500 Message-ID: <20190722202024.14867-3-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190722202024.14867-1-s-anna@ti.com> References: <20190722202024.14867-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the sub-mailbox nodes that are used to communicate between MPU and the two R5F remote processors present in the MCU domain. The parent mailbox cluster nodes are enabled and the interrupts associated with the Mailbox Cluster User interrupt used by the sub-mailbox nodes are also added. The GIC_SPI interrupt to be used is dynamically allocated and managed by the System Firmware through the ti-sci-intr irqchip driver. The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2. These sub-mailbox nodes are added to match the hard-coded mailbox configuration used within the TI RTOS IPC software packages. The Cortex R5F processor sub-system is assumed to be running in Split mode, so a sub-mailbox node is used by each of the R5F cores. Only the sub-mailbox node from cluster 0 is used in case of Lockstep mode. Signed-off-by: Suman Anna --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 2.22.0 diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 0b3ea2a871ee..317563c995b1 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -426,7 +426,13 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; - status = "disabled"; + interrupt-parent = <&intr_main_navss>; + interrupts = <164 0>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; }; mailbox0_cluster1: mailbox@31f81000 { @@ -435,7 +441,13 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; - status = "disabled"; + interrupt-parent = <&intr_main_navss>; + interrupts = <165 0>; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; }; mailbox0_cluster2: mailbox@31f82000 { From patchwork Mon Jul 22 20:20:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Suman Anna X-Patchwork-Id: 169424 Delivered-To: patch@linaro.org Received: by 2002:ac9:2daa:0:0:0:0:0 with SMTP id g42csp668251oce; Mon, 22 Jul 2019 13:20:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqxaOl9NhjCAqOztD5dA+jzs80mEP7yHlX/QRaZJTrpr60iSeIV55gux+tUKFtp2LwggAOQJ X-Received: by 2002:a17:902:424:: with SMTP id 33mr77056781ple.151.1563826846804; Mon, 22 Jul 2019 13:20:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1563826846; cv=none; d=google.com; s=arc-20160816; b=ld9C0H0kOOLG5HhGKPzDmhzQ/uRFOz7nmInbDmrCAVh7zlALeMCt50bT7IcT1jjwh+ dxDgAVo7gjCVcSaDYn3btxqeRJpRCnPhkLkAxIYQ+cyLCCzDoueYDYq153pBgX3PcaCv 2+ePKXcdehNcOfcOjqJGENq28pOMGSoCkfrl9D7owbhhDiXMvXSF3/M7YoNlMkZAk29+ J+GvR5+pS/8LWOdHCYeeBvKnbUEaTYsN7NJwzBVXOV/qqtC+J0Qc+puA9GYjI0EtUPF/ popTYjzHu/Bk3GR/rdsltSlycLtsKRRsk88fZs+YhY+gBAU08ykjYpOwjCKooM8Udj/z 855g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UbNPxVMocMMUdGrJLZc4ntHoL1at3jSQapfzwYB+u1g=; b=islL0tCvACQxjvryjG7Rr9v35XBbYDuOn1Lr8r/Dr5BaZ4zG7WPG9+ADV2wmewucgM VYP+h7pnN+opgwK0Sbt4CH/f0on3AlAzcn4ktvEBkGYaicl4BN/oEcOVmdn/S3Xd4A7M W9y7DrCIH0Kx9wSGAw2Um0u63EeGGRUe0n8gXWwZtdJmN/Xx9lWsV7Yge5+wtriJyJHS OS7YRxek2oIQYAUkDu1e8VzgYqdlZvthY5dslcGzau3Ub7LmEmWXNmzkwfZc2lg0YA0H 1TGB3ufW3HxMLM+iZCxmAMXaODZXE1+OiblpNszpBKizAj+c7NQDpZUEIQg9ed1US7Kg BAdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=m0R3r9f0; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g11si38635670plm.390.2019.07.22.13.20.46; Mon, 22 Jul 2019 13:20:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=m0R3r9f0; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729662AbfGVUUq (ORCPT + 8 others); Mon, 22 Jul 2019 16:20:46 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55414 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729377AbfGVUUq (ORCPT ); Mon, 22 Jul 2019 16:20:46 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x6MKKgFp063272; Mon, 22 Jul 2019 15:20:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1563826842; bh=UbNPxVMocMMUdGrJLZc4ntHoL1at3jSQapfzwYB+u1g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=m0R3r9f0C2ZBrcjfgaospG07EJQn9qLRk+KatrCaOZ0gnqpZxBymbwZNcIOXOHSpi 97+P8PD1R0vF5nib33cyWYs5fZiRct9t/HjbISURgMlAP3StHIzFYxb/J/FLPhJ1X7 x6ILh5zLvf+Riso3RKtAUoil43HNWL9gMMGNbpwE= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x6MKKgWP115214 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Jul 2019 15:20:42 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 22 Jul 2019 15:20:41 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 22 Jul 2019 15:20:41 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6MKKfEo040149; Mon, 22 Jul 2019 15:20:41 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6MKKfZ21521; Mon, 22 Jul 2019 15:20:41 -0500 (CDT) From: Suman Anna To: Tero Kristo , Nishanth Menon CC: , , Suman Anna Subject: [PATCH 3/4] arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes Date: Mon, 22 Jul 2019 15:20:23 -0500 Message-ID: <20190722202024.14867-4-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190722202024.14867-1-s-anna@ti.com> References: <20190722202024.14867-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The J721E Main NavSS block contains a Mailbox IP instance with multiple clusters. Each cluster is equivalent to an Mailbox IP instance on OMAP platforms. Add all the Mailbox clusters as their own nodes under the MAIN NavSS cbass_main_navss interconnect node instead of creating an almost empty parent node for the new K3 mailbox IP and the clusters as its child nodes. All these nodes are marked as disabled, and they need to be enabled along with the appropriate child nodes on a need basis. NOTE: The NavSS only has a limited number of interrupts, so all the interrupts generated by a Mailbox IP are not added by default. Only the needed interrupts that are targeted towards the A72 GIC will need to be be added later on when some sub-mailbox child nodes are added. Signed-off-by: Suman Anna --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 108 ++++++++++++++++++++++ 1 file changed, 108 insertions(+) -- 2.22.0 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index a2e031f7d88e..319d423b3440 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -95,6 +95,114 @@ reg = <0x00 0x30e00000 0x00 0x1000>; #hwlock-cells = <1>; }; + + mailbox0_cluster0: mailbox@31f80000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f80000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster1: mailbox@31f81000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f81000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster2: mailbox@31f82000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f82000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster3: mailbox@31f83000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f83000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster4: mailbox@31f84000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f84000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster5: mailbox@31f85000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f85000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster6: mailbox@31f86000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f86000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster7: mailbox@31f87000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f87000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster8: mailbox@31f88000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f88000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster9: mailbox@31f89000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f89000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster10: mailbox@31f8a000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8a000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; + }; + + mailbox0_cluster11: mailbox@31f8b000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f8b000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + status = "disabled"; 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[209.132.180.67]) by mx.google.com with ESMTP id g11si38635670plm.390.2019.07.22.13.20.47; Mon, 22 Jul 2019 13:20:47 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=xfrpynzP; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729687AbfGVUUr (ORCPT + 8 others); Mon, 22 Jul 2019 16:20:47 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:46560 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729377AbfGVUUq (ORCPT ); Mon, 22 Jul 2019 16:20:46 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x6MKKhkp024076; Mon, 22 Jul 2019 15:20:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1563826843; bh=N9Id44vPnHBsGn8qtGEL/OKGV6syaAqFqHY6EVGYDdM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xfrpynzPsWpAGycl0kv4DILD26MnK9UQOQ+9EsDPBn9yOoKOIH4kbhG99dosOcK5E xFCe+3qwTTBguksKpl7MXhyJyQl9+F1m6zC3zn310U6CK86dn/by9aT7Bxc6nxyuWc jNGmeJ2hTu6grQiGw+9EQRCYWAfnUDOcv7y3UtxY= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x6MKKhVw115462 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 22 Jul 2019 15:20:43 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 22 Jul 2019 15:20:42 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Mon, 22 Jul 2019 15:20:43 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x6MKKgdF100023; Mon, 22 Jul 2019 15:20:42 -0500 Received: from localhost (irmo.dhcp.ti.com [128.247.58.153]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id x6MKKgZ21525; Mon, 22 Jul 2019 15:20:42 -0500 (CDT) From: Suman Anna To: Tero Kristo , Nishanth Menon CC: , , Suman Anna Subject: [PATCH 4/4] arm64: dts: ti: k3-j721e-main: Add IPC sub-mailbox nodes for all R5Fs & DSPs Date: Mon, 22 Jul 2019 15:20:24 -0500 Message-ID: <20190722202024.14867-5-s-anna@ti.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190722202024.14867-1-s-anna@ti.com> References: <20190722202024.14867-1-s-anna@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the sub-mailbox nodes that are used to communicate between MPU and various remote processors present in the J721E SoCs. These include the R5F remote processors in the dual-R5F cluster (MCU_R5FSS0) in the MCU domain and the two dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; the two C66x DSP remote processors and the single C71x DSP remote processor in the MAIN domain. The parent mailbox cluster nodes are also enabled. The sub-mailbox nodes utilize the System Mailbox clusters 0 through 4. These sub-mailbox nodes are added to match the hard-coded mailbox configuration used within the TI RTOS IPC software packages. The R5F processor sub-systems are assumed to be running in Split mode, so a sub-mailbox node is used by each of the R5F cores. The sub-mailbox node for the first R5F core in each cluster is used in case of Lockstep mode. NOTE: The GIC_SPI interrupts to be used are dynamically allocated and managed by the System Firmware through the ti-sci-intr irqchip driver. So, only valid interrupts (each cluster's User 0 IRQ output) that are used by the sub-mailbox devices are enabled. This is done to minimize the number of NavSS Interrupt Router outputs utilized. Signed-off-by: Suman Anna --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 60 +++++++++++++++++++++-- 1 file changed, 55 insertions(+), 5 deletions(-) -- 2.22.0 diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 319d423b3440..2985c73154fd 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -102,7 +102,18 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; - status = "disabled"; + interrupt-parent = <&main_navss_intr>; + interrupts = <214 0>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; mailbox0_cluster1: mailbox@31f81000 { @@ -111,7 +122,18 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; - status = "disabled"; + interrupt-parent = <&main_navss_intr>; + interrupts = <215 0>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; mailbox0_cluster2: mailbox@31f82000 { @@ -120,7 +142,18 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; - status = "disabled"; + interrupt-parent = <&main_navss_intr>; + interrupts = <216 0>; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; mailbox0_cluster3: mailbox@31f83000 { @@ -129,7 +162,18 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; - status = "disabled"; + interrupt-parent = <&main_navss_intr>; + interrupts = <217 0>; + + mbox_c66_0: mbox-c66-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; + + mbox_c66_1: mbox-c66-1 { + ti,mbox-rx = <2 0 0>; + ti,mbox-tx = <3 0 0>; + }; }; mailbox0_cluster4: mailbox@31f84000 { @@ -138,7 +182,13 @@ #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; - status = "disabled"; + interrupt-parent = <&main_navss_intr>; + interrupts = <218 0>; + + mbox_c71_0: mbox-c71-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; }; mailbox0_cluster5: mailbox@31f85000 {