From patchwork Tue Sep 5 10:47:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 720251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33BD1CA0FFA for ; Tue, 5 Sep 2023 16:22:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349554AbjIEQWC (ORCPT ); Tue, 5 Sep 2023 12:22:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354337AbjIEKrm (ORCPT ); Tue, 5 Sep 2023 06:47:42 -0400 Received: from sin.source.kernel.org (sin.source.kernel.org [145.40.73.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 835C2199; Tue, 5 Sep 2023 03:47:38 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id AD2E1CE1178; Tue, 5 Sep 2023 10:47:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B1AA8C433A9; Tue, 5 Sep 2023 10:47:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1693910855; bh=be3LTeFm799ZIVXUkbKCDmqLg5EZsxWtrrfYzGafTQ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Kn2eZZwyL2WrmDC9u1LV85D4PdFEhtw9KkxYls2VcOJ2Yo5YjFuIJlGgulxVuvPra wUc6CkhPD1ZV7DFJe348R2JAET0zkHfPX6h3CS/rx2IC54DEuvPd1Q5wHPFgF3rNo9 hC7IQr88u5L6Cz5LXpYaTnvBueqMQTWjTFPrtEEElSUmNeTdF8cP72MVF8ddZoPBo4 mvYv8Yor76j11jo4Jb13UrqWUyHpfvFSX3Ew5YJu/ryRtvi9X9z+SXOCJfzDrLFfvY 98WKpVK0lpoX6BgwGDci2DWb2UkybEtadDt8A21tDQnvYxmzyjGQeAFTqv20f0fwe1 whP6SGZ3DfxDA== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , Robin Murphy , Mark Rutland , Marc Zyngier , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Rob Herring , Fang Xiang Subject: [PATCH 2/2] irqchip/gic-v3: Enable non-coherent redistributors/ITSes probing Date: Tue, 5 Sep 2023 12:47:21 +0200 Message-Id: <20230905104721.52199-3-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905104721.52199-1-lpieralisi@kernel.org> References: <20230905104721.52199-1-lpieralisi@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The GIC architecture specification defines a set of registers for redistributors and ITSes that control the sharebility and cacheability attributes of redistributors/ITSes initiator ports on the interconnect (GICR_[V]PROPBASER, GICR_[V]PENDBASER, GITS_BASER). Architecturally the GIC provides a means to drive shareability and cacheability attributes signals and related IWB/OWB/ISH barriers but it is not mandatory for designs to wire up the corresponding interconnect signals that control the cacheability/shareability of transactions. Redistributors and ITSes interconnect ports can be connected to non-coherent interconnects that are not able to manage the shareability/cacheability attributes; this implicitly makes the redistributors and ITSes non-coherent observers. So far, the GIC driver on probe executes a write to "probe" for the redistributors and ITSes registers shareability bitfields by writing a value (ie InnerShareable - the shareability domain the CPUs are in) and check it back to detect whether the value sticks or not; this hinges on a GIC programming model behaviour that predates the current specifications, that just define shareability bits as writeable but do not guarantee that writing certain shareability values enable the expected behaviour for the redistributors/ITSes memory interconnect ports. To enable non-coherent GIC designs, introduce the "dma-noncoherent" device tree property to allow firmware to describe redistributors and ITSes as non-coherent observers on the memory interconnect and use the property to force the shareability attributes to be programmed into the redistributors and ITSes registers. Signed-off-by: Lorenzo Pieralisi Cc: Robin Murphy Cc: Mark Rutland Cc: Marc Zyngier Signed-off-by: Marc Zyngier --- drivers/irqchip/irq-gic-v3-its.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e0c2b10d154d..758ea3092305 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -5056,7 +5056,8 @@ static int __init its_compute_its_list_map(struct resource *res, } static int __init its_probe_one(struct resource *res, - struct fwnode_handle *handle, int numa_node) + struct fwnode_handle *handle, int numa_node, + bool non_coherent) { struct its_node *its; void __iomem *its_base; @@ -5148,7 +5149,7 @@ static int __init its_probe_one(struct resource *res, gits_write_cbaser(baser, its->base + GITS_CBASER); tmp = gits_read_cbaser(its->base + GITS_CBASER); - if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) + if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE || non_coherent) tmp &= ~GITS_CBASER_SHAREABILITY_MASK; if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) { @@ -5356,11 +5357,19 @@ static const struct of_device_id its_device_id[] = { {}, }; +static void of_check_rdists_coherent(struct device_node *node) +{ + if (of_property_read_bool(node, "dma-noncoherent")) + gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; +} + static int __init its_of_probe(struct device_node *node) { struct device_node *np; struct resource res; + of_check_rdists_coherent(node); + /* * Make sure *all* the ITS are reset before we probe any, as * they may be sharing memory. If any of the ITS fails to @@ -5396,7 +5405,8 @@ static int __init its_of_probe(struct device_node *node) continue; } - its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); + its_probe_one(&res, &np->fwnode, of_node_to_nid(np), + of_property_read_bool(np, "dma-noncoherent")); } return 0; } @@ -5533,7 +5543,8 @@ static int __init gic_acpi_parse_madt_its(union acpi_subtable_headers *header, } err = its_probe_one(&res, dom_handle, - acpi_get_its_numa_node(its_entry->translation_id)); + acpi_get_its_numa_node(its_entry->translation_id), + false); if (!err) return 0; From patchwork Fri Oct 6 12:59:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 730071 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EC0A31F615; Fri, 6 Oct 2023 12:59:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cxuu05QZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED31BC43395; Fri, 6 Oct 2023 12:59:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1696597190; bh=1a0WYm/JOuoSloUtHO8rcUYP3nlPMtWwDXeoC9j17ng=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Cxuu05QZS2zUIu3FMQpOk4GTxl5etLU3bdmcRa3X9ASqNJV8AQNtb+4cuNWzOCliJ J2kW9cevvgvHxvm2JEB1uR6HDj9cA+D79ZTTMcgylFpaflS9XKt6xPHUksQQphUpP0 YeHTCWvV3aju5DnJZ2jNvxYEYgOaD2jdZ9W+3V2X/HAD7oPblNqmPPCb7BGc2Nq2u4 ba7IrcEIp9aWoA5984O5Nc/ztL1bY609fWg0t+ncvT2vx/dDSQSxyw8E4xW0A3me35 U1zkddfi/3nPuZ/8AKxXknVUuYFpbKzZwt3shyb3JEomgv03yPXktZQ5NywNA5Ef9H vmENa5OnxIeIg== From: Lorenzo Pieralisi To: linux-kernel@vger.kernel.org Cc: Lorenzo Pieralisi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-acpi@vger.kernel.org, Mark Rutland , Robin Murphy , "Rafael J. Wysocki" , Rob Herring , Fang Xiang , Marc Zyngier Subject: [PATCH v3 4/5] ACPICA: Add new MADT GICC/GICR/ITS flags handling [code first] Date: Fri, 6 Oct 2023 14:59:28 +0200 Message-Id: <20231006125929.48591-5-lpieralisi@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231006125929.48591-1-lpieralisi@kernel.org> References: <20230905104721.52199-1-lpieralisi@kernel.org> <20231006125929.48591-1-lpieralisi@kernel.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add new flags and related fields to the MADT GICC/GICR/ITS structures according to the code first ECR: https://bugzilla.tianocore.org/show_bug.cgi?id=4557 Temporary code waiting for ECR approval, for testing purpose only - eventually ACPICA changes will trickle into the kernel from the ACPICA project repos. Signed-off-by: Lorenzo Pieralisi --- include/acpi/actbl2.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h index 3751ae69432f..dd44915efd6b 100644 --- a/include/acpi/actbl2.h +++ b/include/acpi/actbl2.h @@ -1046,6 +1046,7 @@ struct acpi_madt_generic_interrupt { /* ACPI_MADT_ENABLED (1) Processor is usable if set */ #define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1) /* 01: Performance Interrupt Mode */ #define ACPI_MADT_VGIC_IRQ_MODE (1<<2) /* 02: VGIC Maintenance Interrupt mode */ +#define ACPI_MADT_GICC_NON_COHERENT (1<<4) /* 04: GIC redistributor is not coherent */ /* 12: Generic Distributor (ACPI 5.0 + ACPI 6.0 changes) */ @@ -1090,21 +1091,27 @@ struct acpi_madt_generic_msi_frame { struct acpi_madt_generic_redistributor { struct acpi_subtable_header header; - u16 reserved; /* reserved - must be zero */ + u8 flags; + u8 reserved; /* reserved - must be zero */ u64 base_address; u32 length; }; +#define ACPI_MADT_GICR_NON_COHERENT (1) + /* 15: Generic Translator (ACPI 6.0) */ struct acpi_madt_generic_translator { struct acpi_subtable_header header; - u16 reserved; /* reserved - must be zero */ + u8 flags; + u8 reserved; /* reserved - must be zero */ u32 translation_id; u64 base_address; u32 reserved2; }; +#define ACPI_MADT_ITS_NON_COHERENT (1) + /* 16: Multiprocessor wakeup (ACPI 6.4) */ struct acpi_madt_multiproc_wakeup {