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Tue, 5 Sep 2023 18:44:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044EF.mail.protection.outlook.com (10.167.241.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6768.25 via Frontend Transport; Tue, 5 Sep 2023 18:44:36 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 5 Sep 2023 13:44:35 -0500 From: Ben Cheatham To: , , , CC: , , Subject: [PATCH v3 1/3] CXL, PCIE: Add cxl_rcrb_addr file to dport_dev Date: Tue, 5 Sep 2023 13:44:04 -0500 Message-ID: <20230905184406.135851-2-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905184406.135851-1-Benjamin.Cheatham@amd.com> References: <20230905184406.135851-1-Benjamin.Cheatham@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044EF:EE_|MW4PR12MB7287:EE_ X-MS-Office365-Filtering-Correlation-Id: 647301e7-7605-4e8e-5660-08dbae402776 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2023 18:44:36.4857 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 647301e7-7605-4e8e-5660-08dbae402776 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7287 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Add cxl_rcrb_addr to the dport_dev (normally represented by a pcie device) for CXL RCH root ports. The file will print the RCRB base MMIO address of the root port when read and will be used by users looking to inject CXL EINJ error types for RCH hosts. Signed-off-by: Ben Cheatham --- Documentation/ABI/testing/sysfs-bus-cxl | 8 ++++++ drivers/cxl/acpi.c | 2 ++ drivers/cxl/core/port.c | 33 +++++++++++++++++++++++++ drivers/cxl/cxl.h | 2 ++ 4 files changed, 45 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 087f762ebfd5..a7d169235543 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -177,6 +177,14 @@ Description: integer reflects the hardware port unique-id used in the hardware decoder target list. +What: /sys/bus/cxl/devices/portX/dportY/cxl_rcrb_addr +Date: August, 2023 +KernelVersion: v6.6 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) The 'cxl_rcrb_addr' device file gives the MMIO base address + of the RCRB of the corresponding CXL 1.1 downstream port. Only + present for CXL 1.1 dports. What: /sys/bus/cxl/devices/decoderX.Y Date: June, 2021 diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index d1c559879dcc..3e2ca946bf47 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -676,6 +676,8 @@ static int cxl_acpi_probe(struct platform_device *pdev) if (IS_ERR(root_port)) return PTR_ERR(root_port); + set_cxl_root(root_port); + rc = bus_for_each_dev(adev->dev.bus, NULL, root_port, add_host_bridge_dport); if (rc < 0) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 724be8448eb4..b69fd1c1d5d6 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -875,6 +875,14 @@ struct cxl_port *find_cxl_root(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(find_cxl_root, CXL); +static struct cxl_port *cxl_root; + +void set_cxl_root(struct cxl_port *root_port) +{ + cxl_root = root_port; +} +EXPORT_SYMBOL_NS_GPL(set_cxl_root, CXL); + static struct cxl_dport *find_dport(struct cxl_port *port, int id) { struct cxl_dport *dport; @@ -930,11 +938,30 @@ static void cond_cxl_root_unlock(struct cxl_port *port) device_unlock(&port->dev); } +static ssize_t cxl_rcrb_addr_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_dport *dport; + + if (!cxl_root) + return -ENODEV; + + dport = cxl_find_dport_by_dev(cxl_root, dev); + if (!dport) + return -ENODEV; + + return sysfs_emit(buf, "0x%llx\n", dport->rcrb.base); +} +DEVICE_ATTR_RO(cxl_rcrb_addr); + static void cxl_dport_remove(void *data) { struct cxl_dport *dport = data; struct cxl_port *port = dport->port; + if (dport->rch) + device_remove_file(dport->dport_dev, &dev_attr_cxl_rcrb_addr); + xa_erase(&port->dports, (unsigned long) dport->dport_dev); put_device(dport->dport_dev); } @@ -1021,6 +1048,12 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, if (rc) return ERR_PTR(rc); + if (dport->rch && dport->rcrb.base != CXL_RESOURCE_NONE) { + rc = device_create_file(dport_dev, &dev_attr_cxl_rcrb_addr); + if (rc) + return ERR_PTR(rc); + } + return dport; } diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 76d92561af29..4d5bce4bae7e 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -690,6 +690,8 @@ struct cxl_port *devm_cxl_add_port(struct device *host, resource_size_t component_reg_phys, struct cxl_dport *parent_dport); struct cxl_port *find_cxl_root(struct cxl_port *port); +void set_cxl_root(struct cxl_port *root_port); + int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd); void cxl_bus_rescan(void); void cxl_bus_drain(void); From patchwork Tue Sep 5 18:44:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 721148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 781C6CA0FFB for ; Tue, 5 Sep 2023 18:46:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230238AbjIESqs (ORCPT ); Tue, 5 Sep 2023 14:46:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232489AbjIESqr (ORCPT ); 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Tue, 5 Sep 2023 13:44:52 -0500 From: Ben Cheatham To: , , , CC: , , Subject: [PATCH v3 2/3] ACPI, APEI, EINJ: Add CXL 1.1 EINJ error type support Date: Tue, 5 Sep 2023 13:44:05 -0500 Message-ID: <20230905184406.135851-3-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905184406.135851-1-Benjamin.Cheatham@amd.com> References: <20230905184406.135851-1-Benjamin.Cheatham@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044EF:EE_|SJ2PR12MB9140:EE_ X-MS-Office365-Filtering-Correlation-Id: c670849b-d035-4bff-b494-08dbae4031f7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eo+0xS5sZlWep6qkVXPnmmsxZ+kEZwShr+vft6hboaddKY1fKb5WsvKtr85pzk7+DVxH10ltO5HxKGg69hvYqi8iaFZYmKPvLVWNPDsTKqYKrxUP9DSX+NBNQOaLJkcHlqPE1iEMFCmu2VVu/d8T6OQvilbACqGTJNvOsWFeNQOatJGoVCAhwknvUu5+JSB8IueDSAHANxL6fmeRyf7S4nWt+7k0TRLwMWkpD6h0JCTpUt0wOwh/ojhjqu534NGieoIgvH4HT6R9tXWXs14MthNxt+N8iau/yDp22CC70BsW51Nuwigt+KjAQQCGoNMUoEp8tk0HGMjCP7sckjOZIgtpsTkp1Arcxg6TA4DYnlHb19fTSr54Tik+mjCwDmRHw8QlN7YEMQ72izPEPeXYHpJ5H+tYS3rkI1P01VUkPgGGmKjm8G0gDeuGT/q8nSEoAcVkkmvy8D2DNWKtRsnelfYdrAdC88Qr9fIHQTMMglBslnZcEQsqqavl6Q13W8KJVN794KMy3nSqbl/5tpDldumqczlpdA7jcr+XKzqa5Mk2Cd/hMoVu1xsYT9yMHDH/wIrTPiuCXXH0aqKoVKO+BQlPYqtUrBGjp1ArcIAJamSbbgfM+T0Cv+eQdaF5NMcAg8UHFQImdXPkTgnNnmVY2miii4ZUhNdumU3LAorT5Y6wEo6X0fukWQEOGehDpNHWs2GicTnxrf0Gptu66EacE9AxyILIs/Hsk0uXFXYABNkzX1AZwTRaBGQzCO6od8xBfVl6jE/x/MIXcSge0b8Mog== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(396003)(346002)(376002)(136003)(451199024)(186009)(1800799009)(82310400011)(46966006)(40470700004)(36840700001)(54906003)(316002)(2906002)(36756003)(110136005)(86362001)(70586007)(40480700001)(70206006)(8936002)(5660300002)(8676002)(4326008)(41300700001)(40460700003)(1076003)(36860700001)(2616005)(83380400001)(336012)(26005)(16526019)(47076005)(426003)(82740400003)(478600001)(356005)(81166007)(7696005)(6666004)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2023 18:44:54.1108 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c670849b-d035-4bff-b494-08dbae4031f7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB9140 Precedence: bulk List-ID: X-Mailing-List: linux-acpi@vger.kernel.org Add support for CXL EINJ error types for CXL 1.1 hosts added in ACPI v6.5. Because these error types target memory-mapped CXL 1.1 compliant downstream ports and not physical (normal/persistent) memory, these error types are not currently allowed through the memory range validation done by the EINJ driver. The MMIO address of a CXL 1.1 downstream port can be found in the cxl_rcrb_addr file in the corresponding dport directory under /sys/bus/cxl/devices/portX. CXL 1.1 error types follow the same procedure as a memory error type, but with param1 set to the downstream port MMIO address. Example usage: $ cd /sys/kernel/debug/apei/einj $ cat available_error_type 0x00000008 Memory Correctable 0x00000010 Memory Uncorrectable non-fatal 0x00000020 Memory Uncorrectable fatal 0x00000040 PCI Express Correctable 0x00000080 PCI Express Uncorrectable non-fatal 0x00000100 PCI Express Uncorrectable fatal 0x00008000 CXL.mem Protocol Correctable 0x00020000 CXL.mem Protocol Uncorrectable fatal $ echo 0x8000 > error_type $ echo 0xfffffffffffff000 > param2 $ echo 0x3 > flags $ cat /sys/bus/cxl/devices/portX/dportY/cxl_rcrb_addr 0xb2f00000 $ echo 0xb2f00000 > param1 $ echo 1 > error_inject Signed-off-by: Ben Cheatham --- drivers/acpi/apei/einj.c | 26 +++++++++++++++++++++++++- drivers/cxl/core/port.c | 17 +++++++++++++++++ drivers/cxl/cxl.h | 1 + include/linux/cxl.h | 18 ++++++++++++++++++ 4 files changed, 61 insertions(+), 1 deletion(-) create mode 100644 include/linux/cxl.h diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c index 013eb621dc92..0783ddd3ab4d 100644 --- a/drivers/acpi/apei/einj.c +++ b/drivers/acpi/apei/einj.c @@ -21,6 +21,7 @@ #include #include #include +#include #include #include "apei-internal.h" @@ -36,6 +37,7 @@ #define MEM_ERROR_MASK (ACPI_EINJ_MEMORY_CORRECTABLE | \ ACPI_EINJ_MEMORY_UNCORRECTABLE | \ ACPI_EINJ_MEMORY_FATAL) +#define CXL_ERROR_MASK GENMASK(17, 12) /* * ACPI version 5 provides a SET_ERROR_TYPE_WITH_ADDRESS action. @@ -512,6 +514,24 @@ static int __einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, return rc; } +static int is_valid_cxl_addr(u64 addr) +{ + struct cxl_dport *dport; + + if (IS_REACHABLE(CONFIG_CXL_ACPI)) { + dport = cxl_find_rch_dport_by_rcrb((resource_size_t) addr); + + if (!IS_ERR_OR_NULL(dport)) + return 1; + } else { + pr_err("CONFIG_CXL_ACPI is not reachable.\n"); + return 0; + } + + pr_info("Could not find dport with rcrb 0x%llx\n", addr); + return 0; +} + /* Inject the specified hardware error */ static int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, u64 param3, u64 param4) @@ -537,8 +557,11 @@ static int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, if (type & ACPI5_VENDOR_BIT) { if (vendor_flags != SETWA_FLAGS_MEM) goto inject; - } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) + } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) { goto inject; + } else if (type & CXL_ERROR_MASK && is_valid_cxl_addr(param1)) { + goto inject; + } /* * Disallow crazy address masks that give BIOS leeway to pick @@ -807,3 +830,4 @@ module_exit(einj_exit); MODULE_AUTHOR("Huang Ying"); MODULE_DESCRIPTION("APEI Error INJection support"); MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(CXL); diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index b69fd1c1d5d6..3961f099a775 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1122,6 +1122,23 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, } EXPORT_SYMBOL_NS_GPL(devm_cxl_add_rch_dport, CXL); +struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base) +{ + struct cxl_dport *dport; + unsigned long index; + + if (!cxl_root) + return ERR_PTR(-ENODEV); + + xa_for_each(&cxl_root->dports, index, dport) + if ((dport->rch && dport->rcrb.base != CXL_RESOURCE_NONE) + && dport->rcrb.base == rcrb_base) + return dport; + + return NULL; +} +EXPORT_SYMBOL_NS_GPL(cxl_find_rch_dport_by_rcrb, CXL); + static int add_ep(struct cxl_ep *new) { struct cxl_port *port = new->dport->port; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 4d5bce4bae7e..3e6779dbcd23 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -8,6 +8,7 @@ #include #include #include +#include #include /** diff --git a/include/linux/cxl.h b/include/linux/cxl.h new file mode 100644 index 000000000000..09889581d9f1 --- /dev/null +++ b/include/linux/cxl.h @@ -0,0 +1,18 @@ +#ifndef _LINUX_CXL_H +#define _LINUX_CXL_H + +#include +#include + +struct cxl_dport; + +#if IS_ENABLED(CONFIG_CXL_ACPI) +struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base); +#else +struct cxl_dport *cxl_find_rch_dport_by_rcrb(resource_size_t rcrb_base) +{ + return NULL; +} +#endif + +#endif From patchwork Tue Sep 5 18:44:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 720141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8E9DCA0FF7 for ; Tue, 5 Sep 2023 18:47:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232489AbjIESrK (ORCPT ); Tue, 5 Sep 2023 14:47:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233633AbjIESrI (ORCPT ); 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Tue, 5 Sep 2023 13:45:10 -0500 From: Ben Cheatham To: , , , CC: , , Subject: [PATCH v3 3/3] ACPI, APEI, EINJ: Update EINJ documentation Date: Tue, 5 Sep 2023 13:44:06 -0500 Message-ID: <20230905184406.135851-4-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230905184406.135851-1-Benjamin.Cheatham@amd.com> References: <20230905184406.135851-1-Benjamin.Cheatham@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F4:EE_|PH0PR12MB5468:EE_ X-MS-Office365-Filtering-Correlation-Id: 97219117-65df-4b28-6d26-08dbae403c37 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ICpW6HgL2tKddmcmuZ2ddhk7OW/EZSuAX5fFOBJ7fAytSPZqy/ZD1N/Mpj254rLD+KBjdrmcxu8nhqU3rIjwQ1BMsINhMkQQizzbHY4RWukKgbZ/8aeyYWHs2kEsu6GssfibeMCsXp7XstZn+pHiWxFrRZzLuob6m8gUNG0xc433fypFQAJFGkiNZuG2wxhU90mQitOxYq7H85wGBmN8Ryvs2Nn86KBpFR+CJgunjJQ+8Q8HE2DamHeYXhyrGjwVenXasF3qwyyuuWChebXWGcmCLgnSPrYk8L/gXa6hPAor9DU0a9VZ+4DuCTDH2xfgwxzxl1r/wPIfqoIlbQ3xXNyy6mP81tOt+drCOeog06mu+BlP4r43BOJ4aAemPQWbfL/Sbsi7/mVQnd7ALbap3lnIAIeTlocEKMiFg/CK2jFSeWZrkiFZR+4Zg2XMLD4Kf9bQZaRi1cca1m5Xckszq3s6E09dXdp7H4QdI4/Osmvc4Xq06be1PdgI3HshJcCAuGb9SwkiwVw0ieuhG7IMBXyEvJf1avGzP0SpJTM35l5RmCO9E+thDRR+aDaFVS7sEktzABcwYqzH0O0KMdXRck3AUrp91cI7IYDQv+kywFcdbPevTDjLJh2/bHrOV9PlnX6OeK887jQmG6SKwfRktEtJ2AlLCoRRJbbA4+2KBkPLp1rvn52Kgt0Ugav4HVL2tKv5uRrHWmYDOS/61Xz4T0JWBRhh4I/Ter3C8wHROe++hQNK790eLbDs4L6gdbcBfzfs3QxJyyKOoAAHKnTEbQ== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Also fix a formatting error in the param4 file description that caused the description to be on the same line as the bullet point. Signed-off-by: Ben Cheatham --- .../firmware-guide/acpi/apei/einj.rst | 26 ++++++++++++++++--- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/Documentation/firmware-guide/acpi/apei/einj.rst b/Documentation/firmware-guide/acpi/apei/einj.rst index d6b61d22f525..20ae49ec4eac 100644 --- a/Documentation/firmware-guide/acpi/apei/einj.rst +++ b/Documentation/firmware-guide/acpi/apei/einj.rst @@ -32,6 +32,10 @@ configuration:: CONFIG_ACPI_APEI CONFIG_ACPI_APEI_EINJ +To use CXL error types ``CONFIG_CXL_ACPI`` needs to be set. If +``CONFIG_CXL_ACPI`` is set to the "m" then ``CONFIG_ACPI_APEI_EINJ`` +also must be set to "m" or "n". + The EINJ user interface is in /apei/einj. The following files belong to it: @@ -40,9 +44,9 @@ The following files belong to it: This file shows which error types are supported: - ================ =================================== + ================ ========================================= Error Type Value Error Description - ================ =================================== + ================ ========================================= 0x00000001 Processor Correctable 0x00000002 Processor Uncorrectable non-fatal 0x00000004 Processor Uncorrectable fatal @@ -55,7 +59,13 @@ The following files belong to it: 0x00000200 Platform Correctable 0x00000400 Platform Uncorrectable non-fatal 0x00000800 Platform Uncorrectable fatal - ================ =================================== + 0x00001000 CXL.cache Protocol Correctable + 0x00002000 CXL.cache Protocol Uncorrectable non-fatal + 0x00004000 CXL.cache Protocol Uncorrectable fatal + 0x00008000 CXL.mem Protocol Correctable + 0x00010000 CXL.mem Protocol Uncorrectable non-fatal + 0x00020000 CXL.mem Protocol Uncorrectable fatal + ================ ========================================= The format of the file contents are as above, except present are only the available error types. @@ -106,6 +116,7 @@ The following files belong to it: Used when the 0x1 bit is set in "flags" to specify the APIC id - param4 + Used when the 0x4 bit is set in "flags" to specify target PCIe device - notrigger @@ -159,6 +170,13 @@ and param2 (1 = PROCESSOR, 2 = MEMORY, 4 = PCI). See your BIOS vendor documentation for details (and expect changes to this API if vendors creativity in using this feature expands beyond our expectations). +CXL error types are supported from ACPI 6.5 onwards. To use these error +types you need the MMIO address of a CXL 1.1 downstream port. You can +find the address of dportY in /sys/bus/cxl/devices/portX/dportY/cxl_rcrb_addr +(it's possible that the dport is under the CXL root, in that case the +path would be /sys/us/cxl/devices/rootX/dportY/cxl_rcrb_addr). +From there, write the address to param1 and continue as you would for a +memory error type. An error injection example:: @@ -201,4 +219,4 @@ The following sequence can be used: 7) Read from the virtual address. This will trigger the error For more information about EINJ, please refer to ACPI specification -version 4.0, section 17.5 and ACPI 5.0, section 18.6. +version 4.0, section 17.5 and ACPI 6.5, section 18.6.