From patchwork Mon Sep 4 23:14:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aryan Srivastava X-Patchwork-Id: 720049 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84CE9C83F2C for ; Mon, 4 Sep 2023 23:14:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235193AbjIDXPA (ORCPT ); Mon, 4 Sep 2023 19:15:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234209AbjIDXPA (ORCPT ); Mon, 4 Sep 2023 19:15:00 -0400 Received: from gate2.alliedtelesis.co.nz (gate2.alliedtelesis.co.nz [202.36.163.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05484199 for ; Mon, 4 Sep 2023 16:14:55 -0700 (PDT) Received: from svr-chch-seg1.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 7A7432C018E; Tue, 5 Sep 2023 11:14:52 +1200 (NZST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; s=mail181024; t=1693869292; bh=MJlkYMYlLXnuiN67I7n/ykEK9o0Lv6UQ2YSGp2KUgjM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=z8N9xnLgprtAGLCNRgXqQRi8JyeM+/OQePPxgxA/FST5Zjimusg4Cqht2A9teyCgD momYqWlQyQRl92QLiz22Uxu78Cny9/gMSF0yMlA+X1Mb9jOni98nra54XxxwZrKop4 76J7zkzkRvdwOdCd2el41rx9MbVKJtqbNrpvA5qFlj3HVaCVWnVQNG08gRjIzJSoSb Vw7W30UtNgeVUPiIp4RVNKtzPHKdybIT4PGe2Zg5IrFUH/0TJHIWjh+zMhO26QBgGI tvFJYQz2MoxEVbMezOHRtwFoX5QtsjfAz+hhFRFvviee1v1DQpcBBMXtvq3fBHgZbx hbGpwtiI09aaA== Received: from pat.atlnz.lc (Not Verified[10.32.16.33]) by svr-chch-seg1.atlnz.lc with Trustwave SEG (v8,2,6,11305) id ; Tue, 05 Sep 2023 11:14:52 +1200 Received: from aryans-dl.ws.atlnz.lc (aryans-dl.ws.atlnz.lc [10.33.22.26]) by pat.atlnz.lc (Postfix) with ESMTP id 3E13413EE3F; Tue, 5 Sep 2023 11:14:52 +1200 (NZST) Received: by aryans-dl.ws.atlnz.lc (Postfix, from userid 1844) id 3955C2038E4; Tue, 5 Sep 2023 11:14:52 +1200 (NZST) From: Aryan Srivastava To: andi.shyti@kernel.org Cc: aryan.srivastava@alliedtelesis.co.nz, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] i2c:octeon:Add block-mode r/w Date: Tue, 5 Sep 2023 11:14:39 +1200 Message-ID: <20230904231439.485925-1-aryan.srivastava@alliedtelesis.co.nz> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230903123446.vjgpplnogejbzneb@zenone.zhora.eu> References: <20230903123446.vjgpplnogejbzneb@zenone.zhora.eu> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=fYfTNHYF c=1 sm=1 tr=0 a=KLBiSEs5mFS1a/PbTCJxuA==:117 a=zNV7Rl7Rt7sA:10 a=l0UKegxhDiIKDgkKk6AA:9 X-SEG-SpamProfiler-Score: 0 x-atlnz-ls: pat Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org Add support for block mode read/write operations on Thunderx chips. When attempting r/w operations of greater then 8 bytes block mode is used, instead of performing a series of 8 byte reads. Signed-off-by: Aryan Srivastava --- Changes in v2: - comment style and formatting. Changes in v3: - comment style and formatting. --- drivers/i2c/busses/i2c-octeon-core.c | 158 ++++++++++++++++++++++- drivers/i2c/busses/i2c-octeon-core.h | 14 ++ drivers/i2c/busses/i2c-thunderx-pcidrv.c | 4 + 3 files changed, 170 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c index 845eda70b8ca..940cc4647cb0 100644 --- a/drivers/i2c/busses/i2c-octeon-core.c +++ b/drivers/i2c/busses/i2c-octeon-core.c @@ -130,6 +130,25 @@ static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c) octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); } +static void octeon_i2c_block_enable(struct octeon_i2c *i2c) +{ + if (i2c->block_enabled || !TWSI_BLOCK_CTL(i2c)) + return; + + i2c->block_enabled = true; + octeon_i2c_writeq_flush(TWSI_MODE_STRETCH + | TWSI_MODE_BLOCK_MODE, i2c->twsi_base + TWSI_MODE(i2c)); +} + +static void octeon_i2c_block_disable(struct octeon_i2c *i2c) +{ + if (!i2c->block_enabled || !TWSI_BLOCK_CTL(i2c)) + return; + + i2c->block_enabled = false; + octeon_i2c_writeq_flush(TWSI_MODE_STRETCH, i2c->twsi_base + TWSI_MODE(i2c)); +} + /** * octeon_i2c_hlc_wait - wait for an HLC operation to complete * @i2c: The struct octeon_i2c @@ -268,6 +287,7 @@ static int octeon_i2c_start(struct octeon_i2c *i2c) u8 stat; octeon_i2c_hlc_disable(i2c); + octeon_i2c_block_disable(i2c); octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA); ret = octeon_i2c_wait(i2c); @@ -594,6 +614,124 @@ static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msg return ret; } +/* high-level-controller composite block write+read, msg0=addr, msg1=data */ +static int octeon_i2c_hlc_block_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs) +{ + int i, j, len, ret = 0; + u64 cmd = 0, rd = 0; + + octeon_i2c_hlc_enable(i2c); + octeon_i2c_block_enable(i2c); + + /* Write (size - 1) into block control register */ + len = msgs[1].len - 1; + octeon_i2c_writeq_flush((u64)(len), i2c->twsi_base + TWSI_BLOCK_CTL(i2c)); + + /* Prepare core command */ + cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR; + cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; + + if (msgs[0].flags & I2C_M_TEN) + cmd |= SW_TWSI_OP_10_IA; + else + cmd |= SW_TWSI_OP_7_IA; + + if (msgs[0].len == 2) { + u64 ext = 0; + + cmd |= SW_TWSI_EIA; + ext = (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; + cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT; + octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); + } else { + cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; + } + + /* Send command to core (send data to FIFO) */ + octeon_i2c_hlc_int_clear(i2c); + octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); + + /* Wait for transaction to complete */ + ret = octeon_i2c_hlc_wait(i2c); + if (ret) + return ret; + + cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + if ((cmd & SW_TWSI_R) == 0) + return octeon_i2c_check_status(i2c, false); + + /* read data in FIFO */ + octeon_i2c_writeq_flush(TWSI_BLOCK_STS_RESET_PTR, i2c->twsi_base + TWSI_BLOCK_STS(i2c)); + for (i = 0; i < len; i += 8) { + rd = __raw_readq(i2c->twsi_base + TWSI_BLOCK_FIFO(i2c)); + for (j = 7; j >= 0; j--) + msgs[1].buf[i + (7 - j)] = (rd >> (8 * j)) & 0xff; + } + + octeon_i2c_block_disable(i2c); + return ret; +} + +/* high-level-controller composite block write+write, m[0]len<=2, m[1]len<=1024 */ +static int octeon_i2c_hlc_block_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs) +{ + bool set_ext = false; + int i, j, len, ret = 0; + u64 cmd, buf = 0, ext = 0; + + octeon_i2c_hlc_enable(i2c); + octeon_i2c_block_enable(i2c); + + /* Write (size - 1) into block control register */ + len = msgs[1].len - 1; + octeon_i2c_writeq_flush((u64)(len), i2c->twsi_base + TWSI_BLOCK_CTL(i2c)); + + /* Prepare core command */ + cmd = SW_TWSI_V | SW_TWSI_SOVR; + cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; + + if (msgs[0].flags & I2C_M_TEN) + cmd |= SW_TWSI_OP_10_IA; + else + cmd |= SW_TWSI_OP_7_IA; + + if (msgs[0].len == 2) { + cmd |= SW_TWSI_EIA; + ext |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; + set_ext = true; + cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT; + } else { + cmd |= (u64)msgs[0].buf[0] << SW_TWSI_IA_SHIFT; + } + + /* Write msg into FIFO buffer */ + octeon_i2c_writeq_flush(TWSI_BLOCK_STS_RESET_PTR, i2c->twsi_base + TWSI_BLOCK_STS(i2c)); + for (i = 0; i < len; i += 8) { + buf = 0; + for (j = 7; j >= 0; j--) + buf |= (msgs[1].buf[i + (7 - j)] << (8 * j)); + octeon_i2c_writeq_flush(buf, i2c->twsi_base + TWSI_BLOCK_FIFO(i2c)); + } + if (set_ext) + octeon_i2c_writeq_flush(ext, i2c->twsi_base + SW_TWSI_EXT(i2c)); + + /* Send command to core (send data in FIFO) */ + octeon_i2c_hlc_int_clear(i2c); + octeon_i2c_writeq_flush(cmd, i2c->twsi_base + SW_TWSI(i2c)); + + /* Wait for transaction to complete */ + ret = octeon_i2c_hlc_wait(i2c); + if (ret) + goto ret; + + cmd = __raw_readq(i2c->twsi_base + SW_TWSI(i2c)); + if ((cmd & SW_TWSI_R) == 0) + return octeon_i2c_check_status(i2c, false); + + octeon_i2c_block_disable(i2c); + return ret; +} + /** * octeon_i2c_xfer - The driver's master_xfer function * @adap: Pointer to the i2c_adapter structure @@ -619,13 +757,21 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) if ((msgs[0].flags & I2C_M_RD) == 0 && (msgs[1].flags & I2C_M_RECV_LEN) == 0 && msgs[0].len > 0 && msgs[0].len <= 2 && - msgs[1].len > 0 && msgs[1].len <= 8 && + msgs[1].len > 0 && msgs[0].addr == msgs[1].addr) { - if (msgs[1].flags & I2C_M_RD) - ret = octeon_i2c_hlc_comp_read(i2c, msgs); - else - ret = octeon_i2c_hlc_comp_write(i2c, msgs); - goto out; + if (msgs[1].len <= 8) { + if (msgs[1].flags & I2C_M_RD) + ret = octeon_i2c_hlc_comp_read(i2c, msgs); + else + ret = octeon_i2c_hlc_comp_write(i2c, msgs); + goto out; + } else if (msgs[1].len <= 1024 && TWSI_BLOCK_CTL(i2c)) { + if (msgs[1].flags & I2C_M_RD) + ret = octeon_i2c_hlc_block_comp_read(i2c, msgs); + else + ret = octeon_i2c_hlc_block_comp_write(i2c, msgs); + goto out; + } } } diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h index 9bb9f64fdda0..81fcf413c890 100644 --- a/drivers/i2c/busses/i2c-octeon-core.h +++ b/drivers/i2c/busses/i2c-octeon-core.h @@ -85,6 +85,11 @@ #define TWSI_INT_SDA BIT_ULL(10) #define TWSI_INT_SCL BIT_ULL(11) +#define TWSI_MODE_STRETCH BIT_ULL(1) +#define TWSI_MODE_BLOCK_MODE BIT_ULL(2) + +#define TWSI_BLOCK_STS_RESET_PTR BIT_ULL(0) +#define TWSI_BLOCK_STS_BUSY BIT_ULL(1) #define I2C_OCTEON_EVENT_WAIT 80 /* microseconds */ /* Register offsets */ @@ -92,11 +97,19 @@ struct octeon_i2c_reg_offset { unsigned int sw_twsi; unsigned int twsi_int; unsigned int sw_twsi_ext; + unsigned int twsi_mode; + unsigned int twsi_block_ctl; + unsigned int twsi_block_sts; + unsigned int twsi_block_fifo; }; #define SW_TWSI(x) (x->roff.sw_twsi) #define TWSI_INT(x) (x->roff.twsi_int) #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext) +#define TWSI_MODE(x) (x->roff.twsi_mode) +#define TWSI_BLOCK_CTL(x) (x->roff.twsi_block_ctl) +#define TWSI_BLOCK_STS(x) (x->roff.twsi_block_sts) +#define TWSI_BLOCK_FIFO(x) (x->roff.twsi_block_fifo) struct octeon_i2c { wait_queue_head_t queue; @@ -110,6 +123,7 @@ struct octeon_i2c { void __iomem *twsi_base; struct device *dev; bool hlc_enabled; + bool block_enabled; bool broken_irq_mode; bool broken_irq_check; void (*int_enable)(struct octeon_i2c *); diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/i2c-thunderx-pcidrv.c index a77cd86fe75e..abde98117d7e 100644 --- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c +++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c @@ -165,6 +165,10 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev, i2c->roff.sw_twsi = 0x1000; i2c->roff.twsi_int = 0x1010; i2c->roff.sw_twsi_ext = 0x1018; + i2c->roff.twsi_mode = 0x1038; + i2c->roff.twsi_block_ctl = 0x1048; + i2c->roff.twsi_block_sts = 0x1050; + i2c->roff.twsi_block_fifo = 0x1058; i2c->dev = dev; pci_set_drvdata(pdev, i2c);