From patchwork Wed Jun 7 09:16:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 103223 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp1834598qgd; Wed, 7 Jun 2017 02:17:16 -0700 (PDT) X-Received: by 10.84.218.71 with SMTP id f7mr25301760plm.180.1496827036904; Wed, 07 Jun 2017 02:17:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496827036; cv=none; d=google.com; s=arc-20160816; b=WogC9TsU3zHpvW38T34mfuY9sFmYSWmKhg/4YLtQTB/WXWQdwMBdWepiYVTENCEuCX DheGnkuKpVMnBpBtq6KkYvkjHQr0X1yQ+/1XxaWjbIXXxYbt5BYLRbdjOnc2z5HCa6mN ys1D4D9gQEQIk8ahxIGsNb5yDxTP59BkKfM9qJ6UfiGb+FmWqietFObqfIhiww/KfZf6 CRW/qJWm9x1S/kvoPAw3VzmWXr3JF0yO+B57Ac6uHklUCJsoSw6D583lTIruxCbKJLzN xC4ZAGOw6YeTRhWcUJeGjXtBuuUnoay9AVyj2l1EZ0xwFCp4XeWl24Clny9YrHUrbKaN umQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=44Bg9U8BvSrRj6nBK+KhCZq/21LLygqY4TTP9eCfKbk=; b=yFWKUrD/JfR0zm57oO110QWK6MhOCczBTCK/wb/toRdoDsYdSFmUpmwQIoFpXVMzWD AAr3Kji5kNCow+SuWw1gSneYuEoBup+MzfE6lw/5V9uGZkUFdcHFaK9CQKwnIBjK+gMa R4kV0kRJbcDW2xWeJBGJxVLCNP2ESlwAukIgqXplHUpWEGJTcPEGGWdEE0yvjJepDEBU Zd65q4EUl+Hkban2ldJs3L80yvZumvfJrn86/VYtP2MMKH9oJobjWCo689gpSUqrvIss We01mWfr2btJQhw4TLB0gen3EAJsZgvTIuZi/T2L+UXwIq5pF9Wk37JQnOLlexS6qq2/ 6UFA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id d7si1282964pln.460.2017.06.07.02.17.16; Wed, 07 Jun 2017 02:17:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751875AbdFGJQ6 (ORCPT + 25 others); Wed, 7 Jun 2017 05:16:58 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6880 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751684AbdFGJQw (ORCPT ); Wed, 7 Jun 2017 05:16:52 -0400 Received: from 172.30.72.53 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOX19767; Wed, 07 Jun 2017 17:16:34 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Wed, 7 Jun 2017 17:16:19 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v3 1/3] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING Date: Wed, 7 Jun 2017 17:16:06 +0800 Message-ID: <1496826968-10152-2-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1496826968-10152-1-git-send-email-dingtianhong@huawei.com> References: <1496826968-10152-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.5937C473.0039, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 091a113b84247942787b0e7899793cc9 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Casey Leedom The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed Ordering Attribute should not be used on Transaction Layer Packets destined for the PCIe End Node so flagged. Initially flagged this way are Intel E5-26xx Root Complex Ports which suffer from a Flow Control Credit Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which don't obey PCIe 3.0 ordering rules which can lead to Data Corruption. Signed-off-by: Casey Leedom Signed-off-by: Ding Tianhong --- drivers/pci/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 40 insertions(+) -- 1.9.0 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 085fb78..58bdd23 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3999,6 +3999,44 @@ static void quirk_tw686x_class(struct pci_dev *pdev) quirk_tw686x_class); /* + * Some devices have problems with Transaction Layer Packets with the Relaxed + * Ordering Attribute set. Such devices should mark themselves and other + * Device Drivers should check before sending TLPs with RO set. + */ +static void quirk_relaxedordering_disable(struct pci_dev *dev) +{ + dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; +} + +/* + * Intel E5-26xx Root Complex has a Flow Control Credit issue which can + * cause performance problems with Upstream Transaction Layer Packets with + * Relaxed Ordering set. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex + * where Upstream Transaction Layer Packets with the Relaxed Ordering + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 + * November 10, 2010). As a result, on this platform we can't use Relaxed + * Ordering for Upstream TLPs. + */ +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, + quirk_relaxedordering_disable); + +/* * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same * values for the Attribute as were supplied in the header of the * corresponding Request, except as explicitly allowed when IDO is used." diff --git a/include/linux/pci.h b/include/linux/pci.h index 33c2b0b..e1e8428 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -183,6 +183,8 @@ enum pci_dev_flags { PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9), /* Do not use FLR even if device advertises PCI_AF_CAP */ PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10), + /* Don't use Relaxed Ordering for TLPs directed at this device */ + PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11), }; enum pci_irq_reroute_variant { From patchwork Wed Jun 7 09:16:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 103222 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp1834487qgd; Wed, 7 Jun 2017 02:16:58 -0700 (PDT) X-Received: by 10.84.137.1 with SMTP id 1mr27289822plm.128.1496827018539; Wed, 07 Jun 2017 02:16:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496827018; cv=none; d=google.com; s=arc-20160816; b=NITtnaV2puxnUdA0jvXfnH6zql6VRV4JkvaW8RnEaLPvj0ByRCbn216/3wMxZPbA/D YcRq7b9atDkFyRcRpvpr6OIW47j8J/Iqx+4hsATrOy3aCiRzCy0c51h8315a7746jnB2 iz5f0jQbRgJN3+HJEXOpZ0cUbrxBMzsmi0xgHFdGsAR5bUiS22I5PNS5zDa7OlZIncHz g3cfOhw7cvo1xnmEmQZXKmmyaEV3uTmtRqZv4ZLfGYYwVNmOtxF18+WQ+ggHuHjZ7ohm oIHqoZz0TnCCjCrTnCGsx9fUsjQhnUYWXng8gmVsHzSNBGemydLcQA3HHOfXXZb8kGMg EujQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=zxekaofA8SsvYhxmMw6uCHJXftwH5isR3gL+GxTgsaI=; b=CJqCKQ4WnaG82TKBfc/1GPskJQEG4Kgeg934tduwhzgf3YQRDjsL4yAmG0TxsBibkn CZziPCmnrWvg97cU4AP1jwBYYhSXnTrgFqjEtap0jvJRlReIaqwEvFtjJGmsntbrjiOd TvggrAlgdfU92EThOZ+72G9QALounSKUwfY/xPA5bSQe5OnkCkWAddJ7yXDZSSqvreG+ uTEUC+WxkOgJyN/TB/4vzG9Om3TUjLGaEEE5fFMnGFFVUnPAm1WbvOX4uu/+6cW0W/VC /w89pfidLMep3iGRqWalx1z9F4pXh+PN4PZX8RLb4bs2RjFBAT09a72zT+cHpMMONbeS FFqw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h68si1272361pfc.73.2017.06.07.02.16.58; Wed, 07 Jun 2017 02:16:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751818AbdFGJQu (ORCPT + 25 others); Wed, 7 Jun 2017 05:16:50 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6882 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751572AbdFGJQs (ORCPT ); Wed, 7 Jun 2017 05:16:48 -0400 Received: from 172.30.72.53 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOX19766; Wed, 07 Jun 2017 17:16:34 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Wed, 7 Jun 2017 17:16:20 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v3 2/3] PCI: Enable PCIe Relaxed Ordering if supported Date: Wed, 7 Jun 2017 17:16:07 +0800 Message-ID: <1496826968-10152-3-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1496826968-10152-1-git-send-email-dingtianhong@huawei.com> References: <1496826968-10152-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.5937C472.015E, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 90404358deddb78e9d2283886c0d55d6 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The PCIe Device Control Register use the bit 4 to indicate that whether the device is permitted to enable relaxed ordering or not. But relaxed ordering is not safe for some platform which could only use strong write ordering, so devices are allowed (but not required) to enable relaxed ordering bit by default. If a PCIe device didn't enable the relaxed ordering attribute default, we should not do anything in the PCIe configuration, otherwise we should check if any of the devices above us do not support relaxed ordering by the PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag, then base on the result if we get a return that indicate that the relaxed ordering is not supported we should update our device to disable relaxed ordering in configuration space. If the device above us doesn't exist or isn't the PCIe device, we shouldn't do anything and skip updating relaxed ordering because we are probably running in a guest. Signed-off-by: Ding Tianhong --- drivers/pci/pci.c | 29 +++++++++++++++++++++++++++++ drivers/pci/probe.c | 43 +++++++++++++++++++++++++++++++++++++++++++ include/linux/pci.h | 2 ++ 3 files changed, 74 insertions(+) -- 1.9.0 diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b01bd5b..3d42b38 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4878,6 +4878,35 @@ int pcie_set_mps(struct pci_dev *dev, int mps) EXPORT_SYMBOL(pcie_set_mps); /** + * pcie_clear_relaxed_ordering - clear PCI Express relexed ordering bit + * @dev: PCI device to query + * + * If possible clear relaxed ordering + */ +int pcie_clear_relaxed_ordering(struct pci_dev *dev) +{ + return pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_RELAX_EN); +} +EXPORT_SYMBOL(pcie_clear_relaxed_ordering); + +/** + * pcie_get_relaxed_ordering - check PCI Express relexed ordering bit + * @dev: PCI device to query + * + * Returns true if relaxed ordering is been set + */ +int pcie_get_relaxed_ordering(struct pci_dev *dev) +{ + u16 v; + + pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); + + return (v & PCI_EXP_DEVCTL_RELAX_EN) >> 4; +} +EXPORT_SYMBOL(pcie_get_relaxed_ordering); + +/** * pcie_get_minimum_link - determine minimum link settings of a PCI device * @dev: PCI device to query * @speed: storage for minimum speed diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 19c8950..0c94c80 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1701,6 +1701,48 @@ static void pci_configure_extended_tags(struct pci_dev *dev) PCI_EXP_DEVCTL_EXT_TAG); } +/** + * pci_dev_disable_relaxed_ordering - check if the PCI device + * should disable the relaxed ordering attribute. + * @dev: PCI device + * + * Return true if any of the PCI devices above us do not support + * relaxed ordering. + */ +static int pci_dev_disable_relaxed_ordering(struct pci_dev *dev) +{ + int ro_disabled = 0; + + while(dev) { + if (dev->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { + ro_disabled = 1; + break; + } + dev = dev->bus->self; + } + + return ro_disabled; +} + +static void pci_configure_relaxed_ordering(struct pci_dev *dev) +{ + struct pci_dev *bridge = pci_upstream_bridge(dev); + int origin_ero; + + if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge)) + return; + + origin_ero = pcie_get_relaxed_ordering(dev); + /* If the releaxed ordering enable bit is not set, do nothing. */ + if (!origin_ero) + return; + + if (pci_dev_disable_relaxed_ordering(dev)) { + pcie_clear_relaxed_ordering(dev); + dev_info(&dev->dev, "Disable Relaxed Ordering\n"); + } +} + static void pci_configure_device(struct pci_dev *dev) { struct hotplug_params hpp; @@ -1708,6 +1750,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_mps(dev); pci_configure_extended_tags(dev); + pci_configure_relaxed_ordering(dev); memset(&hpp, 0, sizeof(hpp)); ret = pci_get_hp_params(dev, &hpp); diff --git a/include/linux/pci.h b/include/linux/pci.h index e1e8428..299d2f3 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1105,6 +1105,8 @@ int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, void pci_pme_wakeup_bus(struct pci_bus *bus); void pci_d3cold_enable(struct pci_dev *dev); void pci_d3cold_disable(struct pci_dev *dev); +int pcie_clear_relaxed_ordering(struct pci_dev *dev); +int pcie_get_relaxed_ordering(struct pci_dev *dev); static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) From patchwork Wed Jun 7 09:16:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ding Tianhong X-Patchwork-Id: 103225 Delivered-To: patch@linaro.org Received: by 10.140.91.77 with SMTP id y71csp1834732qgd; Wed, 7 Jun 2017 02:17:38 -0700 (PDT) X-Received: by 10.99.175.19 with SMTP id w19mr31379970pge.67.1496827058616; Wed, 07 Jun 2017 02:17:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1496827058; cv=none; d=google.com; s=arc-20160816; b=GCnYD33IyWZdUlXDrj8GIL7RsZFr6CI5N+yAUWDi9E7wn+LGfLztcj5imfiieBY5dO hqqYXrxYZM7I5uQRp5le5XLASkV/gLROUM26R+n7btuhIwGN8wi4q7ffQ9HFDwECWXpS kiSRqHLu67OGLBb10cWZEWxRo/Ahf2VF9Mb5PfBuISmfGFLw/+f4Y6K42zlRa9/JFq9c wyeWjipG1ZSqzk6PFNXFa+q5dPD8KdmgqMaEAndLxHt172Z6F6IteDdZH6w+xudtjhrd PHWI4XmlCXgJytnjBO55fsLmWXyrrmxncuZc5KyYJObNVaQMd3zX9CWddFM08CgJ7lUD RDfg== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id w1si1248177plk.360.2017.06.07.02.17.38; Wed, 07 Jun 2017 02:17:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751878AbdFGJRV (ORCPT + 25 others); Wed, 7 Jun 2017 05:17:21 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:6879 "EHLO szxga02-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751826AbdFGJQz (ORCPT ); Wed, 7 Jun 2017 05:16:55 -0400 Received: from 172.30.72.53 (EHLO DGGEML404-HUB.china.huawei.com) ([172.30.72.53]) by dggrg02-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id AOX19764; Wed, 07 Jun 2017 17:16:34 +0800 (CST) Received: from localhost (10.177.23.32) by DGGEML404-HUB.china.huawei.com (10.3.17.39) with Microsoft SMTP Server id 14.3.301.0; Wed, 7 Jun 2017 17:16:22 +0800 From: Ding Tianhong To: , , , , , , , , , , , , , , , , , , , , , , , CC: Ding Tianhong Subject: [PATCH v3 3/3] net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag Date: Wed, 7 Jun 2017 17:16:08 +0800 Message-ID: <1496826968-10152-4-git-send-email-dingtianhong@huawei.com> X-Mailer: git-send-email 1.8.5.2.msysgit.0 In-Reply-To: <1496826968-10152-1-git-send-email-dingtianhong@huawei.com> References: <1496826968-10152-1-git-send-email-dingtianhong@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.23.32] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020204.5937C472.00F5, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: f17c60bf0664642c4b2280ebb9e18b03 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Casey Leedom cxgb4 Ethernet driver now queries Root Complex Port to determine if it can send TLPs to it with the Relaxed Ordering Attribute set. Signed-off-by: Casey Leedom Signed-off-by: Ding Tianhong --- drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 + drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 17 +++++++++++++++++ drivers/net/ethernet/chelsio/cxgb4/sge.c | 5 +++-- 3 files changed, 21 insertions(+), 2 deletions(-) -- 1.9.0 diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h index e88c180..478f25a 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h @@ -521,6 +521,7 @@ enum { /* adapter flags */ USING_SOFT_PARAMS = (1 << 6), MASTER_PF = (1 << 7), FW_OFLD_CONN = (1 << 9), + ROOT_NO_RELAXED_ORDERING = (1 << 10), }; enum { diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c index 38a5c67..fbfe341 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c @@ -4628,6 +4628,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) #ifdef CONFIG_PCI_IOV u32 v, port_vec; #endif + struct pci_dev *root; printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); @@ -4726,6 +4727,22 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) adapter->msg_enable = DFLT_MSG_ENABLE; memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); + /* If possible, we use PCIe Relaxed Ordering Attribute to deliver + * Ingress Packet Data to Free List Buffers in order to allow for + * chipset performance optimizations between the Root Complex and + * Memory Controllers. (Messages to the associated Ingress Queue + * notifying new Packet Placement in the Free Lists Buffers will be + * send without the Relaxed Ordering Attribute thus guaranteing that + * all preceding PCIe Transaction Layer Packets will be processed + * first.) But some Root Complexes have various issues with Upstream + * Transaction Layer Packets with the Relaxed Ordering Attribute set. + * So we check our Root Complex to see if it's flaged with advice + * against using Relaxed Ordering. + */ + root = pci_find_pcie_root_port(adapter->pdev); + if (pcie_get_relaxed_ordering(root)) + adapter->flags |= ROOT_NO_RELAXED_ORDERING; + spin_lock_init(&adapter->stats_lock); spin_lock_init(&adapter->tid_release_lock); spin_lock_init(&adapter->win0_lock); diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c index f05f0d4..ac229a3 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/sge.c +++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c @@ -2571,6 +2571,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, struct fw_iq_cmd c; struct sge *s = &adap->sge; struct port_info *pi = netdev_priv(dev); + int relaxed = !(adap->flags & ROOT_NO_RELAXED_ORDERING); /* Size needs to be multiple of 16, including status entry. */ iq->size = roundup(iq->size, 16); @@ -2624,8 +2625,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc); c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F | - FW_IQ_CMD_FL0FETCHRO_F | - FW_IQ_CMD_FL0DATARO_F | + FW_IQ_CMD_FL0FETCHRO_V(relaxed) | + FW_IQ_CMD_FL0DATARO_V(relaxed) | FW_IQ_CMD_FL0PADEN_F); if (cong >= 0) c.iqns_to_fl0congen |=