From patchwork Wed Aug 30 11:15:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 718706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2426DC83F19 for ; Wed, 30 Aug 2023 18:35:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231760AbjH3SfW (ORCPT ); Wed, 30 Aug 2023 14:35:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243626AbjH3LPy (ORCPT ); Wed, 30 Aug 2023 07:15:54 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3537FF; Wed, 30 Aug 2023 04:15:48 -0700 (PDT) X-UUID: 8f672978472611ee9cb5633481061a41-20230830 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Kx18OaMeSf/qqPXTnSVp7waI99i5GCj1DfBGCDQUU34=; b=DcVz7Tvcd7vuEFZ/6K8LFr5FmdIxV+QJfvEeihqbh93U4Rs3OhYgiWN+ODFV/ID1kdyfA9r1Vfp8ZUE9YNKftC+YZyNV0o4t08/VBgePB9GOQC2w43oAfHaSJJ+SSo8SnpNW3XtDsSbp5QwzJV860Fx0GLyBIZ1F20UYfVzezgY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31, REQID:890231fa-c6e1-41ee-a6a1-c6104b36664e, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4, CLOUDID:dd8a72c2-1e57-4345-9d31-31ad9818b39f, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 8f672978472611ee9cb5633481061a41-20230830 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1252000189; Wed, 30 Aug 2023 19:15:43 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 30 Aug 2023 19:15:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 30 Aug 2023 19:15:42 +0800 From: Macpaul Lin To: Alexandre Mergnat , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Fabien Parent , Macpaul Lin , , , , CC: Bear Wang , Pablo Sun , Macpaul Lin , Chunfeng Yun , Subject: [PATCH v2 1/4] arm64: dts: mediatek: mt8195-demo: fix the memory size to 8GB Date: Wed, 30 Aug 2023 19:15:29 +0800 Message-ID: <20230830111532.9048-1-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230825114623.16884-1-macpaul.lin@mediatek.com> References: <20230825114623.16884-1-macpaul.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The onboard dram of mt8195-demo board is 8GB. Cc: stable@vger.kernel.org # 6.1, 6.4 Fixes: 6147314aeedc ("arm64: dts: mediatek: Add device-tree for MT8195 Demo board") Signed-off-by: Macpaul Lin --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Changes for v2: - No change. diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index b2485ddfd33b..ff363ab925e9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -48,7 +48,7 @@ memory@40000000 { device_type = "memory"; - reg = <0 0x40000000 0 0x80000000>; + reg = <0 0x40000000 0x2 0x00000000>; }; reserved-memory { From patchwork Wed Aug 30 11:15:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 719259 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4312C83F19 for ; Wed, 30 Aug 2023 18:34:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237226AbjH3SeB (ORCPT ); Wed, 30 Aug 2023 14:34:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47230 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243624AbjH3LPw (ORCPT ); Wed, 30 Aug 2023 07:15:52 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C1CBCC9; Wed, 30 Aug 2023 04:15:48 -0700 (PDT) X-UUID: 8f6926c4472611ee9cb5633481061a41-20230830 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=v0S2k/hBUnuQV7cp1XuI6rFZDG90LyG06RmcSzH+9GM=; b=onUeuCqvQxBgp357i919yCKkd14rYsJrqxHMXjp4N5ZIF/MHADwVOLoXpe+nky5iRxL/j0PSPCjqVr5DLJMpszXYCAnffbcl7xqmkjrC6jh9keK24qCJAVeBTn90nOWcRkkAwLOPrDAKGYq/zcYvzIucaF3PK6nYGrlvV1/c/nU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.31, REQID:748fc6e1-c862-4ec4-a14e-7b8c0f5a19ad, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:0ad78a4, CLOUDID:37295c13-4929-4845-9571-38c601e9c3c9, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 8f6926c4472611ee9cb5633481061a41-20230830 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1771266018; Wed, 30 Aug 2023 19:15:43 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 30 Aug 2023 19:15:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 30 Aug 2023 19:15:42 +0800 From: Macpaul Lin To: Alexandre Mergnat , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Fabien Parent , Macpaul Lin , , , , CC: Bear Wang , Pablo Sun , Macpaul Lin , Chunfeng Yun , Subject: [PATCH v2 2/4] arm64: dts: mediatek: mt8195-demo: update and reorder reserved memory regions Date: Wed, 30 Aug 2023 19:15:30 +0800 Message-ID: <20230830111532.9048-2-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230830111532.9048-1-macpaul.lin@mediatek.com> References: <20230825114623.16884-1-macpaul.lin@mediatek.com> <20230830111532.9048-1-macpaul.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The dts file of the MediaTek MT8195 demo board has been updated to include new reserved memory regions. These reserved memory regions are: - SCP - VPU, - Sound DMA - APU. These regions are defined with the "shared-dma-pool" compatible property. In addition, the existing reserved memory regions have been reordered by their addresses to improve readability and maintainability of the DTS file. Cc: stable@vger.kernel.org # 6.1, 6.4 Fixes: e4a417520101 ("arm64: dts: mediatek: mt8195-demo: fix the memory size of node secmon") Signed-off-by: Macpaul Lin --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 38 ++++++++++++++++---- 1 file changed, 32 insertions(+), 6 deletions(-) Changes for v2: - No change. diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index ff363ab925e9..8aea6f5d72b3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -56,12 +56,6 @@ #size-cells = <2>; ranges; - /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ - bl31_secmon_reserved: secmon@54600000 { - no-map; - reg = <0 0x54600000 0x0 0x200000>; - }; - /* 12 MiB reserved for OP-TEE (BL32) * +-----------------------+ 0x43e0_0000 * | SHMEM 2MiB | @@ -75,6 +69,38 @@ no-map; reg = <0 0x43200000 0 0x00c00000>; }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + vpu_mem: memory@53000000 { + compatible = "shared-dma-pool"; + size = <0 0x1400000>; /* 20 MB */ + alignment = <0 0x10000>; + reg = <0 0x53000000 0 0x1400000>; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_mem: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + snd_dma_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0x1100000>; + no-map; + }; + + apu_mem: memory@62000000 { + compatible = "shared-dma-pool"; + size = <0 0x1400000>; /* 20 MB */ + alignment = <0 0x10000>; + reg = <0 0x62000000 0 0x1400000>; + }; }; }; From patchwork Wed Aug 30 11:15:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 719258 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EEF6C83F1F for ; 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Wed, 30 Aug 2023 19:15:42 +0800 From: Macpaul Lin To: Alexandre Mergnat , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Fabien Parent , Macpaul Lin , , , , CC: Bear Wang , Pablo Sun , Macpaul Lin , Chunfeng Yun Subject: [PATCH v2 3/4] arm64: dts: mediatek: mt6360: add PMIC MT6360 related nodes Date: Wed, 30 Aug 2023 19:15:31 +0800 Message-ID: <20230830111532.9048-3-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230830111532.9048-1-macpaul.lin@mediatek.com> References: <20230825114623.16884-1-macpaul.lin@mediatek.com> <20230830111532.9048-1-macpaul.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MT6360 is the secondary PMIC for MT8195. It supports USB Type-C and PD functions. Add MT6360 related common nodes which is used for MT8195 platform, includes - charger - ADC - LED - regulators Signed-off-by: Macpaul Lin --- arch/arm64/boot/dts/mediatek/mt6360.dtsi | 85 ++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6360.dtsi Change for v2: - Remove the following properties according to Chen-Yu Tsai's suggestion - regulator-name - regulator-min-microvolt - regulator-max-microvolt diff --git a/arch/arm64/boot/dts/mediatek/mt6360.dtsi b/arch/arm64/boot/dts/mediatek/mt6360.dtsi new file mode 100644 index 000000000000..a89fd43d0f1f --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6360.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + */ + +#include + +&mt6360 { + interrupt-controller; + interrupt-parent = <&pio>; + interrupt-names = "IRQB"; + + charger { + compatible = "mediatek,mt6360-chg"; + richtek,vinovp-microvolt = <14500000>; + + otg_vbus_regulator: usb-otg-vbus-regulator { + regulator-compatible = "usb-otg-vbus"; + }; + }; + + adc { + compatible = "mediatek,mt6360-adc"; + #io-channel-cells = <1>; + }; + + led { + compatible = "mediatek,mt6360-led"; + }; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN3-supply = <&mt6360_emi_vddq_buck2_reg>; + + mt6360_emi_vdd2_buck1_reg: buck1-emi-vdd2 { + regulator-compatible = "BUCK1"; + regulator-allowed-modes = ; + }; + + mt6360_emi_vddq_buck2_reg: buck2-emi-vddq { + regulator-compatible = "BUCK2"; + regulator-allowed-modes = ; + }; + + mt6360_tp1_p3v0_ldo1_reg: ldo1-tp1-p3v0 { + regulator-compatible = "LDO1"; + regulator-allowed-modes = ; + }; + + mt6360_panel1_p1v8_ldo2_reg: ldo2-panel1-p1v8 { + regulator-compatible = "LDO2"; + regulator-allowed-modes = ; + }; + + mt6360_vmc_pmu_ldo3_reg: ldo3-vmc-pmu { + regulator-compatible = "LDO3"; + regulator-allowed-modes = ; + }; + + mt6360_vmch_pmu_ldo5_reg: ldo5-vmch-pmu { + regulator-compatible = "LDO5"; + regulator-allowed-modes = ; + }; + + mt6360_ldo6_reg: ldo6-mt6360 { + regulator-compatible = "LDO6"; + regulator-allowed-modes = ; + }; + + mt6360_emi_vmddr_en_ldo7_reg: ldo7-emi-vmddr-en { + regulator-compatible = "LDO7"; + regulator-allowed-modes = ; + }; + }; +}; From patchwork Wed Aug 30 11:15:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 718712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77004C83F1A for ; Wed, 30 Aug 2023 18:34:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235143AbjH3Sep (ORCPT ); Wed, 30 Aug 2023 14:34:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243625AbjH3LPy (ORCPT ); Wed, 30 Aug 2023 07:15:54 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1ADC51BB; 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Wed, 30 Aug 2023 19:15:44 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 30 Aug 2023 19:15:42 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 30 Aug 2023 19:15:42 +0800 From: Macpaul Lin To: Alexandre Mergnat , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Fabien Parent , Macpaul Lin , , , , CC: Bear Wang , Pablo Sun , Macpaul Lin , Chunfeng Yun Subject: [PATCH v2 4/4] arm64: dts: mediatek: mt8195-demo: simplify mt6360 nodes Date: Wed, 30 Aug 2023 19:15:32 +0800 Message-ID: <20230830111532.9048-4-macpaul.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20230830111532.9048-1-macpaul.lin@mediatek.com> References: <20230825114623.16884-1-macpaul.lin@mediatek.com> <20230830111532.9048-1-macpaul.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The dts file for the MediaTek MT8195 demo board has been refactored to improve the configuration of the MT6360 multi-function PMIC. The changes include: - Addition of the mt6360.dtsi include file, which contains the common configuration of the MT6360 for all mt8195 boards. - Removal of the direct inclusion of the mt6360-regulator.h file. - Removal of the common configuration of the MT6360 PMIC since the included mt6360.dtsi is used. - Add names according to the schematic of mt8195-demo board for mt6360 nodes. Signed-off-by: Macpaul Lin --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 173 ++++++++----------- 1 file changed, 74 insertions(+), 99 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index 8aea6f5d72b3..d082d679dbbe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -11,7 +11,6 @@ #include #include #include -#include / { model = "MediaTek MT8195 demo board"; @@ -130,103 +129,9 @@ mt6360: pmic@34 { compatible = "mediatek,mt6360"; reg = <0x34>; - interrupt-controller; + pinctrl-0 = <&mt6360_pins>; + pinctrl-names = "default"; interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; - interrupt-names = "IRQB"; - - charger { - compatible = "mediatek,mt6360-chg"; - richtek,vinovp-microvolt = <14500000>; - - otg_vbus_regulator: usb-otg-vbus-regulator { - regulator-compatible = "usb-otg-vbus"; - regulator-name = "usb-otg-vbus"; - regulator-min-microvolt = <4425000>; - regulator-max-microvolt = <5825000>; - }; - }; - - regulator { - compatible = "mediatek,mt6360-regulator"; - LDO_VIN3-supply = <&mt6360_buck2>; - - mt6360_buck1: buck1 { - regulator-compatible = "BUCK1"; - regulator-name = "mt6360,buck1"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1300000>; - regulator-allowed-modes = ; - regulator-always-on; - }; - - mt6360_buck2: buck2 { - regulator-compatible = "BUCK2"; - regulator-name = "mt6360,buck2"; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1300000>; - regulator-allowed-modes = ; - regulator-always-on; - }; - - mt6360_ldo1: ldo1 { - regulator-compatible = "LDO1"; - regulator-name = "mt6360,ldo1"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-allowed-modes = ; - }; - - mt6360_ldo2: ldo2 { - regulator-compatible = "LDO2"; - regulator-name = "mt6360,ldo2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-allowed-modes = ; - }; - - mt6360_ldo3: ldo3 { - regulator-compatible = "LDO3"; - regulator-name = "mt6360,ldo3"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <3600000>; - regulator-allowed-modes = ; - }; - - mt6360_ldo5: ldo5 { - regulator-compatible = "LDO5"; - regulator-name = "mt6360,ldo5"; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3600000>; - regulator-allowed-modes = ; - }; - - mt6360_ldo6: ldo6 { - regulator-compatible = "LDO6"; - regulator-name = "mt6360,ldo6"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2100000>; - regulator-allowed-modes = ; - }; - - mt6360_ldo7: ldo7 { - regulator-compatible = "LDO7"; - regulator-name = "mt6360,ldo7"; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <2100000>; - regulator-allowed-modes = ; - regulator-always-on; - }; - }; }; }; @@ -259,8 +164,8 @@ cap-sd-highspeed; sd-uhs-sdr50; sd-uhs-sdr104; - vmmc-supply = <&mt6360_ldo5>; - vqmmc-supply = <&mt6360_ldo3>; + vmmc-supply = <&mt6360_vmch_pmu_ldo5_reg>; + vqmmc-supply = <&mt6360_vmc_pmu_ldo3_reg>; status = "okay"; }; @@ -300,6 +205,67 @@ regulator-always-on; }; +#include "mt6360.dtsi" + +&otg_vbus_regulator { + regulator-name = "usb-otg-vbus"; + regulator-min-microvolt = <4425000>; + regulator-max-microvolt = <5825000>; +}; + +&mt6360_emi_vdd2_buck1_reg { + regulator-name = "emi_vdd2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; +}; + +&mt6360_emi_vddq_buck2_reg { + regulator-name = "emi_vddq"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; +}; + +&mt6360_tp1_p3v0_ldo1_reg { + regulator-name = "tp1_p3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; +}; + +&mt6360_panel1_p1v8_ldo2_reg { + regulator-name = "panel1_p1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&mt6360_vmc_pmu_ldo3_reg { + regulator-name = "vmc_pmu"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; +}; + +&mt6360_vmch_pmu_ldo5_reg { + regulator-name = "vmch_pmu"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; +}; + +/* measure point on board */ +&mt6360_ldo6_reg { + regulator-name = "mt6360_ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; +}; + +&mt6360_emi_vmddr_en_ldo7_reg { + regulator-name = "emi_vmddr_en"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; +}; + &pio { eth_default_pins: eth-default-pins { pins-txd { @@ -496,6 +462,15 @@ ; }; }; + + mt6360_pins: mt6360-pins { + pins { + pinmux = , + ; + input-enable; + bias-pull-up; + }; + }; };