From patchwork Tue Aug 29 23:23:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718268 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp244829wrh; Tue, 29 Aug 2023 16:29:44 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE2NeyADzi8Zhunbng/haTN0O4irUos1UX8JygvOWfHfn0q4GEQ9LBxjv0a2ieuNsXPRyMr X-Received: by 2002:a05:622a:550:b0:40b:5ab9:5bac with SMTP id m16-20020a05622a055000b0040b5ab95bacmr550726qtx.43.1693351783882; Tue, 29 Aug 2023 16:29:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351783; cv=none; d=google.com; s=arc-20160816; b=R+V++MMPocILzhsL6v8FTlh+XnnfvZ9v3khExA6YoRH0diQkH+PDhXF6xlP8woWDXH ZzNhx4QFrXFhZ1dJT4HXOvd7ufs/LMo7IWavSxJFNtClEDWmYS9JCv+GJBddaBsdZKIP d4pa3f/OhUs7Y63svYHikWCosVOe1B2aId2ilNttbGQ6+p03XbrVDuoJxyX/5seBGvC+ M+7y83J42F2ah/R3CwDtyI62NFy3g2u/usxKc5amRmiFy4yvGs+9vbUuTVM+Crfc8Yw8 0T+CKajBi/LmTJssIoj2ua/haufhTjuhM3iQVXWREhy1E9guTZB0JWfSdfChIeDwvFK6 loQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GOQxCV2ZeNNpKDkyg+BAXzxnOS5aPcNG/SXJ9WibMEs=; fh=L6OjQZ2TPsHFQEGPRBuboSqhQBavDZ5pPqlyX67xn3A=; b=JvB2AHuWPzwVV0F+AEM7FX2j8QD7po17d1N4+0W7qXUBaHicQjW/DFH1iSKqE5pOvx gXWRPjf0C3+b6t/4dWPGyOJqDJvO18jqVEbl/YwqJNvxeqdIr0iSMODnM0ksyoRwrjJ1 KJXTl+2dMCXi49kRc5QMTFHjXbeAASlzY+4aRYX9l83Nq4K0lJrbCpf4MXu2Lo+/9iow bsBa919FL55p0tfiB8MrLYoHcz9zFncVkynkMqRh4tXsGr+6+usoXadIxvitSbVQ9Bob +aZQS9h5LldCDTPUxXtiaf/9pBC/XNx1U+eaEsgzCegCIihw/DG2ZfphSIQmkBl51dcK HYhQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y4WCu8KI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ox1-20020a05620a828100b00766fce24242si6520355qkn.135.2023.08.29.16.29.43 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:29:43 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y4WCu8KI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83n-0003Mt-2L; Tue, 29 Aug 2023 19:23:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83k-00035T-K3 for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:44 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83f-0001Ls-Gx for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:44 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-68a4bcf8a97so3226329b3a.1 for ; Tue, 29 Aug 2023 16:23:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351418; x=1693956218; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GOQxCV2ZeNNpKDkyg+BAXzxnOS5aPcNG/SXJ9WibMEs=; b=y4WCu8KIwponZSD6lMaiZw81ljVaXROBXBJD26OHL/SracIS+zrYw/7UBFygAL4TtD iHDv1f8aJKepPLzBmbWRzDPy5gcgwTTt3Xo3PCfKLGnPpLTVhUpMD21kSbLqenHpAFxb rvVe7HcNAl9eyFZbKH7qj2NYtfvEB8Jh4lUil0+gH+JNBVIBSTaX+AAZAvycQwfFN/E2 DXiPXu0BbeuuZLpq+m0RwXwnzcyGpf9eNHzZlhy8gfd2Mm2Oh3XW/wDcPpimOJpppW2N 9OCyomXY437Ohk/hQO/aAs2tPn+fhkyJdd4vwtC0NbIsTiiurR9rtOieBKH8YEdMzwYm fzcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351418; x=1693956218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GOQxCV2ZeNNpKDkyg+BAXzxnOS5aPcNG/SXJ9WibMEs=; b=HTq49fy692DVRqxUZCoXb8CSnAjg13heKZC7QlHbL7MG5B10tGMVJ8cDQIbEMcsGby SrDGVYEs9lmTRsKrKC76Y1QHxnmQL0kqxJ/ANb03E/oQpP3QjMQLy/Puw+9o67HMDNr2 8O87ptpzwQ0veEuZSarPtLiK0n40s3RHdS2KHzAsFIk0yYelzdbfbQ0780egEN0IEB8C W/VT9Arc0H7AdExwek3NPpYSDe5+FDe+GwNb9H9HewtKYevmyiKUs9FOWhJg5ZEr/Tzg 3g+Ujtl+lwds7ZkMQ+RRxKmZXJznEeiqBx1AJGGz00hKG85adau7bfVzq9gXxdrf2VO+ Da/w== X-Gm-Message-State: AOJu0YyIXuj3SePwIfAr/7BjAPnLvi8QhkTNAKx6QVqiH6lwhoLJRVcy +d8BkMkgABoVQeDOFNah8GqyHULjje925Vujibo= X-Received: by 2002:a05:6a20:3954:b0:137:e595:830f with SMTP id r20-20020a056a20395400b00137e595830fmr876263pzg.57.1693351418016; Tue, 29 Aug 2023 16:23:38 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 01/12] tests/tcg/aarch64: Adjust pauth tests for FEAT_FPAC Date: Tue, 29 Aug 2023 16:23:24 -0700 Message-Id: <20230829232335.965414-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org With FEAT_FPAC, AUT* instructions that fail authentication do not produce an error value but instead fault. For pauth-2, install a signal handler and verify it gets called. For pauth-4 and pauth-5, we are explicitly testing the error value, so there's nothing to test with FEAT_FPAC, so exit early. Adjust the makefile to use -cpu neoverse-v1, which has FEAT_EPAC but not FEAT_FPAC. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tests/tcg/aarch64/pauth.h | 23 +++++++++++++ tests/tcg/aarch64/pauth-2.c | 54 ++++++++++++++++++++++++++----- tests/tcg/aarch64/pauth-4.c | 18 ++++++++--- tests/tcg/aarch64/pauth-5.c | 10 ++++++ tests/tcg/aarch64/Makefile.target | 6 +++- 5 files changed, 98 insertions(+), 13 deletions(-) create mode 100644 tests/tcg/aarch64/pauth.h diff --git a/tests/tcg/aarch64/pauth.h b/tests/tcg/aarch64/pauth.h new file mode 100644 index 0000000000..543b234437 --- /dev/null +++ b/tests/tcg/aarch64/pauth.h @@ -0,0 +1,23 @@ +/* + * Helper for pauth test case + * + * Copyright (c) 2023 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +static int get_pac_feature(void) +{ + unsigned long isar1, isar2; + + assert(getauxval(AT_HWCAP) & HWCAP_CPUID); + + asm("mrs %0, id_aa64isar1_el1" : "=r"(isar1)); + asm("mrs %0, S3_0_C0_C6_2" : "=r"(isar2)); /* id_aa64isar2_el1 */ + + return ((isar1 >> 4) & 0xf) /* APA */ + | ((isar1 >> 8) & 0xf) /* API */ + | ((isar2 >> 12) & 0xf); /* APA3 */ +} diff --git a/tests/tcg/aarch64/pauth-2.c b/tests/tcg/aarch64/pauth-2.c index 978652ede3..89ffdbf1df 100644 --- a/tests/tcg/aarch64/pauth-2.c +++ b/tests/tcg/aarch64/pauth-2.c @@ -1,5 +1,22 @@ #include +#include +#include #include +#include "pauth.h" + + +static void sigill(int sig, siginfo_t *info, void *vuc) +{ + ucontext_t *uc = vuc; + uint64_t test; + + /* There is only one insn below that is allowed to fault. */ + asm volatile("adr %0, auth2_insn" : "=r"(test)); + assert(test == uc->uc_mcontext.pc); + exit(0); +} + +static int pac_feature; void do_test(uint64_t value) { @@ -27,31 +44,52 @@ void do_test(uint64_t value) * An invalid salt usually fails authorization, but again there * is a chance of choosing another salt that works. * Iterate until we find another salt which does fail. + * + * With FEAT_FPAC, this will SIGILL instead of producing a result. */ for (salt2 = salt1 + 1; ; salt2++) { - asm volatile("autda %0, %2" : "=r"(decode) : "0"(encode), "r"(salt2)); + asm volatile("auth2_insn: autda %0, %2" + : "=r"(decode) : "0"(encode), "r"(salt2)); if (decode != value) { break; } } + assert(pac_feature < 4); /* No FEAT_FPAC */ + /* The VA bits, bit 55, and the TBI bits, should be unchanged. */ assert(((decode ^ value) & 0xff80ffffffffffffull) == 0); /* - * Bits [54:53] are an error indicator based on the key used; - * the DA key above is keynumber 0, so error == 0b01. Otherwise - * bit 55 of the original is sign-extended into the rest of the auth. + * Without FEAT_Pauth2, bits [54:53] are an error indicator based on + * the key used; the DA key above is keynumber 0, so error == 0b01. + * Otherwise, bit 55 of the original is sign-extended into the rest + * of the auth. */ - if ((value >> 55) & 1) { - assert(((decode >> 48) & 0xff) == 0b10111111); - } else { - assert(((decode >> 48) & 0xff) == 0b00100000); + if (pac_feature < 3) { + if ((value >> 55) & 1) { + assert(((decode >> 48) & 0xff) == 0b10111111); + } else { + assert(((decode >> 48) & 0xff) == 0b00100000); + } } } int main() { + static const struct sigaction sa = { + .sa_sigaction = sigill, + .sa_flags = SA_SIGINFO + }; + + pac_feature = get_pac_feature(); + assert(pac_feature != 0); + + if (pac_feature >= 4) { + /* FEAT_FPAC */ + sigaction(SIGILL, &sa, NULL); + } + do_test(0); do_test(0xda004acedeadbeefull); return 0; diff --git a/tests/tcg/aarch64/pauth-4.c b/tests/tcg/aarch64/pauth-4.c index 24a639e36c..b254f413af 100644 --- a/tests/tcg/aarch64/pauth-4.c +++ b/tests/tcg/aarch64/pauth-4.c @@ -2,14 +2,24 @@ #include #include #include +#include "pauth.h" #define TESTS 1000 int main() { + char base[TESTS]; int i, count = 0; float perc; - void *base = malloc(TESTS); + int pac_feature = get_pac_feature(); + + /* + * Exit if no PAuth or FEAT_FPAC, which will SIGILL on AUTIA failure + * rather than return an error for us to check below. + */ + if (pac_feature == 0 || pac_feature >= 4) { + return 0; + } for (i = 0; i < TESTS; i++) { uintptr_t in, x, y; @@ -17,7 +27,7 @@ int main() in = i + (uintptr_t) base; asm("mov %0, %[in]\n\t" - "pacia %0, sp\n\t" /* sigill if pauth not supported */ + "pacia %0, sp\n\t" "eor %0, %0, #4\n\t" /* corrupt single bit */ "mov %1, %0\n\t" "autia %1, sp\n\t" /* validate corrupted pointer */ @@ -36,10 +46,10 @@ int main() if (x != y) { count++; } - } + perc = (float) count / (float) TESTS; - printf("Checks Passed: %0.2f%%", perc * 100.0); + printf("Checks Passed: %0.2f%%\n", perc * 100.0); assert(perc > 0.95); return 0; } diff --git a/tests/tcg/aarch64/pauth-5.c b/tests/tcg/aarch64/pauth-5.c index 67c257918b..ed8d5a926b 100644 --- a/tests/tcg/aarch64/pauth-5.c +++ b/tests/tcg/aarch64/pauth-5.c @@ -1,4 +1,5 @@ #include +#include "pauth.h" static int x; @@ -6,6 +7,15 @@ int main() { int *p0 = &x, *p1, *p2, *p3; unsigned long salt = 0; + int pac_feature = get_pac_feature(); + + /* + * Exit if no PAuth or FEAT_FPAC, which will SIGILL on AUTDA failure + * rather than return an error for us to check below. + */ + if (pac_feature == 0 || pac_feature >= 4) { + return 0; + } /* * With TBI enabled and a 48-bit VA, there are 7 bits of auth, and so diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 681dfa077c..1ee6309920 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -42,7 +42,11 @@ endif ifneq ($(CROSS_CC_HAS_ARMV8_3),) AARCH64_TESTS += pauth-1 pauth-2 pauth-4 pauth-5 pauth-%: CFLAGS += -march=armv8.3-a -run-pauth-%: QEMU_OPTS += -cpu max +run-pauth-1: QEMU_OPTS += -cpu max +run-pauth-2: QEMU_OPTS += -cpu max +# Choose a cpu with FEAT_Pauth but without FEAT_FPAC for pauth-[45]. +run-pauth-4: QEMU_OPTS += -cpu neoverse-v1 +run-pauth-5: QEMU_OPTS += -cpu neoverse-v1 endif # BTI Tests From patchwork Tue Aug 29 23:23:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718252 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp242997wrh; Tue, 29 Aug 2023 16:23:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG/McNBBEaI89X+s1BnVieRIf1rzE0UlNqVejR5IOZuuOeXiT3SL8Qe7iGMuka9g2OHeu5K X-Received: by 2002:a05:620a:1925:b0:76f:d8b:d6bf with SMTP id bj37-20020a05620a192500b0076f0d8bd6bfmr579657qkb.22.1693351437260; Tue, 29 Aug 2023 16:23:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351437; cv=none; d=google.com; s=arc-20160816; b=FpLTyP9g83oQOXKIcZwPtxeqAhJuOQTl/Z0OFeGtpLLdH8StXhD1SHF2ghHImOzKkQ wD+KsRmx0t6ugNZqcUBWEfJ3baWTbYqL4iPYZjSu/gG8WfqNyeH3z0Z+u9XdHsHjnAMq avr8GwxX2OLj4JQfUzfTSQpFbIuVfU5NZkNcL2GI0WjTLnGIIRNbYFHERLUpulsSiaOj acq+xXZV6aajwb00biJoIlUO+qgVGUIAoLXkS16T6yLiSFHn4URXJbf/EcfF238R+a5M wW2cuqdKtIPMqoUqFcNB/yBDlvqfPWSdT2Q5PYUbXM2CYoDVpeMDTqZEJQDc0AecXQ6k ZbBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KJs9VdlYYhcs1M3WHRYBXtRa+lFbPejqKMvTmE5WpOE=; fh=qP6S92UGCiq93e5OjzY/AAEohT0ahWfu7bb+kTROhJM=; b=cnDRx45NADbVQGpCF+pJ8lcE3/VcaWTY6zsE2PLS4IFGuTGcJ8hh85Fyd3jJw5+LVx Ibd18IAtD6AqxBGxFFAt+oSkBesibzOInGQqT4WaCEt1sJvhKK+i0O9/gOS6hFhNf9nf QxAHg52FHhPUgrK9bBQsSYaML7oYvnqQ0V9akn6a9KATF4OMbh2hcpkbxl3ExnFW4F6v DXLwcl5GQYk1PLvrZSqXm1YxaXD1Q8U+Z8am0+eCbYtfoTP9ep9wYLAWWSSVG+YBjS/y 9wHjGwt/97iWcf6jce/uA/gKdIzCFiblzJUAwMjmIFY+eBTmgRdBrrtAZpM6aYUqWtnd /1Xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TQfY7WDB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ay36-20020a05620a17a400b0076cd28ac289si4894500qkb.681.2023.08.29.16.23.57 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:23:57 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TQfY7WDB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83m-0003LL-U0; Tue, 29 Aug 2023 19:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83l-0003A1-0u for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:45 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83g-0001M4-RP for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:44 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-68a56401b9aso3641426b3a.1 for ; Tue, 29 Aug 2023 16:23:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351419; x=1693956219; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KJs9VdlYYhcs1M3WHRYBXtRa+lFbPejqKMvTmE5WpOE=; b=TQfY7WDBlbIvrNCsrBydTFY9cUvHxviWv8/O0IA/CJ2EJTh35GRfAJStIV0CLxkUKR lRFMaqu3V3dnnmpZBVDVYW1uwVJ/icTiW5YX8PJeSN0qioTnLE0MX/A43BzGR+7ABLXM tmxqb7iL7QXEDNjKhZ1/HeF6oGVil3iHitOyNbpBUs/aziWMFhKMg/SNOgVhPyo/U5fQ kIFaUoqQNndUy1ooYSSraAbM4UDnWKXQCDGXAcJuE89LKvvXFkIbNri5g2pVIMx3bJ4A JI3vdjYuBwxiWtQwg5iAuqjaFf6+tHFgZhfSV4fIdVSRQQQ5y7YWujtuEhr3rrfNeaJC zR0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351419; x=1693956219; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KJs9VdlYYhcs1M3WHRYBXtRa+lFbPejqKMvTmE5WpOE=; b=JSJBlolmB7E5snoNMoEUJz6MG5AoNntvd4Lvl0MZNUA3RsU5bWEoVvBLlgzc8JKeAY CstC5uXDDXWNr2WBfp4DOtKVuG7TJr8gO08vWVdbLtwc662YOQjo2G8zIa7kqFAF8h/i TA9R6ow7Z0viZCFA9G76ZK/nuzcUQjgGVr80ojHAHgWnIXZAFQYkTAqD+89d0g7OKLbI 08o1kYN80CYyQBPQadxQOdBGGwOPoDS431nhjTc1ufugp+JzvVD/VGDE9Khaw4SSVTUK xeRO7BZ4c5KdVnsCAe8D1WaTdiJx1CCoaknEcqSsItgEXgaCyryO2DREqwfTOI//ZaDg C/Dw== X-Gm-Message-State: AOJu0Yzbve5vviIrFM5z834EE8UdWPDzPcHCjpXuY9lBfI3H95+FxQXY CM0xCEEhYQYH9RIXsr9DQ/ZbvCXnDF07ez6UHXo= X-Received: by 2002:a05:6a20:d422:b0:13d:2f80:cf1c with SMTP id il34-20020a056a20d42200b0013d2f80cf1cmr747623pzb.17.1693351419039; Tue, 29 Aug 2023 16:23:39 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Ma?= =?utf-8?q?thieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH v5 02/12] target/arm: Add ID_AA64ISAR2_EL1 Date: Tue, 29 Aug 2023 16:23:25 -0700 Message-Id: <20230829232335.965414-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Aaron Lindsay Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Aaron Lindsay [PMM: drop the HVF part of the patch and just comment that we need to do something when the register appears in that API] Signed-off-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 1 + target/arm/kvm64.c | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cdf8600b96..4a5a5e9eb8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1033,6 +1033,7 @@ struct ArchCPU { uint32_t dbgdevid1; uint64_t id_aa64isar0; uint64_t id_aa64isar1; + uint64_t id_aa64isar2; uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; uint64_t id_aa64mmfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 85291d5b8e..b5be68be58 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8439,11 +8439,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, .resetvalue = cpu->isar.id_aa64isar1 }, - { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, + { .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST, .accessfn = access_aa64_tid3, - .resetvalue = 0 }, + .resetvalue = cpu->isar.id_aa64isar2 }, { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST, diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 486f90be1d..546c0e817f 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -847,6 +847,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, + /* Add ID_AA64ISAR2_EL1 here when HVF supports it */ { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 4d904a1d11..ac440c33f9 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -304,6 +304,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) ARM64_SYS_REG(3, 0, 0, 6, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, ARM64_SYS_REG(3, 0, 0, 6, 1)); + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2, + ARM64_SYS_REG(3, 0, 0, 6, 2)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0, ARM64_SYS_REG(3, 0, 0, 7, 0)); err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1, From patchwork Tue Aug 29 23:23:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718259 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp243651wrh; Tue, 29 Aug 2023 16:26:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGiCaaVhMEd6hK3PnWPrnf7XiesTwQZpKeeGQzBaftcDhDaD0L1WQH1ArtadCZFQiZXaHyr X-Received: by 2002:a05:6358:89b:b0:139:b4c0:94d with SMTP id m27-20020a056358089b00b00139b4c0094dmr385325rwj.12.1693351564420; Tue, 29 Aug 2023 16:26:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351564; cv=none; d=google.com; s=arc-20160816; b=f0UoiD+FUec1GcIxkvLxSkYbNKM39H2eGzT3o6Z9HC02HXvlsgMviZr0R4tQARpGtJ ak5Vloxx48qimI6neOWmhXy7XY/4dfK1cZi19Dp2fWHHOJh7MIhs61vuWc3eCTBqi8g6 jDLxEHu4BRjrk/A3iIf19VGh4afSQgXmqUc1uqaORDPBBY58F0DxQVPO4UMsjYOg2grd zqA7wzar9Q2gATqzUixe0um2zNsEsq83Xs/wocE9uQongJa34Zwg3Y9jlivcVZV9/+Co uV43TVtpwyiKOt+fu9UPW8vGYHbGVFRhYzm7MGMQ064rTMmCwFqQTQz7jmm6nW+pUizo yNEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Hb9dMZIAxrLN24ygvHA9pXLZxd+STyR5WIcVAOZOt3k=; fh=L6OjQZ2TPsHFQEGPRBuboSqhQBavDZ5pPqlyX67xn3A=; b=wRAyy/FKCuIxg87+NIAVyanNtAXtJBjFCdchVg4ySot3Sd1WQVifXtpxB6nflFG3aO EwCxPWv7BU+Edp6K3QzC4qpu6UzFSRyCnbKdNPzcgBsFumqeElKYNoSSS/K3hCLnUIus eZaANI1UXtjuqBs/G2mZauv184kPLhjyVJM69SGtmXxuh1AaE9+klksXx9DYFY+v+abz mu/owBzWnXcmR+gRCMo7r4mov8gcV7o7YES0jXFS/YM/OUt4suYIGWR2qKxYmHqRg14F PP4szxsg3cP1A10MGF/xxspzL5rv2fEUje28TD2gSO/pTgzi3Zw56n8YGBPQ5VtRXQcK YZ6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NJ2aySW5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id qr18-20020a05620a391200b0076d7f1f203esi6586340qkn.268.2023.08.29.16.26.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:26:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NJ2aySW5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83p-0003iF-Jb; Tue, 29 Aug 2023 19:23:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83m-0003KV-Ft for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:46 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83h-0001MD-Px for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:46 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1bdbf10333bso39077355ad.1 for ; Tue, 29 Aug 2023 16:23:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351420; x=1693956220; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hb9dMZIAxrLN24ygvHA9pXLZxd+STyR5WIcVAOZOt3k=; b=NJ2aySW5dDJ8u3pIIxwpMHZXyjcXe5FJhvqBhqZd2tUFfoq5FXmiJTYewJ+cLK50Yy X5WtkkTCtxxy2H0BCqXwwYyGFq8IHzU+GPvJ9z75YILeferAPoAbqvTR/0yh9ddPHKwC +DVvgUVX9L175qwh9JCoNxoUs4a/vHMs+nh+ItNEalpuaVblDq38tLTrdE77wwWlLlUa +eTLzSp3LFuDQslhmjH2j62ASCtUzhssMJybrN398W8yzTa1ZHNIZQ+2gO6ZbCblL1WK v6xlSBwhyO2G8JRENGRocICvGOvjmlU4wryqdN7wdR2LXtigGyQ/nrQdplQmR97eLct/ g31w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351420; x=1693956220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hb9dMZIAxrLN24ygvHA9pXLZxd+STyR5WIcVAOZOt3k=; b=fYJqyWdb+MSgYxo4pCpZ2mFIFmAtdOPk9MOMFU54GPXVrr5k8ID5FKiec0eng78wRF mid2JYfpjKZ/1JaQR2nZTguz4hiqX4dOIIj16+cmjIhx1fA//r+V4/RDnen03+pzeU0y EQwfrpcFCN/IPARd80gGpeicUi6q4VWWelWRmsxtFTE0VdE+BmcInv4fTjmWsfPxndjO 56dH5udEZzzgIjMiNeXqMZO6JYYB85AC0zZOkgPY+oymrP3TFC/gWyNrgy8LmO7dc5fZ Po595KJIEv3I4q4nGeJTo+HFGdG7jIM3ohCUsmFeG9wED4/m91uJFegR0hxC1/bTZOAX S54w== X-Gm-Message-State: AOJu0YxJ0M0z9DVDGsEZDGww92YLBQhBNYCOlqSplRfHoTjpDGs8mbZW rcgs/RK5X2bie57YFsoLJ7W8fh7ZWz5C/j33veM= X-Received: by 2002:a17:902:684c:b0:1c0:9abb:4873 with SMTP id f12-20020a170902684c00b001c09abb4873mr503273pln.64.1693351420134; Tue, 29 Aug 2023 16:23:40 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 03/12] target/arm: Add feature detection for FEAT_Pauth2 and extensions Date: Tue, 29 Aug 2023 16:23:26 -0700 Message-Id: <20230829232335.965414-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Aaron Lindsay Rename isar_feature_aa64_pauth_arch to isar_feature_aa64_pauth_qarma5 to distinguish the other architectural algorithm qarma3. Add ARMPauthFeature and isar_feature_pauth_feature to cover the other pauth conditions. Reviewed-by: Peter Maydell Signed-off-by: Aaron Lindsay Message-Id: <20230609172324.982888-3-aaron@os.amperecomputing.com> [rth: Add ARMPauthFeature and eliminate most other predicates] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 47 +++++++++++++++++++++++++++++------ target/arm/tcg/pauth_helper.c | 2 +- 2 files changed, 40 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4a5a5e9eb8..0e2545d631 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3801,28 +3801,59 @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; } +/* + * These are the values from APA/API/APA3. + * In general these must be compared '>=', per the normal Arm ARM + * treatment of fields in ID registers. + */ +typedef enum { + PauthFeat_None = 0, + PauthFeat_1 = 1, + PauthFeat_EPAC = 2, + PauthFeat_2 = 3, + PauthFeat_FPAC = 4, + PauthFeat_FPACCOMBINED = 5, +} ARMPauthFeature; + +static inline ARMPauthFeature +isar_feature_pauth_feature(const ARMISARegisters *id) +{ + /* + * Architecturally, only one of {APA,API,APA3} may be active (non-zero) + * and the other two must be zero. Thus we may avoid conditionals. + */ + return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) | + FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) | + FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3)); +} + static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) { /* * Return true if any form of pauth is enabled, as this * predicate controls migration of the 128-bit keys. */ - return (id->id_aa64isar1 & - (FIELD_DP64(0, ID_AA64ISAR1, APA, 0xf) | - FIELD_DP64(0, ID_AA64ISAR1, API, 0xf) | - FIELD_DP64(0, ID_AA64ISAR1, GPA, 0xf) | - FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; + return isar_feature_pauth_feature(id) != PauthFeat_None; } -static inline bool isar_feature_aa64_pauth_arch(const ARMISARegisters *id) +static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id) { /* - * Return true if pauth is enabled with the architected QARMA algorithm. - * QEMU will always set APA+GPA to the same value. + * Return true if pauth is enabled with the architected QARMA5 algorithm. + * QEMU will always enable or disable both APA and GPA. */ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0; } +static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id) +{ + /* + * Return true if pauth is enabled with the architected QARMA3 algorithm. + * QEMU will always enable or disable both APA3 and GPA3. + */ + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0; +} + static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2; diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 62af569341..6271a84ec9 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -282,7 +282,7 @@ static uint64_t pauth_computepac_impdef(uint64_t data, uint64_t modifier, static uint64_t pauth_computepac(CPUARMState *env, uint64_t data, uint64_t modifier, ARMPACKey key) { - if (cpu_isar_feature(aa64_pauth_arch, env_archcpu(env))) { + if (cpu_isar_feature(aa64_pauth_qarma5, env_archcpu(env))) { return pauth_computepac_architected(data, modifier, key); } else { return pauth_computepac_impdef(data, modifier, key); From patchwork Tue Aug 29 23:23:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718257 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp243576wrh; Tue, 29 Aug 2023 16:25:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG+I+Fi9ePsSa9emQnef/ffoEUCYz21ogbe0gQ0TvGqono5sJ9IaqxomG+CNvlmYmEzTJFW X-Received: by 2002:a05:620a:1707:b0:76f:c5a:8cd5 with SMTP id az7-20020a05620a170700b0076f0c5a8cd5mr520767qkb.56.1693351550347; Tue, 29 Aug 2023 16:25:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351550; cv=none; d=google.com; s=arc-20160816; b=ZJNyfiylNKmL7a0MwSM+SNB3LvXiNtGPkIn2wVOu5X/3J2OnFhzzmtwmJvWY6srfoW LS1oJzNDIOCTZXD9fd13DAh5WzHV4RgDabwQ4ExorB2XhAxhbwNSp8uOEJ3ExUHmEzL6 1QM0yaHZwljBFnSjS0o091ezRlYfFNqbIP9LfOH7Hzov5DkulMZ8TFmeXGYIIZMByRQY jVBU27P/k/xav+9+LZkMqEuqDU1vfqpSm6OYvpBr8UWcvOfxGpjSBh27yxyD3cim61LY IgfDjN80GCi4PPxmuDl83Cq543CcDDaUmLSGKLoCcE1rLsAV38U/3AaVSLTyKBiDIqPH HfIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=L7JWHxmJ23NmS8KMDWOHbcj7S88Z02RWmeeJJ7xEGx8=; fh=L6OjQZ2TPsHFQEGPRBuboSqhQBavDZ5pPqlyX67xn3A=; b=p/Ytld9QmynTP1a/Znytz0Bq+NqvQCAvcT3n+PfSanQbm20XtMfs/gV7pQD2zsb0dU xm/SEOR4L/cLBNhGhoBrjo6Y5CWHs6eVsRJjR+DmChh6mDVAnGDb4qg1sTfzF2IB6Ey/ oPEZX3Bv/c5rWEHrLh9vjqB+zWAJ7BBtenPq+COUAQJ0xIU9r7GSLBwUkWXMa7bLGkN/ WAKaKdVuEKGMmWP4J2st1WFTc6tmkCEZ/adWwl8X3S34PlckOeQSKblxeep7ECd1pkL2 CNpV3yw4FGSDm+isGne98SOuuC/827VGLaapp+G4wqbixngHg+6b9wn0V9df4qG09uyD 7kYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pmWZkM8Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j25-20020a05620a0a5900b0076d9ca72d0esi4355458qka.699.2023.08.29.16.25.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:25:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pmWZkM8Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83p-0003kr-Sp; Tue, 29 Aug 2023 19:23:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83m-0003MD-Sh for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:46 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83i-0001MM-FD for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:46 -0400 Received: by mail-pl1-x636.google.com with SMTP id d9443c01a7336-1bdf4752c3cso30682825ad.2 for ; Tue, 29 Aug 2023 16:23:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351421; x=1693956221; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L7JWHxmJ23NmS8KMDWOHbcj7S88Z02RWmeeJJ7xEGx8=; b=pmWZkM8YjkFeQ15aBt9RyaK0iaT1IBjp6PR8AZw0TqOcU+2Gqm6MEeykm1YK/Ax7X7 1d7v+fSfgb5kYns4ifz4Tly5RiIcF/fvRlUTb4gARerIiSRNaUI6Nj3dEc+/OEhDjfPz +1UsUwq4RD3Z8245YwUsD43aBkp2jqlncxde3YXP/tP5u65sCAJyn3cpEQicPcwC9iJ4 CxWWkiJjVjcb1CvrDgQxyZDhZQ4TGdQL65vjEzlk/xn8PgjtxareVmZV5rQcbMWLdRXS pW0e+BpoeiUX9pHcauZowWcMMTWwj2qCptlXYrZMayOIkoaFWv+z+uuQOQ+5dWWYLhWZ 9dvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351421; x=1693956221; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L7JWHxmJ23NmS8KMDWOHbcj7S88Z02RWmeeJJ7xEGx8=; b=Yz9KNtbzF5TlPRpPRleGXbyHta+Mvi3908VbcivEKVs6xURKAdhVKb6Sk+cv3Zm8Yq iWZ+gKs2Ja9VFc3sAuRHvQ2PF5tzavDXcwUZQmvTmIgMYUL9N7mZylk179zDLzq5ZTlM uFt+lFiKxkNs7dPnEJMiRs9FbrpEHlAMLw/dEz8zBDhLYW4Xnfe5jKrcw2lM/NJBEwae lhmPtiQjKGigKZgBiMzWrfmNn9yjSiFxm4sBOboppji2sglJOVoHHhi3xIbI5MiKjHTn K8n9hA5/nmgFDRV0WzuTVsNTUpRmJhpv+rf+sKpHKBQeGk8GwvH44mSnEFO5HRxiorqK l/Qw== X-Gm-Message-State: AOJu0YwczkHJE5vaHTR+a+ehUXLOJtE+a6fwckNzcOG6R2dOpmp3HoeQ 5ay4Fb7C7G76vdD0y2qIZ1sVeTTo+XiRWcOeZhg= X-Received: by 2002:a17:903:4283:b0:1bf:78d:5cd9 with SMTP id ju3-20020a170903428300b001bf078d5cd9mr388453plb.67.1693351420955; Tue, 29 Aug 2023 16:23:40 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 04/12] target/arm: Don't change pauth features when changing algorithm Date: Tue, 29 Aug 2023 16:23:27 -0700 Message-Id: <20230829232335.965414-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We have cpu properties to adjust the pauth algorithm for the purpose of speed of emulation. Retain the set of pauth features supported by the cpu even as the algorithm changes. This already affects the neoverse-v1 cpu, which has FEAT_EPAC. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 70 +++++++++++++++++++++++++++--------------- target/arm/tcg/cpu64.c | 2 ++ 2 files changed, 47 insertions(+), 25 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 96158093cc..fd584a31da 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -473,37 +473,57 @@ void aarch64_add_sme_properties(Object *obj) void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { - int arch_val = 0, impdef_val = 0; - uint64_t t; + ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu); + uint64_t isar1; - /* Exit early if PAuth is enabled, and fall through to disable it */ - if ((kvm_enabled() || hvf_enabled()) && cpu->prop_pauth) { - if (!cpu_isar_feature(aa64_pauth, cpu)) { - error_setg(errp, "'pauth' feature not supported by %s on this host", - kvm_enabled() ? "KVM" : "hvf"); + /* + * These properties enable or disable Pauth as a whole, or change + * the pauth algorithm, but do not change the set of features that + * are present. We have saved a copy of those features above and + * will now place it into the field that chooses the algorithm. + * + * Begin by disabling all fields. + */ + isar1 = cpu->isar.id_aa64isar1; + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0); + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0); + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0); + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0); + + if (kvm_enabled() || hvf_enabled()) { + /* + * Exit early if PAuth is enabled and fall through to disable it. + * The algorithm selection properties are not present. + */ + if (cpu->prop_pauth) { + if (features == 0) { + error_setg(errp, "'pauth' feature not supported by " + "%s on this host", current_accel_name()); + } + return; + } + } else { + /* Pauth properties are only present when the model supports it. */ + if (features == 0) { + assert(!cpu->prop_pauth); + return; } - return; - } - - /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ - if (cpu->prop_pauth) { - if (cpu->prop_pauth_impdef) { - impdef_val = 1; - } else { - arch_val = 1; + if (cpu->prop_pauth) { + if (cpu->prop_pauth_impdef) { + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features); + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); + } else { + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); + isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); + } + } else if (cpu->prop_pauth_impdef) { + error_setg(errp, "cannot enable pauth-impdef without pauth"); + error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); } - } else if (cpu->prop_pauth_impdef) { - error_setg(errp, "cannot enable pauth-impdef without pauth"); - error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); } - t = cpu->isar.id_aa64isar1; - t = FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); - t = FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); - t = FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); - t = FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); - cpu->isar.id_aa64isar1 = t; + cpu->isar.id_aa64isar1 = isar1; } static Property arm_cpu_pauth_property = diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 8019f00bc3..fec6a4875d 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -758,6 +758,8 @@ void aarch64_max_tcg_initfn(Object *obj) t = cpu->isar.id_aa64isar1; t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ + t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_1); + t = FIELD_DP64(t, ID_AA64ISAR1, API, 1); t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ From patchwork Tue Aug 29 23:23:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718256 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp243549wrh; Tue, 29 Aug 2023 16:25:44 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGWiYtsflEYvgfv1srSjuAaUSEZEpKZLJht3QGe+aoYP1FEGbQ87lePc3wYcBT/7I9PLxo5 X-Received: by 2002:a05:6214:4882:b0:651:800d:ffc9 with SMTP id pc2-20020a056214488200b00651800dffc9mr1759669qvb.22.1693351544409; Tue, 29 Aug 2023 16:25:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351544; cv=none; d=google.com; s=arc-20160816; b=o3hpwfjWGRkcrng/gXzSm9E992jdB1NDvsUjdnuFicbwLXdnBWf0pHMxPZNHMwcegp m+ZPcZh99rJ9sW+PaK1gV3M4xWJ9+hRe6xoBLh8F/pe3gdXzRi3sjJ+UzvTqt9JLmsnU hDZIjfqyvgrfJiirMbJ50tINWNcIiybjjrUjGpFT7UuChNDteDsD9d8PP94t2VEpEwoh 0PAEScDiCm1KyDIlT88v52/7w6L13E4Id0gO7aIxsWnA9WdgO0CssRO9JASBNI7emjJo WaLleZviJUKBoYkVzETI9ym6I3jKehMnoljiNZwDR3IU411rGoo+P/fnonY78goLwfxL NoeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=J5PvsEisUhmViwuTX1kAnQipV1YYI3hKBjw90v7ICj0=; fh=L6OjQZ2TPsHFQEGPRBuboSqhQBavDZ5pPqlyX67xn3A=; b=gyXwrGBwplmFuBQDfgUQOOKgZnWePsdwYwlwjYB8NMg+MjbZPS5/sQILCtO6G+rcQM 0W96XlCOgyjKswpPnbEFCRGgfBUoXxer4AcVo13yOalyyKaxjLMtHG57LpLakdYp+8iV 4XUAudmUqKNXEVW6ksNRHtPRLon8icP3CL6U+J/4p49AmZpK0XyOWlc3LSHHT/aXjT7/ n9Ksz8qr9px3pohp94DWCYAy5jDgmCH1mIWuug0XeEDnE69MCtFZA9dheHjjc5nRc0EZ 6bLBJlhU4YHmFHGd01e6IY06lRGozLeq3Rd/isQ2JqAvH+N3kJG9qkBg8FthuTqyt+S0 jYVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gJw5cozj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h1-20020a0cf441000000b0064f4c7c2dfesi6508073qvm.75.2023.08.29.16.25.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:25:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gJw5cozj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83q-0003oG-M8; Tue, 29 Aug 2023 19:23:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83o-0003dp-T2 for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:48 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83j-0001Mh-55 for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:48 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1bf57366ccdso2210695ad.1 for ; Tue, 29 Aug 2023 16:23:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351422; x=1693956222; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J5PvsEisUhmViwuTX1kAnQipV1YYI3hKBjw90v7ICj0=; b=gJw5cozjVpEviyGyfZfGykTLkXQfc2HTUmdKH1diieOEI3dRQ9JM8PwKBwTeZTDPvY GbS0G54VgiGzae2CM0U8T+oCc+QiPk7k3ZxWeetvOs7VTsMxuODu5KLF+zSruRAKhhlI XnczB5BZRhULibelN2nBdNsdgO9a9R+5Bqx/Vjsp75TC1iS/7L0CQ5sMjGsekn/XRIbY StpOC9u2R57dYiBC0r/SbXbzQHTWZUyVA0xXvuxoyu1u4UPe9b2CBUwJia8hcaDpbvG1 gP2uaLfYyzU262UW68EoCthc+dPKV+gn5sY0DPgy2nPHUT2NoyGNiuKOnReuSF38C2lo tVRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351422; x=1693956222; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J5PvsEisUhmViwuTX1kAnQipV1YYI3hKBjw90v7ICj0=; b=fX+WXdpk+FlWIKJK3mZVKTFiEEtsDf7Z0LpKW7zqhJvIzrwMaUC+L70bpUAVhS3thh k3i4t3BIJ9u23zY44enKqvVBh48gSMU343w3dFPDHV5dbV8BjavLC8R3+6YxwCzxbxe7 1IIMovFYOYiNecZGmTfIt9u1+BhZHTdkjQnAIH+GtboLgSYxRFlSfrdJSEKNCB8nASGF Taeubj88nZqWpd+8Bx7/tFtUoJnkXgoK9VNR8vybyRjMGHX/F/Ea/BNrEha79UZwU1/a qMis554HbPjJDgDUNySHulzfh9H5JUGlvttrh964I5JBeOgU5NGL5s0S70pnf1skSzSR 8dnw== X-Gm-Message-State: AOJu0YziK9mtI2knA6IMVJWQNqaq8gRPopjgmyQxA5qYXyOXEihW23x+ Y855hIejr6LyAu2Pr+yAENPYs2t8xBKHTQhq+HE= X-Received: by 2002:a17:902:c950:b0:1bd:e258:a256 with SMTP id i16-20020a170902c95000b001bde258a256mr1020157pla.32.1693351421791; Tue, 29 Aug 2023 16:23:41 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 05/12] target/arm: Implement FEAT_PACQARMA3 Date: Tue, 29 Aug 2023 16:23:28 -0700 Message-Id: <20230829232335.965414-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Implement the QARMA3 cryptographic algorithm for PAC calculation. Implement a cpu feature to select the algorithm and document it. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20230609172324.982888-4-aaron@os.amperecomputing.com> [rth: Merge cpu feature addition from another patch.] Signed-off-by: Richard Henderson --- docs/system/arm/cpu-features.rst | 21 ++++++++----- docs/system/arm/emulation.rst | 3 ++ target/arm/cpu.h | 1 + target/arm/arm-qmp-cmds.c | 2 +- target/arm/cpu64.c | 24 ++++++++++++-- target/arm/tcg/pauth_helper.c | 54 ++++++++++++++++++++++++++------ tests/qtest/arm-cpu-features.c | 12 ++++++- 7 files changed, 94 insertions(+), 23 deletions(-) diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst index 6bb88a40c7..a5fb929243 100644 --- a/docs/system/arm/cpu-features.rst +++ b/docs/system/arm/cpu-features.rst @@ -210,15 +210,20 @@ TCG VCPU Features TCG VCPU features are CPU features that are specific to TCG. Below is the list of TCG VCPU features and their descriptions. -``pauth-impdef`` - When ``FEAT_Pauth`` is enabled, either the *impdef* (Implementation - Defined) algorithm is enabled or the *architected* QARMA algorithm - is enabled. By default the impdef algorithm is disabled, and QARMA - is enabled. +``pauth`` + Enable or disable ``FEAT_Pauth`` entirely. - The architected QARMA algorithm has good cryptographic properties, - but can be quite slow to emulate. The impdef algorithm used by QEMU - is non-cryptographic but significantly faster. +``pauth-impdef`` + When ``pauth`` is enabled, select the QEMU implementation defined algorithm. + +``pauth-qarma3`` + When ``pauth`` is enabled, select the architected QARMA3 algorithm. + +Without either ``pauth-impdef`` or ``pauth-qarma3`` enabled, +the architected QARMA5 algorithm is used. The architected QARMA5 +and QARMA3 algorithms have good cryptographic properties, but can +be quite slow to emulate. The impdef algorithm used by QEMU is +non-cryptographic but significantly faster. SVE CPU Properties ================== diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index bdafc68819..06af20d10f 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -55,6 +55,9 @@ the following architecture extensions: - FEAT_MTE (Memory Tagging Extension) - FEAT_MTE2 (Memory Tagging Extension) - FEAT_MTE3 (MTE Asymmetric Fault Handling) +- FEAT_PACIMP (Pointer authentication - IMPLEMENTATION DEFINED algorithm) +- FEAT_PACQARMA3 (Pointer authentication - QARMA3 algorithm) +- FEAT_PACQARMA5 (Pointer authentication - QARMA5 algorithm) - FEAT_PAN (Privileged access never) - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN) - FEAT_PAN3 (Support for SCTLR_ELx.EPAN) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0e2545d631..cfca42293a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1072,6 +1072,7 @@ struct ArchCPU { */ bool prop_pauth; bool prop_pauth_impdef; + bool prop_pauth_qarma3; bool prop_lpa2; /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ diff --git a/target/arm/arm-qmp-cmds.c b/target/arm/arm-qmp-cmds.c index c8fa524002..b53d5efe13 100644 --- a/target/arm/arm-qmp-cmds.c +++ b/target/arm/arm-qmp-cmds.c @@ -95,7 +95,7 @@ static const char *cpu_model_advertised_features[] = { "sve640", "sve768", "sve896", "sve1024", "sve1152", "sve1280", "sve1408", "sve1536", "sve1664", "sve1792", "sve1920", "sve2048", "kvm-no-adjvtime", "kvm-steal-time", - "pauth", "pauth-impdef", + "pauth", "pauth-impdef", "pauth-qarma3", NULL }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index fd584a31da..f3d87e001f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -474,7 +474,7 @@ void aarch64_add_sme_properties(Object *obj) void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu); - uint64_t isar1; + uint64_t isar1, isar2; /* * These properties enable or disable Pauth as a whole, or change @@ -490,6 +490,10 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0); isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0); + isar2 = cpu->isar.id_aa64isar2; + isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0); + isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0); + if (kvm_enabled() || hvf_enabled()) { /* * Exit early if PAuth is enabled and fall through to disable it. @@ -510,26 +514,39 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) } if (cpu->prop_pauth) { + if (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) { + error_setg(errp, + "cannot enable both pauth-impdef and pauth-qarma3"); + return; + } + if (cpu->prop_pauth_impdef) { isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features); isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1); + } else if (cpu->prop_pauth_qarma3) { + isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features); + isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1); } else { isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features); isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1); } - } else if (cpu->prop_pauth_impdef) { - error_setg(errp, "cannot enable pauth-impdef without pauth"); + } else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3) { + error_setg(errp, "cannot enable pauth-impdef or " + "pauth-qarma3 without pauth"); error_append_hint(errp, "Add pauth=on to the CPU property list.\n"); } } cpu->isar.id_aa64isar1 = isar1; + cpu->isar.id_aa64isar2 = isar2; } static Property arm_cpu_pauth_property = DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); static Property arm_cpu_pauth_impdef_property = DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); +static Property arm_cpu_pauth_qarma3_property = + DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false); void aarch64_add_pauth_properties(Object *obj) { @@ -549,6 +566,7 @@ void aarch64_add_pauth_properties(Object *obj) cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu); } else { qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma3_property); } } diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 6271a84ec9..bb03409ee5 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -96,6 +96,21 @@ static uint64_t pac_sub(uint64_t i) return o; } +static uint64_t pac_sub1(uint64_t i) +{ + static const uint8_t sub1[16] = { + 0xa, 0xd, 0xe, 0x6, 0xf, 0x7, 0x3, 0x5, + 0x9, 0x8, 0x0, 0xc, 0xb, 0x1, 0x2, 0x4, + }; + uint64_t o = 0; + int b; + + for (b = 0; b < 64; b += 4) { + o |= (uint64_t)sub1[(i >> b) & 0xf] << b; + } + return o; +} + static uint64_t pac_inv_sub(uint64_t i) { static const uint8_t inv_sub[16] = { @@ -209,7 +224,7 @@ static uint64_t tweak_inv_shuffle(uint64_t i) } static uint64_t pauth_computepac_architected(uint64_t data, uint64_t modifier, - ARMPACKey key) + ARMPACKey key, bool isqarma3) { static const uint64_t RC[5] = { 0x0000000000000000ull, @@ -219,6 +234,7 @@ static uint64_t pauth_computepac_architected(uint64_t data, uint64_t modifier, 0x452821E638D01377ull, }; const uint64_t alpha = 0xC0AC29B7C97C50DDull; + int iterations = isqarma3 ? 2 : 4; /* * Note that in the ARM pseudocode, key0 contains bits <127:64> * and key1 contains bits <63:0> of the 128-bit key. @@ -231,7 +247,7 @@ static uint64_t pauth_computepac_architected(uint64_t data, uint64_t modifier, runningmod = modifier; workingval = data ^ key0; - for (i = 0; i <= 4; ++i) { + for (i = 0; i <= iterations; ++i) { roundkey = key1 ^ runningmod; workingval ^= roundkey; workingval ^= RC[i]; @@ -239,32 +255,48 @@ static uint64_t pauth_computepac_architected(uint64_t data, uint64_t modifier, workingval = pac_cell_shuffle(workingval); workingval = pac_mult(workingval); } - workingval = pac_sub(workingval); + if (isqarma3) { + workingval = pac_sub1(workingval); + } else { + workingval = pac_sub(workingval); + } runningmod = tweak_shuffle(runningmod); } roundkey = modk0 ^ runningmod; workingval ^= roundkey; workingval = pac_cell_shuffle(workingval); workingval = pac_mult(workingval); - workingval = pac_sub(workingval); + if (isqarma3) { + workingval = pac_sub1(workingval); + } else { + workingval = pac_sub(workingval); + } workingval = pac_cell_shuffle(workingval); workingval = pac_mult(workingval); workingval ^= key1; workingval = pac_cell_inv_shuffle(workingval); - workingval = pac_inv_sub(workingval); + if (isqarma3) { + workingval = pac_sub1(workingval); + } else { + workingval = pac_inv_sub(workingval); + } workingval = pac_mult(workingval); workingval = pac_cell_inv_shuffle(workingval); workingval ^= key0; workingval ^= runningmod; - for (i = 0; i <= 4; ++i) { - workingval = pac_inv_sub(workingval); - if (i < 4) { + for (i = 0; i <= iterations; ++i) { + if (isqarma3) { + workingval = pac_sub1(workingval); + } else { + workingval = pac_inv_sub(workingval); + } + if (i < iterations) { workingval = pac_mult(workingval); workingval = pac_cell_inv_shuffle(workingval); } runningmod = tweak_inv_shuffle(runningmod); roundkey = key1 ^ runningmod; - workingval ^= RC[4 - i]; + workingval ^= RC[iterations - i]; workingval ^= roundkey; workingval ^= alpha; } @@ -283,7 +315,9 @@ static uint64_t pauth_computepac(CPUARMState *env, uint64_t data, uint64_t modifier, ARMPACKey key) { if (cpu_isar_feature(aa64_pauth_qarma5, env_archcpu(env))) { - return pauth_computepac_architected(data, modifier, key); + return pauth_computepac_architected(data, modifier, key, false); + } else if (cpu_isar_feature(aa64_pauth_qarma3, env_archcpu(env))) { + return pauth_computepac_architected(data, modifier, key, true); } else { return pauth_computepac_impdef(data, modifier, key); } diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 3fc33fc24d..a8a4c668ad 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -417,12 +417,22 @@ static void pauth_tests_default(QTestState *qts, const char *cpu_type) { assert_has_feature_enabled(qts, cpu_type, "pauth"); assert_has_feature_disabled(qts, cpu_type, "pauth-impdef"); + assert_has_feature_disabled(qts, cpu_type, "pauth-qarma3"); assert_set_feature(qts, cpu_type, "pauth", false); assert_set_feature(qts, cpu_type, "pauth", true); assert_set_feature(qts, cpu_type, "pauth-impdef", true); assert_set_feature(qts, cpu_type, "pauth-impdef", false); - assert_error(qts, cpu_type, "cannot enable pauth-impdef without pauth", + assert_set_feature(qts, cpu_type, "pauth-qarma3", true); + assert_set_feature(qts, cpu_type, "pauth-qarma3", false); + assert_error(qts, cpu_type, + "cannot enable pauth-impdef or pauth-qarma3 without pauth", "{ 'pauth': false, 'pauth-impdef': true }"); + assert_error(qts, cpu_type, + "cannot enable pauth-impdef or pauth-qarma3 without pauth", + "{ 'pauth': false, 'pauth-qarma3': true }"); + assert_error(qts, cpu_type, + "cannot enable both pauth-impdef and pauth-qarma3", + "{ 'pauth': true, 'pauth-impdef': true, 'pauth-qarma3': true }"); } static void test_query_cpu_model_expansion(const void *data) From patchwork Tue Aug 29 23:23:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718269 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp244955wrh; Tue, 29 Aug 2023 16:30:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHIZzedbTNpCRqyo8PVARSP0KTPI3whMp1a7j3w8bpeq/nureio+abOS3hId8nd4wG3AfcS X-Received: by 2002:a25:acc3:0:b0:d7a:def7:b96a with SMTP id x3-20020a25acc3000000b00d7adef7b96amr553373ybd.53.1693351808832; Tue, 29 Aug 2023 16:30:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351808; cv=none; d=google.com; s=arc-20160816; b=zDzsSSZw3pFzO1DOf363y9Y/2hLQUf2VZW9M0EFkiDBacfTI5rZZ1xkL7W7mVc39pq sgJqLbdlZeqO1Gru0uKjJ0qXbScZ/j3dYJA7v3tbXQ0AXcit5GQgnkjYYoaHsEYpGoI6 g8H2SQi+q/wG+5leZXidOx+K7mgknK61sO02Rm0EH6v5WIrwTeZ+Pu3zHxPbZBM7vqgL G/ZJ40nrsaV5KfWfYQMSE4+LyI+F/3OGHIQpNC6a9aaeItq16i8N+mNqoYJfZL8jMFYi Jf3rfaxT8qNkBUZIlwfGnQytxaeGn26TxhPwbQNk4OPU3niAPVupS42g9tj7Xsx/CvdL 3VXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dSHDOqmpvVqWZn7zJjJYDufm+wpdwBxF2KdyWkAtGiQ=; fh=L6OjQZ2TPsHFQEGPRBuboSqhQBavDZ5pPqlyX67xn3A=; b=CF5VeqL1cDMQ0Xbcg0q1wIF2Jl9FspM3gqwdOhYOrNb5Z8WZhjuG/ETQ8B4u1OsaUr dXcnODUjSu9EMATvN6id880ef+kHd+pRZpn/Q8cg25eu8LPacPta1KBLrBvae8blLciC Ja2X9r0CBQTfBjdG7UaupNR5XCJyD3E51khrEFmpWh0jG2AxOK8GQfx3qOMxYYeaJvrM wOIRNS952+HO2xY52++Lu+nikO4Xvv1x0xG3l7ZZ3fRyX5WzyIU5PjOZBQbKCCX/74Vq +0S0gJcpgegSDlgyQo3bxAoZ9B3LrwnoT45Ul+H/1YYgHooRCPjfNH3Az6ABcu8X1Q/0 ZIwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RBXDMiCA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m15-20020a05622a054f00b00410ac15cbf6si6761043qtx.456.2023.08.29.16.30.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:30:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RBXDMiCA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83r-0003vm-VX; Tue, 29 Aug 2023 19:23:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83p-0003fi-3t for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:49 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83k-0001N1-9A for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:48 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-68bed286169so4261470b3a.1 for ; Tue, 29 Aug 2023 16:23:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351423; x=1693956223; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dSHDOqmpvVqWZn7zJjJYDufm+wpdwBxF2KdyWkAtGiQ=; b=RBXDMiCAbVEWOh24jzMgBq9SwBVpcHnOk3/ikUpgslogFgev87rbJIm9UFqTo99h+1 xI/c5F72Riu/P1YyUly9Vzy5UkBORtDJ3bp6J8I+1yNXvA/o3NnZb4KRLeIRk/UphrbX hW8zThsIEkc6sc7aDqZutKsJqxklxuA6SYQ8JQf/arAmCVrJX+vqql911fc9ankbDXbK 8zdktD6Tu9TqgbdmreLutguBDRk3MkIRvANfuXrx0ujcr36LqqgyvvqBJXgTgqLNUnyQ Upn2d4l51zR3aGhgD3fpPanjaCVMAC6SPsIY8O9IyCGlnYZogNQVicPLVmH1E2diqFrD aUxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351423; x=1693956223; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dSHDOqmpvVqWZn7zJjJYDufm+wpdwBxF2KdyWkAtGiQ=; b=dikAqFaou1mgclySXlrATd0xmurlIUTedLix+h0lKssUOviXfCY7NG9yL/jcSNrwJ8 XvWHvFy4J68DR9VRC2Lntew/hzLJgyEs5IZiFKpwWQaUgYVc+zHX47X3suezLpPtGJQZ 0m++OT5B7jjrIJlgzbeVxx3ZhRw4OmSAd8wi4CIW/OHDLYKiz1Bb2ab0C886qyDfudvz TxKiqtWf7ypVZc1mLa2UuxtZVGRHljH6bXadjdTfj23esjrhsmw/BeSff/K3dGoeh/dK 6sz6HujeHBcFws7ul5Y2WVSZeDtibrrq49YHyAPM8c9xXJ+QfPWkg23sNzW+E65iwX8g Ejkg== X-Gm-Message-State: AOJu0YwBbuegMJuLqfC0Hvxru5+pqab9xClPw4FOVJMXplhpP11vfn7I Gjd0+hZp/7ds5L2h1KfkIsVnXggCIdWcXPEbGq8= X-Received: by 2002:a05:6a20:4c84:b0:148:d5d9:aaa9 with SMTP id fq4-20020a056a204c8400b00148d5d9aaa9mr554519pzb.33.1693351422849; Tue, 29 Aug 2023 16:23:42 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 06/12] target/arm: Implement FEAT_EPAC Date: Tue, 29 Aug 2023 16:23:29 -0700 Message-Id: <20230829232335.965414-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20230609172324.982888-5-aaron@os.amperecomputing.com> Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 2 +- target/arm/tcg/pauth_helper.c | 16 +++++++++++----- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 06af20d10f..4866a73ca0 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -27,6 +27,7 @@ the following architecture extensions: - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_DoubleFault (Double Fault Extension) - FEAT_E0PD (Preventing EL0 access to halves of address maps) +- FEAT_EPAC (Enhanced pointer authentication) - FEAT_ETS (Enhanced Translation Synchronization) - FEAT_EVT (Enhanced Virtualization Traps) - FEAT_FCMA (Floating-point complex number instructions) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index fec6a4875d..85bf94ee40 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -758,7 +758,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = cpu->isar.id_aa64isar1; t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ - t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_1); + t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_EPAC); t = FIELD_DP64(t, ID_AA64ISAR1, API, 1); t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index bb03409ee5..63e1009ea7 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -326,8 +326,10 @@ static uint64_t pauth_computepac(CPUARMState *env, uint64_t data, static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data) { + ARMCPU *cpu = env_archcpu(env); ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); + ARMPauthFeature pauth_feature = cpu_isar_feature(pauth_feature, cpu); uint64_t pac, ext_ptr, ext, test; int bot_bit, top_bit; @@ -351,11 +353,15 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, */ test = sextract64(ptr, bot_bit, top_bit - bot_bit); if (test != 0 && test != -1) { - /* - * Note that our top_bit is one greater than the pseudocode's - * version, hence "- 2" here. - */ - pac ^= MAKE_64BIT_MASK(top_bit - 2, 1); + if (pauth_feature == PauthFeat_EPAC) { + pac = 0; + } else { + /* + * Note that our top_bit is one greater than the pseudocode's + * version, hence "- 2" here. + */ + pac ^= MAKE_64BIT_MASK(top_bit - 2, 1); + } } /* From patchwork Tue Aug 29 23:23:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718266 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp244612wrh; Tue, 29 Aug 2023 16:29:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGjMNywWiD8rv48eX+OwmJ1x7KC5nzX/rD7eo/jjCwKNaZ1+cvuZLXaUa2vhJrimcstpcod X-Received: by 2002:a0c:c3d2:0:b0:64f:6e53:4e17 with SMTP id p18-20020a0cc3d2000000b0064f6e534e17mr495240qvi.16.1693351741288; Tue, 29 Aug 2023 16:29:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351741; cv=none; d=google.com; s=arc-20160816; b=TCPYR6bd7cCuJ8iJP3jF4y6g8JpM2eXXTOfnrPvRiRLWuDzVRW3sg3eELHYFTV8MnH krjmi3iLqo03vmOk+vngCYfNMU2ZtlbuX7Tv4XOHbqriiw9v899HHjzbb/T9jv9QLxD4 YfgZba6bIgexW8f/zKj0uuP4tosEAZOk8HTKgQ4TbqWPh3p2aSMv4J7MrDpJapW+q56T 5hjpFkGp7/X0raudVkUz4JGBZK/ma2dguDKsiNuCG8u3Jkp3H2KosTHnG1kUjkyTVJZZ VO309EmF7QmfaGC2yer8U8fyZa4CZN4/18gcsWa9Dwxl0+v3irZr68lfAEqN6NDdz6Ur FrXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Tz0aWUu/vHl+1ntPEUMfK/rYoMDJR4BjrdL+Cy/mdVs=; fh=L6OjQZ2TPsHFQEGPRBuboSqhQBavDZ5pPqlyX67xn3A=; b=j/9goabecqmIFO4SbrTX9Y+lqBCvFlASo5xMNbDSea36WZXl/Oo+GqCdnsez2hPY5Y o8VoagPY+bqqRm8OyFZh1JSK00kjKG3vzUUdbdmrlRhabQPoVbz0Ad6wly3fGjDJwbH3 2Om3tMJGXLKEZpkuk+viOktQsIySb4BJDO7vfQlQl6doFtAml2yJdmUqIHOKLM8r43tq qx52UbNBaU2jKJ5sHz8CnEfdAXT0Vv76VwmfJyV3AjdlDMvJ/aCWaZtPOH78pf9hcvP8 bCLh1SERdAE6ZG/D3TR3iJanMIRnCsKuEKORAzSuOFV1jDIc4yk3EC3XyTWiXOUoDxP/ lgbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m6n/TpIp"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i13-20020a05620a248d00b007698899ce1csi6998175qkn.348.2023.08.29.16.29.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:29:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="m6n/TpIp"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83r-0003x1-VK; Tue, 29 Aug 2023 19:23:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83q-0003ly-4n for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:50 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83l-0001NL-3W for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:49 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1c1e3a4a06fso17052885ad.3 for ; Tue, 29 Aug 2023 16:23:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351423; x=1693956223; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Tz0aWUu/vHl+1ntPEUMfK/rYoMDJR4BjrdL+Cy/mdVs=; b=m6n/TpIpbBGNBQuAUKMsHJ23fngCD5iKz2R34+H/gyI8U3PL6yS67MHbC4P/Yy42zf hfuEfuV+o8Y+ekBQLOndgbb6i4puKzsRv9gD8iAcoSF5n1fm6bXr7VN8EO6XJY84UEFW PBMbpty6vScIR284vl7AkzGz4NdxbK/sQTXtAkvDrTgECzBzbjBbL5UkoaiJmgvxoaRn mEl1E2avZwPBgwqwq8HWExlcYhDC3vZ4YRlWMKFF0mM00R9hG4mT/YO0HrTxQguQ10AN bGHCJvFOstoq3cRdQvmoTWS+NDT6JU9Hya7JYofzMxgheSouT2Qdv0eWz2yl24yQqUti NQCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351423; x=1693956223; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tz0aWUu/vHl+1ntPEUMfK/rYoMDJR4BjrdL+Cy/mdVs=; b=hQOXQgP2nAQJJBDKGwr0ELVr5Tb914pVLaA0v8nYzUzDUgQLWsPt2tQe9Pu7yvlUQA X9h/aFxNh6iIcm7v9y/qBuKNhf4U38i46OO0is/ZgdRNktShPFxhvUaHm3yq9CFig+C6 z+sM1Pxu/NukrZqAR0qKNQ13zMe3SY8meRnnEy1HHwn9I6sM4TENWDp3ii6y2cUZDfwL p/L1Euz1U/y4J+VnFaiUeERKBOh+VRQJlqRWlj2iztpHXgMqvs24s1Wlj1TaKa524Xdr JSWYKlzEV4LhZfEoFKkEdv5z5WLfrfVdAagTukMrweCibmj0UrQZp8FtNw9PEMFDqZK+ 1u1Q== X-Gm-Message-State: AOJu0Yy3+xc0Uo4v+Z9S7+83PTPAEV3Ehly8d5mU1tLuOmJKhFGaFVWP 5bz7hKZlOuDKufXMNRjUMP7tdKWDyNnDR4uZXRo= X-Received: by 2002:a17:903:11d1:b0:1b8:78e:7c1 with SMTP id q17-20020a17090311d100b001b8078e07c1mr585119plh.51.1693351423715; Tue, 29 Aug 2023 16:23:43 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 07/12] target/arm: Implement FEAT_Pauth2 Date: Tue, 29 Aug 2023 16:23:30 -0700 Message-Id: <20230829232335.965414-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20230609172324.982888-6-aaron@os.amperecomputing.com> Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c | 2 +- target/arm/tcg/pauth_helper.c | 21 +++++++++++++++++---- 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 4866a73ca0..54234ac090 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -63,6 +63,7 @@ the following architecture extensions: - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN) - FEAT_PAN3 (Support for SCTLR_ELx.EPAN) - FEAT_PAuth (Pointer authentication) +- FEAT_PAuth2 (Enhacements to pointer authentication) - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 85bf94ee40..d3be14137e 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -758,7 +758,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = cpu->isar.id_aa64isar1; t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ - t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_EPAC); + t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_2); t = FIELD_DP64(t, ID_AA64ISAR1, API, 1); t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 63e1009ea7..b6aeb90548 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -353,7 +353,9 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, */ test = sextract64(ptr, bot_bit, top_bit - bot_bit); if (test != 0 && test != -1) { - if (pauth_feature == PauthFeat_EPAC) { + if (pauth_feature >= PauthFeat_2) { + /* No action required */ + } else if (pauth_feature == PauthFeat_EPAC) { pac = 0; } else { /* @@ -368,6 +370,9 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, * Preserve the determination between upper and lower at bit 55, * and insert pointer authentication code. */ + if (pauth_feature >= PauthFeat_2) { + pac ^= ptr; + } if (param.tbi) { ptr &= ~MAKE_64BIT_MASK(bot_bit, 55 - bot_bit + 1); pac &= MAKE_64BIT_MASK(bot_bit, 54 - bot_bit + 1); @@ -394,18 +399,26 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data, int keynumber) { + ARMCPU *cpu = env_archcpu(env); ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data, false); + ARMPauthFeature pauth_feature = cpu_isar_feature(pauth_feature, cpu); int bot_bit, top_bit; - uint64_t pac, orig_ptr, test; + uint64_t pac, orig_ptr, cmp_mask; orig_ptr = pauth_original_ptr(ptr, param); pac = pauth_computepac(env, orig_ptr, modifier, *key); bot_bit = 64 - param.tsz; top_bit = 64 - 8 * param.tbi; - test = (pac ^ ptr) & ~MAKE_64BIT_MASK(55, 1); - if (unlikely(extract64(test, bot_bit, top_bit - bot_bit))) { + cmp_mask = MAKE_64BIT_MASK(bot_bit, top_bit - bot_bit); + cmp_mask &= ~MAKE_64BIT_MASK(55, 1); + + if (pauth_feature >= PauthFeat_2) { + return ptr ^ (pac & cmp_mask); + } + + if ((pac ^ ptr) & cmp_mask) { int error_code = (keynumber << 1) | (keynumber ^ 1); if (param.tbi) { return deposit64(orig_ptr, 53, 2, error_code); From patchwork Tue Aug 29 23:23:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718262 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp244147wrh; Tue, 29 Aug 2023 16:27:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHOrc3WLdsi76EcNdY8eoUgEa8WNhBtKIVs2n4ILl28itN2fY26ubat+uxaWTNlrzGZdTb4 X-Received: by 2002:ac8:5916:0:b0:40f:d021:b0cc with SMTP id 22-20020ac85916000000b0040fd021b0ccmr491603qty.22.1693351655405; Tue, 29 Aug 2023 16:27:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351655; cv=none; d=google.com; s=arc-20160816; b=UwvaBP6dK5v+i3sLKZIcGaa0owotI3cZnJk6FQGClCmB7XweE4DPxCMKmkQrRKVxNa 2hxOWtgkMvADmBtg0VJJXZ7fLandmXemFr1TVROShcterjbw7s8ICO192awf418jqQPM nvJW4ohptWjYwjHYQPHVD4zddBCATMXDfcQUvXGgIy55MZcTroHw4kBu+LTqSYOq08IK 0o5MHV97Wt7cGT8mHJIz39ingv3I4icfBxiqoV+pLnfLEI61C5ZklGKoMvKvrbng3W6j TvL49fiZLz/vfTn0emCUqruFdlZ2Z1dbuxdERrqXwy6FUQqH8eUXrmTDDyQMRM7wRMQD kgww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GBMbwJtbWJINLG/Bi+3dEW8o9qtvntfSHtdu/TS63ec=; fh=O7AqGEi4dcReFaDA9j5gRdMsSxl/oV5ux6DfuDYt/iI=; b=uHyvAiaSz9JKXZWinUX2GQ6wEatvd4bZ02KtAAci42cuBWkbLYLjr9URkz9Q8SrOYh dqW0llt/MlB4clk2n3uoRz8NMN6RWBgo7L4yCYyunBqdS0d6c/nz3VuD1/D2w/uopJOr 6QLjPlvInuAbX8oaKc1L2o17JZkoww6ZjTUtI4tRrciar9TQF2BCZUX4DyyBRTpT8kQK uv8aC8IiMA8k9z/k6uv9xvVU7qwFMNOfQoUkHAfsyQOVLtNgWEFPSJXTjAWPm4+lCjYf FYnZaIfFgc1j8jgBvLClocmkdZBo9R77xRcW1KbXzO1L/UmhRoPzNVVBzgyTPKtc9zXh IPIA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L5REHIAG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d6-20020ac85ac6000000b0040fd23153e3si6472162qtd.68.2023.08.29.16.27.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:27:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L5REHIAG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83u-0004Ki-V4; Tue, 29 Aug 2023 19:23:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83r-0003s5-Cl for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:51 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83l-0001Np-Rz for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:51 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1c09673b006so26288145ad.1 for ; Tue, 29 Aug 2023 16:23:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351424; x=1693956224; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GBMbwJtbWJINLG/Bi+3dEW8o9qtvntfSHtdu/TS63ec=; b=L5REHIAGXj+TQFb1hHVUlwUVL0b+XHMvPHQSsRTfgHOqYyzKflogOgn3oay9iMgJxA f3Pf2uUU6N4aqRFp2qi1xP+LnSWMGR4YNuiZ2vCX8xcFHQkb8P/SNI/Wr+BQTrM1EGR6 vNu6slT09bxQ16Ot3SVCTUu0ktFtLxpuqKvuUIeEXz3Ud4IV6EfFgzL+tEqqiQvgxUEI pXvi09vx6pzqfKtd0KBKchFtozWL2k+E+bkyZPx5UcGye2EnzK58go2LSHfmH6+fUB3E wBoJ9jLYsbAtWNTMyVFWRN0hlLaKSPNmGDjRrVn/RT310je2EEnO3mzrXkJey9DBy2S7 tsDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351424; x=1693956224; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GBMbwJtbWJINLG/Bi+3dEW8o9qtvntfSHtdu/TS63ec=; b=PXh4dEoMWH3MSS1XQ/Z31bjTvFpI/WdtL7M5tZqWaWRlCwdGVj4QWlhfhg9zeqlVHT IWzFL5JKnoCqq9EH6Zg9aBh/oY7U7v8ZtODldtsYWHsDs1B+GthzarcMbl8vVlFoznq0 iwJdzrirmiCIZnqw6xkX1WFAs50iZQ5FXhdabacBTjzrA4ttsRmsegCkIMnkVO9ql51q ZAWKHSGnNJQRcsrdMIWzogWiGMfufVLM/TKTW4p1+lLT8hrFfbMYf/mZJcDVOJ93WbCN lNTIa/0ks3hqq367to2BP3xWsjNnsVxKi4TmReydTzBTRqog6N50Ffktq5/TYO8xJlX6 fHVQ== X-Gm-Message-State: AOJu0YzSY3S7R8L6P8OEVwGSpDuwLEhcuEooFeZt+wYyAAJR9TK+F7lm QFhn6RcM2wJRqzdrObFqDr+9C/HB5Z//NhAoBP0= X-Received: by 2002:a17:902:d48e:b0:1b8:6cae:4400 with SMTP id c14-20020a170902d48e00b001b86cae4400mr635988plg.37.1693351424504; Tue, 29 Aug 2023 16:23:44 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Ma?= =?utf-8?q?thieu-Daud=C3=A9?= Subject: [PATCH v5 08/12] targer/arm: Inform helpers whether a PAC instruction is 'combined' Date: Tue, 29 Aug 2023 16:23:31 -0700 Message-Id: <20230829232335.965414-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Aaron Lindsay An instruction is a 'combined' Pointer Authentication instruction if it does something in addition to PAC -- for instance, branching to or loading an address from the authenticated pointer. Knowing whether a PAC operation is 'combined' is needed to implement FEAT_FPACCOMBINE. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson Message-Id: <20230609172324.982888-7-aaron@os.amperecomputing.com> Signed-off-by: Richard Henderson --- target/arm/tcg/helper-a64.h | 4 ++ target/arm/tcg/pauth_helper.c | 71 +++++++++++++++++++++++++++------- target/arm/tcg/translate-a64.c | 12 +++--- 3 files changed, 68 insertions(+), 19 deletions(-) diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h index 3d5957c11f..57cfd68569 100644 --- a/target/arm/tcg/helper-a64.h +++ b/target/arm/tcg/helper-a64.h @@ -90,9 +90,13 @@ DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacdb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(pacga, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(autia, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autia_combined, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(autib, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autib_combined, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autda_combined, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(autdb_combined, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index b6aeb90548..c05c5b30ff 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -397,7 +397,8 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) } static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, - ARMPACKey *key, bool data, int keynumber) + ARMPACKey *key, bool data, int keynumber, + uintptr_t ra, bool is_combined) { ARMCPU *cpu = env_archcpu(env); ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); @@ -519,44 +520,88 @@ uint64_t HELPER(pacga)(CPUARMState *env, uint64_t x, uint64_t y) return pac & 0xffffffff00000000ull; } -uint64_t HELPER(autia)(CPUARMState *env, uint64_t x, uint64_t y) +static uint64_t pauth_autia(CPUARMState *env, uint64_t x, uint64_t y, + uintptr_t ra, bool is_combined) { int el = arm_current_el(env); if (!pauth_key_enabled(env, el, SCTLR_EnIA)) { return x; } - pauth_check_trap(env, el, GETPC()); - return pauth_auth(env, x, y, &env->keys.apia, false, 0); + pauth_check_trap(env, el, ra); + return pauth_auth(env, x, y, &env->keys.apia, false, 0, ra, is_combined); } -uint64_t HELPER(autib)(CPUARMState *env, uint64_t x, uint64_t y) +uint64_t HELPER(autia)(CPUARMState *env, uint64_t x, uint64_t y) +{ + return pauth_autia(env, x, y, GETPC(), false); +} + +uint64_t HELPER(autia_combined)(CPUARMState *env, uint64_t x, uint64_t y) +{ + return pauth_autia(env, x, y, GETPC(), true); +} + +static uint64_t pauth_autib(CPUARMState *env, uint64_t x, uint64_t y, + uintptr_t ra, bool is_combined) { int el = arm_current_el(env); if (!pauth_key_enabled(env, el, SCTLR_EnIB)) { return x; } - pauth_check_trap(env, el, GETPC()); - return pauth_auth(env, x, y, &env->keys.apib, false, 1); + pauth_check_trap(env, el, ra); + return pauth_auth(env, x, y, &env->keys.apib, false, 1, ra, is_combined); } -uint64_t HELPER(autda)(CPUARMState *env, uint64_t x, uint64_t y) +uint64_t HELPER(autib)(CPUARMState *env, uint64_t x, uint64_t y) +{ + return pauth_autib(env, x, y, GETPC(), false); +} + +uint64_t HELPER(autib_combined)(CPUARMState *env, uint64_t x, uint64_t y) +{ + return pauth_autib(env, x, y, GETPC(), true); +} + +static uint64_t pauth_autda(CPUARMState *env, uint64_t x, uint64_t y, + uintptr_t ra, bool is_combined) { int el = arm_current_el(env); if (!pauth_key_enabled(env, el, SCTLR_EnDA)) { return x; } - pauth_check_trap(env, el, GETPC()); - return pauth_auth(env, x, y, &env->keys.apda, true, 0); + pauth_check_trap(env, el, ra); + return pauth_auth(env, x, y, &env->keys.apda, true, 0, ra, is_combined); } -uint64_t HELPER(autdb)(CPUARMState *env, uint64_t x, uint64_t y) +uint64_t HELPER(autda)(CPUARMState *env, uint64_t x, uint64_t y) +{ + return pauth_autda(env, x, y, GETPC(), false); +} + +uint64_t HELPER(autda_combined)(CPUARMState *env, uint64_t x, uint64_t y) +{ + return pauth_autda(env, x, y, GETPC(), true); +} + +static uint64_t pauth_autdb(CPUARMState *env, uint64_t x, uint64_t y, + uintptr_t ra, bool is_combined) { int el = arm_current_el(env); if (!pauth_key_enabled(env, el, SCTLR_EnDB)) { return x; } - pauth_check_trap(env, el, GETPC()); - return pauth_auth(env, x, y, &env->keys.apdb, true, 1); + pauth_check_trap(env, el, ra); + return pauth_auth(env, x, y, &env->keys.apdb, true, 1, ra, is_combined); +} + +uint64_t HELPER(autdb)(CPUARMState *env, uint64_t x, uint64_t y) +{ + return pauth_autdb(env, x, y, GETPC(), false); +} + +uint64_t HELPER(autdb_combined)(CPUARMState *env, uint64_t x, uint64_t y) +{ + return pauth_autdb(env, x, y, GETPC(), true); } uint64_t HELPER(xpaci)(CPUARMState *env, uint64_t a) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index da686cc953..eab3beef06 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1530,9 +1530,9 @@ static TCGv_i64 auth_branch_target(DisasContext *s, TCGv_i64 dst, truedst = tcg_temp_new_i64(); if (use_key_a) { - gen_helper_autia(truedst, cpu_env, dst, modifier); + gen_helper_autia_combined(truedst, cpu_env, dst, modifier); } else { - gen_helper_autib(truedst, cpu_env, dst, modifier); + gen_helper_autib_combined(truedst, cpu_env, dst, modifier); } return truedst; } @@ -3352,11 +3352,11 @@ static bool trans_LDRA(DisasContext *s, arg_LDRA *a) if (s->pauth_active) { if (!a->m) { - gen_helper_autda(dirty_addr, cpu_env, dirty_addr, - tcg_constant_i64(0)); + gen_helper_autda_combined(dirty_addr, cpu_env, dirty_addr, + tcg_constant_i64(0)); } else { - gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, - tcg_constant_i64(0)); + gen_helper_autdb_combined(dirty_addr, cpu_env, dirty_addr, + tcg_constant_i64(0)); } } From patchwork Tue Aug 29 23:23:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718264 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp244315wrh; Tue, 29 Aug 2023 16:28:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEP4+AH+dpzZ37udPv/cVRpj8NcFjfPbEPZlWjPPJEpuya0qfH1sBt2yXDbD6bMx9yVOmJl X-Received: by 2002:a05:622a:1a9c:b0:403:be93:678 with SMTP id s28-20020a05622a1a9c00b00403be930678mr629160qtc.6.1693351683204; Tue, 29 Aug 2023 16:28:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351683; cv=none; d=google.com; s=arc-20160816; b=GG+tCUmnJVW2oPntPiCCX4bIM4hBunOknwwLUXcScPIv+FnaicdZIMiyqQjX26dO5x DjkuesLIFp6FlCRedszzceQ996l0sZjUksdaZTD5OCY9i2yE5SxaBaOAGSyaPfK8TDZw bJsDbHBxaL+iX8Q6RMeVpXJQrj7qF8lENQR8DUWy7P2meIPJJzDph0tx9+pLklUAQalg w2v86sZ1an1KTA6Y7irW9TtX3DFmudtBmbxlgzCN9bilpX/L5u23Zkt5tsEyQw/VnuE8 vUmuDU4BSnb5HRu+H4Ei3GnBc0l/s7pycuXYjhFuCcWoF1Kmq7oMXspqrHK3NRpl2rYW uCdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QYRPHwHql4RJiTHPJiRJM3r+k6GdWisA6scz9yo7XuE=; fh=EfLVKF30PRMlBBLnPfTKrxZS/PAO9ADHBdRXKXa4nd0=; b=OgPdc12A1hmiAa4gdrHxNr6XcccQe8ivP98QPBHgiNwMWRYI/zD4Wi7dj6xlvTm//M UCSalTFIgRCJbg4PdHSQRfgBCgLEBJM9NhNTfYW0LIDrSvBzGoq9kH0arwYcH9q5Fhuf 4K44znKvBTY8Dvg+87peNltF560nldfRixYh6ow40s6LmdAdR8Hvqj3YRYLslRL9HL9H DWOkyMm/VgIGjfPCXkNy4AYqTwOKaCfGcfn/gzStxoX3tpDH/afTKXur6jZ+4TPucyF8 L20aC7JmDErt+pZCuuktWHey5GM9yUA/GtqAaI4eGSQbnK3kWRSwHyWi062Ybt/lTbXD H6Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SV0bHeYu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p7-20020a05622a00c700b0040555dfef18si4764938qtw.666.2023.08.29.16.28.03 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:28:03 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SV0bHeYu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83w-0004Vp-DJ; Tue, 29 Aug 2023 19:23:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83s-00041L-AP for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:52 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83m-0001O2-L4 for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:52 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1bdbf10333bso39077755ad.1 for ; Tue, 29 Aug 2023 16:23:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351425; x=1693956225; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QYRPHwHql4RJiTHPJiRJM3r+k6GdWisA6scz9yo7XuE=; b=SV0bHeYucokZw3B7Y7d0cL91KpJdUemBbUecIWfQ/b3vN7ZexlMYE5Rw+nfJMR6Uw7 ze4iolneTbSf09B/56mjy5TGv0+wlm6mDyUwJAG6L6geFrpoU0xl/dpM+kTOGpTATwQJ bpE0ZDavVs3tXvXoRPQnKHfX7rUZgQkadzoTjRMCZbWPAXXunN7Ee2h53Ve09BZ6xXkH sIFCUXMqWBrc1PtQOMhqyj7VXX0IstYtwI/zFFJ1X+zLpLHzu34DGGT4yKORu/wam5AK KXBZoNRhHd2JGcQUEhEbIxyddnyIWS7CJCNVYB9C0R1op6/39QvapLAjQoxboeHB13zH XT/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351425; x=1693956225; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QYRPHwHql4RJiTHPJiRJM3r+k6GdWisA6scz9yo7XuE=; b=ddoLAZ5aY3ZA4eupwjUt6Xiqgl6MS5ydCogHF2oJLAKo7rs6fEMQhMVMTwdGhStGNW MJJjMSWWPhMIlYFXnz4bQni4+kdYXeMmF0gp2RrdqlNe+bc/0eEnAsud5d92Ivxd6IrL YlNvmqUQTABElkwMB0UAjXuCO7OC8RC8IEWDimIIQWER2NHy7eUQZJv6F4XZ2MO/lKf1 XULn8zzuED6YMBQCBpE7d4wGimJ+wO54xXL2W1TiZc6d92fRLNJ1ADQVNR4H1kNs+vwn J2ADLZhScJKc+WqdkozgevBYDmrWbWSmpA1sSc8WvzJ9ZN0Qo2Jn7XZCkRGS4S5KG3lD /25Q== X-Gm-Message-State: AOJu0Yx6cJDi80/ickpefexNBymfWw0CPNM/mEgU1SUqHVLc+v/pqGAn w3/cNgsQzo6OtNUaLYjVtFzJQNKIhxOzjgyJRFU= X-Received: by 2002:a17:902:8e89:b0:1c0:b7f4:5b86 with SMTP id bg9-20020a1709028e8900b001c0b7f45b86mr552309plb.65.1693351425350; Tue, 29 Aug 2023 16:23:45 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org Subject: [PATCH v5 09/12] target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE Date: Tue, 29 Aug 2023 16:23:32 -0700 Message-Id: <20230829232335.965414-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson Message-Id: <20230609172324.982888-8-aaron@os.amperecomputing.com> [rth: Simplify fpac comparison, reusing cmp_mask] Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 2 ++ target/arm/syndrome.h | 7 +++++++ target/arm/tcg/cpu64.c | 2 +- target/arm/tcg/pauth_helper.c | 18 +++++++++++++++++- 4 files changed, 27 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 54234ac090..8be04edbcc 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -34,6 +34,8 @@ the following architecture extensions: - FEAT_FGT (Fine-Grained Traps) - FEAT_FHM (Floating-point half-precision multiplication instructions) - FEAT_FP16 (Half-precision floating-point data processing) +- FEAT_FPAC (Faulting on AUT* instructions) +- FEAT_FPACCOMBINE (Faulting on combined pointer authentication instructions) - FEAT_FRINTTS (Floating-point to integer instructions) - FEAT_FlagM (Flag manipulation instructions v2) - FEAT_FlagM2 (Enhancements to flag manipulation instructions) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 62254d0e51..8a6b8f8162 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -49,6 +49,7 @@ enum arm_exception_class { EC_SYSTEMREGISTERTRAP = 0x18, EC_SVEACCESSTRAP = 0x19, EC_ERETTRAP = 0x1a, + EC_PACFAIL = 0x1c, EC_SMETRAP = 0x1d, EC_GPC = 0x1e, EC_INSNABORT = 0x20, @@ -232,6 +233,12 @@ static inline uint32_t syn_smetrap(SMEExceptionType etype, bool is_16bit) | (is_16bit ? 0 : ARM_EL_IL) | etype; } +static inline uint32_t syn_pacfail(bool data, int keynumber) +{ + int error_code = (data << 1) | keynumber; + return (EC_PACFAIL << ARM_EL_EC_SHIFT) | ARM_EL_IL | error_code; +} + static inline uint32_t syn_pactrap(void) { return EC_PACTRAP << ARM_EL_EC_SHIFT; diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index d3be14137e..7734058bb1 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -758,7 +758,7 @@ void aarch64_max_tcg_initfn(Object *obj) t = cpu->isar.id_aa64isar1; t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ - t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_2); + t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED); t = FIELD_DP64(t, ID_AA64ISAR1, API, 1); t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index c05c5b30ff..4da2962ad5 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -396,6 +396,14 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) } } +static G_NORETURN +void pauth_fail_exception(CPUARMState *env, bool data, + int keynumber, uintptr_t ra) +{ + raise_exception_ra(env, EXCP_UDEF, syn_pacfail(data, keynumber), + exception_target_el(env), ra); +} + static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data, int keynumber, uintptr_t ra, bool is_combined) @@ -416,7 +424,15 @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, cmp_mask &= ~MAKE_64BIT_MASK(55, 1); if (pauth_feature >= PauthFeat_2) { - return ptr ^ (pac & cmp_mask); + ARMPauthFeature fault_feature = + is_combined ? PauthFeat_FPACCOMBINED : PauthFeat_FPAC; + uint64_t result = ptr ^ (pac & cmp_mask); + + if (pauth_feature >= fault_feature + && ((result ^ sextract64(result, 55, 1)) & cmp_mask)) { + pauth_fail_exception(env, data, keynumber, ra); + } + return result; } if ((pac ^ ptr) & cmp_mask) { From patchwork Tue Aug 29 23:23:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718254 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp243134wrh; Tue, 29 Aug 2023 16:24:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFnUMQyKb7ogw6l+04gIHYSUp8Bdvm+Zl8J3Mrq1MXiLyZJiHI3+oVz25LEKOTmnj+Afi4N X-Received: by 2002:a05:622a:100c:b0:411:fa39:c340 with SMTP id d12-20020a05622a100c00b00411fa39c340mr596383qte.17.1693351465214; Tue, 29 Aug 2023 16:24:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351465; cv=none; d=google.com; s=arc-20160816; b=RElGm0lDIhAGqC7KH/edsupL22myzvWdHii+lIqOzMaPn7kX3bmO6jjy+zMl1KWq/x 1uieP66K5ian2xtdowRlO91ktomKHJDvAui4wF6g7rE/Y7V20j3rsCrrFF9p4T8kr1ne CHoyMQtlpwvYuPFkx82DOCyWnVUYUut3iRGhOZIjMz1U+RGB/mvEy1J81/oWGE5lrHTw y3sZobeCSPo4eGqmnSsdTBzgzLAx4hqLgW4tURhdr/tbJECTeHAQWK9rLZYr0hfegX5W nfkaopeZPpbc19BNzvYF9HycBMdK2qyB5mond3IQ3YgaJRXnXGcRPUwvz83/ro47e6O8 wkHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fonDp/wXRvCIKOTr9zFpwn6DY7PZ+KvY5INrQDOWD5c=; fh=EfLVKF30PRMlBBLnPfTKrxZS/PAO9ADHBdRXKXa4nd0=; b=vpGcy0+pxbb1+DFfA41Gw1toySmkz3RXKTvkKnBBQDUeY1q4dhbv0vj+rNrwx53j3l 6+i6QvwHru5/OIFLVg9Wt8Zdp7S9TkvcizkYPdbjvUmMK9p+z0yAlK02HTw8ZVj6c7qm ja9CpEnUWmbB0LKqZmB//M3VZgxvWF60Ex45bIH9XT1e230chnRZvloobKskuHsSdSQY blmL8gASy6QOlLkX6wqMj7pzZ09rGBwrzjjf98K2Kg6gj21lZtcmX1cV+34D5xDTodZf HAqJ0QeLN9MhTgh1WZJvhw57W3PmDMGr+BYK2MPsz+oRogkP76mdke9hcsFmpYiwr6bS YcuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kcwbcAEZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n16-20020a05622a11d000b004108ce9253asi6667708qtk.298.2023.08.29.16.24.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:24:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kcwbcAEZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83z-0004p6-NN; Tue, 29 Aug 2023 19:23:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83t-0004AS-Ix for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:53 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83n-0001OU-K5 for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:53 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-68a402c1fcdso3466475b3a.1 for ; Tue, 29 Aug 2023 16:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351426; x=1693956226; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fonDp/wXRvCIKOTr9zFpwn6DY7PZ+KvY5INrQDOWD5c=; b=kcwbcAEZ5WahBfHQjzYIpa0UrmbF2krCmwTtOJZyFfrbRcPT/2XUESjI7jNrgnY3m5 nu4NrJEMCwVKpCH/UcXPKbmDSgNMJkPFv4ebWiqzGys1n1mXXZO3BdshyTxfs+GRDvN1 Jomu9DtDwm7tCKGDcad84a5OqOLu5cqQZEBVPTScdF6j2ePjbAU2Mw6By1057VfV/ubX oyKziDgadVrkoDhhqmeeYFv/rpH6g3wEju4jayGV3W/Bm4lRmLVocOX9JqCylq6VTG/s hgMTeCcBiyOzulwFK07oRMRIbvVLoZwNNfDqWCPtzZoIFSU8w+rboaQWLbPMbykOFl30 d90Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351426; x=1693956226; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fonDp/wXRvCIKOTr9zFpwn6DY7PZ+KvY5INrQDOWD5c=; b=Y51zJzRgbigzfAGWgJTzmJcxkeE2uW4QFRqPZo8/UDDNKG1N54liw+dP7Pe3NRc8wZ hsnt2pjoEUdOv394yuZWBU/3JVa3oNOK3L6fKP/G7JrsNhcPzXT5jK5Y3kGMXHr8VqYQ mPJNwFcsJiWGUlEpnMHsWPETIuozsLMTjilYT2UPKEv6tS6xx50PXujnkMMlMF/afNGW SGYk8sFo35SVeNY7wPKxrN1oZgS8nXe3Sqhh9zNwO/vfV9IgvEq7DqGxYcdvT71QuDgu /ja6oTnqxeso3cfv7ATC/nlCm1rLVGOWtVh95Q+FhJ0sEhzJf14vQ2AJSNrrWrBV51Tm 9iIg== X-Gm-Message-State: AOJu0YzY3IOj15gYa8B83Qm7mZYW2rLztJpLR02ltu6PeS4N+nvzMZga VpTwa+Dc7zOy9gii4fyG00Tgxgd3jiN4uvK/mkk= X-Received: by 2002:a05:6a20:6a1a:b0:133:e3e3:dc07 with SMTP id p26-20020a056a206a1a00b00133e3e3dc07mr893323pzk.49.1693351426151; Tue, 29 Aug 2023 16:23:46 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org Subject: [PATCH v5 10/12] linux-user/aarch64: Add ESR signal frame for SIGSEGV, SIGBUS Date: Tue, 29 Aug 2023 16:23:33 -0700 Message-Id: <20230829232335.965414-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org These are all synchronous exceptions for which the kernel passes on ESR to the user signal handler. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 52 ++++++++++++++++++++++++++++++++++++- target/arm/tcg/tlb_helper.c | 8 +++++- 2 files changed, 58 insertions(+), 2 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index b265cfd470..40a476c33e 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -21,6 +21,7 @@ #include "user-internals.h" #include "signal-common.h" #include "linux-user/trace.h" +#include "target/arm/syndrome.h" struct target_sigcontext { uint64_t fault_address; @@ -64,6 +65,13 @@ struct target_fpsimd_context { uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */ }; +#define TARGET_ESR_MAGIC 0x45535201 + +struct target_esr_context { + struct target_aarch64_ctx head; + uint64_t esr; +}; + #define TARGET_EXTRA_MAGIC 0x45585401 struct target_extra_context { @@ -191,6 +199,14 @@ static void target_setup_end_record(struct target_aarch64_ctx *end) __put_user(0, &end->size); } +static void target_setup_esr_record(struct target_esr_context *esr, + CPUARMState *env) +{ + __put_user(TARGET_ESR_MAGIC, &esr->head.magic); + __put_user(sizeof(struct target_esr_context), &esr->head.size); + __put_user(env->exception.syndrome, &esr->esr); +} + static void target_setup_sve_record(struct target_sve_context *sve, CPUARMState *env, int size) { @@ -443,6 +459,10 @@ static int target_restore_sigframe(CPUARMState *env, fpsimd = (struct target_fpsimd_context *)ctx; break; + case TARGET_ESR_MAGIC: + /* ignore */ + break; + case TARGET_SVE_MAGIC: if (sve || size < sizeof(struct target_sve_context)) { goto err; @@ -558,6 +578,27 @@ static int alloc_sigframe_space(int this_size, target_sigframe_layout *l) return this_loc; } +static bool need_save_esr(target_siginfo_t *info, CPUARMState *env) +{ + int sig = info->si_signo; + int type = info->si_code >> 16; + + if (type != QEMU_SI_FAULT) { + return false; + } + + /* + * See arch/arm64/mm/fault.c, for invocations of set_thread_esr. + * We populate ESR in arm_cpu_record_sigsegv or arm_cpu_record_sigbus, + * called via cpu_loop_exit_{sigsegv,sigbus}. + */ + if (sig == TARGET_SIGSEGV || sig == TARGET_SIGBUS) { + return true; + } + + return false; +} + static void target_setup_frame(int usig, struct target_sigaction *ka, target_siginfo_t *info, target_sigset_t *set, CPUARMState *env) @@ -567,7 +608,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, .total_size = offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0; + int fpsimd_ofs, fr_ofs, esr_ofs = 0, sve_ofs = 0, za_ofs = 0; int sve_size = 0, za_size = 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; @@ -577,6 +618,12 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, fpsimd_ofs = alloc_sigframe_space(sizeof(struct target_fpsimd_context), &layout); + /* ESR state needs saving only for certain signals. */ + if (need_save_esr(info, env)) { + esr_ofs = alloc_sigframe_space(sizeof(struct target_esr_context), + &layout); + } + /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || cpu_isar_feature(aa64_sme, env_archcpu(env))) { @@ -637,6 +684,9 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, layout.extra_size); target_setup_end_record((void *)frame + layout.extra_end_ofs); } + if (esr_ofs) { + target_setup_esr_record((void *)frame + esr_ofs, env); + } if (sve_ofs) { target_setup_sve_record((void *)frame + sve_ofs, env, sve_size); } diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index b22b2a4c6e..27bf30e9e2 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -354,7 +354,13 @@ void arm_cpu_record_sigsegv(CPUState *cs, vaddr addr, { ARMMMUFaultInfo fi = { .type = maperr ? ARMFault_Translation : ARMFault_Permission, - .level = 3, + /* + * In arch/arm64/mm/fault.c, set_thread_esr, for kernel-space + * addresses (i.e. TTBR1) the kernel cleans the ESR value to + * always report level 0. Since we're manufacturing a level + * here, we might as well pick 0 always. + */ + .level = 0, }; ARMCPU *cpu = ARM_CPU(cs); From patchwork Tue Aug 29 23:23:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718267 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp244636wrh; Tue, 29 Aug 2023 16:29:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF+MJm5B0ZcXhCrW3Z87uXX3msR2uPD0v+D+aB343QwD2+5G57n2zvPxL6paAkLoFRXiZua X-Received: by 2002:a05:620a:1792:b0:76f:456:38fb with SMTP id ay18-20020a05620a179200b0076f045638fbmr624841qkb.31.1693351746548; Tue, 29 Aug 2023 16:29:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351746; cv=none; d=google.com; s=arc-20160816; b=GtfOoqYMRxvsGku1A6pyzvxywmQrEMpb/O2atfCXh0Yw+CIAvTLQRe7YDOv2m/VtDS S+LJpE1VSpJroHLsmbK2oK4c+BdxlSHARrIw5gavCn1iXhhdGGynGhBG1byqJY1Hn78g I8um2f1Dqtin/nIAieSAbDEG143Hjo4V2zx4RErEtmoKyPgMINmkNLKVw9jG0KdjeT0w RZmJP0vD4H+WHVdhlXHg0y1ZYGpu7t71ZQGB6/WkdQDCnQRW96WbtxR4LiVvkL+i5ioM RYtvG1E0ljcr+JSuoqd3gEANqHueJI4wizGLKf4coSADqq9No1ky6LjJK7b5Dh75NSag WZ7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1kQdNiCM9Zqst6RWSQxeqs+p1o22wGyR4sXs05ml1eo=; fh=L6OjQZ2TPsHFQEGPRBuboSqhQBavDZ5pPqlyX67xn3A=; b=mpsM7+PMscnSq5Q+kNVJuqjcd76H23vjr7InmfiOMTHc1426aSxBmmw9nzzrestBTT at71VAX8ZgEA+xnLxh9lo0cCKti/rs30CMd5Tj/aRgM/ESA5U9IwfgJm46cEKFjkkxkg 1XDzT0zYi77TD+KWbncTAckOQkPfu2uHKW0teWk9hsu3CPDiEUabUVM/9UeWqOoMdYy2 UzkaQoGAPOcmyfwW1DI7FgQGYtBEFtFdUKJEVqp6wBezeinTrQwdOYpBR370/Kt8xzBa q6kAKykckaKoOOV+Eh89q9mC6yxdVDWv7y4G+/HgaqmNunSWs4KhWfxFNYMEHQr5tWg0 oKog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M1zBRhaF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v16-20020ac85790000000b00403af394f7asi4593979qta.327.2023.08.29.16.29.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:29:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=M1zBRhaF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83x-0004dj-Et; Tue, 29 Aug 2023 19:23:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83t-0004A3-F0 for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:53 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83o-0001Om-C9 for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:53 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-68a42d06d02so3481421b3a.0 for ; Tue, 29 Aug 2023 16:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351427; x=1693956227; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1kQdNiCM9Zqst6RWSQxeqs+p1o22wGyR4sXs05ml1eo=; b=M1zBRhaFJLKf4SKXp8KDIBr9Mw2/K1tBixAa0tOmVz4poIzyXwIM+23+EfA7xlrpBY 59VC1SEr62ngm4Rv9qrCdGA7W1yimBvRWrAUygQZU/JoFkWdV/EWeme1Go5q+buQ45in NnZau6GedSO61cWYed8LrjJLzujjqJ3aboXVWDXeB7G+u56qUb6OfBVGOjOd7WH59Bbz 1NSNMl4EzIm3MbMOFfsN/9f2PCYbIf68nqg13bxKKoOyQrlqdhL6YD+thn2+pvExpIwp ov+TeuXd5DEvQfuZ+ZkkHsEvklMOMFxHDaBB2+RCatgswSHfIZ+IIE0q7trlBJYgZnpK VudA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351427; x=1693956227; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1kQdNiCM9Zqst6RWSQxeqs+p1o22wGyR4sXs05ml1eo=; b=e9UZ1isCiUa7eDMVx0r5IrILbr17IIihZuq6tAgwFIZ+YuWkbzwEDfAo9pOL9Kz4pC REsoC8xbWPjHcLrHuAhPwIyBa4mK3ds4OHj3oldrLw7FUVfAXDEvv6e+3h1Zh+p4gZSE J6pHIUougkbIuI/CZp8gkHcYWPzti0b2TkCo7yaNCIu+R4ZUSSZjrOOxCXG5fZ/K0Z6Q a+7dX6rRqyxlH73ttEx2DZRjJaj9fTF7Ekd/jL72imflI0DccILwYBmCeSzbBeGH+QMB 47PnOBJY0h5hb5ZjAKATvKkOpcpybLiZ2xtZRtOAsCvvvnjd6XjKeRcNsFRm9/Su0GWO eDUA== X-Gm-Message-State: AOJu0YwIKpn7cap8BAB9ufBWWVNJ32XyAX27zB680SF4aTFzzhcyQ+sq +IKLFVGWkLq9PLgl5IxllUYvOSW9ce8tH2Gqqmc= X-Received: by 2002:a05:6a20:138b:b0:14e:3ac2:e10d with SMTP id hn11-20020a056a20138b00b0014e3ac2e10dmr627463pzc.47.1693351426989; Tue, 29 Aug 2023 16:23:46 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 11/12] linux-user/aarch64: Fix normal SIGILL si_code Date: Tue, 29 Aug 2023 16:23:34 -0700 Message-Id: <20230829232335.965414-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Most illegal instructions use ILL_ILLOPC. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 2e2f7cf218..22c9789326 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -110,7 +110,7 @@ void cpu_loop(CPUARMState *env) /* just indicate that signals should be handled asap */ break; case EXCP_UDEF: - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc); break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: From patchwork Tue Aug 29 23:23:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 718265 Delivered-To: patch@linaro.org Received: by 2002:adf:d20a:0:b0:31d:da82:a3b4 with SMTP id j10csp244550wrh; Tue, 29 Aug 2023 16:28:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGgJHciToffAGdJ5wmh7w+8nxezT4vbuiu080CcebkwLIGL44mIS8qV9/eGlg2kroZDzPMR X-Received: by 2002:a0d:d811:0:b0:583:f837:2c1 with SMTP id a17-20020a0dd811000000b00583f83702c1mr547616ywe.8.1693351730765; Tue, 29 Aug 2023 16:28:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1693351730; cv=none; d=google.com; s=arc-20160816; b=PFB7itb1IvTjEjNjdeTuQY2agNsdwRc7K04QmI3NcFR28gD4gOKS1SQTy8ymGCPOIV bycCWV4XZEBUPd1bZ4+0QujGpPjHbbfLSXS2qnePZOtn6FBbnBkU31qMubppV5RtdXrX wDLvkzTMEFWgRG+CeqIpKdhRHHxYNwAS6oFJvKq1aIsjet3c2CyHqzPDvSgM4mVt5F+5 +yXN84jScSOQu8lKicDi556AjpeIBzgm3uIp7QhklrpFnTFbVnr5RIiWFNEIrRlK+5bN UDOXS6WiqGXLyXJFKqeLsjHTsxo4DGw9hn4HTzusT889ATC7LgfOJCIXocpt5sIS5sZc sw5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rbgZWuFBEAnasVpd2Kly8rMi99QBufRW3Lhak1ajaXE=; fh=L6OjQZ2TPsHFQEGPRBuboSqhQBavDZ5pPqlyX67xn3A=; b=SCGLCabsh/4i8Wj9VyIjBUiPoW6UikQQhw79dxlhQy5i5bpbnVvDNGouMkulhUoERE /ZxFI1uJQDtp/20qBkP78YpBPmsUeUEjETPMqwlfNQbt7AUTKDl+cdb7f/km9O9Zdjrc b61T5Etr8drEfm2A+37mvSizgbZgy7VMJw1NDfaKppy0V+9JyuIHUmq5YMcSAzGOhJ7v 8Yowxfem192q9JFmx3FkbYIOEiBMqUE8OeqRCMSEzvTlPc6v8xaay4PUN7clJwdlYxE7 x/asawA6pAeghw12PQfOw6W5QkihO9suEm41loJxsIurFnM7uFBuyLmTZPn5Q9hgBHB2 2tXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gHhryrUm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n16-20020a0cdc90000000b0064f572979aasi4418118qvk.60.2023.08.29.16.28.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 29 Aug 2023 16:28:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gHhryrUm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qb83x-0004fo-SL; Tue, 29 Aug 2023 19:23:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qb83u-0004Hj-GO for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:54 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qb83p-0001Ow-74 for qemu-devel@nongnu.org; Tue, 29 Aug 2023 19:23:54 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1bf3a2f4528so39093565ad.2 for ; Tue, 29 Aug 2023 16:23:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1693351428; x=1693956228; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rbgZWuFBEAnasVpd2Kly8rMi99QBufRW3Lhak1ajaXE=; b=gHhryrUmHCuN0NKKsuWxIXwBWnIbVCONpe3nOOHM8gQznbPGp014AapaSS23ttzKQ9 5pw1nWuWyJxh21YrOaMkp+fG0i4++tcQwnuM3RPJg86STOn7zU2d+2hkeHTqQn6B/R9B ZJhOLJWGnFCIE1iSpYU25Zu2HmFM4bev3PxnU93DRLkG0Q1jN1n+OhwXNn0j8PSc4K/w BrV+4rEjkdzEclt9Y4Rk7DLXbG+lx1rOFWBeuYR1dirXn0+v9v4AG4DdmEs/A+17miCM jnEvi6mH0EzSjFfK/Me/GndgH4GTLkmwCHvG+gu9BgeNp/qD/cVujsks3Os/y3baApeE lFnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1693351428; x=1693956228; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rbgZWuFBEAnasVpd2Kly8rMi99QBufRW3Lhak1ajaXE=; b=c7Edbjc+YOfPEgrJs1mcEYaXrXGP7x8HlMPlYQrjc458HH5NC1bat/F2JWDPB5389o SvQ7Qrhm9eDFJLMRBEXdEk+aL16u2thILRX2FgYsWBA6Pm/w5TkZDupu+itS0I6TG3tI zmjIcX9fRWNAO8zpmT/lsGzot+ylZh2T5Q1k4d4nvPGx2yinMFgwYplS8YqarOzYTo7j xPQm8r1TONi6YjmxZko+9o5BEXyOaCBGs9R/hla5stSg5/saT04LYyElwI5eeoOvDoOt obPcuU5/kcBdOURfEEc8cF9bDleYBRUBCKV7DnwevHGwYk1wO2BA3HOqPs2hdn1c9dCu oapA== X-Gm-Message-State: AOJu0YxSIQnk1ytyoC2GSpONbC1WWzJawGa6jqLJlKvtmSj3Gwd4GGFm yu3R0FMJLTbyYgfi2p6920zrjrxMhjHOWwi094Y= X-Received: by 2002:a17:902:e5cc:b0:1c0:d89e:904a with SMTP id u12-20020a170902e5cc00b001c0d89e904amr610179plf.29.1693351427816; Tue, 29 Aug 2023 16:23:47 -0700 (PDT) Received: from stoup.. ([71.212.131.115]) by smtp.gmail.com with ESMTPSA id t9-20020a170902e84900b001b9dadf8bd2sm9829970plg.190.2023.08.29.16.23.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Aug 2023 16:23:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: aaron@os.amperecomputing.com, qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 12/12] linux-user/aarch64: Add ESR signal frame for PACFAIL Date: Tue, 29 Aug 2023 16:23:35 -0700 Message-Id: <20230829232335.965414-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230829232335.965414-1-richard.henderson@linaro.org> References: <20230829232335.965414-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The PACFAIL fault uses ILL_ILLOPN and includes ESR. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 7 ++++++- linux-user/aarch64/signal.c | 6 ++++++ tests/tcg/aarch64/pauth-2.c | 25 ++++++++++++++++++++++++- 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 22c9789326..5af17e8724 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -110,7 +110,12 @@ void cpu_loop(CPUARMState *env) /* just indicate that signals should be handled asap */ break; case EXCP_UDEF: - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc); + /* See kernel's do_el0_fpac, and our need_save_esr(). */ + if (syn_get_ec(env->exception.syndrome) == EC_PACFAIL) { + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); + } else { + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc); + } break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 40a476c33e..375b8350f6 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -582,6 +582,7 @@ static bool need_save_esr(target_siginfo_t *info, CPUARMState *env) { int sig = info->si_signo; int type = info->si_code >> 16; + int code = info->si_code & 0xffff; if (type != QEMU_SI_FAULT) { return false; @@ -596,6 +597,11 @@ static bool need_save_esr(target_siginfo_t *info, CPUARMState *env) return true; } + /* See arch/arm64/kernel/traps.c, do_el0_fpac, and our cpu_loop(). */ + if (sig == TARGET_SIGILL && code == TARGET_ILL_ILLOPN) { + return true; + } + return false; } diff --git a/tests/tcg/aarch64/pauth-2.c b/tests/tcg/aarch64/pauth-2.c index 89ffdbf1df..aaf7c4a19f 100644 --- a/tests/tcg/aarch64/pauth-2.c +++ b/tests/tcg/aarch64/pauth-2.c @@ -5,14 +5,37 @@ #include "pauth.h" +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + static void sigill(int sig, siginfo_t *info, void *vuc) { ucontext_t *uc = vuc; - uint64_t test; + struct _aarch64_ctx *hdr; + struct esr_context *ec; + uint64_t test, esr; /* There is only one insn below that is allowed to fault. */ asm volatile("adr %0, auth2_insn" : "=r"(test)); assert(test == uc->uc_mcontext.pc); + + /* Find the esr_context. */ + for (hdr = first_ctx(uc); hdr->magic != ESR_MAGIC; hdr = next_ctx(hdr)) { + assert(hdr->magic != 0); + } + + ec = (struct esr_context *)hdr; + esr = ec->esr; + + assert((esr >> 26) == 0x1c); /* EC_PACFAIL */ + assert((esr & 3) == 2); /* AUTDA: data=1 key=0 */ exit(0); }