From patchwork Thu Aug 24 16:13:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 716666 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92C8EC3DA6F for ; Thu, 24 Aug 2023 16:15:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233594AbjHXQO3 (ORCPT ); Thu, 24 Aug 2023 12:14:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242418AbjHXQN6 (ORCPT ); Thu, 24 Aug 2023 12:13:58 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 5340C19A9; Thu, 24 Aug 2023 09:13:50 -0700 (PDT) X-IronPort-AV: E=Sophos;i="6.02,195,1688396400"; d="scan'208";a="177560078" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 25 Aug 2023 01:13:49 +0900 Received: from localhost.localdomain (unknown [10.226.93.115]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 02E9C4013DC0; Fri, 25 Aug 2023 01:13:46 +0900 (JST) From: Biju Das To: Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Biju Das , Geert Uytterhoeven , Magnus Damm , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar Mahadev Lad Subject: [PATCH v2] arm64: dts: renesas: rz-smarc-common: Use versa3 clk for audio mclk Date: Thu, 24 Aug 2023 17:13:44 +0100 Message-Id: <20230824161344.382188-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Currently audio mclk uses a fixed clk of 11.2896MHz (multiple of 44.1kHz). Replace this fixed clk with the programmable versa3 clk that can provide the clocking to support both 44.1kHz (with a clock of 11.2896MHz) and 48kHz (with a clock of 12.2880MHz), based on audio sampling rate for playback and record. Signed-off-by: Biju Das --- v1->v2: * Made Versa3 clock mapping as per HW manual and updated clocks property in codec_dai. * Replaced the node xtal->x1-clock and label x1_x2->x1 as x2 is a different crystal. * Updated clock-frequency = <400000> for i2c0 node in RZ/G2UL SMARC EVK. --- .../boot/dts/renesas/rz-smarc-common.dtsi | 14 +++++------ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 20 ++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 20 ++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 24 +++++++++++++++++++ 4 files changed, 71 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index a7594ba3a998..b7a3e6caa386 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -32,12 +32,6 @@ chosen { stdout-path = "serial0:115200n8"; }; - audio_mclock: audio_mclock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <11289600>; - }; - snd_rzg2l: sound { compatible = "simple-audio-card"; simple-audio-card,format = "i2s"; @@ -55,7 +49,7 @@ cpu_dai: simple-audio-card,cpu { }; codec_dai: simple-audio-card,codec { - clocks = <&audio_mclock>; + clocks = <&versa3 2>; sound-dai = <&wm8978>; }; }; @@ -76,6 +70,12 @@ vccq_sdhi1: regulator-vccq-sdhi1 { gpios-states = <1>; states = <3300000 1>, <1800000 0>; }; + + x1: x1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; }; &audio_clk1 { diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 68eab8e26bf2..c05acd70f1fa 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -105,6 +105,26 @@ &i2c3 { status = "okay"; + versa3: versa3@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; + wm8978: codec@1a { compatible = "wlf,wm8978"; #sound-dai-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 83fce96a2575..3c40b66b33b0 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -121,6 +121,26 @@ &i2c2 { status = "okay"; + versa3: versa3@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; + wm8978: codec@1a { compatible = "wlf,wm8978"; #sound-dai-cells = <0>; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index 8eb411aac80d..dacf35c16648 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -20,6 +20,30 @@ &cpu_dai { sound-dai = <&ssi1>; }; +&i2c0 { + clock-frequency = <400000>; + + versa3: versa3@68 { + compatible = "renesas,5p35023"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&x1>; + + renesas,settings = [ + 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf + 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6 + 80 b0 45 c4 95 + ]; + + assigned-clocks = <&versa3 0>, <&versa3 1>, + <&versa3 2>, <&versa3 3>, + <&versa3 4>, <&versa3 5>; + assigned-clock-rates = <24000000>, <11289600>, + <11289600>, <12000000>, + <25000000>, <12288000>; + }; +}; + &i2c1 { wm8978: codec@1a { compatible = "wlf,wm8978";