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([2602:47:d483:7301:4e3c:f4a4:b92a:b5ab]) by smtp.gmail.com with ESMTPSA id 27-20020a17090a031b00b00264040322desm8761121pje.40.2023.08.22.10.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Aug 2023 10:02:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 1/3] linux-user/aarch64: Add ESR signal frame for SIGSEGV, SIGBUS Date: Tue, 22 Aug 2023 10:02:07 -0700 Message-Id: <20230822170209.1130173-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230822170209.1130173-1-richard.henderson@linaro.org> References: <20230822170209.1130173-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org These are all synchronous exceptions for which the kernel passes on ESR to the user signal handler. Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 48 ++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index b265cfd470..b2280fa9e3 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -21,6 +21,7 @@ #include "user-internals.h" #include "signal-common.h" #include "linux-user/trace.h" +#include "target/arm/syndrome.h" struct target_sigcontext { uint64_t fault_address; @@ -64,6 +65,13 @@ struct target_fpsimd_context { uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */ }; +#define TARGET_ESR_MAGIC 0x45535201 + +struct target_esr_context { + struct target_aarch64_ctx head; + uint64_t esr; +}; + #define TARGET_EXTRA_MAGIC 0x45585401 struct target_extra_context { @@ -191,6 +199,14 @@ static void target_setup_end_record(struct target_aarch64_ctx *end) __put_user(0, &end->size); } +static void target_setup_esr_record(struct target_esr_context *esr, + CPUARMState *env) +{ + __put_user(TARGET_ESR_MAGIC, &esr->head.magic); + __put_user(sizeof(struct target_esr_context), &esr->head.size); + __put_user(env->exception.syndrome, &esr->esr); +} + static void target_setup_sve_record(struct target_sve_context *sve, CPUARMState *env, int size) { @@ -443,6 +459,10 @@ static int target_restore_sigframe(CPUARMState *env, fpsimd = (struct target_fpsimd_context *)ctx; break; + case TARGET_ESR_MAGIC: + /* ignore */ + break; + case TARGET_SVE_MAGIC: if (sve || size < sizeof(struct target_sve_context)) { goto err; @@ -558,6 +578,23 @@ static int alloc_sigframe_space(int this_size, target_sigframe_layout *l) return this_loc; } +static bool need_save_esr(target_siginfo_t *info, CPUARMState *env) +{ + int sig = info->si_signo; + int type = info->si_code >> 16; + + if (type != QEMU_SI_FAULT) { + return false; + } + + /* See arch/arm64/mm/fault.c, set_thread_esr. */ + if (sig == TARGET_SIGSEGV || sig == TARGET_SIGBUS) { + return true; + } + + return false; +} + static void target_setup_frame(int usig, struct target_sigaction *ka, target_siginfo_t *info, target_sigset_t *set, CPUARMState *env) @@ -567,7 +604,7 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, .total_size = offsetof(struct target_rt_sigframe, uc.tuc_mcontext.__reserved), }; - int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0; + int fpsimd_ofs, fr_ofs, esr_ofs = 0, sve_ofs = 0, za_ofs = 0; int sve_size = 0, za_size = 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; @@ -577,6 +614,12 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, fpsimd_ofs = alloc_sigframe_space(sizeof(struct target_fpsimd_context), &layout); + /* ESR state needs saving only for certain signals. */ + if (need_save_esr(info, env)) { + esr_ofs = alloc_sigframe_space(sizeof(struct target_esr_context), + &layout); + } + /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || cpu_isar_feature(aa64_sme, env_archcpu(env))) { @@ -637,6 +680,9 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, layout.extra_size); target_setup_end_record((void *)frame + layout.extra_end_ofs); } + if (esr_ofs) { + target_setup_esr_record((void *)frame + esr_ofs, env); + } if (sve_ofs) { target_setup_sve_record((void *)frame + sve_ofs, env, sve_size); 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Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 2e2f7cf218..22c9789326 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -110,7 +110,7 @@ void cpu_loop(CPUARMState *env) /* just indicate that signals should be handled asap */ break; case EXCP_UDEF: - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc); break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: From patchwork Tue Aug 22 17:02:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 715763 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp374288wrp; Tue, 22 Aug 2023 10:02:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFd8N+Y9/eSwyTxHsrcNaWUYDxIeeespjXcCa/T2hL/EWn5DVPKOtlv7IYPuf1TMCGKOj51 X-Received: by 2002:ac8:5b44:0:b0:403:c9c9:e4ea with SMTP id n4-20020ac85b44000000b00403c9c9e4eamr12686667qtw.38.1692723765214; Tue, 22 Aug 2023 10:02:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692723765; cv=none; d=google.com; s=arc-20160816; b=n5hOCRi57+hOJ5nns2pVbAoFOtNknUg/rNu6EqXEMF5tvvcHmvMtrUnIC1OHRMGd/c aZqg7UEc9F7AOIrBlt/NrNJyo6afJ9qq/CSGvBkjMySEZKBxsk2UtmoBtNYtlIkFNVSp OyQ8pbKAMpQbkVXPC2ZYHRqs58ETUxnmOCFlcb8sojGKP4D/0P3/MjhMjn3oatUYjdxw i6Xc4V8BOnMMRS6N/DtqGMKRbSyzK5ny8+Qxu5A1WlSxJZdIeVAJkHaphh00iVMFOlY4 I/qDW9+oxB6LOyvvG3KTDiXqpDxHFWB5vlC3XW5Wp0//Fow/gtrEsksOrbgwdMDl01pM TGcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WtbxWpkqRs8uhBP9ntrNj0PDPLSc0E50BaiAIV/fKrE=; fh=oweadga+1U1BKjDqlK8hSmEWEC1EUfcsKuPkDinEDsU=; b=z12OanQMxSo9Es7jyR+nmD2mPnEY1skuaM1H7ReUqqaynS2J5PcMFq0iniUwezMLMD GorEpua4OZqu0GAk7+QzJixlr1GtFDECZutZBb788g+xqmyQR0/aAp8yn0R+hkRVbWVW +p6EyJjHBcxfmSq8fx4JV2H5dBF6fFumBbT7BdnALV24+0YsZd0SIM1qInPhNG2qyQEz 5uJL9h/MuL7TXIsIyLkh27TCvxhLsw/DyGDF1ywDIzSsrUBpDgeYvMsme58SbaFRzygj 9/V2uFeq1nPeLj8DG6aW7STsDWYibQfTWClP9wcw4fpuTJfAAc65WMoUsGpqG9Ig39Gi Rp1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pxAWm1bh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d483:7301:4e3c:f4a4:b92a:b5ab]) by smtp.gmail.com with ESMTPSA id 27-20020a17090a031b00b00264040322desm8761121pje.40.2023.08.22.10.02.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Aug 2023 10:02:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 3/3] linux-user/aarch64: Add ESR signal frame for PACFAIL Date: Tue, 22 Aug 2023 10:02:09 -0700 Message-Id: <20230822170209.1130173-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230822170209.1130173-1-richard.henderson@linaro.org> References: <20230822170209.1130173-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The PACFAIL fault uses ILL_ILLOPN and includes ESR. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 7 ++++++- linux-user/aarch64/signal.c | 6 ++++++ tests/tcg/aarch64/pauth-2.c | 25 ++++++++++++++++++++++++- 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 22c9789326..5af17e8724 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -110,7 +110,12 @@ void cpu_loop(CPUARMState *env) /* just indicate that signals should be handled asap */ break; case EXCP_UDEF: - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc); + /* See kernel's do_el0_fpac, and our need_save_esr(). */ + if (syn_get_ec(env->exception.syndrome) == EC_PACFAIL) { + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); + } else { + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc); + } break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index b2280fa9e3..bcdd796cc2 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -582,6 +582,7 @@ static bool need_save_esr(target_siginfo_t *info, CPUARMState *env) { int sig = info->si_signo; int type = info->si_code >> 16; + int code = info->si_code & 0xffff; if (type != QEMU_SI_FAULT) { return false; @@ -592,6 +593,11 @@ static bool need_save_esr(target_siginfo_t *info, CPUARMState *env) return true; } + /* See arch/arm64/kernel/traps.c, do_el0_fpac, and our cpu_loop(). */ + if (sig == TARGET_SIGILL && code == TARGET_ILL_ILLOPN) { + return true; + } + return false; } diff --git a/tests/tcg/aarch64/pauth-2.c b/tests/tcg/aarch64/pauth-2.c index d498d7dd8b..62b39af3d0 100644 --- a/tests/tcg/aarch64/pauth-2.c +++ b/tests/tcg/aarch64/pauth-2.c @@ -4,14 +4,37 @@ #include #include +static inline struct _aarch64_ctx *first_ctx(ucontext_t *uc) +{ + return (struct _aarch64_ctx *)&uc->uc_mcontext.__reserved; +} + +static inline struct _aarch64_ctx *next_ctx(struct _aarch64_ctx *hdr) +{ + return (struct _aarch64_ctx *)((char *)hdr + hdr->size); +} + static void sigill(int sig, siginfo_t *info, void *vuc) { ucontext_t *uc = vuc; - uint64_t test; + struct _aarch64_ctx *hdr; + struct esr_context *ec; + uint64_t test, esr; /* There is only one insn below that is allowed to fault. */ asm volatile("adr %0, auth2_insn" : "=r"(test)); assert(test == uc->uc_mcontext.pc); + + /* Find the esr_context. */ + for (hdr = first_ctx(uc); hdr->magic != ESR_MAGIC; hdr = next_ctx(hdr)) { + assert(hdr->magic != 0); + } + + ec = (struct esr_context *)hdr; + esr = ec->esr; + + assert((esr >> 26) == 0x1c); /* EC_PACFAIL */ + assert((esr & 3) == 2); /* AUTDA: data=1 key=0 */ exit(0); }