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Cc: Patrice Chotard Cc: Patrick Delaunay Signed-off-by: Bhupesh Sharma Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/mach-stm32mp/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index e2f67fc423..8ed065b389 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -90,10 +90,10 @@ static void early_enable_caches(void) if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) return; - if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { +#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) gd->arch.tlb_size = PGTABLE_SIZE; gd->arch.tlb_addr = (unsigned long)&early_tlb; - } +#endif /* enable MMU (default configuration) */ dcache_enable(); From patchwork Tue Aug 22 07:51:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 715711 Delivered-To: patch@linaro.org Received: by 2002:adf:f747:0:b0:317:ecd7:513f with SMTP id z7csp129912wrp; Tue, 22 Aug 2023 00:51:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFQrq6W1VaEWag9mc8FcSItro2AhriFHNPFg4gSha1yZ69HO/adpPsh9WL0Gjcke8b/Pcw5 X-Received: by 2002:a05:600c:2291:b0:3f9:b8df:26ae with SMTP id 17-20020a05600c229100b003f9b8df26aemr6456774wmf.34.1692690706062; Tue, 22 Aug 2023 00:51:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1692690706; cv=none; d=google.com; s=arc-20160816; b=j8OVpb68oe7lRAqWnWW2Vqj9wGS+Z9xgWFdFoMlRSEYy9XK6/GGhO0a+ARC8RkiBZ2 8yIpDstZ4CFc1MB93wq0kM2f4pfl9P9vigbdYEYYngrzuvv40RWmldUTQ/aFSeqtO2D3 PUKiTjGo6gdrhnnIwMId4yds92k7xSpm6OjBL3/V9FbYTY8ku/P+cNxtl7lX5mhg5a3s mjddNEAS5VZRmazqPQECJjzICiOv1ROsvlJytjOLk8Jj7dDjwShO9wKSMMa41P8ALR4G GAe/QaEYSYicjAzm+5aBCOvpvvBwohwvjxviVZyKeVU9qMSujBj8MuEEa97MvgfKgh/e 34kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0B9Pr4vcy2/i4HUXWV6hdXmlscBCPXb7dubV880j6IA=; fh=MDTzgJKs4XQnK6ph6dGI2SesfHHY3ZXriAcZ2DzNDDU=; b=Mvi6eJWQ1M35NwZcfddkMq+wvELHeDJJgZZv18t8VzsZOJR2DbcwarPrnBfb0xoJRC lVpIpWeTtgueBkEpcn1PzNflCiQYcXoqnFx9vALHhGTxbrrMsMgKFVGZaFYvrmMEK0kF +qWK/ePumg6NOVQsMFjiA49ISHOILHRLZ+o0/gy8RYlOZNo2zoSBmc0A/90/vSbW4B39 qNrioCl4dYfVCVZr52N+xcbWYnoNafMV8yOS2KMQz7/h1nPDYcArQ6x2Wj8IHLU42+ty dqCrXBv8HIiQQF21tnceSMYo+UCAUTdkbE/HOUXBj1NFXWhSL3pKwSX/pN2uIITlWWXB AOWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vQfQ3yXw; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. 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However, if some platforms require ICACHE or DCACHE to be disabled only for the smaller SPL stage, we should support such configurations in u-boot as well. Compile-tested for: - qemu arm64 - imx8 - stm32 and run-tested on: - Qualcomm RB3 platform Cc: Tom Rini Cc: Simon Glass Cc: Peng Fan Signed-off-by: Bhupesh Sharma Reviewed-by: Tom Rini --- arch/arm/Kconfig | 2 ++ arch/arm/cpu/armv8/Makefile | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 36ee1e9a3c..92bff715e3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -141,6 +141,7 @@ config THUMB2_KERNEL config SYS_ICACHE_OFF bool "Do not enable icache" + depends on !ARM64 help Do not enable instruction cache in U-Boot. @@ -153,6 +154,7 @@ config SPL_SYS_ICACHE_OFF config SYS_DCACHE_OFF bool "Do not enable dcache" + depends on !ARM64 help Do not enable data cache in U-Boot. diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index bba4f570db..0d0c1728e4 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -5,13 +5,13 @@ extra-y := start.o +obj-y += cache_v8.o obj-y += cpu.o ifndef CONFIG_$(SPL_TPL_)TIMER obj-$(CONFIG_SYS_ARCH_TIMER) += generic_timer.o endif ifndef CONFIG_$(SPL_)SYS_DCACHE_OFF -obj-y += cache_v8.o -obj-y += cache.o +obj-y += cache.o endif ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) += exceptions.o