From patchwork Sat Aug 19 03:17:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 715327 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46284EE49A8 for ; Sat, 19 Aug 2023 03:18:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244645AbjHSDR4 (ORCPT ); Fri, 18 Aug 2023 23:17:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244663AbjHSDRg (ORCPT ); Fri, 18 Aug 2023 23:17:36 -0400 Received: from mail-ot1-x335.google.com (mail-ot1-x335.google.com [IPv6:2607:f8b0:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2008C421D for ; Fri, 18 Aug 2023 20:17:34 -0700 (PDT) Received: by mail-ot1-x335.google.com with SMTP id 46e09a7af769-6bcb5df95c5so1261313a34.1 for ; Fri, 18 Aug 2023 20:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692415053; x=1693019853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=terWZwySlnATmuJMOqlx8HX9SM+9JePulFK7w3bJmCk=; b=uzjnUdmBIA+M9L8UZ815q/Hme4Tyj4IIPDcJIxvfc9JIAjGh2xQs/+apf6waiQbTQf 1GGjkprqSGhXZwyF7wf2UuyUJj/c/3Pp/XUeEx+LvJTK1ymI28NmKaZynCuJCLOMVXyj 2T/PAHrzx/dhxdOsU0YhoalSUHh4ItTqRdNp4YvyiP335Sn7vEfQMrdJkTc3eDF6lwyy MmIlgjNxgD68asVA9VDblH5IJeuEkqjQyp6504HV0GB2svmgH34FxP0CTqL5+2VCGV0t wLlqfyHQF6ycsrg44Pgw2srVBbEdbOFlyHu/KV0eJgksLhpMKmkfkg8hHkxng5yKV03+ Fw8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692415053; x=1693019853; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=terWZwySlnATmuJMOqlx8HX9SM+9JePulFK7w3bJmCk=; b=SxfCRMVYEYeiJ/f9/GVAUORgOckMl9mxnw9ZiFCPUk4ZS0jBCAPmIxPfg3DnFn4ad/ 1M4DEaazeYon//XEY0zQyEAGag5F1ER28aWphdtikxqmtbGaDAZIk4x1ubk50wImu4aY DXZLGorZiIGWUAQs5BXRpglVUHjjHyBcY0K+FQ2J5CN9E5yKfS4Y3stn7AJkP4VcZWm5 bbus4TvoErVQ29MtkCjViD1irpLNowFqdhhGS+fpYHX3w7AXxclVy2H658dxSmAWDY/8 sRQwYDAZ3TRWvsdtNE3IP+HQlxCXdh9Za1STiwki5SXCHHQJY4G1/uI2yp8ajdmXwpeU +X2w== X-Gm-Message-State: AOJu0Yzma0Yw+eFhX0vosz2EatKLfzG4xpI73mK/W+e5ZBDwg0twniJ/ AyAc+j5BkjSrTqr3UXr0WJsjwg== X-Google-Smtp-Source: AGHT+IE9p0fUrSh0BRemD6/2a57NfR3EO4r8wsYb4VaF67YNneCxT3TlxARU9Tja4q4pBzykKbc+LA== X-Received: by 2002:a9d:4d8e:0:b0:6bc:f85e:ab0 with SMTP id u14-20020a9d4d8e000000b006bcf85e0ab0mr1464160otk.3.1692415053415; Fri, 18 Aug 2023 20:17:33 -0700 (PDT) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id a1-20020a056830100100b006b922956cecsm1447686otp.25.2023.08.18.20.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Aug 2023 20:17:32 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Thinh Nguyen Cc: JaeHun Jung , Marek Szyprowski , Sylwester Nawrocki , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Greg Kroah-Hartman , Alim Akhtar , Marc Kleine-Budde , Heiko Stuebner , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 1/8] dt-bindings: usb: samsung,exynos-dwc3: Add Exynos850 support Date: Fri, 18 Aug 2023 22:17:24 -0500 Message-Id: <20230819031731.22618-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230819031731.22618-1-semen.protsenko@linaro.org> References: <20230819031731.22618-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Exynos850 has dwc3 compatible USB controller, so it can reuse existing dwc3 glue layer. Document a new compatible for Exynos850 and its clocks. Signed-off-by: Sam Protsenko --- .../bindings/usb/samsung,exynos-dwc3.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml index 42ceaf13cd5d..fc9a425be5fe 100644 --- a/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/samsung,exynos-dwc3.yaml @@ -15,6 +15,7 @@ properties: - samsung,exynos5250-dwusb3 - samsung,exynos5433-dwusb3 - samsung,exynos7-dwusb3 + - samsung,exynos850-dwusb3 '#address-cells': const: 1 @@ -101,6 +102,21 @@ allOf: - const: usbdrd30_susp_clk - const: usbdrd30_axius_clk + - if: + properties: + compatible: + contains: + const: samsung,exynos850-dwusb3 + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: bus_early + - const: ref + additionalProperties: false examples: From patchwork Sat Aug 19 03:17:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 715326 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F4219EE49B3 for ; Sat, 19 Aug 2023 03:18:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244663AbjHSDR5 (ORCPT ); Fri, 18 Aug 2023 23:17:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244685AbjHSDRg (ORCPT ); Fri, 18 Aug 2023 23:17:36 -0400 Received: from mail-oi1-x230.google.com (mail-oi1-x230.google.com [IPv6:2607:f8b0:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DEA94218 for ; Fri, 18 Aug 2023 20:17:35 -0700 (PDT) Received: by mail-oi1-x230.google.com with SMTP id 5614622812f47-3a7f74134e7so1082386b6e.1 for ; Fri, 18 Aug 2023 20:17:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692415054; x=1693019854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bSHQ+AygjgxqH5HVmvaPgTOe33eIHrHGDBC7hTH/La8=; b=C34abAMhDmVjj+X6tuU7eWDd92FEWuhS5gRSP/sa+1L4FcZLCHkBgX6kMHXhQ0T+vQ EyvCTzZaD6hyYCUXRBpz2uZ4m445iJ6+S4gdz4KUYK/LlS10Y82FzCx7K48KoYuKcS0M M2E4yaNXDzYzKuHIkKyvAbtS5nRz0yNxHwooagrJsYP6UFO/FKuiSu6sDWZ7dw5VGMhu jr4ZTIB0FWTw7p43ZSzKqd0g/pC81IDADqP+JzwZK0XZ+xR3UGZnKRuY+oakOPABXmkW eOEK+7HAtEqwzYqoglQigMBv3WeQclG90iYHmVKWAlDtHDLSnQwbR/srhZ3ui1uvwKb+ 2wjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692415054; x=1693019854; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bSHQ+AygjgxqH5HVmvaPgTOe33eIHrHGDBC7hTH/La8=; b=DtCZBa8lN2Un0E0GeckRCLvsBl0PgFecTWwNUJD8UBcZt2pCi2+7oGX0ENkuFENfq7 hmkKhvf+fkwyhP1j0wiP+9A076B/S0m9e5vWFpdsuVA65Mz4O9affYAAcATRbePqb9+E qidtawyHbkojEOwSHWoFNkud+cxflT3ZvSfwoJTAr2eikXa9BgWJPj0T3iNozpz42lMP 3xD4m3xe1UduvKRHOOqb+0O+D5zt2WNp1UJMXrkjsOhBmuRsz3pzylb93uPMOgOYx1eQ Uf1PA+n3m2oEAhdp1YXZFt3Y5Qc+TkDy+XW3df829zGLigORmX295oilYclTsF6I1w+t aNQw== X-Gm-Message-State: AOJu0YxAnvNwrJF++yoW8peasmOLcsNNvQInLmVkWdhUMK1Y8s/s4pgU cTVExp971f7ogU1muLG9ukjKsQ== X-Google-Smtp-Source: AGHT+IERSFZA2QdkLI3yWfYNxqRffzPPNjLP1datCDevdQ8JNtPW/yFsN0fkEWcyHCH5hK0MtlKi0w== X-Received: by 2002:aca:f045:0:b0:3a7:56a1:9bbe with SMTP id o66-20020acaf045000000b003a756a19bbemr1326198oih.45.1692415054421; Fri, 18 Aug 2023 20:17:34 -0700 (PDT) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id bj38-20020a05680819a600b003a74933a1e2sm1496699oib.46.2023.08.18.20.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Aug 2023 20:17:33 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Thinh Nguyen Cc: JaeHun Jung , Marek Szyprowski , Sylwester Nawrocki , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Greg Kroah-Hartman , Alim Akhtar , Marc Kleine-Budde , Heiko Stuebner , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 2/8] dt-bindings: phy: samsung,usb3-drd-phy: Add Exynos850 support Date: Fri, 18 Aug 2023 22:17:25 -0500 Message-Id: <20230819031731.22618-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230819031731.22618-1-semen.protsenko@linaro.org> References: <20230819031731.22618-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Document Exynos850 compatible. USB 2.0 DRD PHY on Exynos850 has two clocks (ref and phy), which is already described in bindings. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index 5ba55f9f20cc..452e584d9812 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -29,6 +29,7 @@ properties: - samsung,exynos5420-usbdrd-phy - samsung,exynos5433-usbdrd-phy - samsung,exynos7-usbdrd-phy + - samsung,exynos850-usbdrd-phy clocks: minItems: 2 From patchwork Sat Aug 19 03:17:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 715125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDF29EE49B1 for ; Sat, 19 Aug 2023 03:18:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244685AbjHSDR5 (ORCPT ); Fri, 18 Aug 2023 23:17:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244730AbjHSDRh (ORCPT ); Fri, 18 Aug 2023 23:17:37 -0400 Received: from mail-ot1-x331.google.com (mail-ot1-x331.google.com [IPv6:2607:f8b0:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 200D54223 for ; Fri, 18 Aug 2023 20:17:36 -0700 (PDT) Received: by mail-ot1-x331.google.com with SMTP id 46e09a7af769-6bca6c06e56so1250422a34.1 for ; Fri, 18 Aug 2023 20:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692415055; x=1693019855; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pE2SxwAc9ssHdvgA5CR8AU2aj+QN0B7Vb8/YfT44UQo=; b=wsZmh2lRuqo61LoKoXTbKZ4QPkX36QOioP1vC2ZE6A2GkvQOkE9QKAmDc+wmhOFk+V HxA8VFlS4bx5n/XsDD65Y+S6aUjQQX/oHxdfA/lGf8MHKZ0NiExp20GUcm9ZqO6BR/2k TNiTqpf+U4NQdouPRCpwnbVUlEgxpxmsfakT9aN8MGnJDqF7maaammaf/vJEn8iAnqCk o8zb+qN3XM2+3XaCYY/ZNGh8pwN75gB18CXykNsVfrj8uBUuf2qlSy6VP3aCGdmbw27a qki58sjVqAmhdaNmOQQrjxdcwr+P+TKsP7vvtgnk7No3G8wSObYBffos5iJrQn3tNskm 2Wcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692415055; x=1693019855; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pE2SxwAc9ssHdvgA5CR8AU2aj+QN0B7Vb8/YfT44UQo=; b=MfqmfEsXbrCLeGliHExxJudxQMWNdQMgqOEBM4+WHxMPPCXqzacynHUUmlExWPcq8w xE0NnzWngA+an4nhyl+rpMxK/Tg+lZonKBl0CNxMfRW/zGj+g8Juoct4QTDYSlx5eKA7 hzfJw/rVxFQKjHZ5tuuvcd1acywLDdI/Q2js2cqpWXMLjy4hLd1DMhdUu2XPJ5qcc0Uh qQ4AxNhGREd2yAgfSpoZAFumXUvPzA+4iXClGK63w3UKZDlYdyhq+u4Q1XjFTzTh4J2K 0hQ8cRh6PMPIpccdXTKPHj8nKPnQkdaxfhxtr5gqnuAhUqLmnSOrQpCxeN1j54a5NaKz xKtw== X-Gm-Message-State: AOJu0YxvHC38R27tcJ/CCkQ+1SqhhMPXjB9OdmDf3b68cIaf2xDPXkMO yf3+36J+C2eOKO/jBvtfcMNJIA== X-Google-Smtp-Source: AGHT+IGwN20mZxiyx0bg2sXc9CDI9nvRQ0khtew3DAEDJbK4jTTSyqkBbLjLhbnjlq8G3ilSFSFg8g== X-Received: by 2002:a05:6870:e38e:b0:1c8:c27f:7d9b with SMTP id x14-20020a056870e38e00b001c8c27f7d9bmr1474715oad.27.1692415055429; Fri, 18 Aug 2023 20:17:35 -0700 (PDT) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id gq20-20020a056870d91400b001c5a3e31474sm1711347oab.45.2023.08.18.20.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Aug 2023 20:17:35 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Thinh Nguyen Cc: JaeHun Jung , Marek Szyprowski , Sylwester Nawrocki , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Greg Kroah-Hartman , Alim Akhtar , Marc Kleine-Budde , Heiko Stuebner , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 3/8] usb: dwc3: exynos: Add support for Exynos850 variant Date: Fri, 18 Aug 2023 22:17:26 -0500 Message-Id: <20230819031731.22618-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230819031731.22618-1-semen.protsenko@linaro.org> References: <20230819031731.22618-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add Exynos850 compatible string and associated driver data. Only two clocks are needed for this SoC: - bus_early: bus clock needed for registers access - ref: USB 2.0 DRD reference clock (50 MHz) Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- drivers/usb/dwc3/dwc3-exynos.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c index f882dd647340..5d365ca51771 100644 --- a/drivers/usb/dwc3/dwc3-exynos.c +++ b/drivers/usb/dwc3/dwc3-exynos.c @@ -163,6 +163,12 @@ static const struct dwc3_exynos_driverdata exynos7_drvdata = { .suspend_clk_idx = 1, }; +static const struct dwc3_exynos_driverdata exynos850_drvdata = { + .clk_names = { "bus_early", "ref" }, + .num_clks = 2, + .suspend_clk_idx = -1, +}; + static const struct of_device_id exynos_dwc3_match[] = { { .compatible = "samsung,exynos5250-dwusb3", @@ -173,6 +179,9 @@ static const struct of_device_id exynos_dwc3_match[] = { }, { .compatible = "samsung,exynos7-dwusb3", .data = &exynos7_drvdata, + }, { + .compatible = "samsung,exynos850-dwusb3", + .data = &exynos850_drvdata, }, { } }; From patchwork Sat Aug 19 03:17:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 715325 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35085EE49B4 for ; Sat, 19 Aug 2023 03:18:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244763AbjHSDSA (ORCPT ); Fri, 18 Aug 2023 23:18:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244775AbjHSDRj (ORCPT ); Fri, 18 Aug 2023 23:17:39 -0400 Received: from mail-oi1-x234.google.com (mail-oi1-x234.google.com [IPv6:2607:f8b0:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D166D421B for ; Fri, 18 Aug 2023 20:17:36 -0700 (PDT) Received: by mail-oi1-x234.google.com with SMTP id 5614622812f47-3a3efebcc24so1136212b6e.1 for ; Fri, 18 Aug 2023 20:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692415056; x=1693019856; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AMfSbR3cbUtK1t9P7HTJ1o0YtexgiyQjwWLXVl1eo+4=; b=R1oYs//GweGSuLHWZvieqmFIKZokIJNVu6kKiyyCR+v3XpEl+LwHyWvwQHu81u13i/ 3j/Ea0kzS/DbnyreA9JPGAXk3IN/ni2AaiC2Gbz+L156hgkS4zxg41Ehil/SIyz1WS/O maWlg3waegRxlGFrryWqUbDrUXyYF5862m6t0ZLn/TNzW7YN8FQ5CcYRjYh8v3DICpvp vyzwOvmCDPUEUD2zyiUqPWtAsGl/2LzFHdTe7JsB6jJow3E7ZYTz0VU7UldLeNsQOl8/ HDMpPfErCco4bRtreAxqdT77dEll6KCcbwsnwRiJt5dqh06ypbFHJEDKXQdq4m3nZlBg ykFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692415056; x=1693019856; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AMfSbR3cbUtK1t9P7HTJ1o0YtexgiyQjwWLXVl1eo+4=; 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Right now all chips are using exynos5_usbdrd_phy_ops, but it won't always be the case. For example, Exynos850 has very different USB PHY block, so there will be another PHY ops implementation for that chip. No functional change. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 06484abb5705..1ece4a1a1a6e 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -165,6 +165,7 @@ struct exynos5_usbdrd_phy_config { struct exynos5_usbdrd_phy_drvdata { const struct exynos5_usbdrd_phy_config *phy_cfg; + const struct phy_ops *phy_ops; u32 pmu_offset_usbdrd0_phy; u32 pmu_offset_usbdrd1_phy; bool has_common_clk_gate; @@ -779,6 +780,7 @@ static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = { static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = { .phy_cfg = phy_cfg_exynos5, + .phy_ops = &exynos5_usbdrd_phy_ops, .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, .pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL, .has_common_clk_gate = true, @@ -786,12 +788,14 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = { static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = { .phy_cfg = phy_cfg_exynos5, + .phy_ops = &exynos5_usbdrd_phy_ops, .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, .has_common_clk_gate = true, }; static const struct exynos5_usbdrd_phy_drvdata exynos5433_usbdrd_phy = { .phy_cfg = phy_cfg_exynos5, + .phy_ops = &exynos5_usbdrd_phy_ops, .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, .pmu_offset_usbdrd1_phy = EXYNOS5433_USBHOST30_PHY_CONTROL, .has_common_clk_gate = false, @@ -799,6 +803,7 @@ static const struct exynos5_usbdrd_phy_drvdata exynos5433_usbdrd_phy = { static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = { .phy_cfg = phy_cfg_exynos5, + .phy_ops = &exynos5_usbdrd_phy_ops, .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, .has_common_clk_gate = false, }; @@ -906,8 +911,8 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) dev_vdbg(dev, "Creating usbdrd_phy phy\n"); for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) { - struct phy *phy = devm_phy_create(dev, NULL, - &exynos5_usbdrd_phy_ops); + struct phy *phy = devm_phy_create(dev, NULL, drv_data->phy_ops); + if (IS_ERR(phy)) { dev_err(dev, "Failed to create usbdrd_phy phy\n"); return PTR_ERR(phy); From patchwork Sat Aug 19 03:17:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 715124 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53E83EE49B6 for ; Sat, 19 Aug 2023 03:18:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244948AbjHSDR7 (ORCPT ); Fri, 18 Aug 2023 23:17:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244783AbjHSDRj (ORCPT ); Fri, 18 Aug 2023 23:17:39 -0400 Received: from mail-oo1-xc2f.google.com (mail-oo1-xc2f.google.com [IPv6:2607:f8b0:4864:20::c2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CCCF0422A for ; Fri, 18 Aug 2023 20:17:37 -0700 (PDT) Received: by mail-oo1-xc2f.google.com with SMTP id 006d021491bc7-56cc461f34fso1007716eaf.0 for ; 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For some USB PHY controllers (e.g USB DRD PHY block on Exynos850) there is no need to set the refclk frequency at all (and corresponding bits in CLKRSTCTRL[7:5] are marked RESERVED), so that value won't be set in the driver. But even in that case, 26 MHz support still has to be added, otherwise exynos5_rate_to_clk() fails, which leads in turn to probe error. Add the correct value for 26MHz refclk to make it possible to add support for new Exynos USB DRD PHY controllers. Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 1ece4a1a1a6e..41508db87b9b 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -30,6 +30,7 @@ #define EXYNOS5_FSEL_19MHZ2 0x3 #define EXYNOS5_FSEL_20MHZ 0x4 #define EXYNOS5_FSEL_24MHZ 0x5 +#define EXYNOS5_FSEL_26MHZ 0x82 #define EXYNOS5_FSEL_50MHZ 0x7 /* Exynos5: USB 3.0 DRD PHY registers */ @@ -244,6 +245,9 @@ static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg) case 24 * MHZ: *reg = EXYNOS5_FSEL_24MHZ; break; + case 26 * MHZ: + *reg = EXYNOS5_FSEL_26MHZ; + break; case 50 * MHZ: *reg = EXYNOS5_FSEL_50MHZ; break; From patchwork Sat Aug 19 03:17:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 715126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC1D3EE49AF for ; Sat, 19 Aug 2023 03:18:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244925AbjHSDR6 (ORCPT ); Fri, 18 Aug 2023 23:17:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244808AbjHSDRk (ORCPT ); Fri, 18 Aug 2023 23:17:40 -0400 Received: from mail-oa1-x34.google.com (mail-oa1-x34.google.com [IPv6:2001:4860:4864:20::34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B51CF422B for ; Fri, 18 Aug 2023 20:17:38 -0700 (PDT) Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-1c4d8eaa8ebso980070fac.0 for ; Fri, 18 Aug 2023 20:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692415058; x=1693019858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+DQwNNrrtVCT1lLuabGTe5r6Le72ZgleU8XG8wqlJaU=; b=KZnsI2frS8f19EqyRQwavdJnykidAx+LH2FzPONwEGalZsPbjh8DDMo6++Bw8p/kWb JFunValfCFYRcWIsU4vandkZU7eWr0blqGFSQR8kJJi7LTusS8JkQQH8/N/MGy8P3FDC 1se/QTLNn7fXOEsrIQc6St1a92WXH54mgQnjTzjzwBmFXD5USVK6ghGkDUhod6hiCnK3 u++iM22rFYepHpqUMgSx44AevgdbcrhG7gxsyZErip+/NeNCbgCCvLokMOtCOGoRquy8 E3iixOKDXW4y1S/IEk7hI3a7LYelHPozIIGne2EU0nQJVQXGpXmEf3bhMubPVLm6r62I gbDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692415058; x=1693019858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+DQwNNrrtVCT1lLuabGTe5r6Le72ZgleU8XG8wqlJaU=; b=JyI1zF23xZBRKmGaMejQAcxAmbShAmvAgYDAb8sX+2nUNW97O46JJb/3+Q7DNzBvbi UCQpoqzB5ss5YrkmqlMsoHki5dGPBAmdGqY7JTRRQ3+ry6hKPi1Dm9pJouuloXSlCUvx IonCw8z2f6phfo6czVkQo85/5boZ3B3pM5euBBrrMV0NmroG33h4JN66Tkp5io2fGePn ZXTvalStDnRAohk7Tzy1GyOllg/px4EJ+zyLZkRYq4cOZZqjosJgoKnngbzVCZEkCYt2 8zOaj4Z+fEY4yh3iCOcALvTFRxFK1WApO7SgMaPX75I9TM8COxYsSkhdVjomx6j/WJjm vVHQ== X-Gm-Message-State: AOJu0YxmjTbRWd8CNCct75tbPIHCIhVkbBSDYyMLyTuzghN9hXfQVm/4 r5dEbML7zilkxJgJwXW97CI0YA== X-Google-Smtp-Source: AGHT+IG9+tvpUlnk8cAJd8EALh9FR9Ev77lqz1NyZ7whINiZTja6Zelg0JAusKenuNC7JUynVd3GDQ== X-Received: by 2002:a05:6870:2188:b0:19f:6711:8e0a with SMTP id l8-20020a056870218800b0019f67118e0amr1165180oae.32.1692415058070; Fri, 18 Aug 2023 20:17:38 -0700 (PDT) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id r2-20020a056870878200b001c4b473581fsm1725223oam.12.2023.08.18.20.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Aug 2023 20:17:37 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Thinh Nguyen Cc: JaeHun Jung , Marek Szyprowski , Sylwester Nawrocki , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Greg Kroah-Hartman , Alim Akhtar , Marc Kleine-Budde , Heiko Stuebner , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 6/8] phy: exynos5-usbdrd: Add Exynos850 support Date: Fri, 18 Aug 2023 22:17:29 -0500 Message-Id: <20230819031731.22618-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230819031731.22618-1-semen.protsenko@linaro.org> References: <20230819031731.22618-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Implement Exynos850 USB 2.0 DRD PHY controller support. Exynos850 has quite a different PHY controller than Exynos5 compatible controllers, but it's still possible to implement it on top of existing exynos5-usbdrd driver infrastructure. Only UTMI+ (USB 2.0) PHY interface is implemented, as Exynos850 doesn't support USB 3.0. Only two clocks are used for this controller: - phy: bus clock, used for PHY registers access - ref: PHY reference clock (OSCCLK) Signed-off-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 169 +++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index 41508db87b9b..3f310b28bfff 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -145,6 +145,34 @@ #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4) #define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4) +/* Exynos850: USB DRD PHY registers */ +#define EXYNOS850_DRD_LINKCTRL 0x04 +#define LINKCTRL_BUS_FILTER_BYPASS(_x) ((_x) << 4) +#define LINKCTRL_FORCE_QACT BIT(8) + +#define EXYNOS850_DRD_CLKRST 0x20 +#define CLKRST_LINK_SW_RST BIT(0) +#define CLKRST_PORT_RST BIT(1) +#define CLKRST_PHY_SW_RST BIT(3) + +#define EXYNOS850_DRD_UTMI 0x50 +#define UTMI_FORCE_SLEEP BIT(0) +#define UTMI_FORCE_SUSPEND BIT(1) +#define UTMI_DM_PULLDOWN BIT(2) +#define UTMI_DP_PULLDOWN BIT(3) +#define UTMI_FORCE_BVALID BIT(4) +#define UTMI_FORCE_VBUSVALID BIT(5) + +#define EXYNOS850_DRD_HSP 0x54 +#define HSP_COMMONONN BIT(8) +#define HSP_EN_UTMISUSPEND BIT(9) +#define HSP_VBUSVLDEXT BIT(12) +#define HSP_VBUSVLDEXTSEL BIT(13) +#define HSP_FSV_OUT_EN BIT(24) + +#define EXYNOS850_DRD_HSP_TEST 0x5c +#define HSP_TEST_SIDDQ BIT(24) + #define KHZ 1000 #define MHZ (KHZ * KHZ) @@ -716,6 +744,129 @@ static const struct phy_ops exynos5_usbdrd_phy_ops = { .owner = THIS_MODULE, }; +static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *regs_base = phy_drd->reg_phy; + u32 reg; + + /* + * Disable HWACG (hardware auto clock gating control). This will force + * QACTIVE signal in Q-Channel interface to HIGH level, to make sure + * the PHY clock is not gated by the hardware. + */ + reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); + reg |= LINKCTRL_FORCE_QACT; + writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); + + /* Start PHY Reset (POR=high) */ + reg = readl(regs_base + EXYNOS850_DRD_CLKRST); + reg |= CLKRST_PHY_SW_RST; + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); + + /* Enable UTMI+ */ + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg &= ~(UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP | UTMI_DP_PULLDOWN | + UTMI_DM_PULLDOWN); + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + /* Set PHY clock and control HS PHY */ + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg |= HSP_EN_UTMISUSPEND | HSP_COMMONONN; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + + /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ + reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); + reg |= LINKCTRL_BUS_FILTER_BYPASS(0xf); + writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); + + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID; + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; + writel(reg, regs_base + EXYNOS850_DRD_HSP); + + /* Power up PHY analog blocks */ + reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); + reg &= ~HSP_TEST_SIDDQ; + writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); + + /* Finish PHY reset (POR=low) */ + udelay(10); /* required before doing POR=low */ + reg = readl(regs_base + EXYNOS850_DRD_CLKRST); + reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST); + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); + udelay(75); /* required after POR=low for guaranteed PHY clock */ + + /* Disable single ended signal out */ + reg = readl(regs_base + EXYNOS850_DRD_HSP); + reg &= ~HSP_FSV_OUT_EN; + writel(reg, regs_base + EXYNOS850_DRD_HSP); +} + +static int exynos850_usbdrd_phy_init(struct phy *phy) +{ + struct phy_usb_instance *inst = phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + int ret; + + ret = clk_prepare_enable(phy_drd->clk); + if (ret) + return ret; + + /* UTMI or PIPE3 specific init */ + inst->phy_cfg->phy_init(phy_drd); + + clk_disable_unprepare(phy_drd->clk); + + return 0; +} + +static int exynos850_usbdrd_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst = phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); + void __iomem *regs_base = phy_drd->reg_phy; + u32 reg; + int ret; + + ret = clk_prepare_enable(phy_drd->clk); + if (ret) + return ret; + + /* Set PHY clock and control HS PHY */ + reg = readl(regs_base + EXYNOS850_DRD_UTMI); + reg &= ~(UTMI_DP_PULLDOWN | UTMI_DM_PULLDOWN); + reg |= UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP; + writel(reg, regs_base + EXYNOS850_DRD_UTMI); + + /* Power down PHY analog blocks */ + reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); + reg |= HSP_TEST_SIDDQ; + writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); + + /* Link reset */ + reg = readl(regs_base + EXYNOS850_DRD_CLKRST); + reg |= CLKRST_LINK_SW_RST; + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); + udelay(10); /* required before doing POR=low */ + reg &= ~CLKRST_LINK_SW_RST; + writel(reg, regs_base + EXYNOS850_DRD_CLKRST); + + clk_disable_unprepare(phy_drd->clk); + + return 0; +} + +static const struct phy_ops exynos850_usbdrd_phy_ops = { + .init = exynos850_usbdrd_phy_init, + .exit = exynos850_usbdrd_phy_exit, + .power_on = exynos5_usbdrd_phy_power_on, + .power_off = exynos5_usbdrd_phy_power_off, + .owner = THIS_MODULE, +}; + static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd) { unsigned long ref_rate; @@ -782,6 +933,14 @@ static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = { }, }; +static const struct exynos5_usbdrd_phy_config phy_cfg_exynos850[] = { + { + .id = EXYNOS5_DRDPHY_UTMI, + .phy_isol = exynos5_usbdrd_phy_isol, + .phy_init = exynos850_usbdrd_utmi_init, + }, +}; + static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = { .phy_cfg = phy_cfg_exynos5, .phy_ops = &exynos5_usbdrd_phy_ops, @@ -812,6 +971,13 @@ static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = { .has_common_clk_gate = false, }; +static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = { + .phy_cfg = phy_cfg_exynos850, + .phy_ops = &exynos850_usbdrd_phy_ops, + .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, + .has_common_clk_gate = true, +}; + static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { { .compatible = "samsung,exynos5250-usbdrd-phy", @@ -825,6 +991,9 @@ static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { }, { .compatible = "samsung,exynos7-usbdrd-phy", .data = &exynos7_usbdrd_phy + }, { + .compatible = "samsung,exynos850-usbdrd-phy", + .data = &exynos850_usbdrd_phy }, { }, }; From patchwork Sat Aug 19 03:17:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 715123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21C7DEE49BE for ; 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Fri, 18 Aug 2023 20:17:38 -0700 (PDT) Received: from localhost ([136.49.140.41]) by smtp.gmail.com with ESMTPSA id bg8-20020a056871940800b001c530b51082sm1706780oac.46.2023.08.18.20.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 18 Aug 2023 20:17:38 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Thinh Nguyen Cc: JaeHun Jung , Marek Szyprowski , Sylwester Nawrocki , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Greg Kroah-Hartman , Alim Akhtar , Marc Kleine-Budde , Heiko Stuebner , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 7/8] arm64: dts: exynos: Enable USB in Exynos850 Date: Fri, 18 Aug 2023 22:17:30 -0500 Message-Id: <20230819031731.22618-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230819031731.22618-1-semen.protsenko@linaro.org> References: <20230819031731.22618-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Add USB controller and USB PHY controller nodes for Exynos850 SoC. The USB controller has next features: - Dual Role Device (DRD) controller - DWC3 compatible - Supports USB 2.0 host and USB 2.0 device interfaces - Supports full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device 2.0 interface - Supports on-chip USB PHY transceiver - Supports up to 16 bi-directional endpoints (that includes control endpoint 0) - Complies with xHCI 1.00 specification Only USB 2.0 is supported in Exynos850, so only UTMI+ PHY interface is specified in "phys" property (index 0) and PIPE3 is omitted (index 1). Signed-off-by: Sam Protsenko --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 30 +++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index aa077008b3be..198d1dfcc672 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -570,6 +570,36 @@ sysreg_cmgp: syscon@11c20000 { clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; }; + usbdrd: usb@13600000 { + compatible = "samsung,exynos850-dwusb3"; + clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>, + <&cmu_hsi CLK_GOUT_USB_REF_CLK>; + clock-names = "bus_early", "ref"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x13600000 0x10000>; + status = "disabled"; + + usbdrd_dwc3: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + phys = <&usbdrd_phy 0>; + phy-names = "usb2-phy"; + }; + }; + + usbdrd_phy: phy@135d0000 { + compatible = "samsung,exynos850-usbdrd-phy"; + reg = <0x135d0000 0x100>; + clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>, + <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + status = "disabled"; + }; + usi_uart: usi@138200c0 { compatible = "samsung,exynos850-usi"; reg = <0x138200c0 0x20>; From patchwork Sat Aug 19 03:17:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 715324 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 815D2EE49BB for ; Sat, 19 Aug 2023 03:18:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244670AbjHSDSB (ORCPT ); Fri, 18 Aug 2023 23:18:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244858AbjHSDRm (ORCPT ); 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Fri, 18 Aug 2023 20:17:39 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Rob Herring , Thinh Nguyen Cc: JaeHun Jung , Marek Szyprowski , Sylwester Nawrocki , Conor Dooley , Vinod Koul , Kishon Vijay Abraham I , Greg Kroah-Hartman , Alim Akhtar , Marc Kleine-Budde , Heiko Stuebner , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH 8/8] arm64: dts: exynos: Enable USB support on E850-96 board Date: Fri, 18 Aug 2023 22:17:31 -0500 Message-Id: <20230819031731.22618-9-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230819031731.22618-1-semen.protsenko@linaro.org> References: <20230819031731.22618-1-semen.protsenko@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The E850-96 board has a micro-USB socket and two USB 2.0 host sockets. The USB role (host or peripheral) is selected automatically depending on micro-USB cable attachment state: - micro-USB cable is attached: USB device role - micro-USB cable is detached: USB host role USB can't act simultaneously as a device and a host, because Exynos850 SoC has only one USB controller and there are no external USB controllers on the E850-96 board. So the USB switch chip (specifically TS3USB221A) connects SoC USB lines either to micro-USB connector or to USB hub chip (LAN9514), w.r.t. micro-USB cable attachment state. When USB works in the host role, Ethernet capability becomes available too, as LAN9514 chip (providing USB hub) also enables Ethernet PHY and Ethernet MAC. Dynamic role switching is done in gpio-usb-b-connector, using current micro-USB VBUS line level as a trigger: - VBUS=high: SoC USB lines are wired to micro-USB socket - VBUS=low: SoC USB lines are wired to USB hub chip In order to make USB host functional when the board is booted with micro-USB cable disconnected, role-switch-default-mode = "host" is used. One can look at E850-96 board schematics [1] to figure out how exactly all related USB hardware connections and lines reflect into corresponding device tree definitions. As PMIC regulators are not implemented yet, we rely on USB LDOs being already enabled in the bootloader, and a dummy regulator is provided to "usbdrd" vdd nodes for now. [1] https://www.96boards.org/documentation/consumer/e850-96b/hardware-docs/ Signed-off-by: Sam Protsenko --- .../boot/dts/exynos/exynos850-e850-96.dts | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts index 6ed38912507f..8d733361ef82 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -29,6 +29,22 @@ chosen { stdout-path = &serial_0; }; + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-supply = <®_usb_host_vbus>; + id-gpios = <&gpa0 0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <µ_usb_det_pins>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + /* * RAM: 4 GiB (eMCP): * - 2 GiB at 0x80000000 @@ -111,6 +127,20 @@ bt_active_led: led-5 { }; }; + /* TODO: Remove this once PMIC is implemented */ + reg_dummy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "dummy_reg"; + }; + + reg_usb_host_vbus: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpa3 5 GPIO_ACTIVE_LOW>; + }; + /* * RTC clock (XrtcXTI); external, must be 32.768 kHz. * @@ -172,6 +202,12 @@ key_volup_pins: key-volup-pins { samsung,pin-pud = ; samsung,pin-drv = ; }; + + micro_usb_det_pins: micro-usb-det-pins { + samsung,pins = "gpa0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; }; &rtc { @@ -186,6 +222,28 @@ &serial_0 { pinctrl-0 = <&uart1_pins>; }; +&usbdrd { + status = "okay"; + vdd10-supply = <®_dummy>; + vdd33-supply = <®_dummy>; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usbdrd_phy { + status = "okay"; +}; + &usi_uart { samsung,clkreq-on; /* needed for UART mode */ status = "okay";