From patchwork Sat Aug 19 09:26:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikhail Kalashnikov X-Patchwork-Id: 715066 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CBABEE49AC for ; Sat, 19 Aug 2023 10:40:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229820AbjHSKkB (ORCPT ); Sat, 19 Aug 2023 06:40:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229647AbjHSKj6 (ORCPT ); Sat, 19 Aug 2023 06:39:58 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F59526AC1; Sat, 19 Aug 2023 02:26:19 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4fe85fd3d27so2681339e87.0; Sat, 19 Aug 2023 02:26:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1692437177; x=1693041977; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=Bh6dsaKKUVquVJpXCTO55ymTARfAFnjTpQ1R182Ciek=; b=DVW070gsBQVvM/43f3sBXVXb0+mUoFItwxVuR3/kD6CBub7Jg7RPpy+pUH2Y1XIRfl w9mQ/6yLFFcwirMwbyJYw/3rjLg1lQ8P4GVZMiqI1xuMtMkAcMEfBWiwD6RyhpJynln3 9oey0zlWF/NzuyiRcVNzdrn586ug4mxE5n4oCSHzSgNiOYefS3kWLopykpBFieuXXeBp l2Ko7hsXGKcW/KXXMXfi655tXhUxNWmx06AV4tvadqOkj2C1gS9gg2Bm32/2xWdR7IpG 8clVJZuNHTAFV5/25IldR930YhREfGjYSbC83TtpYrZZnqjqPRhqkqe79E8s4YFXasQf zzhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692437177; x=1693041977; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Bh6dsaKKUVquVJpXCTO55ymTARfAFnjTpQ1R182Ciek=; b=WK3qX9k+wFXTSuBVQM4w1OaudTuR05SfHi5coQLuo+lyiVUuPKtJAUe9FivLHakGXt o4dJLVJMnlBl1bKb6fiISpqmg+txAFsdIL0jj8FYukRoc8Rpgkg7Pgvj5IYd6hl+euxI c5r1RoYuFY2TMruy/KM/iNt9rKgPCI5D6TxNdnrYdgUBQYdWzyQFd7yk/U1ki9I+X7Lu H580DDu1ipHOE6NPRbAcY2JiL2op1/8I2M6zOLFS9u97m3oUGvolNo/ECiTATnTi++nk 3H1OiS65RFbRJrCh1G7xOH7xwB8gGo5SBBTcfDBw82GMxCgXRXYgS42aNoS5Wv1CcMBh WILw== X-Gm-Message-State: AOJu0Yzf5vGABj3Dft2TEAtS9iKnhjOl9J1xkPowAO3Yc+ljfwuA6a9+ HPJT/+EXBHx6mIGGDitnuHk= X-Google-Smtp-Source: AGHT+IG5A3rc94WY5hljI+57/ebTM1KRz1yVEyZDePdgiO9REwo+y6kgfmWO2anFVztfE19P9psqJA== X-Received: by 2002:ac2:42c6:0:b0:4ff:8fbc:a5dd with SMTP id n6-20020ac242c6000000b004ff8fbca5ddmr945355lfl.41.1692437177142; Sat, 19 Aug 2023 02:26:17 -0700 (PDT) Received: from SerialExperiment.lan ([46.251.204.228]) by smtp.gmail.com with ESMTPSA id l14-20020ac24a8e000000b004ff8f090057sm732269lfp.59.2023.08.19.02.26.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 19 Aug 2023 02:26:16 -0700 (PDT) From: Mikhail Kalashnikov To: Linus Walleij , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH] pinctrl: sunxi: h616: add extra gpio banks Date: Sat, 19 Aug 2023 12:26:09 +0300 Message-ID: <20230819092609.8136-1-iuncuim@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: iuncuim Some SoCs from the H616 family (for example, T507) have the same die, but more output pins that are used for additional peripherals. The T507 SoC don't have a built-in multiphy such as the AC200 or AC300. With the T507 these pins can be freely used for any other application. So, patch add these missing muxes on banks A, C and D. Signed-off-by: Mikhail Kalashnikov --- drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c | 382 +++++++++++++++++++- 1 file changed, 367 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c index d6ca720ee..a88fed0aa 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c @@ -16,33 +16,81 @@ #include "pinctrl-sunxi.h" static const struct sunxi_desc_pin h616_pins[] = { - /* Internal connection to the AC200 part */ + /* Internally connected to the AC200 part in the H616 SoC */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), - SUNXI_FUNCTION(0x2, "emac1")), /* ERXD1 */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ERXD1 */ + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), - SUNXI_FUNCTION(0x2, "emac1")), /* ERXD0 */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ERXD0 */ + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), - SUNXI_FUNCTION(0x2, "emac1")), /* ECRS_DV */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ECRS_DV */ + SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), - SUNXI_FUNCTION(0x2, "emac1")), /* ERXERR */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ERXERR */ + SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), - SUNXI_FUNCTION(0x2, "emac1")), /* ETXD1 */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ETXD1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), - SUNXI_FUNCTION(0x2, "emac1")), /* ETXD0 */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ETXD0 */ + SUNXI_FUNCTION(0x3, "h_i2s0"), /* DOUT0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), - SUNXI_FUNCTION(0x2, "emac1")), /* ETXCK */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ETXCK */ + SUNXI_FUNCTION(0x3, "h_i2s0"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), - SUNXI_FUNCTION(0x2, "emac1")), /* ETXEN */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* ETXEN */ + SUNXI_FUNCTION(0x3, "h_i2s0"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), - SUNXI_FUNCTION(0x2, "emac1")), /* EMDC */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* EMDC */ + SUNXI_FUNCTION(0x3, "h_i2s0"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), - SUNXI_FUNCTION(0x2, "emac1")), /* EMDIO */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "emac1"), /* EMDIO */ + SUNXI_FUNCTION(0x3, "h_i2s0"), /* DIN0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), - SUNXI_FUNCTION(0x2, "i2c3")), /* SCK */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), - SUNXI_FUNCTION(0x2, "i2c3")), /* SDA */ + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), - SUNXI_FUNCTION(0x2, "pwm5")), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm5"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -149,6 +197,310 @@ static const struct sunxi_desc_pin h616_pins[] = { SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PC_EINT16 */ /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */ + SUNXI_FUNCTION(0x4, "ts0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PD_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */ + SUNXI_FUNCTION(0x4, "ts0"), /* ERR */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PD_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */ + SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PD_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */ + SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PD_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PD_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PD_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */ + SUNXI_FUNCTION(0x4, "ts0"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PD_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */ + SUNXI_FUNCTION(0x4, "ts0"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PD_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PD_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D5 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PD_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VP0 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D6 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PD_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VN0 */ + SUNXI_FUNCTION(0x4, "ts0"), /* D7 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PD_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VP1 */ + SUNXI_FUNCTION(0x4, "sim"), /* VPPEN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PD_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VN1 */ + SUNXI_FUNCTION(0x4, "sim"), /* VPPPP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PD_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VP2 */ + SUNXI_FUNCTION(0x4, "sim"), /* PWREN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PD_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VN2 */ + SUNXI_FUNCTION(0x4, "sim"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PD_EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VPC */ + SUNXI_FUNCTION(0x4, "sim"), /* DATA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PD_EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VNC */ + SUNXI_FUNCTION(0x4, "sim"), /* RST */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PD_EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VP3 */ + SUNXI_FUNCTION(0x4, "sim"), /* DET */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), /* PD_EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds1"), /* VN3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), /* PD_EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)), /* PD_EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)), /* PD_EINT21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)), /* PD_EINT22 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)), /* PD_EINT23 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 24)), /* PD_EINT24 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 25)), /* PD_EINT25 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 26)), /* PD_EINT26 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 27)), /* PD_EINT27 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 28)), /* PD_EINT28 */ + /* Hole */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PE_EINT0 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi_mclk1"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PE_EINT1 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PE_EINT2 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PE_EINT3 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PE_EINT4 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PE_EINT5 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PE_EINT6 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PE_EINT7 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PE_EINT8 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PE_EINT9 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PE_EINT10 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PE_EINT11 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D8 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PE_EINT12 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D9 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PE_EINT13 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D10 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PE_EINT14 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D11 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PE_EINT15 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D12 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PE_EINT16 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D13 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PE_EINT17 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D14 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PE_EINT18 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* D15 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 19)), /* PE_EINT19 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ + SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 20)), /* PE_EINT20 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ + SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 21)), /* PE_EINT21 */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "ncsi_fsin0"), /* FSIN0 */ + SUNXI_FUNCTION(0x4, "tcon0"), /* TRIG0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 22)), /* PE_EINT22 */ + /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), @@ -545,4 +897,4 @@ static struct platform_driver h616_pinctrl_driver = { .of_match_table = h616_pinctrl_match, }, }; -builtin_platform_driver(h616_pinctrl_driver); +builtin_platform_driver(h616_pinctrl_driver); \ No newline at end of file