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Wed, 16 Aug 2023 08:44:48 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 16 Aug 2023 08:44:47 -0700 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Wed, 16 Aug 2023 08:44:46 -0700 From: Asmaa Mnebhi To: , , , , , CC: Asmaa Mnebhi Subject: [PATCH v2 1/2] pinctrl: mlxbf3: Remove gpio_disable_free() Date: Wed, 16 Aug 2023 11:44:41 -0400 Message-ID: <20230816154442.8417-2-asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20230816154442.8417-1-asmaa@nvidia.com> References: <20230816154442.8417-1-asmaa@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F5:EE_|SJ2PR12MB7941:EE_ X-MS-Office365-Filtering-Correlation-Id: a81ba836-c75e-44d3-273b-08db9e6fbf9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2023 15:44:59.5491 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a81ba836-c75e-44d3-273b-08db9e6fbf9e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7941 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Remove support for gpio_disable_free() because it is called when the libgpiod command "gpioset" is invoked. This gives the GPIO control back to hardware which cancels out the effort to set the GPIO value. Reminder of the code flow to change a GPIO value from software: 1) All GPIOs are controlled by hardware by default 2) To change the GPIO value, enable software control via a mux. 3) Once software has control over the GPIO pin, the gpio-mlxbf3 driver will be able to change the direction and value of the GPIO. When the user runs "gpioset gpiochip0 0=0" for example, the gpio pin value should change from 1 to 0. In this case, mlxbf3_gpio_request_enable() is called via gpiochip_generic_request(). The latter switches GPIO control from hardware to software. Then the GPIO value is changed from 1 to 0. However, gpio_disable_free() is also called which changes control back to hardware which changes the GPIO value back to 1. Fixes: d11f932808d ("pinctrl: mlxbf3: Add pinctrl driver support") Signed-off-by: Asmaa Mnebhi --- v1->v2: - Clean up mlxbf3_gpio_add_pin_ranges drivers/pinctrl/pinctrl-mlxbf3.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mlxbf3.c b/drivers/pinctrl/pinctrl-mlxbf3.c index d9944e6a0af9..0e852a0d5ec2 100644 --- a/drivers/pinctrl/pinctrl-mlxbf3.c +++ b/drivers/pinctrl/pinctrl-mlxbf3.c @@ -223,26 +223,12 @@ static int mlxbf3_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } -static void mlxbf3_gpio_disable_free(struct pinctrl_dev *pctldev, - struct pinctrl_gpio_range *range, - unsigned int offset) -{ - struct mlxbf3_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); - - /* disable GPIO functionality by giving control back to hardware */ - if (offset < MLXBF3_NGPIOS_GPIO0) - writel(BIT(offset), priv->fw_ctrl_clr0); - else - writel(BIT(offset % MLXBF3_NGPIOS_GPIO0), priv->fw_ctrl_clr1); -} - static const struct pinmux_ops mlxbf3_pmx_ops = { .get_functions_count = mlxbf3_pmx_get_funcs_count, .get_function_name = mlxbf3_pmx_get_func_name, .get_function_groups = mlxbf3_pmx_get_groups, .set_mux = mlxbf3_pmx_set, .gpio_request_enable = mlxbf3_gpio_request_enable, - .gpio_disable_free = mlxbf3_gpio_disable_free, }; static struct pinctrl_desc mlxbf3_pin_desc = { From patchwork Wed Aug 16 15:44:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Asmaa Mnebhi X-Patchwork-Id: 714182 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41631C001E0 for ; Wed, 16 Aug 2023 15:45:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344331AbjHPPpY (ORCPT ); Wed, 16 Aug 2023 11:45:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344307AbjHPPpG (ORCPT ); Wed, 16 Aug 2023 11:45:06 -0400 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2068.outbound.protection.outlook.com [40.107.223.68]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 409FA26A6; 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Wed, 16 Aug 2023 08:44:50 -0700 Received: from rnnvmail205.nvidia.com (10.129.68.10) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Wed, 16 Aug 2023 08:44:50 -0700 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.10) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Wed, 16 Aug 2023 08:44:49 -0700 From: Asmaa Mnebhi To: , , , , , CC: Asmaa Mnebhi Subject: [PATCH v2 2/2] gpio: mlxbf3: Support add_pin_ranges() Date: Wed, 16 Aug 2023 11:44:42 -0400 Message-ID: <20230816154442.8417-3-asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20230816154442.8417-1-asmaa@nvidia.com> References: <20230816154442.8417-1-asmaa@nvidia.com> MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3B:EE_|MN2PR12MB4373:EE_ X-MS-Office365-Filtering-Correlation-Id: a28b9db6-fd7c-44b7-4904-08db9e6fc0b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2023 15:45:01.3602 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a28b9db6-fd7c-44b7-4904-08db9e6fc0b7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4373 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Support add_pin_ranges() so that pinctrl_gpio_request() can be called. The GPIO value is not modified when the user runs the "gpioset" tool. This is because when gpiochip_generic_request is invoked by the gpio-mlxbf3 driver, "pin_ranges" is empty so it skips "pinctrl_gpio_request()". pinctrl_gpio_request() is essential in the code flow because it changes the mux value so that software has control over modifying the GPIO value. Adding add_pin_ranges() creates a dependency on the pinctrl-mlxbf3.c driver. Fixes: cd33f216d24 ("gpio: mlxbf3: Add gpio driver support") Signed-off-by: Asmaa Mnebhi --- v1->v2: - No changes. drivers/gpio/gpio-mlxbf3.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpio/gpio-mlxbf3.c b/drivers/gpio/gpio-mlxbf3.c index e30cee108986..d00cc61ea7b8 100644 --- a/drivers/gpio/gpio-mlxbf3.c +++ b/drivers/gpio/gpio-mlxbf3.c @@ -158,6 +158,19 @@ static const struct irq_chip gpio_mlxbf3_irqchip = { GPIOCHIP_IRQ_RESOURCE_HELPERS, }; +static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip) +{ + unsigned int id = 0; + int ret; + + if (chip->ngpio % MLXBF3_GPIO_MAX_PINS_PER_BLOCK) + id = 1; + + return gpiochip_add_pin_range(chip, "MLNXBF34:00", + chip->base, id * MLXBF3_GPIO_MAX_PINS_PER_BLOCK, + chip->ngpio); +} + static int mlxbf3_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -197,6 +210,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pdev) gc->request = gpiochip_generic_request; gc->free = gpiochip_generic_free; gc->owner = THIS_MODULE; + gc->add_pin_ranges = mlxbf3_gpio_add_pin_ranges; irq = platform_get_irq(pdev, 0); if (irq >= 0) { @@ -243,6 +257,7 @@ static struct platform_driver mlxbf3_gpio_driver = { }; module_platform_driver(mlxbf3_gpio_driver); +MODULE_SOFTDEP("pre: pinctrl-mlxbf3"); MODULE_DESCRIPTION("NVIDIA BlueField-3 GPIO Driver"); MODULE_AUTHOR("Asmaa Mnebhi "); MODULE_LICENSE("Dual BSD/GPL");