From patchwork Thu Aug 10 02:35:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 712343 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:baf:b0:129:c516:61db with SMTP id gf47csp354905rwb; Wed, 9 Aug 2023 19:36:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHCeHknxrQCTL6nQtezRZqw4wrhxWH+LMpasVsk5Iic61i6p0p5QEdR6toP8PQkkvcigrWJ X-Received: by 2002:a05:6214:163:b0:626:290f:3e80 with SMTP id y3-20020a056214016300b00626290f3e80mr992329qvs.50.1691635015406; Wed, 09 Aug 2023 19:36:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691635015; cv=none; d=google.com; s=arc-20160816; b=r+Ak1v1644vdnC/Msc1Pt0G0cXr4W2I91oPE0qTV27Yzs8vHBdbu28+WV38E7xenyk fBG648xQbSqfONcOy/HHIGg/Gf2KVsTtb22YTzE1cWFp7C1VsCqxO1XT7EkwxlZUkj8w hqKzUaI4+B7bIun+epuSFjHTq/dz1XxFHrpT2/QIbhiVk5c+Cjdml70a53ZUYTZda3RS Eq0WUNBItgo+sHGjko/gZcBg9+cLjqW/YkHsbC9nMqwVI0hbibtqT78KUEDNwBlasZ9V OpzhulTGgyEyG6nAxzZxVAY7RN5v3w0m8Yv8PHn+UOA43dPEUcJAgaxkfHhbKvpstQoJ B72w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=phrIw6b5pWNBBmVHR2P9mXRKZKLN/f9yT3V1nvx09pc=; fh=j4Z1An09Ve/stdydd/yoEYU5jCtTlZP/o+LZJGsiADc=; b=kJFjgTsYkkFSP/NzpWRtcs3m1rbrTIFYJhQvk2VXaqcl6AcG03z/mL7Byq/YRcfDwy EGHQnlmLKCwxm9km/JrOKUH6BhpAnNw425aenggL00GfwOsV3fhy6nAQbLLdgRWDi2Vn 7F7kpfuFgyh/1UynIV7W5JXcTru0gDdLmbMzQc3xS4Wv/WqV2HceZXm/+QVp1dQ324xh 75YQFJMWcWuWrlyKPf09EOlvzgj+ZkNwDtmcPHI2Wet/Nun91P0/1M/LSynZUwetDevj /666kRXKk3Q/AoAH7W+6cxEPP3RaC+GyH52lbQLFXhmTOtjnIDwEX5xLF+sGBFOMQKRW 92DA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hetcGLST; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a10-20020a0ce34a000000b0063d52f6e529si247736qvm.56.2023.08.09.19.36.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Aug 2023 19:36:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hetcGLST; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTvWp-0000zW-L6; Wed, 09 Aug 2023 22:35:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTvWj-0000uY-RH for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:53 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTvWi-0004x8-7U for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:53 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-686f38692b3so370698b3a.2 for ; Wed, 09 Aug 2023 19:35:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691634951; x=1692239751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=phrIw6b5pWNBBmVHR2P9mXRKZKLN/f9yT3V1nvx09pc=; b=hetcGLSTvMBODJofQGfMVBISegsvqZdiKKEbSfvqqqx+d99tfCCDuaJWnrsG3hV+gX HeX00d8gGHe9ieeT8E3SnzLZiy0K+JL/Vf3EN5EDq1i9CFp1PrEhJ4mVePQ9vO1g7tbZ herQk+zbXxrFUzSytvWYr3gFniGDMuDmXW9GFngAh3r5ExlIX7IiyEzofpDk4+ypzfkG KX43SBIB+cpGu/HC3yzMxaRaVi3mlnug36VLLig+Q2A0/ZwpQ4O0Q3l5uU5e7AY6RIBV PimncngeezMtCofNYYrpyqc49LtO1xjVFWkcLo7R5y/t1KpFpCsRx8Pmrkj6MbxU2VzH H8Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691634951; x=1692239751; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=phrIw6b5pWNBBmVHR2P9mXRKZKLN/f9yT3V1nvx09pc=; b=AX2PWhf1ZTgUn9kSAckmH1NH+NXZnNCvlHfSG1XupyLA+n8YSU3xWhi7wcd1/93wAN 5IP9RHb8K0K9q90ZPn5rFQs+7dzyBw11QbKQvu212g+jOD3tuVGWbwbgLSb/Lwosbpk8 4DCM1aezieTV0fYFoYztANWibmoCnsiSD5E8yJNJ1SXCTJHZIaOqwk5vsgJgfFTAKxrV P2oCbtGeeYLtlFTVRmUASGvffTMIcwW3COFtfoh54MrbImw4pEhp6WUf+LXsohTcteM1 yVPNGJR84uXi8FoIp/FkJp0kCWhHxgmkUmxDha3EMaGkO9P/3qmJryzPAoP6FKFo9GSX eeCw== X-Gm-Message-State: AOJu0YymsuusrddBxeddiEUJ0uAztZcyPAwt1Tf+kTAdZUpPOXotY6FX ncoqnP+ZnHvlmVFuEtnH+KlqB0FFTMIP4kFz0ho= X-Received: by 2002:a05:6a00:23d1:b0:687:520e:4b17 with SMTP id g17-20020a056a0023d100b00687520e4b17mr1382835pfc.8.1691634950943; Wed, 09 Aug 2023 19:35:50 -0700 (PDT) Received: from stoup.. ([2602:47:d483:7301:6bf0:9674:6ac4:f74c]) by smtp.gmail.com with ESMTPSA id z7-20020aa791c7000000b0066ebaeb149dsm287283pfa.88.2023.08.09.19.35.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 19:35:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-stable@nongnu.org Subject: [PATCH 1/5] target/arm: Disable FEAT_TRF in neoverse-v1 Date: Wed, 9 Aug 2023 19:35:44 -0700 Message-Id: <20230810023548.412310-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810023548.412310-1-richard.henderson@linaro.org> References: <20230810023548.412310-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Self-hosted trace is out of scope for QEMU. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson --- target/arm/tcg/cpu64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 8019f00bc3..60e5f034d9 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -618,7 +618,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->dcz_blocksize = 4; cpu->id_aa64afr0 = 0x00000000; cpu->id_aa64afr1 = 0x00000000; - cpu->isar.id_aa64dfr0 = 0x000001f210305519ull; + cpu->isar.id_aa64dfr0 = 0x000000f210305519ull; /* w/o FEAT_TRF */ cpu->isar.id_aa64dfr1 = 0x00000000; cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */ cpu->isar.id_aa64isar1 = 0x0111000001211032ull; @@ -628,7 +628,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj) cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; cpu->id_afr0 = 0x00000000; - cpu->isar.id_dfr0 = 0x15011099; + cpu->isar.id_dfr0 = 0x05011099; /* w/o FEAT_TRF */ cpu->isar.id_isar0 = 0x02101110; cpu->isar.id_isar1 = 0x13112111; cpu->isar.id_isar2 = 0x21232042; From patchwork Thu Aug 10 02:35:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 712345 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:baf:b0:129:c516:61db with SMTP id gf47csp355162rwb; Wed, 9 Aug 2023 19:37:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG0mVcGUo6NnXn3pRyoorG3cbKHtvrjivu6laK0HXD3xeglOf78uYPw7eE6y0lv2TO3yqpx X-Received: by 2002:a0c:ab47:0:b0:63d:3d9:6391 with SMTP id i7-20020a0cab47000000b0063d03d96391mr852830qvb.12.1691635049085; Wed, 09 Aug 2023 19:37:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691635049; cv=none; d=google.com; s=arc-20160816; b=mqErNsPLjOdSSKHQ5Zlb/ubANQgtj8qXUTRYZiPMj4C++RVLxl9l21n9WPL/0sVsV2 +5Ry454trq2QIQK6XqMHGBkjB213PvHEWyWKgQ5OkLSq+WcExiJvaefoKdbCaiBKYxN6 HJC8NY/tuezv0G8xPGfJi7fk0RG/w2512n4JiM4gL3FDyW3T++szHOHVTz9/FhTCODXf J5hKdkeDtfihW2iT+hpX01VwMDh7QyVbuhm4WvFfYd0pyNuyY7cdMogMYQa+VJhdhAsx ZkGd5/u1a9wwBb1pEML1BN0He/7gRyjyiYeY/Vw5IwIhIQPHi+EzRY+b4vnjdFQCFEvT mT+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UIUuncYK5LuF874bLlgv9Sndabs4GqkeEig1nWblAF4=; fh=oweadga+1U1BKjDqlK8hSmEWEC1EUfcsKuPkDinEDsU=; b=KVs9/6GQDfdtmJnB4M5dE/OIrkS+qpqaM1ciCFIF1YwgxSrTXQYTUorgC2P770OXyG O6YNmp+Sp42AZi7oMNBYohB4lrwVdTLk2dEXos+AqLLqq3XGtL/iu6Nh/H/m6711A76k OJEOzqPzMR0zmJU0cm1Jm4XWOI5BrpHqXd0QHRmpLyCIDVYJ3LJwxnW97sicuYNxpyA4 AlX5+bjOcP/EF8e5vWeLR+f3JX8+7a/vuLfzhv0kL/7HvIKzu3c+JxED+rxJYQx2ob7T gDxRWjdv4BZME+IKTidbyeN7FLl0mbToRCeyI0iiP8L2Wl+omYbOcJY0e2BZEN7gcESs 6lSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J14rMj2a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f15-20020a0ccc8f000000b0063d4cfb4d53si224633qvl.438.2023.08.09.19.37.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Aug 2023 19:37:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J14rMj2a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTvWr-00011B-Kg; Wed, 09 Aug 2023 22:36:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTvWl-0000vz-4l for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:55 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTvWj-0004xO-7W for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:54 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-686f38692b3so370707b3a.2 for ; Wed, 09 Aug 2023 19:35:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691634952; x=1692239752; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UIUuncYK5LuF874bLlgv9Sndabs4GqkeEig1nWblAF4=; b=J14rMj2aacj5EX9ezHdfTZFOQTc/yhy+QR3vqDVS+RdKti+m6kXabo1mjwCdIYysEq USjXsFOrRhtjwnD6dpZV2zQ8PFEPdgA8g+WZa92hxeXeHrl1j1HLW6oBIJ69a9Y/CpHy H9YHx8OevAaKxQHWcaRLAIePumywdmXHd/bfP6XkM/NHlj3TDlQV3KhapA5KgNjpvNpW jD2fXlXoTXppb6dN94vlYjioEuClCbZI/0ChNZ8NMFWqo91GCR2uTzlmx2BQB/qZNr3D 0x6qwhbS+PfxXzcSNkKAiQfal5ptWj+AUxQqlsg5ef+OSZrmNhWp6XPzMh0BQt3x4hs5 7CWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691634952; x=1692239752; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UIUuncYK5LuF874bLlgv9Sndabs4GqkeEig1nWblAF4=; b=UYPqNLRGn+b1qNLmFstjA5DScFFIaWH4msYvz9S2n/6aSK8zTyugN4J5xFp4Zq11u/ CBskpTIJ8xonjStvInBfXz5wi0JcL5vUY2yde9nVmZd6Da14ArBvqwHILIVYYBjFadOA AIweePGKvsT47Iw8kWp8EyGUFR8rJMkKiW5xgBQY0EZqN5ccS45rIu7MGL2AMrHGBQNj tHuglpxcTbdPWGJoB6NLTwZYIQQNM6JFdPym7XMj6bcRoSOGSuWlyVA4ncyQF79SEd7j aD4QRSaUC0wCfzysoxgUMq/hDv+yffWgqMdfzUNsNv2s1fZdWYUtFF7H0eMG3NUXc+xA 0/bw== X-Gm-Message-State: AOJu0YxwedutejVBwnBBsInccleTXIGI19dGp4ojSGUIu/bkVTS0x7NJ fDHvFMu2mPTkmLoa18fhGpNqDiVHUUTUspa8PoY= X-Received: by 2002:a05:6a00:14c8:b0:687:5c3f:d834 with SMTP id w8-20020a056a0014c800b006875c3fd834mr1585369pfu.11.1691634951983; Wed, 09 Aug 2023 19:35:51 -0700 (PDT) Received: from stoup.. ([2602:47:d483:7301:6bf0:9674:6ac4:f74c]) by smtp.gmail.com with ESMTPSA id z7-20020aa791c7000000b0066ebaeb149dsm287283pfa.88.2023.08.09.19.35.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 19:35:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 2/5] target/arm: Reduce dcz_blocksize to uint8_t Date: Wed, 9 Aug 2023 19:35:45 -0700 Message-Id: <20230810023548.412310-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810023548.412310-1-richard.henderson@linaro.org> References: <20230810023548.412310-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This value is only 4 bits wide. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 88e5accda6..7fedbb34ba 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1074,7 +1074,8 @@ struct ArchCPU { bool prop_lpa2; /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ - uint32_t dcz_blocksize; + uint8_t dcz_blocksize; + uint64_t rvbar_prop; /* Property/input signals. */ /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ From patchwork Thu Aug 10 02:35:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 712346 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:baf:b0:129:c516:61db with SMTP id gf47csp355257rwb; Wed, 9 Aug 2023 19:37:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG4ST/LpNqOw/6l5ybe+MayfmI5VYdnLngUOGkH7Fo8aXXlKht5xpoaWEHik4e+A55FryF+ X-Received: by 2002:ac8:5810:0:b0:403:3583:68eb with SMTP id g16-20020ac85810000000b00403358368ebmr1599570qtg.19.1691635062453; Wed, 09 Aug 2023 19:37:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691635062; cv=none; d=google.com; s=arc-20160816; b=Jql8HtiApuRZfjBoZr4kUyBpjczenfAwrkQtYsX52/kglIULTCocksnZSecD3J5slx LUMK8i/2cWQhCrNhyVUMZnwLDhfasi5H789jMQ6oGgiEEvJ8EeWK4X0IBLiAEeL771FW jmWj1mEVIKpLNtcYaR6b5mZ5LFTvTOJh4sn2PgFRDm7bJva+no+bPNVbsx339OYhc9Yd 8Vpt+jwQdrmbfviCTAsJtSSk5ySZh9WCkyIfDXlXNsWxxDmfH/Th/eFa7BYs7hPzjAtK 8gQ6K6DImArhPlSpmDmkxZjUjoOzVE0KNuMB8zJ0olWTHm8vPFHgnv9zBrIilFM+oGXU wfnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Nf9XjMu3LHBxXgSXZqt7S0nPQIM+HaIPhW4YZS55L/M=; fh=oweadga+1U1BKjDqlK8hSmEWEC1EUfcsKuPkDinEDsU=; b=pXzI+JlQ5WlXTbqLOzOflwWdmqiNotVUotf6vasw1mTL6O41aIgw1mmRawAUrYDllq fd5tFNEhFAJNj6goxEqNAHshJAIa+G5jzBNbKFQaqSnnmoxda/BMlz0HqH+5F0t6VeOE q3qs3WIo5M4t3QK+ZezRLQNp+ZKYpW84oH8T+SzcVa99yDJxdEcmnjM+NPEQ8GSiMfWq N1MBDadqA6HbRGkT1D0jhmcXj6AUe/rqdH3G59ZLyG5vWWKhy3D4oo+TPgb/kQcYvryz 4JB/CAaYZEcqpxgeTjd2M75KQytL3MQtIcTx4JXUdrLrAB5A60EibgDUMq2EOyeWpYpn Ze6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BY3fq7DT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m22-20020ac85b16000000b00405ff62aad6si354007qtw.61.2023.08.09.19.37.42 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Aug 2023 19:37:42 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BY3fq7DT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTvWr-00011y-VK; Wed, 09 Aug 2023 22:36:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTvWl-0000wg-P9 for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:57 -0400 Received: from mail-qk1-x735.google.com ([2607:f8b0:4864:20::735]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTvWj-0004xl-Uq for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:55 -0400 Received: by mail-qk1-x735.google.com with SMTP id af79cd13be357-76ad8892d49so32778185a.1 for ; Wed, 09 Aug 2023 19:35:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691634953; x=1692239753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nf9XjMu3LHBxXgSXZqt7S0nPQIM+HaIPhW4YZS55L/M=; b=BY3fq7DTH1R8/mWIJh41Tbldrn7lZoQn9OFh9Eq4rZSq+en2APuk6TI6ocT+qBcg+f dGvr4UzJ0SJghLhapRh/s2IaevB7OOPdW9FNH4vvUTll3IhJmoMscePcz2ulf9N+7Elz gys/VIGsxW4VyOJ8bjLRHlrR2xRF9zf84QDS41ndOCGOiWhZwiqbcSv1iqdK0Q1lPYzJ pidYXRmuYMYKADxoNFzTU8CDeK7F5OaI+bo8Oo0Biruvic79V6SKf9p9Ch/kaId3yDdz BkmvhbEFSHdT8bEwwb5l0G51AHI7bXhASet+lhwbaS1dH81BT/s6RMC/tLs5KtVSpCCL P57g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691634953; x=1692239753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nf9XjMu3LHBxXgSXZqt7S0nPQIM+HaIPhW4YZS55L/M=; b=Lk/vYVBuRWhNASylmS2ce4SPnVO7voS1HftdvEax1SAO+eVvQbpEvA1qgV19DHZoLy nJ9F7yRflcuZjH5YzBU8gO3eoqdO/t3r4EMY2oxzNu0qkAZFdDtKdqhkHb+RDeW5fvn+ TPnQK6WY5sBHA74+peJk35W3IWeJJA4YRzsT+436iSH8wX7XaLQ9YiseMqZaJIy/MhdQ /I6QM0F+KoXfi29mwZ6AdewAez+JkAvtxYaSUAnRpXsbwszg/wqB+flrSt+uB2mT+dyt TMQNevvfIli2kx8l5EDNbKAyegPiilrSJiuJ/+JvxVLzz6MdnyxMZaZVN8lPLI33CxWm RUCA== X-Gm-Message-State: AOJu0YyVD8pM4z5Q24VTU0Z+t4c+AXP3qH/61ESukP2E2cbOMU5+7yu/ pcmO3Mwuc/ikvrYyBpf+P4WGwfucNTIUedKNSCc= X-Received: by 2002:a05:620a:3953:b0:768:14a8:9eb with SMTP id qs19-20020a05620a395300b0076814a809ebmr1113205qkn.9.1691634952888; Wed, 09 Aug 2023 19:35:52 -0700 (PDT) Received: from stoup.. ([2602:47:d483:7301:6bf0:9674:6ac4:f74c]) by smtp.gmail.com with ESMTPSA id z7-20020aa791c7000000b0066ebaeb149dsm287283pfa.88.2023.08.09.19.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 19:35:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 3/5] target/arm: Allow cpu to configure GM blocksize Date: Wed, 9 Aug 2023 19:35:46 -0700 Message-Id: <20230810023548.412310-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810023548.412310-1-richard.henderson@linaro.org> References: <20230810023548.412310-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::735; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x735.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Previously we hard-coded the blocksize with GMID_EL1_BS. But the value we choose for -cpu max does not match the value that cortex-a710 uses. Mirror the way we handle dcz_blocksize. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 6 ----- target/arm/tcg/translate.h | 2 ++ target/arm/helper.c | 11 +++++--- target/arm/tcg/cpu64.c | 1 + target/arm/tcg/mte_helper.c | 46 ++++++++++++++++++++++------------ target/arm/tcg/translate-a64.c | 5 ++-- 7 files changed, 45 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7fedbb34ba..dfa02eb4dc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1075,6 +1075,8 @@ struct ArchCPU { /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */ uint8_t dcz_blocksize; + /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */ + uint8_t gm_blocksize; uint64_t rvbar_prop; /* Property/input signals. */ diff --git a/target/arm/internals.h b/target/arm/internals.h index 0f01bc32a8..6fcf12c178 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1243,12 +1243,6 @@ void arm_log_exception(CPUState *cs); #endif /* !CONFIG_USER_ONLY */ -/* - * The log2 of the words in the tag block, for GMID_EL1.BS. - * The is the maximum, 256 bytes, which manipulates 64-bits of tags. - */ -#define GMID_EL1_BS 6 - /* * SVE predicates are 1/8 the size of SVE vectors, and cannot use * the same simd_desc() encoding due to restrictions on size. diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index d1cacff0b2..f748ba6f39 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -151,6 +151,8 @@ typedef struct DisasContext { int8_t btype; /* A copy of cpu->dcz_blocksize. */ uint8_t dcz_blocksize; + /* A copy of cpu->gm_blocksize. */ + uint8_t gm_blocksize; /* True if this page is guarded. */ bool guarded_page; /* Bottom two bits of XScale c15_cpar coprocessor access control reg */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 50f61e42ca..f5effa30f7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7643,10 +7643,6 @@ static const ARMCPRegInfo mte_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6, .access = PL1_RW, .accessfn = access_mte, .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) }, - { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, - .access = PL1_R, .accessfn = access_aa64_tid5, - .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS }, { .name = "TCO", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7, .type = ARM_CP_NO_RAW, @@ -9237,6 +9233,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) * then define only a RAZ/WI version of PSTATE.TCO. */ if (cpu_isar_feature(aa64_mte, cpu)) { + ARMCPRegInfo gmid_reginfo = { + .name = "GMID_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4, + .access = PL1_R, .accessfn = access_aa64_tid5, + .type = ARM_CP_CONST, .resetvalue = cpu->gm_blocksize, + }; + define_one_arm_cp_reg(cpu, &gmid_reginfo); define_arm_cp_regs(cpu, mte_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 60e5f034d9..5ca9070c14 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -868,6 +868,7 @@ void aarch64_max_tcg_initfn(Object *obj) cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ #endif + cpu->gm_blocksize = 6; /* 256 bytes */ cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); cpu->sme_vq.supported = SVE_VQ_POW2_MAP; diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 9c64def081..3640c6e57f 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -421,46 +421,54 @@ void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr) } } -#define LDGM_STGM_SIZE (4 << GMID_EL1_BS) - uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) { int mmu_idx = cpu_mmu_index(env, false); uintptr_t ra = GETPC(); + int gm_bs = env_archcpu(env)->gm_blocksize; + int gm_bs_bytes = 4 << gm_bs; void *tag_mem; - ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); + ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); /* Trap if accessing an invalid page. */ tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, - LDGM_STGM_SIZE, MMU_DATA_LOAD, - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); + gm_bs_bytes, MMU_DATA_LOAD, + gm_bs_bytes / (2 * TAG_GRANULE), ra); /* The tag is squashed to zero if the page does not support tags. */ if (!tag_mem) { return 0; } - QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); /* - * We are loading 64-bits worth of tags. The ordering of elements - * within the word corresponds to a 64-bit little-endian operation. + * The ordering of elements within the word corresponds to + * a little-endian operation. */ - return ldq_le_p(tag_mem); + switch (gm_bs) { + case 6: + /* 256 bytes -> 16 tags -> 64 result bits */ + return ldq_le_p(tag_mem); + default: + /* cpu configured with unsupported gm blocksize. */ + g_assert_not_reached(); + } } void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) { int mmu_idx = cpu_mmu_index(env, false); uintptr_t ra = GETPC(); + int gm_bs = env_archcpu(env)->gm_blocksize; + int gm_bs_bytes = 4 << gm_bs; void *tag_mem; - ptr = QEMU_ALIGN_DOWN(ptr, LDGM_STGM_SIZE); + ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); /* Trap if accessing an invalid page. */ tag_mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, - LDGM_STGM_SIZE, MMU_DATA_LOAD, - LDGM_STGM_SIZE / (2 * TAG_GRANULE), ra); + gm_bs_bytes, MMU_DATA_LOAD, + gm_bs_bytes / (2 * TAG_GRANULE), ra); /* * Tag store only happens if the page support tags, @@ -470,12 +478,18 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) return; } - QEMU_BUILD_BUG_ON(GMID_EL1_BS != 6); /* - * We are storing 64-bits worth of tags. The ordering of elements - * within the word corresponds to a 64-bit little-endian operation. + * The ordering of elements within the word corresponds to + * a little-endian operation. */ - stq_le_p(tag_mem, val); + switch (gm_bs) { + case 6: + stq_le_p(tag_mem, val); + break; + default: + /* cpu configured with unsupported gm blocksize. */ + g_assert_not_reached(); + } } void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5fa1257d32..d822d9a9af 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3786,7 +3786,7 @@ static bool trans_STGM(DisasContext *s, arg_ldst_tag *a) gen_helper_stgm(cpu_env, addr, tcg_rt); } else { MMUAccessType acc = MMU_DATA_STORE; - int size = 4 << GMID_EL1_BS; + int size = 4 << s->gm_blocksize; clean_addr = clean_data_tbi(s, addr); tcg_gen_andi_i64(clean_addr, clean_addr, -size); @@ -3818,7 +3818,7 @@ static bool trans_LDGM(DisasContext *s, arg_ldst_tag *a) gen_helper_ldgm(tcg_rt, cpu_env, addr); } else { MMUAccessType acc = MMU_DATA_LOAD; - int size = 4 << GMID_EL1_BS; + int size = 4 << s->gm_blocksize; clean_addr = clean_data_tbi(s, addr); tcg_gen_andi_i64(clean_addr, clean_addr, -size); @@ -13900,6 +13900,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, dc->cp_regs = arm_cpu->cp_regs; dc->features = env->features; dc->dcz_blocksize = arm_cpu->dcz_blocksize; + dc->gm_blocksize = arm_cpu->gm_blocksize; #ifdef CONFIG_USER_ONLY /* In sve_probe_page, we assume TBI is enabled. */ From patchwork Thu Aug 10 02:35:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 712342 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:baf:b0:129:c516:61db with SMTP id gf47csp354840rwb; Wed, 9 Aug 2023 19:36:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH0p03kYtoxJANKpCXeEeaGEsWr24Op4NyWMDLOeYXZF0X//VVQIoUedM+PRcjc00M5nA0z X-Received: by 2002:a05:6214:108c:b0:63d:419c:5914 with SMTP id o12-20020a056214108c00b0063d419c5914mr1160013qvr.57.1691635006811; Wed, 09 Aug 2023 19:36:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691635006; cv=none; d=google.com; s=arc-20160816; b=ohl7Hs/9g/+U9J9MmdRcsotTQK1LZhHHC6kGXmOid3EiLFMyLP3igRxPQQnWa4X9t4 6Gf8hpPnwpb03kijslqokXWXJUPMxXxBUeiqROSnflo1SuoPBxoT670GuYEd8udm8LM8 /EFnnhvZryHsm81ucqzWyQhsiQbvukg7VCmte4u5Ci9bTK/BHVvJ4yuG4MtRCaZX+Fku x+gNM6hpnkZKA52iLZB/vvZ6hX2Goj6ZsyXPqEBwnQKKiLOkXHpNco7ZMabxx8tp9Ep1 CSbRB2eYTEdP7DBCl4ZGE+H9g8dxMwdJA6/tKXYDXu6k/QYQ69HLhXAJsOOnjX6m3+3d 7cLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DxgqNR4/eVoHsIiiFC5Te9EYL+Uy4Gcd+N/BbwRB+MQ=; fh=oweadga+1U1BKjDqlK8hSmEWEC1EUfcsKuPkDinEDsU=; b=HSRBoLP0Saz3LKD1+pWPVkgfPpxr87KgfmUodYPiFS4ttaL/hnXWG7ptiAyF8qkg7G A8dj2wlHufV4/JslO1JeFMobYTDdYYsjI6M+35Jz7MqCHPsbfu3qQLrbZYePbEmY+vPS dtX5HsqE7HXTBULtrNwqse/cgf465MDej9NVWmHMq2aH3J/Ust3FxMQmOjZGfcqfTNq5 QG9UiLGslsREHjfXiaD6ZLt2+qd1tLgnNayHMJxUkTCY9nKf/uhLVYIho0BoU6XB38sF SekXLXhhntVVna6K4u3JiAgPpYhmNZvQNWB75TiKWWEo6W1g4Z+mAUF7cdPAAq94ktEa Rn8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f5dJmtSx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b1-20020a0c9b01000000b0063d68f71c94si244145qve.63.2023.08.09.19.36.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Aug 2023 19:36:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f5dJmtSx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTvWq-00010L-U2; Wed, 09 Aug 2023 22:36:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTvWn-0000x7-3c for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:57 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTvWk-0004yA-TX for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:56 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-686f0d66652so382587b3a.2 for ; Wed, 09 Aug 2023 19:35:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691634953; x=1692239753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DxgqNR4/eVoHsIiiFC5Te9EYL+Uy4Gcd+N/BbwRB+MQ=; b=f5dJmtSxVZskh73aGB1ynAf/qnaTllGhYpUrauK0PYHAXj020th+U2B0UqM7akwREb NrQtRV4stAv1H7oaJU5dteu3ruw/OYMoq8VoDq8vMzEHgUrnwUPPmrsT2oCisxJ3f1P7 UOPiIyCHMTwt65dO6SDb3rRvkOx/7h+V6ndv+ouW1HRQLRVStlJNObnoaEDWU+9c6o9g x0Y09fcp1EmDEeYtw1YA1/bPzHhYzDZA2pToNM5mtwSEynVp4I5q+IQRhdicNX7I6L4I 83hSNCt6jUvm8L4Wj3Xp2w0G9sKhDUq6qiQqoMAKiqPKjWCftnT7i89ra6q208yoD26o 9B4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691634953; x=1692239753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DxgqNR4/eVoHsIiiFC5Te9EYL+Uy4Gcd+N/BbwRB+MQ=; b=Y+bef9XXcExaRBP/nxWZ7w3lCEbB3q4XCdZERsRH9I3dQ5g8UUrF7fiq0bau0Q+nxA 12tMvAZP4jEpxZaWf5IJQiZHEQs/TvRomlNAlR10YAHAji/uZkXSm1aNJFVKcJJUKIYI /R2iqapSGdnn+zOndNFEIXSFwB0cGj2iMqsb8Ymhjh+vru15474qh1/ZSSHwQ+K74b/z WT2Ps//aNn0qHr0GgSsJq+kM4bTBS8UQieRivYcL5sLhXNxYQwU0GUDu5btlfGvQ77Or nGIY7wEw76CsSUgL3o+Y18FLuyffEM1vNXH47TQup414WPyb6s64INli5ABGmShcd2eY jGbw== X-Gm-Message-State: AOJu0Yx97Q27SYcwJ9E2SZb2cUSHv+SilADsvE7CvzqE9Jqh82hiP5aL HjRT2ybPKGssFEpL0prnOxckJYGCrg3cnqlFtWM= X-Received: by 2002:a05:6a00:1588:b0:64d:46b2:9a58 with SMTP id u8-20020a056a00158800b0064d46b29a58mr1753737pfk.26.1691634953603; Wed, 09 Aug 2023 19:35:53 -0700 (PDT) Received: from stoup.. ([2602:47:d483:7301:6bf0:9674:6ac4:f74c]) by smtp.gmail.com with ESMTPSA id z7-20020aa791c7000000b0066ebaeb149dsm287283pfa.88.2023.08.09.19.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 19:35:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 4/5] target/arm: Support more GM blocksizes Date: Wed, 9 Aug 2023 19:35:47 -0700 Message-Id: <20230810023548.412310-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810023548.412310-1-richard.henderson@linaro.org> References: <20230810023548.412310-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Support all of the easy GM block sizes. Use direct memory operations, since the pointers are aligned. While BS=2 (16 bytes, 1 tag) is a legal setting, that requires an atomic store of one nibble. This is not difficult, but there is also no point in supporting it until required. Note that cortex-a710 sets GM blocksize to match its cacheline size of 64 bytes. I expect many implementations will also match the cacheline, which makes 16 bytes very unlikely. Signed-off-by: Richard Henderson --- target/arm/tcg/mte_helper.c | 61 ++++++++++++++++++++++++++++++++----- 1 file changed, 53 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 3640c6e57f..6faf4e42d5 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -428,6 +428,8 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) int gm_bs = env_archcpu(env)->gm_blocksize; int gm_bs_bytes = 4 << gm_bs; void *tag_mem; + uint64_t ret; + int shift; ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); @@ -443,16 +445,39 @@ uint64_t HELPER(ldgm)(CPUARMState *env, uint64_t ptr) /* * The ordering of elements within the word corresponds to - * a little-endian operation. + * a little-endian operation. Computation of shift comes from + * + * index = address + * data = tag + * + * Because of the alignment of ptr above, BS=6 has shift=0. + * All memory operations are aligned. */ switch (gm_bs) { - case 6: - /* 256 bytes -> 16 tags -> 64 result bits */ - return ldq_le_p(tag_mem); - default: + case 2: /* cpu configured with unsupported gm blocksize. */ g_assert_not_reached(); + case 3: + /* 32 bytes -> 2 tags -> 8 result bits */ + ret = *(uint8_t *)tag_mem; + break; + case 4: + /* 64 bytes -> 4 tags -> 16 result bits */ + ret = cpu_to_le16(*(uint16_t *)tag_mem); + break; + case 5: + /* 128 bytes -> 8 tags -> 32 result bits */ + ret = cpu_to_le32(*(uint32_t *)tag_mem); + break; + case 6: + /* 256 bytes -> 16 tags -> 64 result bits */ + return cpu_to_le64(*(uint64_t *)tag_mem); + default: + /* cpu configured with invalid gm blocksize. */ + g_assert_not_reached(); } + shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; + return ret << shift; } void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) @@ -462,6 +487,7 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) int gm_bs = env_archcpu(env)->gm_blocksize; int gm_bs_bytes = 4 << gm_bs; void *tag_mem; + int shift; ptr = QEMU_ALIGN_DOWN(ptr, gm_bs_bytes); @@ -480,14 +506,33 @@ void HELPER(stgm)(CPUARMState *env, uint64_t ptr, uint64_t val) /* * The ordering of elements within the word corresponds to - * a little-endian operation. + * a little-endian operation. See LDGM for comments on shift. + * All memory operations are aligned. */ + shift = extract64(ptr, LOG2_TAG_GRANULE, 4) * 4; + val >>= shift; switch (gm_bs) { + case 2: + /* cpu configured with unsupported gm blocksize. */ + g_assert_not_reached(); + case 3: + /* 32 bytes -> 2 tags -> 8 result bits */ + *(uint8_t *)tag_mem = val; + break; + case 4: + /* 64 bytes -> 4 tags -> 16 result bits */ + *(uint16_t *)tag_mem = cpu_to_le16(val); + break; + case 5: + /* 128 bytes -> 8 tags -> 32 result bits */ + *(uint32_t *)tag_mem = cpu_to_le32(val); + break; case 6: - stq_le_p(tag_mem, val); + /* 256 bytes -> 16 tags -> 64 result bits */ + *(uint64_t *)tag_mem = cpu_to_le64(val); break; default: - /* cpu configured with unsupported gm blocksize. */ + /* cpu configured with invalid gm blocksize. */ g_assert_not_reached(); } } From patchwork Thu Aug 10 02:35:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 712344 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:baf:b0:129:c516:61db with SMTP id gf47csp355150rwb; Wed, 9 Aug 2023 19:37:26 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHoFR7aapWw4GwSP9Gkw3X3luBZ1WYoX7/FbAgUQ4fuGAOT+3j5jtL2YCZVuDwJQ5fu3PIf X-Received: by 2002:a05:622a:390:b0:40f:b77d:22d6 with SMTP id j16-20020a05622a039000b0040fb77d22d6mr1553595qtx.0.1691635046460; Wed, 09 Aug 2023 19:37:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691635046; cv=none; d=google.com; s=arc-20160816; b=isg5dNSDKjDp9NxgfZLbmMPeu99cpo9JeU8ziQvAkDmB0H13vyyISj9rC1js0YzHoX s/DQHN7Uh/DnjMCXMVsSW9SC6JlxrLMw46eXAOHz+gzk9T7HnleLAiPdoMvqZaMi/AoT MsHiEZWdyYBWkV2HR70F2TX1nO+bDVG6T/4jwCoNsbby2tAjmrhHWoOvY4oOw6vksHQn h9JdlSavslKqzi4uG/XwTvO9hC35eXidj6TzwPQn+yQIA3r0LeJJ3eEBdmzyQ9xUlPRp i+JwW++TkFiwqnSLRmfIOB0hHW7gX1MH7tbDRyrZzsLczKTigisa8E/M7WiUDTSgZ1L2 pn3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zAYDJTdawZ3d8edXM0V7IrgfXqP83Zo/hY/QUM86iSw=; fh=oweadga+1U1BKjDqlK8hSmEWEC1EUfcsKuPkDinEDsU=; b=UdI1umghzbpbKxksdsOnk97VcrmbeI4HjCF+RGGrYzlosnfcwq2Rrsl52zEKpxJ1la ELcngOS5xCWuys1rcwz4sg9DFCxzssn7ahDNVW5CPjM3Tl8BzCKlubEjAI7PkfDqCR3D zpo9gutTcq+X19GpYLaJFHXNRaycTimgg9rk6UFW2b4kHK+VPHgQi5GcD+TWpFI3bra0 S9GP9sENSoqJI1Pp6RSqWnFl/V5NbQxQbAI4L0vw8o/pHHSC3nWEcPWZMYvYFgYqIPZp 4losQ2nzmkgVzyeTlQqZGwckkFWtl6DNbvlN6asSc0xK80l+65lK9lQMqgWdLyOk1qPn hvBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uTvHPUyF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e16-20020ac84e50000000b00403b0042146si325548qtw.467.2023.08.09.19.37.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 09 Aug 2023 19:37:26 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uTvHPUyF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTvWr-00011M-NL; Wed, 09 Aug 2023 22:36:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTvWo-0000yX-IK for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:59 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTvWl-0004ye-VT for qemu-devel@nongnu.org; Wed, 09 Aug 2023 22:35:57 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-686daaa5f1fso314632b3a.3 for ; Wed, 09 Aug 2023 19:35:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691634955; x=1692239755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zAYDJTdawZ3d8edXM0V7IrgfXqP83Zo/hY/QUM86iSw=; b=uTvHPUyFAJxSGZ1vUWo65FG3SGJlHTHFip8ogoG2B5xZHnSbdm2vGM9dhP4DGa7mFN KFKNXySA9ZPWK610u1m6AzujI3BrM/5eQ53kJ7hi+UCoEn0m9h78jKc57VkjRtrHQx/J 0sbN2zEDeipGKbGIpdbunyr0cdLqRFOGsWEAcVnlesP/j/oQuGJtwfNN70nm0K4Apuk8 6hpSdO+l7cwMsO2WmwGCPhrMjVJtXZPy3h8mknK9KT/wNRcdiuGQt5ygDxRnhSCo2pzC CfGQDBWalIzSaWkQs+T/5zQhyijvghsmGTrkDt7ZMczbCAETvWHDzgxVhu7NwLbJTTfS mq/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691634955; x=1692239755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zAYDJTdawZ3d8edXM0V7IrgfXqP83Zo/hY/QUM86iSw=; b=gRjOJI1REybJKbo00zaUc+oqSRb6J32OkZzPy2N2YPeAin0LOYMTLT71FLvACnCL+7 sZYsZmLvA/wXkqCxA6BoDnMdeh0+ePyCvq038Jr5bJfiYTktylnN4sKBwcbdnFNDtMfX NsylLkMAvDnCpK2ZMjDHlwOgE1aQ07XT710MEzs8YqXckZC5oiwG9peaEpn+ihykf97p 8dlseQPkTR7u3jdgSxmK8DieBuRst4POfCqGRkKd5geSNuAZiacEsPDekVsMc2ihinfJ KIhJQ2IdTt1RHQ4MdezoOMsTGLtBcXOVMUruCNOSPxGjCGAIjhBT/NUl3FZ5sJdFAZQB AP+Q== X-Gm-Message-State: AOJu0Yz8tnSRyWcQD9HbO2lmoqXLwV/x8LrJesKCbIVfdlEw5E3cLdh3 sxMsa+odMsL9AEAcMdkq/JR1lFD4HBuNxp60Gi8= X-Received: by 2002:a05:6a20:cea9:b0:13f:53b1:c063 with SMTP id if41-20020a056a20cea900b0013f53b1c063mr1010138pzb.49.1691634954479; Wed, 09 Aug 2023 19:35:54 -0700 (PDT) Received: from stoup.. ([2602:47:d483:7301:6bf0:9674:6ac4:f74c]) by smtp.gmail.com with ESMTPSA id z7-20020aa791c7000000b0066ebaeb149dsm287283pfa.88.2023.08.09.19.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Aug 2023 19:35:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 5/5] target/arm: Implement cortex-a710 Date: Wed, 9 Aug 2023 19:35:48 -0700 Message-Id: <20230810023548.412310-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230810023548.412310-1-richard.henderson@linaro.org> References: <20230810023548.412310-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The cortex-a710 is a first generation ARMv9.0-A processor. Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c | 1 + target/arm/tcg/cpu64.c | 167 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 169 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 51cdac6841..e1697ac8f4 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -58,6 +58,7 @@ Supported guest CPU types: - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) - ``cortex-a76`` (64-bit) +- ``cortex-a710`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``neoverse-n1`` (64-bit) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7d9dbc2663..d1522c305d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -211,6 +211,7 @@ static const char *valid_cpus[] = { ARM_CPU_TYPE_NAME("cortex-a55"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), + ARM_CPU_TYPE_NAME("cortex-a710"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("neoverse-v1"), diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 5ca9070c14..6f555a39ce 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -700,6 +700,172 @@ static void aarch64_neoverse_v1_initfn(Object *obj) aarch64_add_sve_properties(obj); } +static const ARMCPRegInfo cortex_a710_cp_reginfo[] = { + /* TODO: trapped by HCR_EL2.TIDCP */ + { .name = "CPUACTLR4_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 3, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUECTLR2_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 5, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUACTLR5_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUACTLR6_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUACTLR7_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 8, .opc2 = 2, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPPMCR4_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 4, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPPMCR5_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 5, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPPMCR6_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 2, .opc2 = 6, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUACTLR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 4, .opc2 = 0, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPOR2_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 4, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "CPUPMR2_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 8, .opc2 = 5, + .access = PL3_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + + /* + * Stub RAMINDEX, as we don't actually implement caches, + * BTB, or anything else with cpu internal memory. + * "Read" zeros into the IDATA* and DDATA* output registers. + */ + { .name = "RAMINDEX_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0, + .access = PL3_W, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "IDATA0_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 0, + .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "IDATA1_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 1, + .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "IDATA2_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 0, .opc2 = 2, + .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "DDATA0_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 0, + .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "DDATA1_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 1, + .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "DDATA2_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 1, .opc2 = 2, + .access = PL3_R, .type = ARM_CP_CONST, .resetvalue = 0 }, +}; + +static void define_cortex_a710_cp_reginfo(ARMCPU *cpu) +{ + /* + * The Cortex A710 has all of the Neoverse V1's IMPDEF + * registers and a few more of its own. + */ + define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); + define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo); + define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); +} + +static void aarch64_a710_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cpu->dtb_compatible = "arm,cortex-a710"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by Section B.4: AArch64 registers */ + cpu->midr = 0x412FD471; /* r2p1 */ + cpu->revidr = cpu->midr; /* mirror midr: "no significance" */ + cpu->isar.id_pfr0 = 0x21110131; + cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ + cpu->isar.id_dfr0 = 0x06011099; /* w/o FEAT_TRF */ + cpu->id_afr0 = 0; + cpu->isar.id_mmfr0 = 0x10201105; + cpu->isar.id_mmfr1 = 0x40000000; + cpu->isar.id_mmfr2 = 0x01260000; + cpu->isar.id_mmfr3 = 0x02122211; + cpu->isar.id_isar0 = 0x02101110; + cpu->isar.id_isar1 = 0x13112111; + cpu->isar.id_isar2 = 0x21232042; + cpu->isar.id_isar3 = 0x01112131; + cpu->isar.id_isar4 = 0x00010142; + cpu->isar.id_isar5 = 0x11011121; + cpu->isar.id_mmfr4 = 0x21021110; + cpu->isar.id_isar6 = 0x01111111; + cpu->isar.mvfr0 = 0x10110222; + cpu->isar.mvfr1 = 0x13211111; + cpu->isar.mvfr2 = 0x00000043; + cpu->isar.id_pfr2 = 0x00000011; + /* GIC filled in later; w/o FEAT_MPAM */ + cpu->isar.id_aa64pfr0 = 0x1201101120111112ull; + cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; + cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; + cpu->isar.id_aa64dfr0 = 0x000000f210305619ull; /* w/o FEAT_{TRF,TRBE} */ + cpu->isar.id_aa64dfr1 = 0; + cpu->id_aa64afr0 = 0; + cpu->id_aa64afr1 = 0; + cpu->isar.id_aa64isar0 = 0x0221111110212120ull; + cpu->isar.id_aa64isar1 = 0x0010111101211032ull; + cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull; + cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull; + cpu->clidr = 0x0000002282000023ull; + cpu->gm_blocksize = 4; + cpu->ctr = 0x00000004b444c004ull; /* with DIC set */ + cpu->dcz_blocksize = 4; + /* TODO FEAT_MPAM: mpamidr_el1 = 0x0000_0001_0006_003f */ + + /* Section B.5.2: PMCR_EL0 */ + cpu->isar.reset_pmcr_el0 = 0xa000; /* with 20 counters */ + + /* Section B.6.7: ICH_VTR_EL2 */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; + cpu->gic_pribits = 5; + + /* Section 14: Scalable Vector Extensions support */ + cpu->sve_vq.supported = 1 << 0; /* 128bit */ + + /* + * The cortex-a710 TRM does not list CCSIDR values. + * The layout of the cache is in text in Table 7-1 (L1-I), + * Table 8-1 (L1-D), and Table 9-1 (L2). + * + * L1: 4-way set associative 64-byte line size, total either 32K or 64K. + * We pick 64K, so this has 256 sets. + * + * L2: 8-way set associative 64 byte line size, total either 256K or 512K. + * We pick 512K, so this has 1024 sets. + */ + cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */ + cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */ + cpu->ccsidr[2] = 0x000003ff0000003aull; /* 512KB L2 cache */ + + /* ??? Not documented -- copied from neoverse-v1 */ + cpu->reset_sctlr = 0x30c50838; + + define_cortex_a710_cp_reginfo(cpu); + aarch64_add_pauth_properties(obj); + aarch64_add_sve_properties(obj); +} + /* * -cpu max: a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu32.c; @@ -889,6 +1055,7 @@ static const ARMCPUInfo aarch64_cpus[] = { { .name = "cortex-a55", .initfn = aarch64_a55_initfn }, { .name = "cortex-a72", .initfn = aarch64_a72_initfn }, { .name = "cortex-a76", .initfn = aarch64_a76_initfn }, + { .name = "cortex-a710", .initfn = aarch64_a710_initfn }, { .name = "a64fx", .initfn = aarch64_a64fx_initfn }, { .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn }, { .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn },