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Tue, 8 Aug 2023 10:25:52 +0000 From: Xu Yang To: stern@rowland.harvard.edu Cc: gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, jun.li@nxp.com Subject: [PATCH 1/2] usb: ehci: add workaround for chipidea PORTSC.PEC bug Date: Tue, 8 Aug 2023 18:29:58 +0800 Message-Id: <20230808102959.479264-1-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: SG2P153CA0002.APCP153.PROD.OUTLOOK.COM (2603:1096::12) To DB7PR04MB4505.eurprd04.prod.outlook.com (2603:10a6:5:39::26) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB7PR04MB4505:EE_|AS8PR04MB8372:EE_ X-MS-Office365-Filtering-Correlation-Id: 36574ec7-2333-419f-61f0-08db97f9d743 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CFQJXY0zKNdh0tEscUK9fwoSdZrOQeG5LfVfuxso3VLVJ8P8M/5QO4RSPASnGpf3vx1hi8vUablyS/FC/J0Vu4vbFZNWDuvt2FqH6C8ESRhtSmoey/rQW9T+XAag8Dz1B/JbDbq9EtdaVsyaHbCL0N6uU1GHYBuct9AiiDLqbOzdNwqD87Qj0RBBeVD4uzyB3CNe0r0UxESHbFvIwiCwM0mPSOzTYFze1LZ5+imiXjhQvkygYPTKkIhbSSoeNpIFQ4BaQo4pZy4REUkaIUfJsNC65D6kF1OPpuZl0gts/vlA+fHKzLqKxUHDhq24n5bpQBS4Dt1sEhd6o+HHu9iQrz/UL6q9EXzBXAgOZ7haRIGO4z3saYYSz7IyI6DVPvlsd+3+8R6mnssvvz5X1469pqqQmorbNj4gPwpsLCuBMMvxOKFwLDtQTPygS2D7KQw4DD8/J4ratknNc682QBRnsEicOqgzgpO+uAoNKEkEEc3fctoS60ZRXZj73S+b7VqnBfXXLs1wNZyj9PQxBQwI2zTdFoTGi8a+xOpgymJyVasTz55Sm1czIJBUHcFUL6oCsdid78OchyXWBdW4tsBuXmo+LNLKot4cIrYFRf0NB0nM1j+83ADcCtEflNCo+gsn X-Forefront-Antispam-Report: CIP:255.255.255.255; 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As per 4.15.1.1.1 Serial Bus Babble: A babble condition also exists if IN transaction is in progress at High-speed SOF2 point. This is called frame balle. The host controller must disable the port to which the frame babble is detected. The USB controller has disabled the port (PE cleared) and has asserted USBERRINT when frame babble is detected, but PEC is not asserted. Therefore, the SW didn't aware that port has been disabled. Then the SW keeps sending packets to this port, but all of the transfers will fail. This workaround will firstly assert PCD by SW when USBERRINT is detected and then judge whether port change has really occurred or not by polling roothub status. Because the PEC doesn't get asserted in our case, this patch will also assert it by SW when specific conditions are satisfied. Signed-off-by: Xu Yang --- drivers/usb/host/ehci-hcd.c | 5 +++++ drivers/usb/host/ehci-hub.c | 10 +++++++++- drivers/usb/host/ehci.h | 10 ++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index a1930db0da1c..d6b276c354db 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -762,6 +762,11 @@ static irqreturn_t ehci_irq (struct usb_hcd *hcd) bh = 1; } + /* Force to check port status */ + if (ehci->has_ci_pec_bug && (status & STS_ERR) + && !(status & STS_PCD)) + status |= STS_PCD; + /* complete the unlinking of some qh [4.15.2.3] */ if (status & STS_IAA) { diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c index efe30e3be22f..1aee392e8492 100644 --- a/drivers/usb/host/ehci-hub.c +++ b/drivers/usb/host/ehci-hub.c @@ -674,7 +674,8 @@ ehci_hub_status_data (struct usb_hcd *hcd, char *buf) if ((temp & mask) != 0 || test_bit(i, &ehci->port_c_suspend) || (ehci->reset_done[i] && time_after_eq( - jiffies, ehci->reset_done[i]))) { + jiffies, ehci->reset_done[i])) + || ehci_has_ci_pec_bug(ehci, temp)) { if (i < 7) buf [0] |= 1 << (i + 1); else @@ -875,6 +876,13 @@ int ehci_hub_control( if (temp & PORT_PEC) status |= USB_PORT_STAT_C_ENABLE << 16; + if (ehci_has_ci_pec_bug(ehci, temp)) { + status |= USB_PORT_STAT_C_ENABLE << 16; + ehci_info(ehci, + "PE is cleared by HW port:%d PORTSC:%08x\n", + wIndex + 1, temp); + } + if ((temp & PORT_OCC) && (!ignore_oc && !ehci->spurious_oc)){ status |= USB_PORT_STAT_C_OVERCURRENT << 16; diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index c5c7f8782549..1441e3400796 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -207,6 +207,7 @@ struct ehci_hcd { /* one per controller */ unsigned has_fsl_port_bug:1; /* FreeScale */ unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */ unsigned has_fsl_susp_errata:1; /* NXP SUSP quirk */ + unsigned has_ci_pec_bug:1; /* ChipIdea PEC bug */ unsigned big_endian_mmio:1; unsigned big_endian_desc:1; unsigned big_endian_capbase:1; @@ -707,6 +708,15 @@ ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc) */ #define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata) +/* + * Some Freescale/NXP processors using ChipIdea IP have a bug in which + * disabling the port (PE is cleared) does not cause PEC to be asserted + * when frame babble is detected. + */ +#define ehci_has_ci_pec_bug(e, portsc) \ + ((e)->has_ci_pec_bug && ((e)->command & CMD_PSE) \ + && !(portsc & PORT_PEC) && !(portsc & PORT_PE)) + /* * While most USB host controllers implement their registers in * little-endian format, a minority (celleb companion chip) implement From patchwork Tue Aug 8 10:37:34 2023 Content-Type: text/plain; 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Tue, 8 Aug 2023 10:33:29 +0000 From: Xu Yang To: stern@rowland.harvard.edu, peter.chen@kernel.org Cc: gregkh@linuxfoundation.org, linux-usb@vger.kernel.org, jun.li@nxp.com, xu.yang_2@nxp.com Subject: [PATCH 2/2] usb: chipidea: add workaround for chipidea PEC bug Date: Tue, 8 Aug 2023 18:37:34 +0800 Message-Id: <20230808103734.494321-2-xu.yang_2@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808103734.494321-1-xu.yang_2@nxp.com> References: <20230808103734.494321-1-xu.yang_2@nxp.com> X-ClientProxiedBy: SI1PR02CA0032.apcprd02.prod.outlook.com (2603:1096:4:1f6::12) To DB7PR04MB4505.eurprd04.prod.outlook.com (2603:10a6:5:39::26) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DB7PR04MB4505:EE_|AM7PR04MB6936:EE_ X-MS-Office365-Filtering-Correlation-Id: 908e5275-d98b-4adb-c395-08db97fae804 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mu1lmd8g22SgEGNiGDMcxPzvAFn19Sb8+BL1ylvGFclZFauNvh2ph0PRt20lAs8jyglSpdxmNoGmY46tZe2hXC+IPmW9SEvSTHcC5PSI8XwdQ2RqM8Rnws/cBczl1kpFuhoC+SxFFp6bhdyS1LH8YdNG/kURihxttoUP0lfRMKIXuF9FgFUhwNDvijyxEVqC9IC886ezmJWVdkZzA/P60aWUm6D0UfmyeA3ze3BGQT7YPj5vZcufupmL76lIRWsMHQGGPiQ7CClyH0fBUQHixYHGfb66TBBIGLgEvsOyLsJX3kFkEPEVEVKSZUUjaDA0I+47Dhij4CXm+wuLCKOeb0U6NvD7z/DrT8aHoOFcBke1FZh9Xq9v22VTnbbvBBjcVCjhR19NXf7prFMdjwEBT0zLE8QXnoEI3sKwrqmpVKl+iTyHPfYoaK4BacyHazTwspPUMrRGAHZ4x5EiudIlGmauO0Bf5OtwIGsDBOmbA/eON/aDnr1dsPf5Xkd9mIChgBCATFoI9XkijSYfIPZZ7k/d1qcCIWNJVWJVTXi01JTvy2AdIAa4c5zQmiehoCNS+s8nRIkIeN/gDuDAw6N2dHJhdwHTv2sZUVhZsxSMJlI4u9BZsuCrK7HLg/VuZj6M X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Issue description: In USB camera test, our controller is host in HS mode. In ISOC IN, when device sends data across the micro frame, it causes the babble in host controller. This will clear the PE bit. In spec, it also requires to set the PEC bit and then set the PCI bit. Without the PCI interrupt, the software does not know the PE is cleared. This will add a flag CI_HDRC_HAS_PORTSC_PEC_MISSED to some impacted platform datas. And the ehci host driver will assert PEC by SW when specific conditions are satisfied. Signed-off-by: Xu Yang --- drivers/usb/chipidea/ci.h | 1 + drivers/usb/chipidea/ci_hdrc_imx.c | 4 +++- drivers/usb/chipidea/core.c | 2 ++ drivers/usb/chipidea/host.c | 1 + include/linux/usb/chipidea.h | 1 + 5 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h index d262b9df7b3d..d9bb3d3f026e 100644 --- a/drivers/usb/chipidea/ci.h +++ b/drivers/usb/chipidea/ci.h @@ -257,6 +257,7 @@ struct ci_hdrc { bool id_event; bool b_sess_valid_event; bool imx28_write_fix; + bool has_portsc_pec_bug; bool supports_runtime_pm; bool in_lpm; bool wakeup_int; diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c b/drivers/usb/chipidea/ci_hdrc_imx.c index 772bbdade994..e28bb2f2612d 100644 --- a/drivers/usb/chipidea/ci_hdrc_imx.c +++ b/drivers/usb/chipidea/ci_hdrc_imx.c @@ -68,11 +68,13 @@ static const struct ci_hdrc_imx_platform_flag imx7d_usb_data = { static const struct ci_hdrc_imx_platform_flag imx7ulp_usb_data = { .flags = CI_HDRC_SUPPORTS_RUNTIME_PM | + CI_HDRC_HAS_PORTSC_PEC_MISSED | CI_HDRC_PMQOS, }; static const struct ci_hdrc_imx_platform_flag imx8ulp_usb_data = { - .flags = CI_HDRC_SUPPORTS_RUNTIME_PM, + .flags = CI_HDRC_SUPPORTS_RUNTIME_PM | + CI_HDRC_HAS_PORTSC_PEC_MISSED, }; static const struct of_device_id ci_hdrc_imx_dt_ids[] = { diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 6e1196b53253..7ac39a281b8c 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -1044,6 +1044,8 @@ static int ci_hdrc_probe(struct platform_device *pdev) CI_HDRC_IMX28_WRITE_FIX); ci->supports_runtime_pm = !!(ci->platdata->flags & CI_HDRC_SUPPORTS_RUNTIME_PM); + ci->has_portsc_pec_bug = !!(ci->platdata->flags & + CI_HDRC_HAS_PORTSC_PEC_MISSED); platform_set_drvdata(pdev, ci); ret = hw_device_init(ci, base); diff --git a/drivers/usb/chipidea/host.c b/drivers/usb/chipidea/host.c index ebe7400243b1..08af26b762a2 100644 --- a/drivers/usb/chipidea/host.c +++ b/drivers/usb/chipidea/host.c @@ -151,6 +151,7 @@ static int host_start(struct ci_hdrc *ci) ehci->has_hostpc = ci->hw_bank.lpm; ehci->has_tdi_phy_lpm = ci->hw_bank.lpm; ehci->imx28_write_fix = ci->imx28_write_fix; + ehci->has_ci_pec_bug = ci->has_portsc_pec_bug; priv = (struct ehci_ci_priv *)ehci->priv; priv->reg_vbus = NULL; diff --git a/include/linux/usb/chipidea.h b/include/linux/usb/chipidea.h index ee38835ed77c..0b4f2d5faa08 100644 --- a/include/linux/usb/chipidea.h +++ b/include/linux/usb/chipidea.h @@ -63,6 +63,7 @@ struct ci_hdrc_platform_data { #define CI_HDRC_IMX_IS_HSIC BIT(14) #define CI_HDRC_PMQOS BIT(15) #define CI_HDRC_PHY_VBUS_CONTROL BIT(16) +#define CI_HDRC_HAS_PORTSC_PEC_MISSED BIT(17) enum usb_dr_mode dr_mode; #define CI_HDRC_CONTROLLER_RESET_EVENT 0 #define CI_HDRC_CONTROLLER_STOPPED_EVENT 1