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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V1 1/6] ACPI: CPPC: Add get the highest performance cppc control Date: Tue, 8 Aug 2023 16:09:56 +0800 Message-ID: <20230808081001.2215240-2-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808081001.2215240-1-li.meng@amd.com> References: <20230808081001.2215240-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E9:EE_|SA0PR12MB7089:EE_ X-MS-Office365-Filtering-Correlation-Id: b0970465-1843-47ad-0c82-08db97e702e9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 78HoVerrP/U/kIRrQ2gfxx238Oy6x0CWZbE/Q7St3oixRkBgrUQPvhwHXN9096Cu2lE76xalC1YPK47DQLrwMa3tS10sf9K64VzzM87TflzGcIFM5QQEKqqH191grv9i5TxIsZC67OBz1pDGY07SMUt/pRAA8THd3FIpJbYkyJ7zBa2bCxm/7X3hsq0dN8pbn6vceCXog2SPyjSXrSZ54xP6hgrUKd/E0LGa+yOlBjVS9Qo3z5sfH1hPvXuSTMp5mutSu4bK/fb4U5B73glgzOGUB4fYQ5auuEEHjIbChwvqfOKBB9quJMH3uVFJmKwYib8xlJOpfwb+VkRTpKuGZQ3S15QU2DAq4b4zPHYgE5sXF9sZ+BsbeLtKiWG4MPpE2c0ZNORPJum9uXIJ1Gis8dxaOKnY4q2Vf8yjhO3SMUvqQVIvi2bHZn3Sjj43IZHjtObh9aIqaLvSemEOKmen8Tql9sCt6TQwqRPuODR7qW02eb0SE2sDNlmqLKAVDQxX4mgA3WvkfTFaImQ+4UEp1Yn7LEjOSalaOB6EMJ16DTcYmZcxv1QvMDOel1GqG3BY+QRgDKiY8mJo+1Lii2TiKh+AYGnnK8hBEHCFbrxZ18x5hTniSrbznY6Dx6cbvCfKzK7HH3S/QKWC3U42+nu1EkmlkwE9s4ZKntpj1QJ6WDbtUuComJpwvbZ94xWrsMG6EIcjxEPlcX2csL5WCGjSSB61J9bcDex1kLEba1RwcvOFpmpY4wFx3hJ7m2Zt9dvLNYd+4Nfkx6Ggt9aYS1HQ2N7Htb9aGrlvajE30sDYIf6WxweNlrzebI+10T40PBTuo6b2j3Joky0UNDUn4fL8UWQ/ajtbs/obhUqMUjfhayI= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(376002)(346002)(136003)(396003)(39860400002)(451199021)(1800799003)(186006)(90011799007)(90021799007)(82310400008)(40470700004)(36840700001)(46966006)(40480700001)(316002)(36860700001)(47076005)(426003)(40460700003)(2616005)(2906002)(82740400003)(356005)(81166007)(36756003)(16526019)(336012)(8936002)(8676002)(26005)(1076003)(5660300002)(7696005)(41300700001)(70586007)(4326008)(70206006)(6636002)(478600001)(54906003)(110136005)(86362001)(15583001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2023 08:11:04.3718 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0970465-1843-47ad-0c82-08db97e702e9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7089 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add support for getting the highest performance to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values. Signed-off-by: Meng Li Reviewed-by: Mario Limonciello --- drivers/acpi/cppc_acpi.c | 13 +++++++++++++ include/acpi/cppc_acpi.h | 5 +++++ 2 files changed, 18 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 7ff269a78c20..ad388a0e8484 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1154,6 +1154,19 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); } +/** + * cppc_get_highest_perf - Get the highest performance register value. + * @cpunum: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_highest_perf(int cpunum, u64 *highest_perf) +{ + return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_highest_perf); + /** * cppc_get_epp_perf - Get the epp register value. * @cpunum: CPU from which to get epp preference value. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 6126c977ece0..c0b69ffe7bdb 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -139,6 +139,7 @@ struct cppc_cpudata { #ifdef CONFIG_ACPI_CPPC_LIB extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); +extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_enable(int cpu, bool enable); @@ -165,6 +166,10 @@ static inline int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) { return -ENOTSUPP; } +static inline int cppc_get_highest_perf(int cpunum, u64 *highest_perf) +{ + return -ENOTSUPP; +} static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs) { return -ENOTSUPP; From patchwork Tue Aug 8 08:09:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li \(Jassmine\)" X-Patchwork-Id: 712227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAFACC41513 for ; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V1 2/6] cpufreq: amd-pstate: Enable AMD Pstate Preferred Core Supporting. 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We call it AMD Pstate Preferrred Core. Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. AMD Pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority. The initial core rankings are set up by AMD Pstate when the system boots. Add device attribute for preferred core states. Add one new early parameter `enable` to allow user to enable the preferred core if the processor and power firmware can support preferred core feature. Signed-off-by: Meng Li Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 149 +++++++++++++++++++++++++++++++---- 1 file changed, 133 insertions(+), 16 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..e919b3f4ab18 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,8 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 +#define AMD_PSTATE_MAX_CPPC_PERF 255 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -65,6 +68,14 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; +/* + * CPPC Preferred Core feature is supported by power firmware + */ +static bool prefcore_enabled = false; + +/* Disable AMD Pstate Preferred Core loading */ +static bool no_prefcore __read_mostly = true; + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -290,23 +301,21 @@ static inline int amd_pstate_enable(bool enable) static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; - u32 highest_perf; int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; - /* - * TODO: Introduce AMD specific power feature. - * - * CPPC entry doesn't indicate the highest performance in some ASICs. + /* For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as + * the default max perf. */ - highest_perf = amd_get_highest_perf(); - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (!prefcore_enabled) + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + else + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +327,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) static int cppc_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; - u32 highest_perf; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - highest_perf = amd_get_highest_perf(); - if (highest_perf > cppc_perf.highest_perf) - highest_perf = cppc_perf.highest_perf; - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (!prefcore_enabled) + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); + else + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); WRITE_ONCE(cpudata->lowest_nonlinear_perf, @@ -676,6 +683,90 @@ static void amd_perf_ctl_reset(unsigned int cpu) wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } +/* + * Set AMD Pstate Preferred Core enable can't be done directly from cpufreq callbacks + * due to locking, so queue the work for later. + */ +static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); + +/** + * Get the highest performance register value. + * @cpu: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +static int amd_pstate_get_highest_perf(int cpu, u64 *highest_perf) +{ + int ret; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 cap1; + + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + } else { + ret = cppc_get_highest_perf(cpu, highest_perf); + } + + return (ret); +} + +static void amd_pstate_init_prefcore(void) +{ + int cpu, ret; + u64 highest_perf; + + if (no_prefcore) + return; + + for_each_possible_cpu(cpu) { + ret = amd_pstate_get_highest_perf(cpu, &highest_perf); + if (ret) + break; + + sched_set_itmt_core_prio(highest_perf, cpu); + } + + /* + * This code can be run during CPU online under the + * CPU hotplug locks, so sched_set_amd_prefcore_support() + * cannot be called from here. Queue up a work item + * to invoke it. + */ + schedule_work(&sched_prefcore_work); +} + +/* + * Check if AMD Pstate Preferred core feature is supported and enabled + * 1) no_prefcore is used to enable or disable AMD Pstate Preferred Core + * loading when user would like to enable or disable it. Without that, + * AMD Pstate Preferred Core will be disabled by default if the processor + * and power firmware can support preferred core feature. + * 2) prefcore_enabled is used to indicate whether CPPC preferred core is enabled. + */ +static void check_prefcore_supported(int cpu) +{ + u64 highest_perf; + int ret; + + if (no_prefcore) + return; + + ret = amd_pstate_get_highest_perf(cpu, &highest_perf); + if (ret) + return; + + if(highest_perf < AMD_PSTATE_MAX_CPPC_PERF) + prefcore_enabled = true; +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -697,6 +788,9 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; + /* check if CPPC preferred core feature is enabled*/ + check_prefcore_supported(policy->cpu); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1037,6 +1131,12 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, return ret < 0 ? ret : count; } +static ssize_t prefcore_state_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%s\n", prefcore_enabled ? "enabled" : "disabled"); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -1044,6 +1144,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); +static DEVICE_ATTR_RO(prefcore_state); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -1063,6 +1164,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, + &dev_attr_prefcore_state.attr, NULL }; @@ -1114,6 +1216,9 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; cpudata->epp_policy = 0; + /* check if CPPC preferred core feature is supported*/ + check_prefcore_supported(policy->cpu); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1506,6 +1611,8 @@ static int __init amd_pstate_init(void) } } + amd_pstate_init_prefcore(); + return ret; global_attr_free: @@ -1527,7 +1634,17 @@ static int __init amd_pstate_param(char *str) return amd_pstate_set_driver(mode_idx); } + +static int __init amd_prefcore_param(char *str) +{ + if (!strcmp(str, "enable")) + no_prefcore = false; + + return 0; +} + early_param("amd_pstate", amd_pstate_param); +early_param("amd_prefcore", amd_prefcore_param); MODULE_AUTHOR("Huang Rui "); MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); From patchwork Tue Aug 8 08:09:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li \(Jassmine\)" X-Patchwork-Id: 712228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCC00C001DB for ; Tue, 8 Aug 2023 16:58:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233782AbjHHQ6G (ORCPT ); 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000971E9.mail.protection.outlook.com (10.167.243.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6652.19 via Frontend Transport; Tue, 8 Aug 2023 08:11:08 +0000 Received: from jasmine-meng.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 8 Aug 2023 03:11:04 -0500 From: Meng Li To: "Rafael J . Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V1 3/6] cpufreq: Add a notification message that the highest perf has changed Date: Tue, 8 Aug 2023 16:09:58 +0800 Message-ID: <20230808081001.2215240-4-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808081001.2215240-1-li.meng@amd.com> References: <20230808081001.2215240-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E9:EE_|DM6PR12MB4297:EE_ X-MS-Office365-Filtering-Correlation-Id: 00895c46-dd95-418b-75d1-08db97e7059c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: f1mekc82Xxrn0f6Pi9ueUJ2MJEQxyfA51/Vunt8JGsPlMXehrh4MDiIV0UBNjcxZPb+EoLvS88lh+heHULl0MPXT6AblQTDCcOv2vxgByqprqbu3YGn0PKilKVW0U7YzbiSt7bec4l6AmhgAA2de4hGzv/yOIEgpb3jljAB12vtN7V5FKvVzsJFa80gjfS2Owzh82g2US6A9DxyNQu2u6XloSANBvxsUaP43pJU3W/ZNawLOnulYJFC2j5JXwrlwTGFH46H3AGlSyDoyiT5lPJwWDXbjexzHlBOO2QaGjeyEVkZoUzwGPpU0iDjnvx73DT5pkLqgeSsdT+biwD5qDjP4LXXTki8Vsaj9hWf2ztK+kTNiqUuSbB6tnrHXvb42UtinWfi0spx4UWxTrXF6fmmUPNGUHh6y2dwgNgekPu8Bb3XttbT2oertaeA9J5/P4PQck8E+YxOsYm5Bfup7rQmalHC6YptD6205YC9RhkG7SgsnfPQLBcOmHwjBGAY7j7QtGM5XtmumFmzEfniuNFR6yITOIyQg0+B/1eyMOkNSXkjQOV0wQ5tPfl3ydY9YFgS+PsALNe26oeFUuVXsF0/+9piQrduAxQU2qovM4NO9fsaX2HZL3PM0kKfzkn2KEr8+zdZTJSiMZn1mkwfOwWnvvwAaCwiI/mYoCN8gUzUxfjeGSy8pFPKesBH2oZhxn/uIkJRWvzZMeMnlmdZJ7pAZDUb9qaa7UtdsevV35sAASqoSulI0/PjKT+5zh6vZJT2oKM3r1he3hnIZ28qyedBE1WkXZUjSMww0dSNLbnFO80WDrLr+qimNmooS4J6d/9J8kyL9bIZLPqBjNSwR0EnXYRMQgWufw07oAKKBHkg= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(136003)(346002)(39860400002)(396003)(376002)(90011799007)(186006)(1800799003)(82310400008)(451199021)(90021799007)(36840700001)(40470700004)(46966006)(8676002)(110136005)(4326008)(41300700001)(8936002)(40480700001)(70206006)(70586007)(54906003)(36756003)(6636002)(5660300002)(15650500001)(316002)(40460700003)(81166007)(36860700001)(356005)(478600001)(7696005)(6666004)(966005)(2906002)(16526019)(83380400001)(336012)(86362001)(26005)(1076003)(82740400003)(47076005)(426003)(2616005)(226483002)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2023 08:11:08.9030 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00895c46-dd95-418b-75d1-08db97e7059c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4297 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Please refer to the ACPI_Spec for details on the highest performance and notify events of CPPC. Signed-off-by: Meng Li Link: https://uefi.org/htmlspecs/AddCPI_Spec_6_4_html/08_Processor_Configuration_and_Control/declaring-processors.html?highlight=0x85#highest-performance --- drivers/acpi/processor_driver.c | 6 ++++++ drivers/cpufreq/cpufreq.c | 13 +++++++++++++ include/linux/cpufreq.h | 4 ++++ 3 files changed, 23 insertions(+) diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c index 4bd16b3f0781..29b2fb68a35d 100644 --- a/drivers/acpi/processor_driver.c +++ b/drivers/acpi/processor_driver.c @@ -27,6 +27,7 @@ #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80 #define ACPI_PROCESSOR_NOTIFY_POWER 0x81 #define ACPI_PROCESSOR_NOTIFY_THROTTLING 0x82 +#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED 0x85 MODULE_AUTHOR("Paul Diefenbaugh"); MODULE_DESCRIPTION("ACPI Processor Driver"); @@ -83,6 +84,11 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data) acpi_bus_generate_netlink_event(device->pnp.device_class, dev_name(&device->dev), event, 0); break; + case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED: + cpufreq_update_highest_perf(pr->id); + acpi_bus_generate_netlink_event(device->pnp.device_class, + dev_name(&device->dev), event, 0); + break; default: acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event); break; diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 50bbc969ffe5..842357abfae6 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2675,6 +2675,19 @@ void cpufreq_update_limits(unsigned int cpu) } EXPORT_SYMBOL_GPL(cpufreq_update_limits); +/** + * cpufreq_update_highest_perf - Update highest performance for a given CPU. + * @cpu: CPU to update the highest performance for. + * + * Invoke the driver's ->update_highest_perf callback if present + */ +void cpufreq_update_highest_perf(unsigned int cpu) +{ + if (cpufreq_driver->update_highest_perf) + cpufreq_driver->update_highest_perf(cpu); +} +EXPORT_SYMBOL_GPL(cpufreq_update_highest_perf); + /********************************************************************* * BOOST * *********************************************************************/ diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 172ff51c1b2a..766c83a4fae7 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -231,6 +231,7 @@ int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu); void refresh_frequency_limits(struct cpufreq_policy *policy); void cpufreq_update_policy(unsigned int cpu); void cpufreq_update_limits(unsigned int cpu); +void cpufreq_update_highest_perf(unsigned int cpu); bool have_governor_per_policy(void); bool cpufreq_supports_freq_invariance(void); struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy); @@ -376,6 +377,9 @@ struct cpufreq_driver { /* Called to update policy limits on firmware notifications. */ void (*update_limits)(unsigned int cpu); + /* Called to update highest performance on firmware notifications. */ + void (*update_highest_perf)(unsigned int cpu); + /* optional */ int (*bios_limit)(int cpu, unsigned int *limit); From patchwork Tue Aug 8 08:09:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li \(Jassmine\)" X-Patchwork-Id: 711823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2B41C04A6A for ; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V1 4/6] cpufreq: amd-pstate: Update AMD Pstate Preferred Core ranking dynamically Date: Tue, 8 Aug 2023 16:09:59 +0800 Message-ID: <20230808081001.2215240-5-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808081001.2215240-1-li.meng@amd.com> References: <20230808081001.2215240-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E9:EE_|LV8PR12MB9153:EE_ X-MS-Office365-Filtering-Correlation-Id: c50d111a-7258-48bf-ac87-08db97e70940 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: yhFQrvrMw8IJY33pm1gcio0kEVhLSu44pHdVsTY3cq2cz8D6HO2YxCFITlcI7f1+LgjpQX49ylod6paUqqrtw0091EDDJ+rYqx3Wu3ijBYo+fkMXHm1ImhJR1bCJDZyCRFAXoATB9vJT1ryU0ZZQgtcwj7huiR7wi7t3rn42ufuRts9IvUxBuTmhWL+M4KGLdagY0qwhJzMouEZqTPIW3+y9uYMbxmgVVE+sCobrWf7KFnQuR9KQyl8SHNDHCk7nLYFK7QLg39AIj7SH+aMFfRguWWkIxAp7Q1Iu+NlXr5QfHezEwIn1Z9z9v/pLiEetB2B/0ToaRfNMaEykTdWIKpy4yeJg8iBxh/G4kfnFGO+ETPOT+/SMl0H71oTEU0RJVCZ12zbVW6f+ldZ9flQG0qC4VEqOKNgh9rzqqtsF5ZqdZAc/h1fCKE6ErPPKDgtANroeyiUUScDmclYjddUeKFfdT2nBjoruVN03ACPZOEKF8O39l7uUASozv0idr6Oj04DvLXV1fdvucigdBp9hQUaGMc5VKELuBlTMdqcnyk9zW5nHvtmqBOTZOxKuEp38hVi9L5MMaVtTh7as7oG372xaTBZhdfJYxYH8r2TBHBqRDzlzANmuJKlHEpco26O5Ry3SG8gA9ZUr0lVPOL6wmIplO0GTD90xLcX807/GTO6KlBX8SYhdBl9ao4BHfNcLmu4ibK6ZnwfTtTm3stUtbBEOiYd0MEGliA+TyxqwUiGrbr7SphWcYftTeaIYqpTSDtcd7sfXxO/273lvDS/Wfs7CSdgxIEZiOIgHv9DS0OfmPijBR7mFoj0JM7tFNu9+h9BtdBNAnwbYE5RUoB6iFg== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(136003)(376002)(346002)(39860400002)(396003)(90021799007)(82310400008)(1800799003)(186006)(451199021)(90011799007)(46966006)(36840700001)(40470700004)(426003)(15650500001)(1076003)(41300700001)(26005)(2906002)(5660300002)(83380400001)(8676002)(36860700001)(47076005)(8936002)(16526019)(40460700003)(2616005)(40480700001)(336012)(81166007)(6636002)(316002)(82740400003)(7696005)(70206006)(110136005)(356005)(54906003)(478600001)(70586007)(6666004)(86362001)(4326008)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2023 08:11:15.0123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c50d111a-7258-48bf-ac87-08db97e70940 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9153 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Preferred core rankings can be changed dynamically by the platform based on the workload and platform conditions and accounting for thermals and aging. When this occurs, cpu priority need to be set. Signed-off-by: Meng Li --- drivers/cpufreq/amd-pstate.c | 32 ++++++++++++++++++++++++++++++++ include/linux/amd-pstate.h | 1 + 2 files changed, 33 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index e919b3f4ab18..ba10aa971dcb 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -320,6 +320,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); + WRITE_ONCE(cpudata->prefcore_highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); return 0; } @@ -341,6 +342,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->lowest_nonlinear_perf, cppc_perf.lowest_nonlinear_perf); WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); + WRITE_ONCE(cpudata->prefcore_highest_perf, cppc_perf.highest_perf); if (cppc_state == AMD_PSTATE_ACTIVE) return 0; @@ -743,6 +745,34 @@ static void amd_pstate_init_prefcore(void) schedule_work(&sched_prefcore_work); } +static void amd_pstate_update_highest_perf(unsigned int cpu) +{ + struct cpufreq_policy *policy; + struct amd_cpudata *cpudata; + u32 prev_high = 0, cur_high = 0; + u64 highest_perf; + int ret; + + if (!prefcore_enabled) + return; + + ret = amd_pstate_get_highest_perf(cpu, &highest_perf); + if (ret) + return; + + policy = cpufreq_cpu_get(cpu); + cpudata = policy->driver_data; + cur_high = highest_perf; + prev_high = READ_ONCE(cpudata->prefcore_highest_perf); + + if (prev_high != cur_high) { + WRITE_ONCE(cpudata->prefcore_highest_perf, cur_high); + sched_set_itmt_core_prio(cur_high, cpu); + } + + cpufreq_cpu_put(policy); +} + /* * Check if AMD Pstate Preferred core feature is supported and enabled * 1) no_prefcore is used to enable or disable AMD Pstate Preferred Core @@ -1497,6 +1527,7 @@ static struct cpufreq_driver amd_pstate_driver = { .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, .set_boost = amd_pstate_set_boost, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate", .attr = amd_pstate_attr, }; @@ -1511,6 +1542,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .online = amd_pstate_epp_cpu_online, .suspend = amd_pstate_epp_suspend, .resume = amd_pstate_epp_resume, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 446394f84606..fa86bc953d3e 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -70,6 +70,7 @@ struct amd_cpudata { u32 nominal_perf; u32 lowest_nonlinear_perf; u32 lowest_perf; + u32 prefcore_highest_perf; u32 max_freq; u32 min_freq; From patchwork Tue Aug 8 08:10:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li \(Jassmine\)" X-Patchwork-Id: 712230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32384C001DE for ; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V1 5/6] Documentation: amd-pstate: introduce AMD Pstate Preferred Core Date: Tue, 8 Aug 2023 16:10:00 +0800 Message-ID: <20230808081001.2215240-6-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808081001.2215240-1-li.meng@amd.com> References: <20230808081001.2215240-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E8:EE_|DS0PR12MB7850:EE_ X-MS-Office365-Filtering-Correlation-Id: e5a7daef-589a-476c-cb13-08db97e7169d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: IWb6XxjF625mNZLRF3t+HUs8Isfb387RRx8nm8QYO1UxjzusdxVMrp4AfLpKy9EPOIPsf8oVQvO3ZRV8ZXsenLY+DkW3BtLigx4H3Bz4/5a2npCeIJJDFgmIRxwfcdCHlo4e1xRkniclgmiUZvF72sR1HTzOfPC7rMGKSiJgjuvLWI8H+hWMc9AXUbpD9gqqbfmEMqCKIHWEQgqL1JgAQWH7CGtaLi/a5LAFhtc6qXmSNv64dxcn0+z3LuT5YlZuQKnvDyae3u0It8GLpD/x2RDphz8XTR4Ogol9/UG5UV0MMAJLLEnv0umbOpoUVm4Tjag1iv4iUjKOP0F8/t7TJ/nn2JqfWnN5Ak6xyskUuusuPnC2NnK/xSRZG/HuLO2ALagJgOH5uAs1QvU9pHIir/MsztwIZctuzniNqBDYYgTzTGe1Nfg1tB67GuWetrtG4X25aCSc+V3qJqumPNTQQ/gjTjyrtdG3tx8/pa3n8CVBzPGZ99ZU62T9do8bwMeDELisHRPAVR0DfbA1dziCQwPGiG8stx8wcFjwYAYajzAV3LGdmjM+PZfQAhrZnk8WVaBtOxa+OdQyfaRzS6p4FHyP9QrhJmICpmaSwEsM56mc7xs3SqaAa/8ozB2t3E5M260MBTM92JuJvssEbK1LaHzi7TBR525Ovg4vGUpvY+NcbujCADq/x3XZGqSRnrg/Ey9M8NvmINe9OOZSAcxdb1mSPQjDSpvEBbLfJncErzw2DHrOejXv3g2S3bJiVw/oPTm+9GRywka9TM1X9XtnTVLwVUoN3ZQoADlaeg1r9u0nWHXzaaVTUzR5t82cSA6OQ9rYUnixnkiMaJZSVMi5lA== X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(376002)(346002)(39860400002)(396003)(136003)(90021799007)(82310400008)(1800799003)(186006)(451199021)(90011799007)(46966006)(36840700001)(40470700004)(426003)(1076003)(41300700001)(26005)(2906002)(5660300002)(83380400001)(8676002)(36860700001)(47076005)(8936002)(16526019)(40460700003)(2616005)(40480700001)(336012)(81166007)(478600001)(316002)(7696005)(356005)(54906003)(70206006)(110136005)(70586007)(82740400003)(6666004)(6636002)(86362001)(4326008)(36756003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2023 08:11:37.4174 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5a7daef-589a-476c-cb13-08db97e7169d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7850 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Introduce AMD Pstate Preferred Core. check preferred core state: $ cat /sys/devices/system/cpu/amd-pstate/prefcore_state Signed-off-by: Meng Li --- Documentation/admin-guide/pm/amd-pstate.rst | 55 +++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1cf40f69278c..4a30cf235425 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -353,6 +353,49 @@ is activated. In this mode, driver requests minimum and maximum performance level and the platform autonomously selects a performance level in this range and appropriate to the current workload. +AMD Pstate Preferred Core +================================= + +The core frequency is subjected to the process variation in semiconductors. +Not all cores are able to reach the maximum frequency respecting the +infrastructure limits. Consequently, AMD has redefined the concept of +maximum frequency of a part. This means that a fraction of cores can reach +maximum frequency. To find the best process scheduling policy for a given +scenario, OS needs to know the core ordering informed by the platform through +highest performance capability register of the CPPC interface. + +``AMD Pstate Preferred Core`` use ITMT arch provides functions and data structures +for enabling the scheduler to favor scheduling on cores can be get a higher frequency +with lower voltage under preferred core. And it has the ability to dynamically +change the preferred core based on the workload and platform conditions and +accounting for thermals and aging. + +The priority metric will be initialized by the AMD Pstate driver. The AMD Pstate +driver will also determine whether or not ``AMD Pstate Preferred Core`` is +supported by the platform. + +AMD Pstate driver will provide an initial core ordering when the system boots. +The platform uses the CPPC interfaces to communicate the core ranking to the +operating system and scheduler to make sure that OS is choosing the cores +with highest performance firstly for scheduling the process. When AMD Pstate +driver receives a message with the highest performance change, it will +update the core ranking and set the cpu's priority. + +AMD Preferred Core Switch +================================= +Kernel Parameters +----------------- + +``AMD Pstate Preferred Core`` has two states: enable and disable. +Enable/disable states can be chosen by different kernel parameters. +Default disable ``AMD Pstate Preferred Core``. + +``amd_prefcore=enable`` + +If ``amd_prefcore=enable`` is passed to kernel command line option +then enable ``AMD Pstate Preferred Core`` if the processor and power +firmware can support preferred core feature. + User Space Interface in ``sysfs`` - General =========================================== @@ -385,6 +428,18 @@ control its functionality at the system level. They are located in the to the operation mode represented by that string - or to be unregistered in the "disable" case. +``prefcore_state`` + Preferred Core state of the driver: "enabled" or "disabled". + + "enabled" + Enable the AMD Preferred Core. + + "disabled" + Disable the AMD Preferred Core + + + This attribute is read-only to check the state of Preferred Core. + ``cpupower`` tool support for ``amd-pstate`` =============================================== From patchwork Tue Aug 8 08:10:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Meng, Li \(Jassmine\)" X-Patchwork-Id: 711826 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EA5AC41513 for ; Tue, 8 Aug 2023 16:21:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230155AbjHHQUw (ORCPT ); Tue, 8 Aug 2023 12:20:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231229AbjHHQT3 (ORCPT ); Tue, 8 Aug 2023 12:19:29 -0400 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2070.outbound.protection.outlook.com [40.107.101.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59CEF900E; Tue, 8 Aug 2023 08:48:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jJZh0sAxNNQT2xSe9z2Z4pxhf3JBVInAWHuHYhhaVoaxh/5NPM5xZrEtW0kIVZwaW7dkuowD1a8PA2fw79oeuYF6YGXfqG/2tx6xbU02LzMqxIahi65sV3JP4bYpwgZWBJY5ab7QRwTNdR8CQhyF2PR7r3ZsS/2iGRL7gKg3iUAZ/659FvL+QT3igjd5h5xWriZvyIekCWPXpA9VIABe6S+VtCJG66aFG/llUxA7sOIQnc4+lmUh6a6jHZ8F4Qw6M3O3eRHZbXprItE7Y1jtihhPy8dlD4bo4A17iP3GASsI3oduoe8HiWi1wL73vEhYBISaPlYXl7IlKvRFvf0Jvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=esVSysetGhzh6t5ORSQSSD6Oz46VS/5ZRsXchN81E0w=; b=ZtiW7nPpIeJ1tTeUF/fFg1LQ35lPiSY1mitqay5vtkynRC/dHmMITZU0ReCLHntCtlx4SPJ55ne6WmjsleY1WgSM37qZr6KbfJnNays/3hWM7pn/BdsXssm6nvdC8Qqpo4ZQfkzhw179ZpiMIwbH3TfXG/h7WlPhVKQ7lnTKJNu/lelFycKJVM2vkVSYrttaotor0Buv6tMNHh2E13cZvaNXBx38g7RN2PHvJadIENP1xvXpp18Y9SkGYncPGIqMqjVPlnCjYuhcoAukrJ6c3pKUKtSuzxGE/GoxiRcDe8gIzeinLgy2Wswq+cuyfrvLhJSV44fFMGCE+E7vL0F3dA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=esVSysetGhzh6t5ORSQSSD6Oz46VS/5ZRsXchN81E0w=; b=xqCQuWvyoG19yc6iCvifNAFK1NXDzqMwGq9GmrGBr/jTFhlWoHmvigs7Bu7+ygEwoHxZAXV5pP6DmVmVQChs1uBkjdrhpKF7u7nOUyrbo4ad9qk6KXdq3XG+FaU6rOjgrzf1xa+vXDBjoWRA0CzlayXqq9mAXF1htiRD69hhc4E= Received: from MW4PR04CA0344.namprd04.prod.outlook.com (2603:10b6:303:8a::19) by DM3PR12MB9325.namprd12.prod.outlook.com (2603:10b6:0:46::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6652.27; Tue, 8 Aug 2023 08:12:37 +0000 Received: from MWH0EPF000971E9.namprd02.prod.outlook.com (2603:10b6:303:8a:cafe::9a) by MW4PR04CA0344.outlook.office365.com (2603:10b6:303:8a::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6652.27 via Frontend Transport; Tue, 8 Aug 2023 08:12:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000971E9.mail.protection.outlook.com (10.167.243.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6652.19 via Frontend Transport; Tue, 8 Aug 2023 08:12:37 +0000 Received: from jasmine-meng.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 8 Aug 2023 03:11:35 -0500 From: Meng Li To: "Rafael J . Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , Meng Li Subject: [PATCH V1 6/6] Documentation: introduce AMD Pstate Preferrd Core mode kernel command line options Date: Tue, 8 Aug 2023 16:10:01 +0800 Message-ID: <20230808081001.2215240-7-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808081001.2215240-1-li.meng@amd.com> References: <20230808081001.2215240-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000971E9:EE_|DM3PR12MB9325:EE_ X-MS-Office365-Filtering-Correlation-Id: 71c336c2-ae13-403f-0fa0-08db97e73a3b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: bGGRQABzEAOEQ5DAoStKk2a3nrUY92wyQ+Zvh+Gm88Flku/3tClT7AGEDWckV9FeTswTKN2nNPsEixVKbbVZwdM1p2pOpt2LauezIwoFCzHl8HjPhO5PcUIIvmh829wHGazwNncgGI/Ry4s0eZP/6GmDwhmGW+MZ5TrGtUEhgwAkbTcjnGEDWAZyI15XRe2vWxSzMX7CLfFWUHtVK+NnpWEQlZ3s9NCwHKddD0MQXiUtH8qvtauXSU/4dc0te/dXzGz4x72HkfojZM5J39dxHXfHEcndLw7C1BJNL6K5gYcwomWfVtR7smcyab75LPAelDInjWJY5giKnp1pAHNVjLsurJTZBwVxVAUDsNBFLhpK/WXHmPOAegbUzhWy6+ck6Hp0S3KCGLFqBXXfyCs7Bv22t+5sRqbKZUvoHbsw6T3VJjf33PbR1MU9AenktGt0RNSDuXRRCRZiaJYd32/wrGf/Zf8zTcCIn9dodU7lmR3DsRSHE9DXX2o+qTWetevTngxnZTsTZe5P15fZmLYwcuZHI3KfAm44SgSI4P54xYdYhe5/tyrLPvszMu6Ezz6F3L30t8wNBfmdW9H0tWhabRSuK1QdFfEIc3n9Rym1XkySITyBdg2NpYxkumzwddKtnqM1cchGMIfQtOuFkKUe8qW40Ta9cOx/Ox3HHnbM8JIYYW9pgyntB8C6CU9+acAVsyV5jSkLfJCPzPU2f4aHVpABIpB6lO9FKG23WVUbbXx2jv8eSBY4iAfQ9lDlcz1M5tFzUkTZj+B4oMLDwsNGnoqo0p8PoTj8XBiLyvougqFowkjrbZ69/rD65bFCSzplB62VHaA0IZRpGMezZpplJ0IcHgP7QHm2W7mUfMqbcxBpGKs4pYvP7uM3cUU3eYYO X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230028)(4636009)(136003)(39860400002)(396003)(346002)(376002)(82310400008)(1800799003)(186006)(90021799007)(451199021)(90011799007)(46966006)(40470700004)(36840700001)(2616005)(7696005)(1076003)(26005)(36756003)(16526019)(336012)(6666004)(82740400003)(478600001)(81166007)(356005)(110136005)(54906003)(70586007)(70206006)(6636002)(4326008)(41300700001)(426003)(316002)(8936002)(8676002)(5660300002)(40460700003)(4744005)(2906002)(36860700001)(83380400001)(47076005)(86362001)(40480700001)(36900700001)(14943795004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2023 08:12:37.1527 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71c336c2-ae13-403f-0fa0-08db97e73a3b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9325 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org AMD Pstate driver support enable/disable Preferred core. Default disabled on platforms supporting AMD Preferred Core. Enable AMD Pstate Preferred Core with "amd_prefcore=enable" added to the kernel command line. Signed-off-by: Meng Li --- Documentation/admin-guide/kernel-parameters.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 2de235d52fac..bc92e178431b 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -363,6 +363,11 @@ selects a performance level in this range and appropriate to the current workload. + amd_prefcore= + [X86] + enable + Enable AMD Pstate Preferred Core. + amijoy.map= [HW,JOY] Amiga joystick support Map of devices attached to JOY0DAT and JOY1DAT Format: ,