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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 01/24] tcg: Introduce negsetcond opcodes Date: Mon, 7 Aug 2023 20:11:20 -0700 Message-Id: <20230808031143.50925-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce a new opcode for negative setcond. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- docs/devel/tcg-ops.rst | 6 ++++++ include/tcg/tcg-op-common.h | 4 ++++ include/tcg/tcg-op.h | 2 ++ include/tcg/tcg-opc.h | 2 ++ include/tcg/tcg.h | 1 + tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 1 + tcg/i386/tcg-target.h | 2 ++ tcg/loongarch64/tcg-target.h | 3 +++ tcg/mips/tcg-target.h | 2 ++ tcg/ppc/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 2 ++ tcg/s390x/tcg-target.h | 2 ++ tcg/sparc64/tcg-target.h | 2 ++ tcg/tci/tcg-target.h | 2 ++ tcg/optimize.c | 41 +++++++++++++++++++++++++++++++++++- tcg/tcg-op.c | 36 +++++++++++++++++++++++++++++++ tcg/tcg.c | 6 ++++++ 18 files changed, 117 insertions(+), 1 deletion(-) diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 6a166c5665..fbde8040d7 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -498,6 +498,12 @@ Conditional moves | | Set *dest* to 1 if (*t1* *cond* *t2*) is true, otherwise set to 0. + * - negsetcond_i32/i64 *dest*, *t1*, *t2*, *cond* + + - | *dest* = -(*t1* *cond* *t2*) + | + | Set *dest* to -1 if (*t1* *cond* *t2*) is true, otherwise set to 0. + * - movcond_i32/i64 *dest*, *c1*, *c2*, *v1*, *v2*, *cond* - | *dest* = (*c1* *cond* *c2* ? *v1* : *v2*) diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index be382bbf77..a53b15933b 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -344,6 +344,8 @@ void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret, + TCGv_i32 arg1, TCGv_i32 arg2); void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, @@ -540,6 +542,8 @@ void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret, + TCGv_i64 arg1, TCGv_i64 arg2); void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index d63683c47b..80cfcf8104 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -200,6 +200,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 #define tcg_gen_setcond_tl tcg_gen_setcond_i64 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 +#define tcg_gen_negsetcond_tl tcg_gen_negsetcond_i64 #define tcg_gen_mul_tl tcg_gen_mul_i64 #define tcg_gen_muli_tl tcg_gen_muli_i64 #define tcg_gen_div_tl tcg_gen_div_i64 @@ -317,6 +318,7 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 #define tcg_gen_setcond_tl tcg_gen_setcond_i32 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 +#define tcg_gen_negsetcond_tl tcg_gen_negsetcond_i32 #define tcg_gen_mul_tl tcg_gen_mul_i32 #define tcg_gen_muli_tl tcg_gen_muli_i32 #define tcg_gen_div_tl tcg_gen_div_i32 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index acfa5ba753..5044814d15 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -46,6 +46,7 @@ DEF(mb, 0, 0, 1, 0) DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) DEF(setcond_i32, 1, 2, 1, 0) +DEF(negsetcond_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_negsetcond_i32)) DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32)) /* load/store */ DEF(ld8u_i32, 1, 1, 1, 0) @@ -111,6 +112,7 @@ DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32)) DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) DEF(setcond_i64, 1, 2, 1, IMPL64) +DEF(negsetcond_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_negsetcond_i64)) DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64)) /* load/store */ DEF(ld8u_i64, 1, 1, 1, IMPL64) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 0875971719..f00bff9c85 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -104,6 +104,7 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 0 /* Turn some undef macros into true macros. */ #define TCG_TARGET_HAS_add2_i32 1 #define TCG_TARGET_HAS_sub2_i32 1 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index ce64de06e5..6080fddf73 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -94,6 +94,7 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_div_i64 1 @@ -129,6 +130,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 +#define TCG_TARGET_HAS_negsetcond_i64 0 /* * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load, diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index c649db72a6..b076d033a9 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -122,6 +122,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_div_i32 use_idiv_instructions #define TCG_TARGET_HAS_rem_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 2a2e3fffa8..41df0e5ae1 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -156,6 +156,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 0 #if TCG_TARGET_REG_BITS == 64 /* Keep 32-bit values zero-extended in a register. */ @@ -193,6 +194,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 #else #define TCG_TARGET_HAS_qemu_st8_i32 1 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 26f1aab780..ce8fa3507e 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -118,6 +118,7 @@ typedef enum { #define TCG_TARGET_HAS_ctpop_i32 0 #define TCG_TARGET_HAS_brcond2 0 #define TCG_TARGET_HAS_setcond2 0 +#define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 /* 64-bit operations */ @@ -157,6 +158,8 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 +#define TCG_TARGET_HAS_negsetcond_i64 0 + #define TCG_TARGET_HAS_qemu_ldst_i128 0 #define TCG_TARGET_DEFAULT_MO (0) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index dd2efa795c..68e6cc33cc 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -128,6 +128,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 +#define TCG_TARGET_HAS_negsetcond_i32 0 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 @@ -150,6 +151,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_mulsh_i64 1 #define TCG_TARGET_HAS_ext32s_i64 1 #define TCG_TARGET_HAS_ext32u_i64 1 +#define TCG_TARGET_HAS_negsetcond_i64 0 #endif /* optional instructions detected at runtime */ diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 9a41fab8cc..ba4fd3eb3a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -101,6 +101,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 +#define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 @@ -141,6 +142,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 +#define TCG_TARGET_HAS_negsetcond_i64 0 #endif #define TCG_TARGET_HAS_qemu_ldst_i128 \ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index e1d8110ee4..b2961fec8e 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -120,6 +120,7 @@ extern bool have_zbb; #define TCG_TARGET_HAS_ctpop_i32 have_zbb #define TCG_TARGET_HAS_brcond2 1 #define TCG_TARGET_HAS_setcond2 1 +#define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_movcond_i64 1 @@ -158,6 +159,7 @@ extern bool have_zbb; #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 +#define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 9a405003b9..24e207c2d4 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -104,6 +104,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_div2_i64 1 @@ -138,6 +139,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_muls2_i64 HAVE_FACILITY(MISC_INSN_EXT2) #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_qemu_ldst_i128 1 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index d454278811..1faadc704b 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -112,6 +112,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_extrl_i64_i32 1 @@ -149,6 +150,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 use_vis3_instructions #define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 0 #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 37ee10c959..ca18ddaaad 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -73,6 +73,7 @@ #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 @@ -114,6 +115,7 @@ #define TCG_TARGET_HAS_mulu2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 0 #else #define TCG_TARGET_HAS_mulu2_i32 1 #endif /* TCG_TARGET_REG_BITS == 64 */ diff --git a/tcg/optimize.c b/tcg/optimize.c index d2156367a3..0b4590ec7a 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -1530,14 +1530,22 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) if (arg_is_const(op->args[3]) && arg_is_const(op->args[4])) { uint64_t tv = arg_info(op->args[3])->val; uint64_t fv = arg_info(op->args[4])->val; - TCGOpcode opc; + TCGOpcode opc, negopc = 0; switch (ctx->type) { case TCG_TYPE_I32: opc = INDEX_op_setcond_i32; + if (TCG_TARGET_HAS_negsetcond_i32) { + negopc = INDEX_op_negsetcond_i32; + } + tv = (int32_t)tv; + fv = (int32_t)fv; break; case TCG_TYPE_I64: opc = INDEX_op_setcond_i64; + if (TCG_TARGET_HAS_negsetcond_i64) { + negopc = INDEX_op_negsetcond_i64; + } break; default: g_assert_not_reached(); @@ -1549,6 +1557,14 @@ static bool fold_movcond(OptContext *ctx, TCGOp *op) } else if (fv == 1 && tv == 0) { op->opc = opc; op->args[3] = tcg_invert_cond(cond); + } else if (negopc) { + if (tv == -1 && fv == 0) { + op->opc = negopc; + op->args[3] = cond; + } else if (fv == -1 && tv == 0) { + op->opc = negopc; + op->args[3] = tcg_invert_cond(cond); + } } } return false; @@ -1759,6 +1775,26 @@ static bool fold_setcond(OptContext *ctx, TCGOp *op) return false; } +static bool fold_negsetcond(OptContext *ctx, TCGOp *op) +{ + TCGCond cond = op->args[3]; + int i; + + if (swap_commutative(op->args[0], &op->args[1], &op->args[2])) { + op->args[3] = cond = tcg_swap_cond(cond); + } + + i = do_constant_folding_cond(ctx->type, op->args[1], op->args[2], cond); + if (i >= 0) { + return tcg_opt_gen_movi(ctx, op, op->args[0], -i); + } + + /* Value is {0,-1} so all bits are repititions of the sign. */ + ctx->s_mask = -1; + return false; +} + + static bool fold_setcond2(OptContext *ctx, TCGOp *op) { TCGCond cond = op->args[5]; @@ -2216,6 +2252,9 @@ void tcg_optimize(TCGContext *s) CASE_OP_32_64(setcond): done = fold_setcond(&ctx, op); break; + CASE_OP_32_64(negsetcond): + done = fold_negsetcond(&ctx, op); + break; case INDEX_op_setcond2_i32: done = fold_setcond2(&ctx, op); break; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7aadb37756..76d2377669 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -276,6 +276,21 @@ void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, tcg_gen_setcond_i32(cond, ret, arg1, tcg_constant_i32(arg2)); } +void tcg_gen_negsetcond_i32(TCGCond cond, TCGv_i32 ret, + TCGv_i32 arg1, TCGv_i32 arg2) +{ + if (cond == TCG_COND_ALWAYS) { + tcg_gen_movi_i32(ret, -1); + } else if (cond == TCG_COND_NEVER) { + tcg_gen_movi_i32(ret, 0); + } else if (TCG_TARGET_HAS_negsetcond_i32) { + tcg_gen_op4i_i32(INDEX_op_negsetcond_i32, ret, arg1, arg2, cond); + } else { + tcg_gen_setcond_i32(cond, ret, arg1, arg2); + tcg_gen_neg_i32(ret, ret); + } +} + void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { if (arg2 == 0) { @@ -1567,6 +1582,27 @@ void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, } } +void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret, + TCGv_i64 arg1, TCGv_i64 arg2) +{ + if (cond == TCG_COND_ALWAYS) { + tcg_gen_movi_i64(ret, -1); + } else if (cond == TCG_COND_NEVER) { + tcg_gen_movi_i64(ret, 0); + } else if (TCG_TARGET_HAS_negsetcond_i64) { + tcg_gen_op4i_i64(INDEX_op_negsetcond_i64, ret, arg1, arg2, cond); + } else if (TCG_TARGET_REG_BITS == 32) { + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, TCGV_LOW(ret), + TCGV_LOW(arg1), TCGV_HIGH(arg1), + TCGV_LOW(arg2), TCGV_HIGH(arg2), cond); + tcg_gen_neg_i32(TCGV_LOW(ret), TCGV_LOW(ret)); + tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_LOW(ret)); + } else { + tcg_gen_setcond_i64(cond, ret, arg1, arg2); + tcg_gen_neg_i64(ret, ret); + } +} + void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { if (arg2 == 0) { diff --git a/tcg/tcg.c b/tcg/tcg.c index ddfe9a96cb..b7f8f007ca 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1879,6 +1879,8 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_sar_i32: return true; + case INDEX_op_negsetcond_i32: + return TCG_TARGET_HAS_negsetcond_i32; case INDEX_op_movcond_i32: return TCG_TARGET_HAS_movcond_i32; case INDEX_op_div_i32: @@ -1977,6 +1979,8 @@ bool tcg_op_supported(TCGOpcode op) case INDEX_op_extu_i32_i64: return TCG_TARGET_REG_BITS == 64; + case INDEX_op_negsetcond_i64: + return TCG_TARGET_HAS_negsetcond_i64; case INDEX_op_movcond_i64: return TCG_TARGET_HAS_movcond_i64; case INDEX_op_div_i64: @@ -2510,11 +2514,13 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) switch (c) { case INDEX_op_brcond_i32: case INDEX_op_setcond_i32: + case INDEX_op_negsetcond_i32: case INDEX_op_movcond_i32: case INDEX_op_brcond2_i32: case INDEX_op_setcond2_i32: case INDEX_op_brcond_i64: case INDEX_op_setcond_i64: + case INDEX_op_negsetcond_i64: case INDEX_op_movcond_i64: case INDEX_op_cmp_vec: case INDEX_op_cmpsel_vec: From patchwork Tue Aug 8 03:11:21 2023 Content-Type: text/plain; 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 02/24] tcg: Use tcg_gen_negsetcond_* Date: Mon, 7 Aug 2023 20:11:21 -0700 Message-Id: <20230808031143.50925-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/tcg-op-gvec.c | 6 ++---- tcg/tcg-op.c | 6 ++---- 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index a062239804..e260a07c61 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -3692,8 +3692,7 @@ static void expand_cmp_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs, for (i = 0; i < oprsz; i += 4) { tcg_gen_ld_i32(t0, cpu_env, aofs + i); tcg_gen_ld_i32(t1, cpu_env, bofs + i); - tcg_gen_setcond_i32(cond, t0, t0, t1); - tcg_gen_neg_i32(t0, t0); + tcg_gen_negsetcond_i32(cond, t0, t0, t1); tcg_gen_st_i32(t0, cpu_env, dofs + i); } tcg_temp_free_i32(t1); @@ -3710,8 +3709,7 @@ static void expand_cmp_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs, for (i = 0; i < oprsz; i += 8) { tcg_gen_ld_i64(t0, cpu_env, aofs + i); tcg_gen_ld_i64(t1, cpu_env, bofs + i); - tcg_gen_setcond_i64(cond, t0, t0, t1); - tcg_gen_neg_i64(t0, t0); + tcg_gen_negsetcond_i64(cond, t0, t0, t1); tcg_gen_st_i64(t0, cpu_env, dofs + i); } tcg_temp_free_i64(t1); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 76d2377669..b4f1f24cab 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -863,8 +863,7 @@ void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, } else { TCGv_i32 t0 = tcg_temp_ebb_new_i32(); TCGv_i32 t1 = tcg_temp_ebb_new_i32(); - tcg_gen_setcond_i32(cond, t0, c1, c2); - tcg_gen_neg_i32(t0, t0); + tcg_gen_negsetcond_i32(cond, t0, c1, c2); tcg_gen_and_i32(t1, v1, t0); tcg_gen_andc_i32(ret, v2, t0); tcg_gen_or_i32(ret, ret, t1); @@ -2563,8 +2562,7 @@ void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, } else { TCGv_i64 t0 = tcg_temp_ebb_new_i64(); TCGv_i64 t1 = tcg_temp_ebb_new_i64(); - tcg_gen_setcond_i64(cond, t0, c1, c2); - tcg_gen_neg_i64(t0, t0); + tcg_gen_negsetcond_i64(cond, t0, c1, c2); tcg_gen_and_i64(t1, v1, t0); tcg_gen_andc_i64(ret, v2, t0); tcg_gen_or_i64(ret, ret, t1); From patchwork Tue Aug 8 03:11:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711557 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1915418rwb; Mon, 7 Aug 2023 20:14:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHLLeD+OXQcLk0mUUv4LmJS95A9La7TqOGe4juwLinRyl2Z1YJnW/oxQn0J5RTqr4cIPK/m X-Received: by 2002:a05:622a:1345:b0:3f6:adda:afd6 with SMTP id w5-20020a05622a134500b003f6addaafd6mr10888892qtk.10.1691464473094; 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 03/24] target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero Date: Mon, 7 Aug 2023 20:11:22 -0700 Message-Id: <20230808031143.50925-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The setcond + neg + and sequence is a complex method of performing a conditional move. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/alpha/translate.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 846f3d8091..0839182a1f 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -517,10 +517,9 @@ static void gen_fold_mzero(TCGCond cond, TCGv dest, TCGv src) case TCG_COND_GE: case TCG_COND_LT: - /* For >= or <, map -0.0 to +0.0 via comparison and mask. */ - tcg_gen_setcondi_i64(TCG_COND_NE, dest, src, mzero); - tcg_gen_neg_i64(dest, dest); - tcg_gen_and_i64(dest, dest, src); + /* For >= or <, map -0.0 to +0.0. */ + tcg_gen_movcond_i64(TCG_COND_NE, dest, src, tcg_constant_i64(mzero), + src, tcg_constant_i64(0)); break; default: From patchwork Tue Aug 8 03:11:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711569 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1916679rwb; Mon, 7 Aug 2023 20:18:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFMeYmeO1VEH47FQ8b0/oluotwVvdv9Nfw2necQxiPlChQZWWzF1n6lT2nDgn5dm0OLt5PL X-Received: by 2002:a0c:b40d:0:b0:63d:43aa:e076 with SMTP id u13-20020a0cb40d000000b0063d43aae076mr10368551qve.1.1691464693656; Mon, 07 Aug 2023 20:18:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464693; cv=none; d=google.com; s=arc-20160816; b=PmTTME2lIGuvT+8qMHR0JIq5HOZAIr5tlATLKLDl8GHElIF0dh/8gvZxZ5tLYF509B 2DRAHOBgW8tpQEwqfzKLpWP1JmKMhO/pwsmU4rzEtJT8aYk/GvYYVJMJ45OdfP79HnZv qPO8T9twdl1Lip1KzykItNKI1hvKmNTCsx0tH87g0udAvKpbn2oMKqU8OOXLqq0bYu/E ayKFv45cBOcHjN6NgPhqBPnWoIPrnHe97O9sIyALDshcWuY0STZ5so1sP2mM40Do48sU lx0wrQQgn2gFRoGtL6yAaVkPvysLuDLxlACNb+TT9wUruagHtPKGHQW/FB3uQ7O4FUxL 5E7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HftGyFuliXonCmDTfSQ595T2noxt1RPBvVTS1fEpJE4=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=hVeutMXnO3NdF8/4v/IArCumFgnDstOmmiVFMPFduWTcuOurLdNJleYcfW8cItFnpo GZ0DMY6XOcg1bEk/KEQjelmCt6mArNsye1Z+CpnUGJP26zKV00hHRNyLNeh/7dyed/g2 RFAD5h8mIS7fXQKxcZCBRj1Q7aysJ1QIRu4Lf7LNzVpHJ+kUOLTzmo+q11NLjiAV9XRu Kp9DaygujgMQNzziz5mjvuseB/k16CAHd0bbBNiUdxq0yOOJbJxj76UQVrNFJCVF+RIy tuCmpz36tzCqIojK3YNPAUElQZ5a7zxQURb/L2sCq7rhcfGMdlXpWpFZj71Ur2maoUfy AznQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qyZ4ShXL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 04/24] target/arm: Use tcg_gen_negsetcond_* Date: Mon, 7 Aug 2023 20:11:23 -0700 Message-Id: <20230808031143.50925-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 22 +++++++++------------- target/arm/tcg/translate.c | 12 ++++-------- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5fa1257d32..ac16593699 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4935,9 +4935,12 @@ static void disas_cond_select(DisasContext *s, uint32_t insn) if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { /* CSET & CSETM. */ - tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero); if (else_inv) { - tcg_gen_neg_i64(tcg_rd, tcg_rd); + tcg_gen_negsetcond_i64(tcg_invert_cond(c.cond), + tcg_rd, c.value, zero); + } else { + tcg_gen_setcond_i64(tcg_invert_cond(c.cond), + tcg_rd, c.value, zero); } } else { TCGv_i64 t_true = cpu_reg(s, rn); @@ -8670,13 +8673,10 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u, } break; case 0x6: /* CMGT, CMHI */ - /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0. - * We implement this using setcond (test) and then negating. - */ cond = u ? TCG_COND_GTU : TCG_COND_GT; do_cmop: - tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); - tcg_gen_neg_i64(tcg_rd, tcg_rd); + /* 64 bit integer comparison, result = test ? -1 : 0. */ + tcg_gen_negsetcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); break; case 0x7: /* CMGE, CMHS */ cond = u ? TCG_COND_GEU : TCG_COND_GE; @@ -9265,14 +9265,10 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, } break; case 0xa: /* CMLT */ - /* 64 bit integer comparison against zero, result is - * test ? (2^64 - 1) : 0. We implement via setcond(!test) and - * subtracting 1. - */ + /* 64 bit integer comparison against zero, result is test ? 1 : 0. */ cond = TCG_COND_LT; do_cmop: - tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0); - tcg_gen_neg_i64(tcg_rd, tcg_rd); + tcg_gen_negsetcond_i64(cond, tcg_rd, tcg_rn, tcg_constant_i64(0)); break; case 0x8: /* CMGT, CMGE */ cond = u ? TCG_COND_GE : TCG_COND_GT; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b71ac2d0d5..31d3130e4c 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -2946,13 +2946,11 @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, #define GEN_CMP0(NAME, COND) \ static void gen_##NAME##0_i32(TCGv_i32 d, TCGv_i32 a) \ { \ - tcg_gen_setcondi_i32(COND, d, a, 0); \ - tcg_gen_neg_i32(d, d); \ + tcg_gen_negsetcond_i32(COND, d, a, tcg_constant_i32(0)); \ } \ static void gen_##NAME##0_i64(TCGv_i64 d, TCGv_i64 a) \ { \ - tcg_gen_setcondi_i64(COND, d, a, 0); \ - tcg_gen_neg_i64(d, d); \ + tcg_gen_negsetcond_i64(COND, d, a, tcg_constant_i64(0)); \ } \ static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \ { \ @@ -3863,15 +3861,13 @@ void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { tcg_gen_and_i32(d, a, b); - tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0); - tcg_gen_neg_i32(d, d); + tcg_gen_negsetcond_i32(TCG_COND_NE, d, d, tcg_constant_i32(0)); } void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { tcg_gen_and_i64(d, a, b); - tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0); - tcg_gen_neg_i64(d, d); + tcg_gen_negsetcond_i64(TCG_COND_NE, d, d, tcg_constant_i64(0)); } static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b) From patchwork Tue Aug 8 03:11:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711567 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1916395rwb; Mon, 7 Aug 2023 20:17:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG/2WdOY0EVnehmhRLG6bIG+ic/Gx+H/Dfils7OnmXlbNwf/ecvh8GD4zEcVR64idALfZs3 X-Received: by 2002:ac8:5acb:0:b0:403:ed26:4083 with SMTP id d11-20020ac85acb000000b00403ed264083mr15229049qtd.61.1691464644433; Mon, 07 Aug 2023 20:17:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464644; cv=none; d=google.com; s=arc-20160816; b=gR5WJjvHBuzDTp6qtDHQKalVVZaH2GLNhyYOmQtjWm9W8wBeuzL7WOxowi6KaJ1Vcr fF/ZCD35nDsg1PQaI/o09hk8qxrlyVzC6U90rU2Q/Mt3dLEMMoZ2oEq6DE3YaXkCAtkB ApqJcZAb9/gQgG7fgas7dDn4e4gUff/3BkaGeTHwZLW4YDIUzVElezbgAGAF+JcdH8iI HGl7un83sbmHYnHDgW2DGTbx+1UfuUhvO3c4Y3+kUMoxhHOJCUbp/QGOS5p9r6zcbzd5 9ZFutHfvLQOXxxgSkPj/pcfVxpe2DJJsbXFjHRWbzXqDTcQAHDaM/wWVyLcUQosvAYzJ qhgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZfPoEwU2O4IK9AqxqstJxMdbJLfYwviBA2IVblhOckE=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=kaFTPGy2wbjueaw1nQTIqaEzzzBzDIC0p5WBMSLI20V+T7KHnW1BVqkbtVzgZtqRSD TD80zO3Bi4BG4I6oZPvB2q0mQIKPdInGHK+3sxd0Y2Z986YdAEI+KC1gJhQd3sri0L0R wF6+htyRoCFoV4GuMIvGlkwCqxbKfOT+DoTYURrrh1OB7sJ8vVbaEbVKmRuNMobfQ8kX rHF5D3G+w2iTlSs6P26fQK0GkBmx0bjG89lBvNawn5CFtaRGW/86bLy+RHN9zGsItjEr RiXb6GksTuaXBxc51dGT2nfWqB256Cmjm1WGK1vjbGeKedRRNdN8dusauJgSl8VfWDO5 8evw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CYy0zxEg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 05/24] target/m68k: Use tcg_gen_negsetcond_* Date: Mon, 7 Aug 2023 20:11:24 -0700 Message-Id: <20230808031143.50925-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/m68k/translate.c | 24 ++++++++++-------------- 1 file changed, 10 insertions(+), 14 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index e07161d76f..37954d11a6 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1357,8 +1357,7 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond) case 14: /* GT (!(Z || (N ^ V))) */ case 15: /* LE (Z || (N ^ V)) */ c->v1 = tmp = tcg_temp_new(); - tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); - tcg_gen_neg_i32(tmp, tmp); + tcg_gen_negsetcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2); tmp2 = tcg_temp_new(); tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V); tcg_gen_or_i32(tmp, tmp, tmp2); @@ -1437,9 +1436,8 @@ DISAS_INSN(scc) gen_cc_cond(&c, s, cond); tmp = tcg_temp_new(); - tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); + tcg_gen_negsetcond_i32(c.tcond, tmp, c.v1, c.v2); - tcg_gen_neg_i32(tmp, tmp); DEST_EA(env, insn, OS_BYTE, tmp, NULL); } @@ -2771,13 +2769,14 @@ DISAS_INSN(mull) tcg_gen_muls2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); /* QREG_CC_V is -(QREG_CC_V != (QREG_CC_N >> 31)) */ tcg_gen_sari_i32(QREG_CC_Z, QREG_CC_N, 31); - tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_Z); + tcg_gen_negsetcond_i32(TCG_COND_NE, QREG_CC_V, + QREG_CC_V, QREG_CC_Z); } else { tcg_gen_mulu2_i32(QREG_CC_N, QREG_CC_V, src1, DREG(ext, 12)); /* QREG_CC_V is -(QREG_CC_V != 0), use QREG_CC_C as 0 */ - tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, QREG_CC_C); + tcg_gen_negsetcond_i32(TCG_COND_NE, QREG_CC_V, + QREG_CC_V, QREG_CC_C); } - tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); tcg_gen_mov_i32(DREG(ext, 12), QREG_CC_N); tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N); @@ -3346,14 +3345,13 @@ static inline void shift_im(DisasContext *s, uint16_t insn, int opsize) if (!logical && m68k_feature(s->env, M68K_FEATURE_M68K)) { /* if shift count >= bits, V is (reg != 0) */ if (count >= bits) { - tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V); + tcg_gen_negsetcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V); } else { TCGv t0 = tcg_temp_new(); tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1); tcg_gen_sari_i32(t0, reg, bits - count - 1); - tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0); + tcg_gen_negsetcond_i32(TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0); } - tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); } } else { tcg_gen_shri_i32(QREG_CC_C, reg, count - 1); @@ -3437,9 +3435,8 @@ static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize) /* Ignore the bits below the sign bit. */ tcg_gen_andi_i64(t64, t64, -1ULL << (bits - 1)); /* If any bits remain set, we have overflow. */ - tcg_gen_setcondi_i64(TCG_COND_NE, t64, t64, 0); + tcg_gen_negsetcond_i64(TCG_COND_NE, t64, t64, tcg_constant_i64(0)); tcg_gen_extrl_i64_i32(QREG_CC_V, t64); - tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V); } } else { tcg_gen_shli_i64(t64, t64, 32); @@ -5318,9 +5315,8 @@ DISAS_INSN(fscc) gen_fcc_cond(&c, s, cond); tmp = tcg_temp_new(); - tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2); + tcg_gen_negsetcond_i32(c.tcond, tmp, c.v1, c.v2); - tcg_gen_neg_i32(tmp, tmp); DEST_EA(env, insn, OS_BYTE, tmp, NULL); } From patchwork Tue Aug 8 03:11:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711551 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1915082rwb; Mon, 7 Aug 2023 20:13:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEoDTDXKGkv6IThYUByHG/gdLjLj+LXpO2sKptPeMMo8+VVAvgsTt5QArb1Lx91e5v8njVU X-Received: by 2002:ad4:53ab:0:b0:62d:eda3:4335 with SMTP id j11-20020ad453ab000000b0062deda34335mr8839453qvv.29.1691464411125; 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 06/24] target/openrisc: Use tcg_gen_negsetcond_* Date: Mon, 7 Aug 2023 20:11:25 -0700 Message-Id: <20230808031143.50925-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/openrisc/translate.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index a86360d4f5..7c6f80daf1 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -253,9 +253,8 @@ static void gen_mul(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) tcg_gen_muls2_tl(dest, cpu_sr_ov, srca, srcb); tcg_gen_sari_tl(t0, dest, TARGET_LONG_BITS - 1); - tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); + tcg_gen_negsetcond_tl(TCG_COND_NE, cpu_sr_ov, cpu_sr_ov, t0); - tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); gen_ove_ov(dc); } @@ -309,9 +308,8 @@ static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb) tcg_gen_muls2_i64(cpu_mac, high, t1, t2); tcg_gen_sari_i64(t1, cpu_mac, 63); - tcg_gen_setcond_i64(TCG_COND_NE, t1, t1, high); + tcg_gen_negsetcond_i64(TCG_COND_NE, t1, t1, high); tcg_gen_trunc_i64_tl(cpu_sr_ov, t1); - tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov); gen_ove_ov(dc); } From patchwork Tue Aug 8 03:11:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711554 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1915294rwb; Mon, 7 Aug 2023 20:14:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEzZnCgkZ1ZdDnzntLoIcEtJbnSxwyxCi9ACI3IQk2v5p2B3ZQjyHrh5RjmrPqJVyOxcYsw X-Received: by 2002:a05:622a:345:b0:403:c9c9:e4ea with SMTP id r5-20020a05622a034500b00403c9c9e4eamr15569415qtw.38.1691464448303; Mon, 07 Aug 2023 20:14:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464448; cv=none; d=google.com; s=arc-20160816; b=Fwz0vEvpuauBTTXy5y0PR2ej8kaNqaok7+yzKofoGX6H74INFzEaIqfcrHwxDdgEh8 a5a2tPsEQ/PBru4QI+fDwr+gH5nhg//A0VY5JHAiLSfpX8EzofyY1OFHL/tP8cPkfLJ4 sxhA3SZpgjljy6VYIAe6uM1/4+YVru+So4ew4t2UXpYr2hA0DeUDEjel/ZKtYp00fc77 10Z/hOr2KrYUbsQDiQo9xUX3Fkj2Bjsm8ObYF4rLet7UU2kFL8777Ep0qPnuEcxOs9WZ zUsc3DqHyu3OJaCOfmDLbTFA0QgGy+NE+GsLq+WNp3vR70iFSsUPNnwDADYdhf8ebx4y 5SsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=h47eic5iqOAhfWM944hqigKUjin3wD6PihSMVViXfj4=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=D36dyizXBHLQm79KORR7wVQStvkX9MgjSjUc+hks9o47cJTqxcf2rw5DJ3/SsbhpBe w09TTQFT/KCeoFa7HcH3kkDKHEUtC4F+BmWpSUpu2b2cxdx2RX/ZLyPcSRgpyaVe8YBm sBY2bLVWM0hCHzPRFBZVblOYW7n1iuxkBhHaH4U2ZZz+fBB2Ts+ylvZVgBtzm+OAWs2H G3Hs4Il9bVITksbl77TCPST2d0YmsvpfKEiDOy3ttMovreDMOq1katcXpKcV4jdHuCol X31zkDTxrWCGhaKc9Pr1jYacDVHrfCXrIpQAEYGeEbgSZsVnuIFxdYdEt4G8Tp9ouv1i c58A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="YX/AgPjY"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 07/24] target/ppc: Use tcg_gen_negsetcond_* Date: Mon, 7 Aug 2023 20:11:26 -0700 Message-Id: <20230808031143.50925-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Reviewed-by: Nicholas Piggin Tested-by: Nicholas Piggin --- target/ppc/translate/fixedpoint-impl.c.inc | 6 ++++-- target/ppc/translate/vmx-impl.c.inc | 8 +++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index f47f1a50e8..4ce02fd3a4 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -342,12 +342,14 @@ static bool do_set_bool_cond(DisasContext *ctx, arg_X_bi *a, bool neg, bool rev) uint32_t mask = 0x08 >> (a->bi & 0x03); TCGCond cond = rev ? TCG_COND_EQ : TCG_COND_NE; TCGv temp = tcg_temp_new(); + TCGv zero = tcg_constant_tl(0); tcg_gen_extu_i32_tl(temp, cpu_crf[a->bi >> 2]); tcg_gen_andi_tl(temp, temp, mask); - tcg_gen_setcondi_tl(cond, cpu_gpr[a->rt], temp, 0); if (neg) { - tcg_gen_neg_tl(cpu_gpr[a->rt], cpu_gpr[a->rt]); + tcg_gen_negsetcond_tl(cond, cpu_gpr[a->rt], temp, zero); + } else { + tcg_gen_setcond_tl(cond, cpu_gpr[a->rt], temp, zero); } return true; } diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index c8712dd7d8..6d7669aabd 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1341,8 +1341,7 @@ static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a) tcg_gen_xor_i64(t1, t0, t1); tcg_gen_or_i64(t1, t1, t2); - tcg_gen_setcondi_i64(TCG_COND_EQ, t1, t1, 0); - tcg_gen_neg_i64(t1, t1); + tcg_gen_negsetcond_i64(TCG_COND_EQ, t1, t1, tcg_constant_i64(0)); set_avr64(a->vrt, t1, true); set_avr64(a->vrt, t1, false); @@ -1365,15 +1364,14 @@ static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a, bool sign) get_avr64(t0, a->vra, false); get_avr64(t1, a->vrb, false); - tcg_gen_setcond_i64(TCG_COND_GTU, t2, t0, t1); + tcg_gen_negsetcond_i64(TCG_COND_GTU, t2, t0, t1); get_avr64(t0, a->vra, true); get_avr64(t1, a->vrb, true); tcg_gen_movcond_i64(TCG_COND_EQ, t2, t0, t1, t2, tcg_constant_i64(0)); - tcg_gen_setcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t1, t0, t1); + tcg_gen_negsetcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t1, t0, t1); tcg_gen_or_i64(t1, t1, t2); - tcg_gen_neg_i64(t1, t1); set_avr64(a->vrt, t1, true); set_avr64(a->vrt, t1, false); From patchwork Tue Aug 8 03:11:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711559 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1915620rwb; Mon, 7 Aug 2023 20:15:05 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGkdavsPy2ji97mttvxpoTSfAZeDWmzIIl0bd9362P15pAFybrRsG3vauITR1zzEb9y90Bz X-Received: by 2002:a05:620a:1a1f:b0:762:499d:d9dc with SMTP id bk31-20020a05620a1a1f00b00762499dd9dcmr15485525qkb.54.1691464505288; Mon, 07 Aug 2023 20:15:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464505; cv=none; d=google.com; s=arc-20160816; b=HV5drWBNsPPNf80eXMxokxKMUtVL3toHLYAYhSDEpvY3yXLVsQNgIgYF+JvnVhhcO0 a1RSSr5I0ebXPKnyauII9dsmK8cZGZMsDoUzCKIyXKnBJIVPWaSnE8MzHAWehhXIrAly 3lFhoN/v9/s6fbRs7I4EbUS6efTH2+GBPE8h7/EYG/Be3rjbBSLtxu7buHbZ6VLW8eso fAXs5Z9/P1pKNPErylPW6E2WDnUDv+kyqccZfnX07/afVXRtTPlcuSu66QQ9F2y+yuxd ii1ZLYCORQBfrGz7qwm2Z2U7eZqXU7yygxnRbsBF2JDUxVP4MxfgbZftcz1h4eQ7uq7M vs0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=g8a+pmsyT7JaiJjb96T8aB4eik7cv3ApHNhItnmJcZ8=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=P7tPy1ylhMwL+QOz6V1/cWaOL1yhTOvk/VgIciwf0ylNpox1l3I1oFhJ+64MS7cmMh ZBDK4vS6T4hyrCvYbjq0hSa6PjhsgUe0aRzJ9szg80VxOLlJ2vFSYGPVuLWaJo20sM1G e98N3aZhdjBGMQmDOc8TrOOFfSbllqbknrNU/ILciaOJof8wqBdBCLOsMdVMWhjd6J2M 8QS9ChfRPSDTjpAlzGZ1bhWJ2rpu9My6q9WCKkzNBGjcXnA5aVVr/gANJyRzKL60+A4X NLHXlGKE5Vahc/BltMcL3yIczBrrPMpaX9w/jinGiDaY3dwtZQlwgocuphWatpLiDfce gUAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aJ7FU4JQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 08/24] target/sparc: Use tcg_gen_movcond_i64 in gen_edge Date: Mon, 7 Aug 2023 20:11:27 -0700 Message-Id: <20230808031143.50925-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The setcond + neg + or sequence is a complex method of performing a conditional move. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/sparc/translate.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index bd877a5e4a..fa80a91161 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2916,7 +2916,7 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, tcg_gen_shr_tl(lo1, tcg_constant_tl(tabl), lo1); tcg_gen_shr_tl(lo2, tcg_constant_tl(tabr), lo2); - tcg_gen_andi_tl(dst, lo1, omask); + tcg_gen_andi_tl(lo1, lo1, omask); tcg_gen_andi_tl(lo2, lo2, omask); amask = -8; @@ -2926,18 +2926,9 @@ static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2, tcg_gen_andi_tl(s1, s1, amask); tcg_gen_andi_tl(s2, s2, amask); - /* We want to compute - dst = (s1 == s2 ? lo1 : lo1 & lo2). - We've already done dst = lo1, so this reduces to - dst &= (s1 == s2 ? -1 : lo2) - Which we perform by - lo2 |= -(s1 == s2) - dst &= lo2 - */ - tcg_gen_setcond_tl(TCG_COND_EQ, lo1, s1, s2); - tcg_gen_neg_tl(lo1, lo1); - tcg_gen_or_tl(lo2, lo2, lo1); - tcg_gen_and_tl(dst, dst, lo2); + /* Compute dst = (s1 == s2 ? lo1 : lo1 & lo2). */ + tcg_gen_and_tl(lo2, lo2, lo1); + tcg_gen_movcond_tl(TCG_COND_EQ, dst, s1, s2, lo1, lo2); } static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) From patchwork Tue Aug 8 03:11:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711555 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1915383rwb; Mon, 7 Aug 2023 20:14:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFJvp9imdah64YeSbaEaFFZgkvoIKrfVk/yDDmcyOiebQmxwro2solB0rcoCLoubVvhgaJa X-Received: by 2002:a05:620a:290d:b0:767:2d95:fae4 with SMTP id m13-20020a05620a290d00b007672d95fae4mr13543346qkp.73.1691464465525; Mon, 07 Aug 2023 20:14:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464465; cv=none; d=google.com; s=arc-20160816; b=hHMQo+lL5FZ5/WzREzXh9XFHCrGJwPoEpFmCr867bF90XCfO6sxINDyoDwR0RsCKXp nNAxTQ0iucxQLiBrdfUUyIKlxLoTOQE7SciC6Ilp2/6kljfh8jddpDpg8VW7BwqfVrOF VnW1pu3RSnLL7pvAZK402UECZTpdKvYMb6h/4PXiV7WcrqZooSrh5os7gKzh9UBNHOj6 PCuJVNC6P9o2hf99GgsjbDog/PCeihy6GBIJs4qxuG65V+quyyml3YxUmGt5zZpi2Ose 56uC0vrnukkTTmfLTtjFxQRjZOSDNCkrbOZekWGnQD2CDFhQwDSjANCaVvYeVPPouI+H tujA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iebNd9NWSI/oGO+XQT1osPqubnSl7SPT7dJSjDKV1XY=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=mtujpfDF/HFcFrzhQZhkmrxYh39HQMSbN6XUfysxNlr2LWFu6iG9wq365Mi/R4m8Gg 6K92cd/SUduLkowdsEgV/iZ3DMD8T2BJyLD+FZ+eX66f+Ar8WhcspZchQC9+VVjO1z8d Rypha/Emb9Oos9hCX/mGYSoEp9QJYayMydqyV5eOYlZ2z+kRR68FvI6hM1BbF/bx4JZw WxBg4Z5qd3jI4Yft24sO/yBIJg7X4hJpaqxULVA2eQ3HMrCSRZkVWnBTtgbppDWlOeCs 7oyaloIYLpbthHJldY6bUd33wkb41MyzXL0iB8TsUMYdsw8ucCJhpjyev3E9pxnxGSTT CP+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZqW6SJLS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 09/24] target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl Date: Mon, 7 Aug 2023 20:11:28 -0700 Message-Id: <20230808031143.50925-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x336.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Bastian Koppelmann --- target/tricore/translate.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 1947733870..6ae5ccbf72 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -2680,13 +2680,6 @@ gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con, gen_accumulating_cond(cond, ret, r1, temp, op); } -/* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/ -static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2) -{ - tcg_gen_setcond_tl(cond, ret, r1, r2); - tcg_gen_neg_tl(ret, ret); -} - static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con) { TCGv b0 = tcg_temp_new(); @@ -5692,7 +5685,8 @@ static void decode_rr_accumulator(DisasContext *ctx) gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_EQ_W: - gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); + tcg_gen_negsetcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], + cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_EQANY_B: gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); @@ -5729,10 +5723,12 @@ static void decode_rr_accumulator(DisasContext *ctx) gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_LT_W: - gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); + tcg_gen_negsetcond_tl(TCG_COND_LT, cpu_gpr_d[r3], + cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_LT_WU: - gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); + tcg_gen_negsetcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], + cpu_gpr_d[r1], cpu_gpr_d[r2]); break; case OPC2_32_RR_MAX: tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1], From patchwork Tue Aug 8 03:11:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711546 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1914660rwb; Mon, 7 Aug 2023 20:12:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEHArx5xdZxrD/67iV/2v+XN50yb+6lH/D5uxFfzD1BrxrJk+eFoPLNADJSF2vpX2D2kcP2 X-Received: by 2002:a05:620a:4152:b0:76c:a957:b2f1 with SMTP id k18-20020a05620a415200b0076ca957b2f1mr14269046qko.66.1691464345668; Mon, 07 Aug 2023 20:12:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464345; cv=none; d=google.com; s=arc-20160816; b=dWaGPESne1X2QOVxqFTTUAix7u9/UVzqCfzGeMg+SWdQsPfLRp/QT1oQYvuGLJAxk6 Bq8sKMGQ3bQ9Me6j9rdhx9na6Po27MZ/5XfpsnhIqDPqn+2GPiy1TEsKZaQ+EbZ4Z7cd RDEquDQkzmClAryoYExzC5GRKKaiO/X5/rkR1P9pjFaLViE7slKYpbft/RiRKVbB8zR6 5ZXEItp3XbfX3j53YrB4+VnKQyrc6fTj0u+KYQlUL5MDA4GxtWZo9EK/oVgRY7oSKd6I SBMfYSGIZty33IqhO2OiWV5dDqSny3rm2zs16omVOVM2DFy2kmb65l7N3rScn8iug4l8 w9vg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Zlp57K00otmxuxrznRTj8naNd4cFVTyLFrTG1OoXOXI=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=aDtyx5DQ5a+6cm7DT5FBTgAgKaqwKzHGrVJTfB4J+vaE6US8IOnFRI6ncOS16Lhlsu XfrUyHhQGmBvx1Sj4OeBiS19uXERoHoEIH5saHSwy+5cvXmsZl2DxlXlEk5mX58URTpM pHBlDUb1l206Su5l4O0IryoW4XDAS7vVEHibq7xT/ulHRI6XiKRIeNFvZFT8eX86J8KL sCIxYpwLBZVQ/an0Hs/GiOtrwOcTIxTikoT4DBBqDG8b+54HHFOXeem8wtHgNn36m6Kh pHJE9j+ltTSmAtgr2onjISsbnGhMVBBhnasGYh2gUMNB8l63IJPFjv4SB4ZWrE7X+zAx xieQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lDUUqxd1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 10/24] tcg/ppc: Implement negsetcond_* Date: Mon, 7 Aug 2023 20:11:29 -0700 Message-Id: <20230808031143.50925-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x329.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In the general case we simply negate. However with isel we may load -1 instead of 1 with no extra effort. Consolidate EQ0 and NE0 logic. Replace the NE0 zero-extension with inversion+negation of EQ0, which is never worse and may eliminate one insn. Provide a special case for -EQ0. Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza --- tcg/ppc/tcg-target.h | 4 +- tcg/ppc/tcg-target.c.inc | 127 ++++++++++++++++++++++++--------------- 2 files changed, 82 insertions(+), 49 deletions(-) diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index ba4fd3eb3a..a143b8f1e0 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -101,7 +101,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 -#define TCG_TARGET_HAS_negsetcond_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #if TCG_TARGET_REG_BITS == 64 @@ -142,7 +142,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 -#define TCG_TARGET_HAS_negsetcond_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 1 #endif #define TCG_TARGET_HAS_qemu_ldst_i128 \ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 511e14b180..10448aa0e6 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1548,8 +1548,20 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, } static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, - TCGReg dst, TCGReg src) + TCGReg dst, TCGReg src, bool neg) { + if (neg && (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I64)) { + /* + * X != 0 implies X + -1 generates a carry. + * RT = (~X + X) + CA + * = -1 + CA + * = CA ? 0 : -1 + */ + tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); + tcg_out32(s, SUBFE | TAB(dst, src, src)); + return; + } + if (type == TCG_TYPE_I32) { tcg_out32(s, CNTLZW | RS(src) | RA(dst)); tcg_out_shri32(s, dst, dst, 5); @@ -1557,18 +1569,28 @@ static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, tcg_out32(s, CNTLZD | RS(src) | RA(dst)); tcg_out_shri64(s, dst, dst, 6); } + if (neg) { + tcg_out32(s, NEG | RT(dst) | RA(dst)); + } } -static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src) +static void tcg_out_setcond_ne0(TCGContext *s, TCGType type, + TCGReg dst, TCGReg src, bool neg) { - /* X != 0 implies X + -1 generates a carry. Extra addition - trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */ - if (dst != src) { - tcg_out32(s, ADDIC | TAI(dst, src, -1)); - tcg_out32(s, SUBFE | TAB(dst, dst, src)); - } else { + if (!neg && (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I64)) { + /* + * X != 0 implies X + -1 generates a carry. Extra addition + * trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. + */ tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src)); + return; + } + tcg_out_setcond_eq0(s, type, dst, src, false); + if (neg) { + tcg_out32(s, ADDI | TAI(dst, dst, -1)); + } else { + tcg_out_xori32(s, dst, dst, 1); } } @@ -1590,9 +1612,10 @@ static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2, static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, TCGArg arg0, TCGArg arg1, TCGArg arg2, - int const_arg2) + int const_arg2, bool neg) { - int crop, sh; + int sh; + bool inv; tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); @@ -1605,14 +1628,10 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, if (arg2 == 0) { switch (cond) { case TCG_COND_EQ: - tcg_out_setcond_eq0(s, type, arg0, arg1); + tcg_out_setcond_eq0(s, type, arg0, arg1, neg); return; case TCG_COND_NE: - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { - tcg_out_ext32u(s, TCG_REG_R0, arg1); - arg1 = TCG_REG_R0; - } - tcg_out_setcond_ne0(s, arg0, arg1); + tcg_out_setcond_ne0(s, type, arg0, arg1, neg); return; case TCG_COND_GE: tcg_out32(s, NOR | SAB(arg1, arg0, arg1)); @@ -1621,9 +1640,17 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, case TCG_COND_LT: /* Extract the sign bit. */ if (type == TCG_TYPE_I32) { - tcg_out_shri32(s, arg0, arg1, 31); + if (neg) { + tcg_out_sari32(s, arg0, arg1, 31); + } else { + tcg_out_shri32(s, arg0, arg1, 31); + } } else { - tcg_out_shri64(s, arg0, arg1, 63); + if (neg) { + tcg_out_sari64(s, arg0, arg1, 63); + } else { + tcg_out_shri64(s, arg0, arg1, 63); + } } return; default: @@ -1641,7 +1668,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, isel = tcg_to_isel[cond]; - tcg_out_movi(s, type, arg0, 1); + tcg_out_movi(s, type, arg0, neg ? -1 : 1); if (isel & 1) { /* arg0 = (bc ? 0 : 1) */ tab = TAB(arg0, 0, arg0); @@ -1655,51 +1682,47 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, return; } + inv = false; switch (cond) { case TCG_COND_EQ: arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); - tcg_out_setcond_eq0(s, type, arg0, arg1); - return; + tcg_out_setcond_eq0(s, type, arg0, arg1, neg); + break; case TCG_COND_NE: arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); - /* Discard the high bits only once, rather than both inputs. */ - if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { - tcg_out_ext32u(s, TCG_REG_R0, arg1); - arg1 = TCG_REG_R0; - } - tcg_out_setcond_ne0(s, arg0, arg1); - return; + tcg_out_setcond_ne0(s, type, arg0, arg1, neg); + break; + case TCG_COND_LE: + case TCG_COND_LEU: + inv = true; + /* fall through */ case TCG_COND_GT: case TCG_COND_GTU: - sh = 30; - crop = 0; - goto crtest; - - case TCG_COND_LT: - case TCG_COND_LTU: - sh = 29; - crop = 0; + sh = 30; /* CR7 CR_GT */ goto crtest; case TCG_COND_GE: case TCG_COND_GEU: - sh = 31; - crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT); + inv = true; + /* fall through */ + case TCG_COND_LT: + case TCG_COND_LTU: + sh = 29; /* CR7 CR_LT */ goto crtest; - case TCG_COND_LE: - case TCG_COND_LEU: - sh = 31; - crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT); crtest: tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); - if (crop) { - tcg_out32(s, crop); - } tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); + if (neg && inv) { + tcg_out32(s, ADDI | TAI(arg0, arg0, -1)); + } else if (neg) { + tcg_out32(s, NEG | RT(arg0) | RA(arg0)); + } else if (inv) { + tcg_out_xori32(s, arg0, arg0, 1); + } break; default: @@ -2982,11 +3005,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_setcond_i32: tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], - const_args[2]); + const_args[2], false); break; case INDEX_op_setcond_i64: tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], - const_args[2]); + const_args[2], false); + break; + case INDEX_op_negsetcond_i32: + tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], + const_args[2], true); + break; + case INDEX_op_negsetcond_i64: + tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], + const_args[2], true); break; case INDEX_op_setcond2_i32: tcg_out_setcond2(s, args, const_args); @@ -3724,6 +3755,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rotl_i32: case INDEX_op_rotr_i32: case INDEX_op_setcond_i32: + case INDEX_op_negsetcond_i32: case INDEX_op_and_i64: case INDEX_op_andc_i64: case INDEX_op_shl_i64: @@ -3732,6 +3764,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i64: case INDEX_op_setcond_i64: + case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, ri); case INDEX_op_mul_i32: From patchwork Tue Aug 8 03:11:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711556 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1915386rwb; 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 11/24] tcg/ppc: Use the Set Boolean Extension Date: Mon, 7 Aug 2023 20:11:30 -0700 Message-Id: <20230808031143.50925-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc31.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The SETBC family of instructions requires exactly two insns for all comparisions, saving 0-3 insns per (neg)setcond. Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Tested-by: Nicholas Piggin --- tcg/ppc/tcg-target.c.inc | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 10448aa0e6..090f11e71c 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -447,6 +447,11 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define TW XO31( 4) #define TRAP (TW | TO(31)) +#define SETBC XO31(384) /* v3.10 */ +#define SETBCR XO31(416) /* v3.10 */ +#define SETNBC XO31(448) /* v3.10 */ +#define SETNBCR XO31(480) /* v3.10 */ + #define NOP ORI /* ori 0,0,0 */ #define LVX XO31(103) @@ -1624,6 +1629,23 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, arg2 = (uint32_t)arg2; } + /* With SETBC/SETBCR, we can always implement with 2 insns. */ + if (have_isa_3_10) { + tcg_insn_unit bi, opc; + + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + + /* Re-use tcg_to_bc for BI and BO_COND_{TRUE,FALSE}. */ + bi = tcg_to_bc[cond] & (0x1f << 16); + if (tcg_to_bc[cond] & BO(8)) { + opc = neg ? SETNBC : SETBC; + } else { + opc = neg ? SETNBCR : SETBCR; + } + tcg_out32(s, opc | RT(arg0) | bi); + return; + } + /* Handle common and trivial cases before handling anything else. */ if (arg2 == 0) { switch (cond) { From patchwork Tue Aug 8 03:11:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711553 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1915159rwb; Mon, 7 Aug 2023 20:13:44 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF/ZxpnOACQerOaVetzHf/ri/rwst8gGPZcDQpzAi2OyJjTxu4csRCjUQU/srDMn7zEYqJ8 X-Received: by 2002:a05:6214:5841:b0:637:85e3:2a2d with SMTP id ml1-20020a056214584100b0063785e32a2dmr11201087qvb.58.1691464424255; Mon, 07 Aug 2023 20:13:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464424; cv=none; d=google.com; s=arc-20160816; b=sZPUQNOxYvWFkiMCg9AGv1/m0S8UN7A6574gZrUpJ7IkLH3BgzRVIMLboXuZkPA1Vj prEe+b7PTj40UwoaKOnW4SzERcn8FBzaCTmTFjfyl4/LsnvgZKH6RgZTnL/TZefWYhek kq3v76eqeYvOBVCps+hi2EyKycZz8ePTTZlIYXWeYCbdN27/2CI9sPYvptq2b+7XobhB ruPhAgXPZOvqr5Q9WmMgCFCP7oOt3btgJonx4PjS6W277hO11qxDdiYTZW24BA3Zp2aj uNnGZH5BGsZKTKoSpzsBzAUFp79Z/xodzzfVH6CympfEgf+OXXMRzxaUk6kp9ZR8Q2jb wHxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=82T4pR6asvjS0K/TieV1fa+Y+4r718itxbMRosKOlXE=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=i4MRS6zxiyuqp38SuoOxKR9GnPyjIP0Qtoc+gyJn83ctetae/ei2ya2YB7DFQDwg8k HiuuJH/C68UxlyL0ib/5ppFmzN4i6lmBpPHV7DOomPfUNgc4yrYVi+3u2OTSlh0FlRXZ tZhLWhYL7MzVT4mQDlLcf1BFvFbTv2/cufRENkwrIvhD6dqdfnQKJT9VAy3hvptxWkNW 7VtwOSZV5VLkOw2KX22/RELZ8NEYGq4S6l025BPE/E2h7YEcNLag7gFeg4F6ke0elEFY CQqQSqwI2Ov+JI6MJL3sQ+xFasRHiXqpiVLnAwmt6PiVRXYShXXhZELVUMXecVa6orDS UdBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="s25KEC//"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 12/24] tcg/aarch64: Implement negsetcond_* Date: Mon, 7 Aug 2023 20:11:31 -0700 Message-Id: <20230808031143.50925-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Trivial, as aarch64 has an instruction for this: CSETM. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/aarch64/tcg-target.h | 4 ++-- tcg/aarch64/tcg-target.c.inc | 12 ++++++++++++ 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 6080fddf73..e3faa9cff4 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -94,7 +94,7 @@ typedef enum { #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 -#define TCG_TARGET_HAS_negsetcond_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_div_i64 1 @@ -130,7 +130,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 -#define TCG_TARGET_HAS_negsetcond_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 1 /* * Without FEAT_LSE2, we must use LDXP+STXP to implement atomic 128-bit load, diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 35ca80cd56..7d8d114c9e 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2262,6 +2262,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCG_REG_XZR, tcg_invert_cond(args[3])); break; + case INDEX_op_negsetcond_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_negsetcond_i64: + tcg_out_cmp(s, ext, a1, a2, c2); + /* Use CSETM alias of CSINV Wd, WZR, WZR, invert(cond). */ + tcg_out_insn(s, 3506, CSINV, ext, a0, TCG_REG_XZR, + TCG_REG_XZR, tcg_invert_cond(args[3])); + break; + case INDEX_op_movcond_i32: a2 = (int32_t)a2; /* FALLTHRU */ @@ -2868,6 +2878,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: + case INDEX_op_negsetcond_i32: + case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rA); case INDEX_op_mul_i32: From patchwork Tue Aug 8 03:11:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711566 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1916223rwb; Mon, 7 Aug 2023 20:16:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHweLfn2Jt8Tuu4fe20NaJj1Slm/WrgllZlhEdjOxvMpRK/mK6UwVBkL1hq2OzUaAPx+Gpy X-Received: by 2002:a05:620a:b8d:b0:765:aac1:100c with SMTP id k13-20020a05620a0b8d00b00765aac1100cmr10169668qkh.78.1691464614066; Mon, 07 Aug 2023 20:16:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464614; cv=none; d=google.com; s=arc-20160816; b=IW0TklE3LjWFzi6I+BL7LD+l6/ok5QLqPsspTaH8DaogEGFmvWkod1LTLf3zqKG3MF J6H2zctYlVp/749rFn0awtLPJjlh2gH8VOUhzcyjVprBTlbywgcLZozKInO0vfnqWU+Q JLGwDP7tx7b+lQdUAC7llQKd93asooldWNH15rQ3kdBBwGmaYOqEl6MznKa7mFDXZ8q0 QG42SC1SQrvri1NTf1RgHBIQhKY300CCKlU3y4AeSgCOX96CStS8mB8rr43Z6/5XD3nb kJbIa7JNIIXDHS7CMKk6Xw8wsciqO8Vjul3+5fSaS6R4MY0bZyRVkJqSvdkYK4KR7iU7 GK6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gzWqj3MGsLV9R8E01giJK4jPvvtSNzy1Q6wuC0RlJy0=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=V3hjlZ3alyc/yWS36cW84IvvdBcK9A+470WA6vm81Lt94Dsx5XT/EM6TedDG0SoG7O 5L00C2anexJB4soo3YzarfNrvqAzA1hyc2513VQx7w/WOlwYIphwZBzS3wphAbzeRquN Zlmzzxj0gVtT8ccLxS8njj9F109DgeIVEBm5jnLwrmTdyF6rK0J7/OduB3URO70jJqML qZORLQDws7Af8R44pf8C3yuWKdfqEv3uhSf66fpiD3WGTAlPtRybfvx10qZ/GUzdb6BJ RLvMXiGDwoffYUC6/mmpS8JrWHD86RohRyeFDhWeA41IqeV0Vai2evqTU6Xvbw+6uNF2 0/tw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iaBPZHwC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 13/24] tcg/arm: Implement negsetcond_i32 Date: Mon, 7 Aug 2023 20:11:32 -0700 Message-Id: <20230808031143.50925-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc31.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Trivial, as we simply need to load a different constant in the conditional move. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/arm/tcg-target.h | 2 +- tcg/arm/tcg-target.c.inc | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index b076d033a9..b064bbda9f 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -122,7 +122,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_div_i32 use_idiv_instructions #define TCG_TARGET_HAS_rem_i32 0 -#define TCG_TARGET_HAS_negsetcond_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 83e286088f..162df38c73 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1975,6 +1975,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], ARITH_MOV, args[0], 0, 0); break; + case INDEX_op_negsetcond_i32: + tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0, + args[1], args[2], const_args[2]); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]], + ARITH_MVN, args[0], 0, 0); + tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])], + ARITH_MOV, args[0], 0, 0); + break; case INDEX_op_brcond2_i32: c = tcg_out_cmp2(s, args, const_args); @@ -2112,6 +2120,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_add_i32: case INDEX_op_sub_i32: case INDEX_op_setcond_i32: + case INDEX_op_negsetcond_i32: return C_O1_I2(r, r, rIN); case INDEX_op_and_i32: From patchwork Tue Aug 8 03:11:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711548 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1914762rwb; Mon, 7 Aug 2023 20:12:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFkJl1Y6eb4Po/Plruy1Qez+pcEWjxtzkH0OZqfFxq3MS+VFqqj7jYVybOuf4aZiJvccK9S X-Received: by 2002:a05:620a:254d:b0:767:e785:15cb with SMTP id s13-20020a05620a254d00b00767e78515cbmr14486456qko.76.1691464358158; Mon, 07 Aug 2023 20:12:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464358; cv=none; d=google.com; s=arc-20160816; b=mT+32PTEi5BbJeTfFLaJyM6Ab1b71dbJI6Qvq3MoH4Rgy2w2tEvo2TMkjol2TbLxqx aQELSXwZAMznW2SztACAoxzV2OpKhIWs4Nhm/UWMyev2RTYihHubkfCu15WImk3NLJPl 9X1HR9u2hlWAbqADAiQGa/fNP17GkhAcxwuseItEIMMjyNQimQvU5w+gEN4BDb+/XZ1u AWO2xZaLiN7IVhKkzwqPR2IolEDnMrzqaHWqalpOVyyNtDKLW4jvxZK8MgXJs+2yjLpR iDuGfUqThdTuINt5e4lzEAAOQPrJ+VTeJoD9iaW0yEFE99mh+/trSjQogGoTN4jqI8uG i5Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2j5vEpa4xN9aVYYq+cztOssEG+ehvNVdIB8DhEEWJso=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=P2ssSxLKQd58TyptYXW8lwXrBZVB/nnFOSEEzfEcFdOwkBy+zg+qkzn3mIPo9Wuby5 2VHyGz8VkVvaD6jzg+teaHeRpfRVD5xIJZfgLwi5EvZNnQB+33ebUaBrbY+VhKQEK5ol kiyLfdMHvSxM1kVP50XTo70qArtRycSKDwoZeWdTquK9IBi8mAmKAmggqWiRnv5XP2rZ ToHO9tZ7PCqQeJYE+wZqrBrh3VZif3fZfCPOnMwEKcRpO08mT09sHQMNN7TgKUXX5NXA NhruQEiQrMG9H2T+WVtuLm6OToITB3IjWNAsL2RYwwYlfls96/ZCyodgthyGTaSyY4JD n7Zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a6y8J+x4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 14/24] tcg/riscv: Implement negsetcond_* Date: Mon, 7 Aug 2023 20:11:33 -0700 Message-Id: <20230808031143.50925-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72c.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza --- tcg/riscv/tcg-target.h | 4 ++-- tcg/riscv/tcg-target.c.inc | 45 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index b2961fec8e..7e8ac48a7d 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -120,7 +120,7 @@ extern bool have_zbb; #define TCG_TARGET_HAS_ctpop_i32 have_zbb #define TCG_TARGET_HAS_brcond2 1 #define TCG_TARGET_HAS_setcond2 1 -#define TCG_TARGET_HAS_negsetcond_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_movcond_i64 1 @@ -159,7 +159,7 @@ extern bool have_zbb; #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 1 #define TCG_TARGET_HAS_mulsh_i64 1 -#define TCG_TARGET_HAS_negsetcond_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index eeaeb6b6e3..232b616af3 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -936,6 +936,44 @@ static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, } } +static void tcg_out_negsetcond(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg arg1, tcg_target_long arg2, bool c2) +{ + int tmpflags; + TCGReg tmp; + + /* For LT/GE comparison against 0, replicate the sign bit. */ + if (c2 && arg2 == 0) { + switch (cond) { + case TCG_COND_GE: + tcg_out_opc_imm(s, OPC_XORI, ret, arg1, -1); + arg1 = ret; + /* fall through */ + case TCG_COND_LT: + tcg_out_opc_imm(s, OPC_SRAI, ret, arg1, TCG_TARGET_REG_BITS - 1); + return; + default: + break; + } + } + + tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); + tmp = tmpflags & ~SETCOND_FLAGS; + + /* If intermediate result is zero/non-zero: test != 0. */ + if (tmpflags & SETCOND_NEZ) { + tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); + tmp = ret; + } + + /* Produce the 0/-1 result. */ + if (tmpflags & SETCOND_INV) { + tcg_out_opc_imm(s, OPC_ADDI, ret, tmp, -1); + } else { + tcg_out_opc_reg(s, OPC_SUB, ret, TCG_REG_ZERO, tmp); + } +} + static void tcg_out_movcond_zicond(TCGContext *s, TCGReg ret, TCGReg test_ne, int val1, bool c_val1, int val2, bool c_val2) @@ -1782,6 +1820,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_setcond(s, args[3], a0, a1, a2, c2); break; + case INDEX_op_negsetcond_i32: + case INDEX_op_negsetcond_i64: + tcg_out_negsetcond(s, args[3], a0, a1, a2, c2); + break; + case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: tcg_out_movcond(s, args[5], a0, a1, a2, c2, @@ -1910,6 +1953,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_xor_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: + case INDEX_op_negsetcond_i32: + case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rI); 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 15/24] tcg/s390x: Implement negsetcond_* Date: Mon, 7 Aug 2023 20:11:34 -0700 Message-Id: <20230808031143.50925-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x331.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.h | 4 +- tcg/s390x/tcg-target.c.inc | 78 +++++++++++++++++++++++++------------- 2 files changed, 54 insertions(+), 28 deletions(-) diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 24e207c2d4..cd3d245be0 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -104,7 +104,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_mulsh_i32 0 #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 -#define TCG_TARGET_HAS_negsetcond_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_div2_i64 1 @@ -139,7 +139,7 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_HAS_muls2_i64 HAVE_FACILITY(MISC_INSN_EXT2) #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 -#define TCG_TARGET_HAS_negsetcond_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_qemu_ldst_i128 1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index a94f7908d6..ecd8aaf2a1 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1266,7 +1266,8 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, } static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, - TCGReg dest, TCGReg c1, TCGArg c2, int c2const) + TCGReg dest, TCGReg c1, TCGArg c2, + bool c2const, bool neg) { int cc; @@ -1275,11 +1276,27 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, /* Emit: d = 0, d = (cc ? 1 : d). */ cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_insn(s, RIEg, LOCGHI, dest, 1, cc); + tcg_out_insn(s, RIEg, LOCGHI, dest, neg ? -1 : 1, cc); return; } - restart: + switch (cond) { + case TCG_COND_GEU: + case TCG_COND_LTU: + case TCG_COND_LT: + case TCG_COND_GE: + /* Swap operands so that we can use LEU/GTU/GT/LE. */ + if (!c2const) { + TCGReg t = c1; + c1 = c2; + c2 = t; + cond = tcg_swap_cond(cond); + } + break; + default: + break; + } + switch (cond) { case TCG_COND_NE: /* X != 0 is X > 0. */ @@ -1292,11 +1309,20 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, case TCG_COND_GTU: case TCG_COND_GT: - /* The result of a compare has CC=2 for GT and CC=3 unused. - ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. */ + /* + * The result of a compare has CC=2 for GT and CC=3 unused. + * ADD LOGICAL WITH CARRY considers (CC & 2) the carry bit. + */ tgen_cmp(s, type, cond, c1, c2, c2const, true); tcg_out_movi(s, type, dest, 0); tcg_out_insn(s, RRE, ALCGR, dest, dest); + if (neg) { + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, LCR, dest, dest); + } else { + tcg_out_insn(s, RRE, LCGR, dest, dest); + } + } return; case TCG_COND_EQ: @@ -1310,27 +1336,17 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, case TCG_COND_LEU: case TCG_COND_LE: - /* As above, but we're looking for borrow, or !carry. - The second insn computes d - d - borrow, or -1 for true - and 0 for false. So we must mask to 1 bit afterward. */ + /* + * As above, but we're looking for borrow, or !carry. + * The second insn computes d - d - borrow, or -1 for true + * and 0 for false. So we must mask to 1 bit afterward. + */ tgen_cmp(s, type, cond, c1, c2, c2const, true); tcg_out_insn(s, RRE, SLBGR, dest, dest); - tgen_andi(s, type, dest, 1); - return; - - case TCG_COND_GEU: - case TCG_COND_LTU: - case TCG_COND_LT: - case TCG_COND_GE: - /* Swap operands so that we can use LEU/GTU/GT/LE. */ - if (!c2const) { - TCGReg t = c1; - c1 = c2; - c2 = t; - cond = tcg_swap_cond(cond); - goto restart; + if (!neg) { + tgen_andi(s, type, dest, 1); } - break; + return; default: g_assert_not_reached(); @@ -1339,7 +1355,7 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, cc = tgen_cmp(s, type, cond, c1, c2, c2const, false); /* Emit: d = 0, t = 1, d = (cc ? t : d). */ tcg_out_movi(s, TCG_TYPE_I64, dest, 0); - tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1); + tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, neg ? -1 : 1); tcg_out_insn(s, RRFc, LOCGR, dest, TCG_TMP0, cc); } @@ -2288,7 +2304,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_setcond_i32: tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], - args[2], const_args[2]); + args[2], const_args[2], false); + break; + case INDEX_op_negsetcond_i32: + tgen_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], + args[2], const_args[2], true); break; case INDEX_op_movcond_i32: tgen_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], @@ -2566,7 +2586,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_setcond_i64: tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], - args[2], const_args[2]); + args[2], const_args[2], false); + break; + case INDEX_op_negsetcond_i64: + tgen_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], + args[2], const_args[2], true); break; case INDEX_op_movcond_i64: tgen_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], @@ -3109,8 +3133,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: case INDEX_op_setcond_i32: + case INDEX_op_negsetcond_i32: return C_O1_I2(r, r, ri); case INDEX_op_setcond_i64: + case INDEX_op_negsetcond_i64: return C_O1_I2(r, r, rA); case INDEX_op_clz_i64: From patchwork Tue Aug 8 03:11:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711558 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1915553rwb; Mon, 7 Aug 2023 20:14:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IErvRszTsQwP9uwnUA4MKpd3HS29P21K8kSn5lxGotISPodiGbinovAYak7DRMB58pA0ML/ X-Received: by 2002:a05:622a:34e:b0:40f:f435:1af7 with SMTP id r14-20020a05622a034e00b0040ff4351af7mr15809978qtw.19.1691464490746; Mon, 07 Aug 2023 20:14:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464490; cv=none; d=google.com; s=arc-20160816; b=e4ChXd72eK/wG+hvLV2xn97ViSNU7Ccztd5vGdvyY3crgKevGioaH4NDrM/EFr5t5V VqNa1BwikCvSrCXnCpTqnFRCjbYbAu8qwSsIaRZMIGnOjjBh9zpkE61VC5SzvgbJt/GM khe9RBZbv25cBFCo9unTUgJGFFvV0BVkq1GcmOPZhQY1zXqHw2flv4sP9Tu9uXzfh14b RVMAvX/suHGA2EVDQp8N3zNP5yo6s3WxAliVgp/LnBnRs1J+IEWTHooxKA8Bzqk09Xlk rmO82zZfuK747EXZ2guaw7XSipcM1w9M+p/ztepFdsSAnv5ffT6TPxknuA1zRR6sVbKs zmOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LA0FQj2p5NOMPjxNHlx5J0GOa6DvzlceCBNs3CReXBc=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=A8QU2dWJSNsG+NapFy8aCMXR7g/C7Cydqn2K/iB8ntMiLSQc7i4v69KHdhiH9LmPOb Esrw11s75vaSeff0yjpNmKSxrWqMKEzhEy+F35pjoUHJfcpA2XlLb+y/iQ1DDHbcRm13 oPKDv0ySBuS33SlhKuT1g7J8M7juzmcGls7jUmtLbfH8w6lGZYQ+BSIWblG+vi+9LS7Q FEF4sbJvCMVmarC11KqYrUS/SRdgVsJxNyJyqu1N4HagXlf1VZ2uQIHS/WnrnAgWXfTF r8DyZhCWGwYmn80+DoXO4M9nz/YhcGQA70oUEwT36HfU6NGuUpytXV1jdV5FWl5DYg5l uMAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kU83p5nP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 16/24] tcg/sparc64: Implement negsetcond_* Date: Mon, 7 Aug 2023 20:11:35 -0700 Message-Id: <20230808031143.50925-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/sparc64/tcg-target.h | 4 ++-- tcg/sparc64/tcg-target.c.inc | 36 ++++++++++++++++++++++++++---------- 2 files changed, 28 insertions(+), 12 deletions(-) diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 1faadc704b..4bbd825bd8 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -112,7 +112,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_negsetcond_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #define TCG_TARGET_HAS_extrl_i64_i32 1 @@ -150,7 +150,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_muls2_i64 0 #define TCG_TARGET_HAS_muluh_i64 use_vis3_instructions #define TCG_TARGET_HAS_mulsh_i64 0 -#define TCG_TARGET_HAS_negsetcond_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_qemu_ldst_i128 0 diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index ffcb879211..37839f9a21 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -720,7 +720,7 @@ static void tcg_out_movcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, } static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg c1, int32_t c2, int c2const) + TCGReg c1, int32_t c2, int c2const, bool neg) { /* For 32-bit comparisons, we can play games with ADDC/SUBC. */ switch (cond) { @@ -760,22 +760,30 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, default: tcg_out_cmp(s, c1, c2, c2const); tcg_out_movi_s13(s, ret, 0); - tcg_out_movcc(s, cond, MOVCC_ICC, ret, 1, 1); + tcg_out_movcc(s, cond, MOVCC_ICC, ret, neg ? -1 : 1, 1); return; } tcg_out_cmp(s, c1, c2, c2const); if (cond == TCG_COND_LTU) { - tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); + if (neg) { + tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_SUBC); + } else { + tcg_out_arithi(s, ret, TCG_REG_G0, 0, ARITH_ADDC); + } } else { - tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); + if (neg) { + tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_ADDC); + } else { + tcg_out_arithi(s, ret, TCG_REG_G0, -1, ARITH_SUBC); + } } } static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, - TCGReg c1, int32_t c2, int c2const) + TCGReg c1, int32_t c2, int c2const, bool neg) { - if (use_vis3_instructions) { + if (use_vis3_instructions && !neg) { switch (cond) { case TCG_COND_NE: if (c2 != 0) { @@ -796,11 +804,11 @@ static void tcg_out_setcond_i64(TCGContext *s, TCGCond cond, TCGReg ret, if the input does not overlap the output. */ if (c2 == 0 && !is_unsigned_cond(cond) && c1 != ret) { tcg_out_movi_s13(s, ret, 0); - tcg_out_movr(s, cond, ret, c1, 1, 1); + tcg_out_movr(s, cond, ret, c1, neg ? -1 : 1, 1); } else { tcg_out_cmp(s, c1, c2, c2const); tcg_out_movi_s13(s, ret, 0); - tcg_out_movcc(s, cond, MOVCC_XCC, ret, 1, 1); + tcg_out_movcc(s, cond, MOVCC_XCC, ret, neg ? -1 : 1, 1); } } @@ -1355,7 +1363,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond_i32(s, a2, a0, a1, const_args[1], arg_label(args[3])); break; case INDEX_op_setcond_i32: - tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2); + tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, false); + break; + case INDEX_op_negsetcond_i32: + tcg_out_setcond_i32(s, args[3], a0, a1, a2, c2, true); break; case INDEX_op_movcond_i32: tcg_out_movcond_i32(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); @@ -1437,7 +1448,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond_i64(s, a2, a0, a1, const_args[1], arg_label(args[3])); break; case INDEX_op_setcond_i64: - tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2); + tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, false); + break; + case INDEX_op_negsetcond_i64: + tcg_out_setcond_i64(s, args[3], a0, a1, a2, c2, true); break; case INDEX_op_movcond_i64: tcg_out_movcond_i64(s, args[5], a0, a1, a2, c2, args[3], const_args[3]); @@ -1564,6 +1578,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sar_i64: case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: + case INDEX_op_negsetcond_i32: + case INDEX_op_negsetcond_i64: return C_O1_I2(r, rZ, rJ); case INDEX_op_brcond_i32: From patchwork Tue Aug 8 03:11:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711547 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1914763rwb; Mon, 7 Aug 2023 20:12:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFCGG34DQfj/OMMcE/wHSCbtbv4RLpIzIjKEF8K9vI7J1yWnTn0U+MhrYEuQu5pQFhnBLb3 X-Received: by 2002:ac8:5d86:0:b0:40f:da27:b3ec with SMTP id d6-20020ac85d86000000b0040fda27b3ecmr15167874qtx.14.1691464358302; Mon, 07 Aug 2023 20:12:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464358; cv=none; d=google.com; s=arc-20160816; b=gM+JmqWsZpdda7F/5gu43ovhpE/JBRTtCUbgL5q7jgCyUtf1aGla4jgP5Hprprj2kY x5aCWK7huKKfPql7JGc/QOK4L6QWVJFDpFpjmd1EKE3g8lm3zg7yqTcW58YSihdlFkts hwj2p8p+uhbXlLkRMoQnMOUccVqiniRzdnvV+OalJkS/3mJyM7czlBrbxYv1kU26e/JZ SabzLKq5Gt9ulMrl7W8/JJb0ktpeGzFvT+nD1obFNAWaU8RYnMVVPAOLYNCWiophNnge Fit0lW9DJ1wm5sJjDqHBS8oT01GZecY+FD6G97Y14cL3vsL/t/rxDb8kqYkx6Ka30jb8 +oPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=t2qRbN3xywAnflNfFcs6TASp0rwMLR7CT6jzuqfZ0as=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=JUYLj51Yy0bbBoiEsEwhO/4H9N0335G3Lh5jG2d8I1aaSJ2/TQnOrbU1Y9qy/hhU+g oVHI1um33w6INAGw54yG3VNxSMqfkD51T8lUTvvNRMM3ZKY2uYjPTSkTgovYjp3pTSBh CFqtJGtjaG1Ke/OZehO3wO9Sc0KRmcfzU/BXu7tVLQb1l3oKIe0fQmmAk4ZujLIBdmcB N6CkSLkmFGob9lR9ibihHdEhErzPIoNjaWTHLvGKwIjftDrq0MPOQf0VB8LvQLF445nh JAedA9h6tGQzgC3/NSOii0iOtT2JR9foJg32d70+N+EHuQ9Ai5gQHB6pR4ohRTGTPFUc QcMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UZaZfncF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 17/24] tcg/i386: Merge tcg_out_brcond{32,64} Date: Mon, 7 Aug 2023 20:11:36 -0700 Message-Id: <20230808031143.50925-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32f; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32f.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass a rexw parameter instead of duplicating the functions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.c.inc | 110 +++++++++++++++++--------------------- 1 file changed, 49 insertions(+), 61 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 77482da070..b9673b55bd 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1433,99 +1433,89 @@ static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, } } -static void tcg_out_brcond32(TCGContext *s, TCGCond cond, - TCGArg arg1, TCGArg arg2, int const_arg2, - TCGLabel *label, int small) +static void tcg_out_brcond(TCGContext *s, int rexw, TCGCond cond, + TCGArg arg1, TCGArg arg2, int const_arg2, + TCGLabel *label, bool small) { - tcg_out_cmp(s, arg1, arg2, const_arg2, 0); + tcg_out_cmp(s, arg1, arg2, const_arg2, rexw); tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); } -#if TCG_TARGET_REG_BITS == 64 -static void tcg_out_brcond64(TCGContext *s, TCGCond cond, - TCGArg arg1, TCGArg arg2, int const_arg2, - TCGLabel *label, int small) -{ - tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); - tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); -} -#else -/* XXX: we implement it at the target level to avoid having to - handle cross basic blocks temporaries */ +#if TCG_TARGET_REG_BITS == 32 static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, - const int *const_args, int small) + const int *const_args, bool small) { TCGLabel *label_next = gen_new_label(); TCGLabel *label_this = arg_label(args[5]); switch(args[4]) { case TCG_COND_EQ: - tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], - label_next, 1); - tcg_out_brcond32(s, TCG_COND_EQ, args[1], args[3], const_args[3], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_NE, args[0], args[2], const_args[2], + label_next, 1); + tcg_out_brcond(s, 0, TCG_COND_EQ, args[1], args[3], const_args[3], + label_this, small); break; case TCG_COND_NE: - tcg_out_brcond32(s, TCG_COND_NE, args[0], args[2], const_args[2], - label_this, small); - tcg_out_brcond32(s, TCG_COND_NE, args[1], args[3], const_args[3], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_NE, args[0], args[2], const_args[2], + label_this, small); + tcg_out_brcond(s, 0, TCG_COND_NE, args[1], args[3], const_args[3], + label_this, small); break; case TCG_COND_LT: - tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_LT, args[1], args[3], const_args[3], + label_this, small); tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_LTU, args[0], args[2], const_args[2], + label_this, small); break; case TCG_COND_LE: - tcg_out_brcond32(s, TCG_COND_LT, args[1], args[3], const_args[3], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_LT, args[1], args[3], const_args[3], + label_this, small); tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_LEU, args[0], args[2], const_args[2], + label_this, small); break; case TCG_COND_GT: - tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_GT, args[1], args[3], const_args[3], + label_this, small); tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_GTU, args[0], args[2], const_args[2], + label_this, small); break; case TCG_COND_GE: - tcg_out_brcond32(s, TCG_COND_GT, args[1], args[3], const_args[3], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_GT, args[1], args[3], const_args[3], + label_this, small); tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_GEU, args[0], args[2], const_args[2], + label_this, small); break; case TCG_COND_LTU: - tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_LTU, args[1], args[3], const_args[3], + label_this, small); tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LTU, args[0], args[2], const_args[2], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_LTU, args[0], args[2], const_args[2], + label_this, small); break; case TCG_COND_LEU: - tcg_out_brcond32(s, TCG_COND_LTU, args[1], args[3], const_args[3], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_LTU, args[1], args[3], const_args[3], + label_this, small); tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_LEU, args[0], args[2], const_args[2], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_LEU, args[0], args[2], const_args[2], + label_this, small); break; case TCG_COND_GTU: - tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_GTU, args[1], args[3], const_args[3], + label_this, small); tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GTU, args[0], args[2], const_args[2], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_GTU, args[0], args[2], const_args[2], + label_this, small); break; case TCG_COND_GEU: - tcg_out_brcond32(s, TCG_COND_GTU, args[1], args[3], const_args[3], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_GTU, args[1], args[3], const_args[3], + label_this, small); tcg_out_jxx(s, JCC_JNE, label_next, 1); - tcg_out_brcond32(s, TCG_COND_GEU, args[0], args[2], const_args[2], - label_this, small); + tcg_out_brcond(s, 0, TCG_COND_GEU, args[0], args[2], const_args[2], + label_this, small); break; default: g_assert_not_reached(); @@ -2571,8 +2561,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1); break; - case INDEX_op_brcond_i32: - tcg_out_brcond32(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); + OP_32_64(brcond): + tcg_out_brcond(s, rexw, a2, a0, a1, const_args[1], + arg_label(args[3]), 0); break; case INDEX_op_setcond_i32: tcg_out_setcond32(s, args[3], a0, a1, a2, const_a2); @@ -2727,9 +2718,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; - case INDEX_op_brcond_i64: - tcg_out_brcond64(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0); 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:12:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 18/24] tcg/i386: Merge tcg_out_setcond{32,64} Date: Mon, 7 Aug 2023 20:11:37 -0700 Message-Id: <20230808031143.50925-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass a rexw parameter instead of duplicating the functions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.c.inc | 24 +++++++----------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index b9673b55bd..ec3c7012d4 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1524,23 +1524,16 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, } #endif -static void tcg_out_setcond32(TCGContext *s, TCGCond cond, TCGArg dest, - TCGArg arg1, TCGArg arg2, int const_arg2) +static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, + TCGArg dest, TCGArg arg1, TCGArg arg2, + int const_arg2) { - tcg_out_cmp(s, arg1, arg2, const_arg2, 0); + tcg_out_cmp(s, arg1, arg2, const_arg2, rexw); tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); tcg_out_ext8u(s, dest, dest); } -#if TCG_TARGET_REG_BITS == 64 -static void tcg_out_setcond64(TCGContext *s, TCGCond cond, TCGArg dest, - TCGArg arg1, TCGArg arg2, int const_arg2) -{ - tcg_out_cmp(s, arg1, arg2, const_arg2, P_REXW); - tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); - tcg_out_ext8u(s, dest, dest); -} -#else +#if TCG_TARGET_REG_BITS == 32 static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, const int *const_args) { @@ -2565,8 +2558,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_brcond(s, rexw, a2, a0, a1, const_args[1], arg_label(args[3]), 0); break; - case INDEX_op_setcond_i32: - tcg_out_setcond32(s, args[3], a0, a1, a2, const_a2); + OP_32_64(setcond): + tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2); break; case INDEX_op_movcond_i32: tcg_out_movcond32(s, args[5], a0, a1, a2, const_a2, args[3]); @@ -2718,9 +2711,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; - case INDEX_op_setcond_i64: - tcg_out_setcond64(s, args[3], a0, a1, a2, const_a2); - break; case INDEX_op_movcond_i64: tcg_out_movcond64(s, args[5], a0, a1, a2, const_a2, args[3]); break; From patchwork Tue Aug 8 03:11:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711565 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1916213rwb; Mon, 7 Aug 2023 20:16:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH9br8I88zrpch7TwFUU/TcaCXKKj7HDzlqQRGiid3SB9llDwyed8qJxiYYHVWgXnMZz6Cg X-Received: by 2002:ac8:5a84:0:b0:403:a1e0:e3e with SMTP id c4-20020ac85a84000000b00403a1e00e3emr14582980qtc.24.1691464612490; Mon, 07 Aug 2023 20:16:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464612; cv=none; d=google.com; s=arc-20160816; b=AyRo1zirjX7H6j/btIKy8EyMVYdSIFKdUcytZOMxfnj9IJWHYmbN1Uj3lY3iobEBCy 6MWsIg0FikcSgusJ0udK6hUpG5ogcelu+pqxPslOulKTpwGLDJIiI8+YGad7dBHp8Rdd GxC4DydWu/B8NgEdeO4Vcr4FcguGMKDygxn9kL6QNvWKhaTe7M/yD2gecXhaPxRimQLg Te38KEfkxqDKJcw3FyWgP3Can/QagNzlxPU1y2jf+C91Vo5AtakHqT2KmAHSrffLbXMr c/ZOKANCB8dxV9hsTGA5WQGIP3G3udwZjCG+IkOZzdpEk9asXg0IR+GFKEo4O4QfcNyu obkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=sfMK4oMzpluAk19ya+JPxEIiB0HyoTLNffeRU4faKRc=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=mFBPObeLrFh/0PGnm1JVDWjg3veTMzU3FTSgdFulhmBvCd18MZ8esTqbAyw/KHjEnG j2RiEgk9LRYLhqLN6GyJievSljvJOZBID1+kKEMClEQCL7wtezbCDQ8PoS+0IWSsBQf5 pprMPy/nysJMJinXAh7jVNe8aOmcsivW4Qj/ZV4jBLwntI+xfOg95o6PrUrcbuvbnbIU t4LSY+3WnVyVOyYolKKomstm6gHj48oPpnO3OnaUusQ1aTBuIE/uHC/F+6I5//GhnI+z 85eTh6xepq23l5zu5JBqWUWvlcGTDJ+dapGQTcgZJSOTNXeRA0DtKZOHkictnxOZlcbd nzVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pCsOwg39; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:12:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 19/24] tcg/i386: Merge tcg_out_movcond{32,64} Date: Mon, 7 Aug 2023 20:11:38 -0700 Message-Id: <20230808031143.50925-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass a rexw parameter instead of duplicating the functions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.c.inc | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index ec3c7012d4..b88fc14afd 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1590,24 +1590,14 @@ static void tcg_out_cmov(TCGContext *s, TCGCond cond, int rexw, } } -static void tcg_out_movcond32(TCGContext *s, TCGCond cond, TCGReg dest, - TCGReg c1, TCGArg c2, int const_c2, - TCGReg v1) +static void tcg_out_movcond(TCGContext *s, int rexw, TCGCond cond, + TCGReg dest, TCGReg c1, TCGArg c2, int const_c2, + TCGReg v1) { - tcg_out_cmp(s, c1, c2, const_c2, 0); - tcg_out_cmov(s, cond, 0, dest, v1); + tcg_out_cmp(s, c1, c2, const_c2, rexw); + tcg_out_cmov(s, cond, rexw, dest, v1); } -#if TCG_TARGET_REG_BITS == 64 -static void tcg_out_movcond64(TCGContext *s, TCGCond cond, TCGReg dest, - TCGReg c1, TCGArg c2, int const_c2, - TCGReg v1) -{ - tcg_out_cmp(s, c1, c2, const_c2, P_REXW); - tcg_out_cmov(s, cond, P_REXW, dest, v1); -} -#endif - static void tcg_out_ctz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, TCGArg arg2, bool const_a2) { @@ -2561,8 +2551,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, OP_32_64(setcond): tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2); break; - case INDEX_op_movcond_i32: - tcg_out_movcond32(s, args[5], a0, a1, a2, const_a2, args[3]); + OP_32_64(movcond): + tcg_out_movcond(s, rexw, args[5], a0, a1, a2, const_a2, args[3]); break; OP_32_64(bswap16): @@ -2711,10 +2701,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; - case INDEX_op_movcond_i64: - tcg_out_movcond64(s, args[5], a0, a1, a2, const_a2, args[3]); - break; - case INDEX_op_bswap64_i64: tcg_out_bswap64(s, a0); break; From patchwork Tue Aug 8 03:11:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711564 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1916030rwb; Mon, 7 Aug 2023 20:16:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEp8VyOcIJIB4/fwO4T6+iWPRbMRGOg6Talytz6t//XXjAS8FD68YNnxWSissCRuWXJpVDQ X-Received: by 2002:a0c:a9ca:0:b0:63d:2b84:a3b0 with SMTP id c10-20020a0ca9ca000000b0063d2b84a3b0mr8409111qvb.49.1691464576748; Mon, 07 Aug 2023 20:16:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464576; cv=none; d=google.com; s=arc-20160816; b=gYf6UcSTZE+qmptBHv1ddublQNnGCBcU/zBGulbgPcFa0dCeKBMtgyaf3Ul/OScZey qcD+pd22JWd9VVOXmXvqExVBaqcsuFtwF1YWX4sYGdBca+0GfaCudFRXkaEWV0VfAJFj Mn07S0cckzvaXmu7KFlUe53lbptYGUmMgK5Z+oDWIYxeLg+hNQUZZPiP6KMyxnFjPKyB xCXFwqOrlvfFhD/VHF9X2nG7q8KEjcnwW4H/iFACxxRIjo/QDTzStE1pcMOkSoI21aik K79UCbdFg2obSsJbyGY28bXd+EB3BovPQ4H+73yixyho7dWx9CvJwTVwpP6M9szMqHUs jY0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tmotEscJTq84Ab7ZtBPgGyq95MOlwaj6T0nGog5dLQg=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=aaP9vrTto53/LPtF8DoSMrC/bPe9eUxGib2zjvbxqRZIobNNEQHLDRFA52RomKaQV4 79tG+6aGcvyaqlapHeRu+eh6tvGy/BUv/+dYL9V+FNgymb9WkWPlV1ukoEx295bqGu7S 56qK6QlppJDq6kRouaR2EPKxgXIHu9KgsSfVb6BoinddX42Vps1R8Od3yoVr+GoGI85w IkCwXDhR0+VpgpfEKLh37ofj/D6S95469W9wdNRZxg0a4Ag4NfFqH+3sAA/GBXvJgJ3f 3h5exQCsjUpB7xPqzAVCRsBkX5BBOJ+3EqdR4m+hwD9+UgDiNlVng0ozE0bNUyz6kEfO eDKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ei4t0Zwi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.12.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:12:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 20/24] tcg/i386: Add cf parameter to tcg_out_cmp Date: Mon, 7 Aug 2023 20:11:39 -0700 Message-Id: <20230808031143.50925-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32b.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add the parameter to avoid TEST and pass along to tgen_arithi. All current users pass false. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index b88fc14afd..56549ff2a0 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1418,15 +1418,15 @@ static void tcg_out_jxx(TCGContext *s, int opc, TCGLabel *l, bool small) } } -static void tcg_out_cmp(TCGContext *s, TCGArg arg1, TCGArg arg2, - int const_arg2, int rexw) +static void tcg_out_cmp(TCGContext *s, int rexw, TCGArg arg1, TCGArg arg2, + int const_arg2, bool cf) { if (const_arg2) { - if (arg2 == 0) { + if (arg2 == 0 && !cf) { /* test r, r */ tcg_out_modrm(s, OPC_TESTL + rexw, arg1, arg1); } else { - tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, 0); + tgen_arithi(s, ARITH_CMP + rexw, arg1, arg2, cf); } } else { tgen_arithr(s, ARITH_CMP + rexw, arg1, arg2); @@ -1437,7 +1437,7 @@ static void tcg_out_brcond(TCGContext *s, int rexw, TCGCond cond, TCGArg arg1, TCGArg arg2, int const_arg2, TCGLabel *label, bool small) { - tcg_out_cmp(s, arg1, arg2, const_arg2, rexw); + tcg_out_cmp(s, rexw, arg1, arg2, const_arg2, false); tcg_out_jxx(s, tcg_cond_to_jcc[cond], label, small); } @@ -1528,7 +1528,7 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, TCGArg dest, TCGArg arg1, TCGArg arg2, int const_arg2) { - tcg_out_cmp(s, arg1, arg2, const_arg2, rexw); + tcg_out_cmp(s, rexw, arg1, arg2, const_arg2, false); tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); tcg_out_ext8u(s, dest, dest); } @@ -1594,7 +1594,7 @@ static void tcg_out_movcond(TCGContext *s, int rexw, TCGCond cond, TCGReg dest, TCGReg c1, TCGArg c2, int const_c2, TCGReg v1) { - tcg_out_cmp(s, c1, c2, const_c2, rexw); + tcg_out_cmp(s, rexw, c1, c2, const_c2, false); tcg_out_cmov(s, cond, rexw, dest, v1); } @@ -1637,7 +1637,7 @@ static void tcg_out_clz(TCGContext *s, int rexw, TCGReg dest, TCGReg arg1, tgen_arithi(s, ARITH_XOR + rexw, dest, rexw ? 63 : 31, 0); /* Since we have destroyed the flags from BSR, we have to re-test. */ - tcg_out_cmp(s, arg1, 0, 1, rexw); + tcg_out_cmp(s, rexw, arg1, 0, 1, false); tcg_out_cmov(s, TCG_COND_EQ, rexw, dest, arg2); } } From patchwork Tue Aug 8 03:11:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711563 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1916010rwb; Mon, 7 Aug 2023 20:16:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEkg70RFxjR7AUHNLcg+vR+PyCbkRgtXCJUI1o1Qj2DGNZ6DW+tJl0NbSm7cjxRRGWEq9j1 X-Received: by 2002:ac8:5a45:0:b0:40c:7b4:37a9 with SMTP id o5-20020ac85a45000000b0040c07b437a9mr15783390qta.51.1691464575022; Mon, 07 Aug 2023 20:16:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464575; cv=none; d=google.com; s=arc-20160816; b=viZTQpueVgB7dUQ0qGOUgJQGdGtoe9rAi54bpTpouTNkUNtsQgqdJ4Uxv/AsmTOHzZ zYDrr30BcHpjt0VOTb6WvbRL+UpwFkjAkPhekilMNcDhFNQ7UeE/RJdRr7FxIN8V+LMM F/uODd8ZyVDX/5m+ApG6qRNMkR1W55jmfttqO+5FqWbDPJ6+4BrgnkXyap6MqUBOuZgy 5ngVq1JFKy7GfkxBL6PJEPXa9RB6qYBj24W/QGOtv8SN89mo8E+rhOw9NeWUmXtoUMeg Btf7zT8bFWhUGDpQesAXengberO/a2a7wGk4gi5s/I7AsndyzPoocPoJ2AfcYMNUM0m4 t67w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/f7JkVfHL643EJ3O1Eknq2OobIgOuuERSYG+cUCRBXY=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=uzJuPdq9jqGrf2Y4m5Iv6UQh/i/Kkb4768hnEsXEVhqzluCRXZUVla1Agjk68xTHuH KIJn6qjGiBtl1voX0v/lXOBMiXpOQKKpcvBAGkxlbXzCVKf24fyRV4mXNv1qmg346CA6 iNyaZzC+HAjrQ7JcWtwdm9vwwyOV+0HTWzg48sPGwK1zZYY0N0xTsrwIQlzi6+BC4Hra QDSjKZM3EWR6KpiKhNQlPttCMkbYEK89JvnpJW6CgskdaW4SKVImID/d/KzHHtGFNXhx isXJvxy9Dnxzkt4u6sjHqM3vUylEt0tcHqp4fHEnUq1BNk48CmUq9CvmHJzCYH5yVxZt GdUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zT39XaoS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.12.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:12:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 21/24] tcg/i386: Use CMP+SBB in tcg_out_setcond Date: Mon, 7 Aug 2023 20:11:40 -0700 Message-Id: <20230808031143.50925-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::730; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x730.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use the carry bit to optimize some forms of setcond. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.c.inc | 50 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 56549ff2a0..e06ac638b0 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1528,6 +1528,56 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, TCGArg dest, TCGArg arg1, TCGArg arg2, int const_arg2) { + bool inv = false; + + switch (cond) { + case TCG_COND_NE: + inv = true; + /* fall through */ + case TCG_COND_EQ: + /* If arg2 is 0, convert to LTU/GEU vs 1. */ + if (const_arg2 && arg2 == 0) { + arg2 = 1; + goto do_ltu; + } + break; + + case TCG_COND_LEU: + inv = true; + /* fall through */ + case TCG_COND_GTU: + /* If arg2 is a register, swap for LTU/GEU. */ + if (!const_arg2) { + TCGReg t = arg1; + arg1 = arg2; + arg2 = t; + goto do_ltu; + } + break; + + case TCG_COND_GEU: + inv = true; + /* fall through */ + case TCG_COND_LTU: + do_ltu: + /* + * Relying on the carry bit, use SBB to produce -1 if LTU, 0 if GEU. + * We can then use NEG or INC to produce the desired result. + * This is always smaller than the SETCC expansion. + */ + tcg_out_cmp(s, rexw, arg1, arg2, const_arg2, true); + tgen_arithr(s, ARITH_SBB, dest, dest); /* T:-1 F:0 */ + if (inv) { + tgen_arithi(s, ARITH_ADD, dest, 1, 0); /* T:0 F:1 */ + } else { + tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NEG, dest); /* T:1 F:0 */ + } + return; + + default: + break; + } + tcg_out_cmp(s, rexw, arg1, arg2, const_arg2, false); tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); tcg_out_ext8u(s, dest, dest); From patchwork Tue Aug 8 03:11:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711568 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1916533rwb; Mon, 7 Aug 2023 20:17:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEJkB69dS9RVMoaNvYlNaeVivYUdWHPrDuRVs3BB7VMpFYBMLEaGdcLBqSTbTHb7Uh1y9Tq X-Received: by 2002:a05:620a:47b0:b0:768:3bef:da86 with SMTP id dt48-20020a05620a47b000b007683befda86mr14676647qkb.37.1691464671028; Mon, 07 Aug 2023 20:17:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464671; cv=none; d=google.com; s=arc-20160816; b=RkrGn4vuYEkxDoBn28XsYR+X86p/e3GImWRMtPtXoSzCd/OB5u1IjV3hcjtVUkaWAZ xCrU4lkm4fHDjmxQO0XAYbASA91CcKiGFmvUUQmuGF7+NaPS4t2dt4sc+St6tsG20Zs5 OMMikgsO6l8IuVAmmjhWE8pHun2yeuK+Dq0MSiLjvHxfcuOjlRyfu1ny1C7v5NA4RtDE lZdy+9Uf+n78ZFrmz63uaB9vjYYw2k9bcBfutTLCiGSV1YMT/3ptWqV95DTFO4/Rx/4L a9j/fLf6MYSuP4NPjNV8mEEGF0Gk9Cuof4s0GwzluGlVSZvi41WsmDvi4AUuZmK1Z3zX Lplw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kot5PEmuPDK/CyGN6ee3rwJzaEBsQpYk5OnUPUMG6UA=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=hoEO/EVnoaa1UV/BNLpiHHpdEbFECKsyc8SMtDx+pjat5xdlagnqHxyeVnUlrNuvst ABeUFoqx8OZKf8lXD9PtjXln+FeePtIqhcgDpzwKEmxLUPfMwahLUqXlALll0BP3LXM0 RF1vpK6DfXZj5IeGbDqCNwCfa962VANHAD+LWGLyoLb0OEOYf5gJ7GbrESTDP3Aa49iw 5oJyxxkJZXW04nzGYywSA4ojGH6ZmB4acQ5wCQ9eRugckJwklNwgMuPFQXLulkmjBlRh uk+EFISYJoQ2uFSyMpfYS3NZx+J4mk2Eh4zNPZ/3hMS7r4nvV5OqGTkExOrALDQdF4w+ rJ9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="H0N+6wB/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.12.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:12:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 22/24] tcg/i386: Clear dest first in tcg_out_setcond if possible Date: Mon, 7 Aug 2023 20:11:41 -0700 Message-Id: <20230808031143.50925-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72d; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72d.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Using XOR first is both smaller and more efficient, though cannot be applied if it clobbers an input. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.c.inc | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index e06ac638b0..cca49fe63a 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1529,6 +1529,7 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, int const_arg2) { bool inv = false; + bool cleared; switch (cond) { case TCG_COND_NE: @@ -1578,9 +1579,23 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, break; } + /* + * If dest does not overlap the inputs, clearing it first is preferred. + * The XOR breaks any false dependency for the low-byte write to dest, + * and is also one byte smaller than MOVZBL. + */ + cleared = false; + if (dest != arg1 && (const_arg2 || dest != arg2)) { + tgen_arithr(s, ARITH_XOR, dest, dest); + cleared = true; + } + tcg_out_cmp(s, rexw, arg1, arg2, const_arg2, false); tcg_out_modrm(s, OPC_SETCC | tcg_cond_to_jcc[cond], 0, dest); - tcg_out_ext8u(s, dest, dest); + + if (!cleared) { + tcg_out_ext8u(s, dest, dest); + } } #if TCG_TARGET_REG_BITS == 32 From patchwork Tue Aug 8 03:11:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711549 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1914930rwb; Mon, 7 Aug 2023 20:13:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFJRxZ8QUuKtVJ/q8ekGq6cwLC8dP6pRoaIOpgjSa8M8emruvSUjxRFIzsjc8QIyqECwXyL X-Received: by 2002:a05:6214:448b:b0:631:e5e4:a936 with SMTP id on11-20020a056214448b00b00631e5e4a936mr11719808qvb.28.1691464385927; Mon, 07 Aug 2023 20:13:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464385; cv=none; d=google.com; s=arc-20160816; b=T4qnfjwameZYcDxhj6W4mT5lnMgSugMRvGv4J/5U9SM50RRJRoT9/8bCE9UW/j0f4a VYV5V1AEs06pd5trrrrHp3th74keyljHCk3olOOby8vtMn+ecscz6bzW3fOTWN0tisnL cDwUTngVPeXHuaeGivkXU/BKt1yDba+5tUz+oTH1zDEQXXAupPiXVc4CPFSZ7MBPwA7B YT9eCAcxQRE8Lnfo7sarKQ2/SJ9lCBajTL/VEa64dVHn1TCHuUUJ/hC74cU/LsOy1sCI yhE07dnhb8PmqUZyuJr0/6uPChogjaUGuOVCWVCu/1Tt9Ynj3v/SF7NdzUxczMctamlQ 2Z5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6EOxe5rq5CkC99jUD9BB2Rzj7nk3YmOBqVYbqZbgC9Y=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=ht2129NmqfQtrtRmwbzoNdW4I4z9i1b+XcNzZn3A5HigCcFir1Dr4BdoQ51FLmWB0O S4DXiQUDqsAdeOYduZg6pe2EM4JnYj08RF+wHxdC9bnwBS2Cx8GpW5FtcQFaqC6VyEh9 ghjpvLk7hfF2qhgBu3o+kkzJ/EMjEKi3BXCito2LrQRP1HtbgNn1oqgRrfrC+xy9jZ6S IMlcdtvQ8sWu5ZCWXyQw7jxjxpyWPl49tpYVQ9SH/fYqGbar/ZPoufTCxwlwwEkRXm/Q wR+FS6UwbtkJUV66Xqxj6Man/+rHMrEK3nPsvF1Ikjl0vTBgdqONdXDDBQENpjV31gvW /Fvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YtCr5WT4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.12.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:12:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 23/24] tcg/i386: Use shift in tcg_out_setcond Date: Mon, 7 Aug 2023 20:11:42 -0700 Message-Id: <20230808031143.50925-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For LT/GE vs zero, shift down the sign bit. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.c.inc | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index cca49fe63a..f68722b8a5 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1575,6 +1575,21 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, } return; + case TCG_COND_GE: + inv = true; + /* fall through */ + case TCG_COND_LT: + /* If arg2 is 0, extract the sign bit. */ + if (const_arg2 && arg2 == 0) { + tcg_out_mov(s, rexw ? TCG_TYPE_I64 : TCG_TYPE_I32, dest, arg1); + if (inv) { + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest); + } + tcg_out_shifti(s, SHIFT_SHR + rexw, dest, rexw ? 63 : 31); + return; + } + break; + default: break; } From patchwork Tue Aug 8 03:11:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711561 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1915730rwb; Mon, 7 Aug 2023 20:15:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHYpoIXpBKavfTWqevCz1W2tQ1MHDc2fXAEvP4BNW41ltFOjMrVc2E0sItqie9VdITiCjBV X-Received: by 2002:a0c:b299:0:b0:631:fb35:27e1 with SMTP id r25-20020a0cb299000000b00631fb3527e1mr9446078qve.4.1691464523687; Mon, 07 Aug 2023 20:15:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464523; cv=none; d=google.com; s=arc-20160816; b=CXIg+2vmsbp7yxm6wAnSSIt7iPV2wAFNA20KUwOrAZUNieqJZ8G2NwrRmT+elkte6F dko6XhTn4iuRNK38ff2rzrTXIkxpD45yxWXyGtut48XC17ZDdiu8Wx9EzfiiBe7xXm4s T3ee8sUF6Oinu6MnWwEfHITjhJYCruCN7ceP4ugSTL0IzuRZ70mJok1+jauNe6dGc57q yqmK6EpuqcBFmj9dD/E3maLUIteihIAsNbHbTBCjliTN+QneYUyo8Q5O5a2hMyGQr+uR tLXk2biEzioAN2NpcFU9qty+c07tVBvCculgqxIlxsjoArxHeUZp/2xxyJ1HC9sjARu6 M6/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=K5i2/ldl7oLGbxu7tue5+kLhhv2CxQ17wq9IIxK3hMA=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=gxU4EyDhfHOjRtVTuwd0pfoY1npktIaqkoYwa+hnL+R/xNp2Xo3ScnOlrpdL2iqxcX 9CZ4PUdgRnpCeccpLEWDhoak6vAMilEqeT+pXd5wsv/382SGNlmckpirWCVQMXtXEbUf USUIqT+XSRYphdJDu5da0gjuMv1iJXoWDWfnMH0KgKYVcA7KdvBfG+x0jdRVEE7raJ3O OvIabYUIdGx5yDbPlWroAHOPxT+luvSqYooo33gXv2ZhLJNyH3lzW1G6KLWuRcCeKbvS hPv4Fb6XnrkvvAlcrkItv2D7IA8/Xc40o6kZLJpBlXAq2MrIi7+NocNnV4t/3PHWFHVh a1DQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rq6GfIBS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.12.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:12:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 24/24] tcg/i386: Implement negsetcond_* Date: Mon, 7 Aug 2023 20:11:43 -0700 Message-Id: <20230808031143.50925-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72c.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/i386/tcg-target.h | 4 ++-- tcg/i386/tcg-target.c.inc | 27 +++++++++++++++++++-------- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 41df0e5ae1..1a9025d786 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -156,7 +156,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i32 1 #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_negsetcond_i32 0 +#define TCG_TARGET_HAS_negsetcond_i32 1 #if TCG_TARGET_REG_BITS == 64 /* Keep 32-bit values zero-extended in a register. */ @@ -194,7 +194,7 @@ typedef enum { #define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 -#define TCG_TARGET_HAS_negsetcond_i64 0 +#define TCG_TARGET_HAS_negsetcond_i64 1 #define TCG_TARGET_HAS_qemu_st8_i32 0 #else #define TCG_TARGET_HAS_qemu_st8_i32 1 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index f68722b8a5..cc75653bb8 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1526,7 +1526,7 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, TCGArg dest, TCGArg arg1, TCGArg arg2, - int const_arg2) + int const_arg2, bool neg) { bool inv = false; bool cleared; @@ -1567,11 +1567,13 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, * This is always smaller than the SETCC expansion. */ tcg_out_cmp(s, rexw, arg1, arg2, const_arg2, true); - tgen_arithr(s, ARITH_SBB, dest, dest); /* T:-1 F:0 */ - if (inv) { - tgen_arithi(s, ARITH_ADD, dest, 1, 0); /* T:0 F:1 */ - } else { - tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NEG, dest); /* T:1 F:0 */ + tgen_arithr(s, ARITH_SBB + (neg ? rexw : 0), dest, dest); /* T:-1 F:0 */ + if (inv && neg) { + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest); /* T:0 F:-1 */ + } else if (inv) { + tgen_arithi(s, ARITH_ADD, dest, 1, 0); /* T:0 F:1 */ + } else if (!neg) { + tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_NEG, dest); /* T:1 F:0 */ } return; @@ -1585,7 +1587,8 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, if (inv) { tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NOT, dest); } - tcg_out_shifti(s, SHIFT_SHR + rexw, dest, rexw ? 63 : 31); + tcg_out_shifti(s, (neg ? SHIFT_SAR : SHIFT_SHR) + rexw, + dest, rexw ? 63 : 31); return; } break; @@ -1611,6 +1614,9 @@ static void tcg_out_setcond(TCGContext *s, int rexw, TCGCond cond, if (!cleared) { tcg_out_ext8u(s, dest, dest); } + if (neg) { + tcg_out_modrm(s, OPC_GRP3_Ev + rexw, EXT3_NEG, dest); + } } #if TCG_TARGET_REG_BITS == 32 @@ -2629,7 +2635,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, arg_label(args[3]), 0); break; OP_32_64(setcond): - tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2); + tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2, false); + break; + OP_32_64(negsetcond): + tcg_out_setcond(s, rexw, args[3], a0, a1, a2, const_a2, true); break; OP_32_64(movcond): tcg_out_movcond(s, rexw, args[5], a0, a1, a2, const_a2, args[3]); @@ -3357,6 +3366,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_setcond_i32: case INDEX_op_setcond_i64: + case INDEX_op_negsetcond_i32: + case INDEX_op_negsetcond_i64: return C_O1_I2(q, r, re); case INDEX_op_movcond_i32: