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[209.51.188.17]) by mx.google.com with ESMTPS id j13-20020a056102134d00b004479d0c005csi616188vsl.664.2023.08.07.07.15.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 Aug 2023 07:15:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b9GWWpqX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qT10z-000076-RF; Mon, 07 Aug 2023 10:15:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qT10y-00005U-6v for qemu-devel@nongnu.org; Mon, 07 Aug 2023 10:15:20 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qT10w-0005RC-Gj for qemu-devel@nongnu.org; Mon, 07 Aug 2023 10:15:19 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3fe4cdb724cso25946915e9.1 for ; Mon, 07 Aug 2023 07:15:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691417717; x=1692022517; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=Bd+htH+P/WAjyuut/9qNXD2yHqngSJFvzj95KpMX1XE=; b=b9GWWpqXYW/sxNzDU1E9+PZeNZADDu5zouObLzVPCQcoP4Q0517U1RCjfzutnvs5qo QOILXRh/Df8QxzEgRWrkmlVetzFYs6EFCkAQ+hdWWyQpcf2qNj/zFsjPAdJ1W14ZeSQ6 sQYhmiemo+8aBhlWD+rAIYKQDGrsqzwUz46f22odvZJaQWMhG+VWDomJsPg+yja7LT0L b+DJdEC59q+8Ks5JWNndKupjs3gfKcd3UuvsZQBQ0d4qp1x1vGLJjUcR8brGoLAkwkjB 0vI+MglgY1QbNuGlWzjqYJbB/diNdsDMNufycfaqt/jfOwOW7nnLmcUCi6DL0PLW3CoJ RHpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691417717; x=1692022517; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bd+htH+P/WAjyuut/9qNXD2yHqngSJFvzj95KpMX1XE=; b=DMOR69zuhhXf034eKLvmPxkmHwXNyU5If0OT8DQntGvJAOr6gPXj+LEXwzxf//6IO7 CBr2ylfdAxeIkx4Nqk6funMMJ3EjZSiz3wdHpy1t++faWgpES/FZOq13NcWJfut6IHYf WA6QlkxSPE3xpxZ5DWPDwXVdy/mpmcSe4dH+2N8c5igjRlZhdC0c3aISDJ0T02sMRw1Q DIGmtIVuo8iOUQan8hNzpkkQaTspIEKXdyRJja5Z+y+0fn9lnBXmGkRnS05zcZEo/aA2 s2foEwxNJLBAxfzefAGNpdcxywpRzWweCJ9D99hpOpPO9Ag+3gcZ2z3beAf2nb9b40E3 RKDA== X-Gm-Message-State: AOJu0YwKyycrjdPj3ODuWhKr8ITcAk4//kSdP/UjxD8dbtsuP03XQCcq eNtZ9KGLR2k4hvNgdQo923sJphhZytOdif8oYYc= X-Received: by 2002:a7b:c846:0:b0:3fe:20ef:1d32 with SMTP id c6-20020a7bc846000000b003fe20ef1d32mr7428318wml.10.1691417717000; Mon, 07 Aug 2023 07:15:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:16 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 01/15] target/arm/ptw: Don't set fi->s1ptw for UnsuppAtomicUpdate fault Date: Mon, 7 Aug 2023 15:15:00 +0100 Message-Id: <20230807141514.19075-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org For an Unsupported Atomic Update fault where the stage 1 translation table descriptor update can't be done because it's to an unsupported memory type, this is a stage 1 abort (per the Arm ARM R_VSXXT). This means we should not set fi->s1ptw, because this will cause the code in the get_phys_addr_lpae() error-exit path to mark it as stage 2. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8f94100c61f..bafeb876ad7 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -701,7 +701,6 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, if (unlikely(!host)) { fi->type = ARMFault_UnsuppAtomicUpdate; - fi->s1ptw = true; return 0; } From patchwork Mon Aug 7 14:15:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711114 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1564549rwb; Mon, 7 Aug 2023 07:16:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEPYJQbHyKdt3tdhzRUUSVk2tWBnFy8zf9YUm6eKFqCTcgLv/2K3pPbjJLeTpLGi+r+NnR2 X-Received: by 2002:a67:f550:0:b0:443:9248:3410 with SMTP id z16-20020a67f550000000b0044392483410mr4061713vsn.32.1691417772601; Mon, 07 Aug 2023 07:16:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417772; cv=none; d=google.com; s=arc-20160816; b=yTNsPto1qmpiDQYQzsCmqNLmjaa9pA8PJH775YdYDiDVRRsRcWEvj446fnnyYDZwro jm82EowIgawhmfWr1zGBGdqforrTz0/ywWxHsSdqYQ1GYj8apf2STOTsxR/7126eoPf5 113iUeNKDfxqlI9SrEBc+sBVWfFmlj5R0hInZ+PkpYlj5fjGp72Iz37hW550J8gj5rWs muEwTQqD2nUUKZE2u5XwmiNZJXOv3llCGoJ03Z4ri4ykw31wRxO8xXy1TWvPVyXty+Tj SJWMpYsZ5zcAOdYs4iu+ML8ZSkMAJx0LP16jrMZsB7ovU48UPRF8x3ptFp527cKOzrYp WCIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=mTF0rpR5T9/+RGJwHtQl5zTiqKLJXEt3Fbl4hFG5dDw=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=FqjNksnlWgAc7pecnruCUPwpvzk6G4Ke3oamyRrFtC6N1tqGwHJfOh3UwtAvEVPSjC Kxhts8kGOudh4XtDG+6vTUpsJsMpAWEm0EssAoJY4DzLkit+rUzPXo9mgNVjvI6L9iNG ddbNAN/By3295/o3sAmqLR5+ENMclfQQ3NA5BlWoAT/OHp1k8VYsTtmpMxNWWlb8mcWN v/58RzbZF9F/+n8HFkboabluFGmWAjv1rE3ghJs1hM4DOvyqmJI+302F+MOB64BCVyDX 2hCfe/BIo1aEQcqLDtlcxOADJ9BZdGfJzwVWUOmGpRgZLPzqwK654e2a+JmNJtl46TSy MWBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kmnnw5f6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 02/15] target/arm/ptw: Don't report GPC faults on stage 1 ptw as stage2 faults Date: Mon, 7 Aug 2023 15:15:01 +0100 Message-Id: <20230807141514.19075-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In S1_ptw_translate() we set up the ARMMMUFaultInfo if the attempt to translate the page descriptor address into a physical address fails. This used to only be possible if we are doing a stage 2 ptw for that descriptor address, and so the code always sets fi->stage2 and fi->s1ptw to true. However, with FEAT_RME it is also possible for the lookup of the page descriptor address to fail because of a Granule Protection Check fault. These should not be reported as stage 2, otherwise arm_deliver_fault() will incorrectly set HPFAR_EL2. Similarly the s1ptw bit should only be set for stage 2 faults on stage 1 translation table walks, i.e. not for GPC faults. Add a comment to the the other place where we might detect a stage2-fault-on-stage-1-ptw, in arm_casq_ptw(), noting why we know in that case that it must really be a stage 2 fault and not a GPC fault. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index bafeb876ad7..eb57ebd897b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -600,8 +600,8 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fi->type = ARMFault_GPCFOnWalk; } fi->s2addr = addr; - fi->stage2 = true; - fi->s1ptw = true; + fi->stage2 = regime_is_stage2(s2_mmu_idx); + fi->s1ptw = fi->stage2; fi->s1ns = !is_secure; return false; } @@ -719,6 +719,12 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, env->tlb_fi = NULL; if (unlikely(flags & TLB_INVALID_MASK)) { + /* + * We know this must be a stage 2 fault because the granule + * protection table does not separately track read and write + * permission, so all GPC faults are caught in S1_ptw_translate(): + * we only get here for "readable but not writeable". + */ assert(fi->type != ARMFault_None); fi->s2addr = ptw->out_virt; fi->stage2 = true; From patchwork Mon Aug 7 14:15:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711123 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1565653rwb; Mon, 7 Aug 2023 07:17:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGiT3v3T+SoNV6o9triEG1FeEAUmwdA3Q2X+i/ST6DKv3gshOm2dS9QadI7Sbg+w14lePhT X-Received: by 2002:a1f:4513:0:b0:487:17be:114d with SMTP id s19-20020a1f4513000000b0048717be114dmr4591408vka.8.1691417860909; Mon, 07 Aug 2023 07:17:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417860; cv=none; d=google.com; s=arc-20160816; b=DzYGHhfBT/eE0ek8w6h+Yz0kDf7PbqtDuAq/D88I6rEPnFvhGtLocwrwkKTdoysIY8 8Q9j2xNEW4VHmzjQIyuhFtP74eKPa8teOC4TtHX1UxwPyI66F2vQ36Pt62gVmr4IBkwM nZMeUxsTXhjQuQgUlUv0fAMa0uPZDpYye5wYC2692VkrmeZMs7w3Nx3oPau1g73nlYe6 I5smI/r9fpi/wJ0aRbKYK1XzBjmQ0o8i940JPST7Io3tRNQMah2F7sYNOWH/GbCjlO5C NywXfyZhp937N8oiof8h+5NU6khgCw6jUrBcGj4ExGQfQ5xKIhfs8uZdpouOQV92D6BO 7ofA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lEu4y95quZyOnfSNj/UQtZgzoOcsDey9aZLknEbvT3o=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=bvteMpzugMEHjXCeya2+MBBHVfo7XzWhA15Y9qOX/eULDxHdGyJRyU8XksjMY/rhSs 7NE9E1YjLOcUFDRhidshzaeRfEprL3Wn15rKlOI2IJoN0+AeB6Ws4uqXZpuH0nlafU/o QC2CPUThmN4Wtye28F+Spymt4JJvu7xKomoEZboUx/giJEamS9RJTFMiHYUWgrciP4gL gK1ubc2uUf9yfq5eehBGv/Uv4/2sDHsHqVxeCE8UP21Sf3mzYzKijFcFBTo3Audag/M3 BSPRxmQL+KmCP3PO6/x4Pqqa6ojWEuy9uVG36PirLEW+hbMtVVN4kVmiwJSnxc0V1yjD X0Vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zyd9Hod5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 03/15] target/arm/ptw: Set s1ns bit in fault info more consistently Date: Mon, 7 Aug 2023 15:15:02 +0100 Message-Id: <20230807141514.19075-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The s1ns bit in ARMMMUFaultInfo is documented as "true if we faulted on a non-secure IPA while in secure state". Both the places which look at this bit only do so after having confirmed that this is a stage 2 fault and we're dealing with Secure EL2, which leaves the ptw.c code free to set the bit to any random value in the other cases. Instead of taking advantage of that freedom, consistently make the bit be set to false for the "not a stage 2 fault for Secure EL2" cases. This removes some cases where we were using an 'is_secure' boolean and leaving the reader guessing about whether that was the right thing for Realm and Root cases. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index eb57ebd897b..67078ae3509 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -514,6 +514,17 @@ static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space, } } +static bool fault_s1ns(ARMSecuritySpace space, ARMMMUIdx s2_mmu_idx) +{ + /* + * For stage 2 faults in Secure EL22, S1NS indicates + * whether the faulting IPA is in the Secure or NonSecure + * IPA space. For all other kinds of fault, it is false. + */ + return space == ARMSS_Secure && regime_is_stage2(s2_mmu_idx) + && s2_mmu_idx == ARMMMUIdx_Stage2_S; +} + /* Translate a S1 pagetable walk through S2 if needed. */ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) @@ -586,7 +597,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fi->s2addr = addr; fi->stage2 = true; fi->s1ptw = true; - fi->s1ns = !is_secure; + fi->s1ns = fault_s1ns(ptw->in_space, s2_mmu_idx); return false; } } @@ -602,7 +613,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, fi->s2addr = addr; fi->stage2 = regime_is_stage2(s2_mmu_idx); fi->s1ptw = fi->stage2; - fi->s1ns = !is_secure; + fi->s1ns = fault_s1ns(ptw->in_space, s2_mmu_idx); return false; } @@ -729,7 +740,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, fi->s2addr = ptw->out_virt; fi->stage2 = true; fi->s1ptw = true; - fi->s1ns = !ptw->in_secure; + fi->s1ns = fault_s1ns(ptw->in_space, ptw->in_ptw_idx); return 0; } @@ -2030,7 +2041,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, fi->level = level; /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ fi->stage2 = fi->s1ptw || regime_is_stage2(mmu_idx); - fi->s1ns = mmu_idx == ARMMMUIdx_Stage2; + fi->s1ns = fault_s1ns(ptw->in_space, mmu_idx); return true; } From patchwork Mon Aug 7 14:15:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711116 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1564868rwb; Mon, 7 Aug 2023 07:16:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFRUNpf38gmIPmq/G0F5NrNO0FImxO+F/D94SjIwU6p/SM6WTXfIHxl6tLCKE0MM1kfuqKT X-Received: by 2002:a05:620a:2914:b0:76c:b539:6dc3 with SMTP id m20-20020a05620a291400b0076cb5396dc3mr13928688qkp.72.1691417797086; Mon, 07 Aug 2023 07:16:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417797; cv=none; d=google.com; s=arc-20160816; b=XC/wGQwtvGa9v1nUhIXtBRCOMGNlFaG8knFp0BJblWKHPSPWUy7fJw5tK+FWEXpWO8 5aQyRmlqxWCo6jn9wB6ucDtjCgwh5gkZCeEEUWhqMCx7m3DslZhPP4+d3pAbdktviubh EkNQGO+mi6q43czLIooAl83yT92foZnf5ZJaIJkas9jIAZBTIiYt0hcI3plIc64s0Msf fOSJiN/bxE0y8/1q6eQmiGtGU4mpvVYI06zBVoTv0wiViZAqCjscPH97sxU8DUTso7dK r7EByBqBWOXPJVQgxZhbGONO8LAFHf9e3X3hfATiTyyJiuOfM4w4NDQxws1v7HeIpGkM rYqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=sGWyEVC15cSw0RGmrkTizt56Pprj0lvgMLuupfaouu0=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=aDvbnLNuDGCLADEeVESpI17wuIGr9FZZwYRt2PzFQ3Iz8n/WY3S3s/xoKWWC3UqoXO A/+cIR/HyQEe0ST0qo2nPflzCJfAnFaK4ULHj87blgbiz1937yNvuF+xjFNehzFVWqDb 8QYqMpW1AF7+j/sBZW1NL77lM66Cxrofs4zRC5N0ydYg6mTqlc7uBjMR6+1vr9TQ9b/3 z65I9ORpegthM1uHDT/dd6crXAqYVUljgEla8hmzvK5eqI5vyPHG/5oFFUFfN4BlxQHn k21CLqQmR9nrD+VGdNS/RUQGrC8Ye8BKRKqvnUJdQ+S7ugCTojFFQTZNSQJUukgkQzVm 5dcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DyRaoKnh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:18 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 04/15] target/arm/ptw: Pass ptw into get_phys_addr_pmsa*() and get_phys_addr_disabled() Date: Mon, 7 Aug 2023 15:15:03 +0100 Message-Id: <20230807141514.19075-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit 6d2654ffacea813916176 we created the S1Translate struct and used it to plumb through various arguments that we were previously passing one-at-a-time to get_phys_addr_v5(), get_phys_addr_v6(), and get_phys_addr_lpae(). Extend that pattern to get_phys_addr_pmsav5(), get_phys_addr_pmsav7(), get_phys_addr_pmsav8() and get_phys_addr_disabled(), so that all the get_phys_addr_* functions we call from get_phys_addr_nogpc() take the S1Translate struct rather than the mmu_idx and is_secure bool. (This refactoring is a prelude to having the called functions look at ptw->is_space rather than using an is_secure boolean.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 57 ++++++++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 67078ae3509..a873fbe0239 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2045,15 +2045,19 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, return true; } -static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, +static bool get_phys_addr_pmsav5(CPUARMState *env, + S1Translate *ptw, + uint32_t address, + MMUAccessType access_type, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { int n; uint32_t mask; uint32_t base; + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_user = regime_is_user(env, mmu_idx); + bool is_secure = arm_space_is_secure(ptw->in_space); if (regime_translation_disabled(env, mmu_idx, is_secure)) { /* MPU disabled. */ @@ -2210,14 +2214,18 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, return regime_sctlr(env, mmu_idx) & SCTLR_BR; } -static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool secure, GetPhysAddrResult *result, +static bool get_phys_addr_pmsav7(CPUARMState *env, + S1Translate *ptw, + uint32_t address, + MMUAccessType access_type, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { ARMCPU *cpu = env_archcpu(env); int n; + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_user = regime_is_user(env, mmu_idx); + bool secure = arm_space_is_secure(ptw->in_space); result->f.phys_addr = address; result->f.lg_page_size = TARGET_PAGE_BITS; @@ -2736,12 +2744,16 @@ void v8m_security_lookup(CPUARMState *env, uint32_t address, } } -static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool secure, GetPhysAddrResult *result, +static bool get_phys_addr_pmsav8(CPUARMState *env, + S1Translate *ptw, + uint32_t address, + MMUAccessType access_type, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { V8M_SAttributes sattrs = {}; + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; + bool secure = arm_space_is_secure(ptw->in_space); bool ret; if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { @@ -3045,12 +3057,15 @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr, * MMU disabled. S1 addresses within aa64 translation regimes are * still checked for bounds -- see AArch64.S1DisabledOutput(). */ -static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address, +static bool get_phys_addr_disabled(CPUARMState *env, + S1Translate *ptw, + target_ulong address, MMUAccessType access_type, - ARMMMUIdx mmu_idx, bool is_secure, GetPhysAddrResult *result, ARMMMUFaultInfo *fi) { + ARMMMUIdx mmu_idx = ptw->in_mmu_idx; + bool is_secure = arm_space_is_secure(ptw->in_space); uint8_t memattr = 0x00; /* Device nGnRnE */ uint8_t shareability = 0; /* non-shareable */ int r_el; @@ -3252,8 +3267,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, case ARMMMUIdx_Phys_Root: case ARMMMUIdx_Phys_Realm: /* Checking Phys early avoids special casing later vs regime_el. */ - return get_phys_addr_disabled(env, address, access_type, mmu_idx, - is_secure, result, fi); + return get_phys_addr_disabled(env, ptw, address, access_type, + result, fi); case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: @@ -3321,16 +3336,16 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ - ret = get_phys_addr_pmsav8(env, address, access_type, mmu_idx, - is_secure, result, fi); + ret = get_phys_addr_pmsav8(env, ptw, address, access_type, + result, fi); } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ - ret = get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - is_secure, result, fi); + ret = get_phys_addr_pmsav7(env, ptw, address, access_type, + result, fi); } else { /* Pre-v7 MPU */ - ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - is_secure, result, fi); + ret = get_phys_addr_pmsav5(env, ptw, address, access_type, + result, fi); } qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", @@ -3348,8 +3363,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, /* Definitely a real MMU, not an MPU */ if (regime_translation_disabled(env, mmu_idx, is_secure)) { - return get_phys_addr_disabled(env, address, access_type, mmu_idx, - is_secure, result, fi); + return get_phys_addr_disabled(env, ptw, address, access_type, + result, fi); } if (regime_using_lpae_format(env, mmu_idx)) { From patchwork Mon Aug 7 14:15:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711118 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1565169rwb; Mon, 7 Aug 2023 07:17:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGuRxJAgMIhVlXoFAB1Wj/LCpIFaWKrAiHFO5nc1z4FFM6kQszCKxk+W5XLyvcuOzX1EIRz X-Received: by 2002:a05:620a:c4b:b0:766:27c2:cec8 with SMTP id u11-20020a05620a0c4b00b0076627c2cec8mr10324643qki.16.1691417823876; Mon, 07 Aug 2023 07:17:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417823; cv=none; d=google.com; s=arc-20160816; b=VJG7fvf5iZi3ABAQHaZJCXgToFPAP/HK+L7r+rCeHYT2RlV1N7uqr5Rf5Yi/4PAvMa vDsWQy1IJkgkBPJmUmBCOCT+DSWsjShY9Ro9auPFF/iaSP4FD6buCclAmFKZuDd5cD2H oj47vsKOk0CDFlYQ32CJTG3+E0pQlHJeSnZzCpDgnkKYVScmlA8/2JT6+Q9dCnLiM7/9 nJECQQOLFrAV15J4+aDmGOFEyTsOP93KUzEEy3r/rmCY1bDLWFjcCNnO8+T0ncm+WW1y DM1CGl0oL9ocKEYz8Uj+CD7a8kpZDejByZ1ZjBymjioBeQXObrlYVkJqvkJ1yxjtBq89 j3cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=NbiccwBAU2xAl/qEFIXdbuxGrXw7jKmkAECaPM8LQRA=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=wda736BnDMD93Tiahqn/lzjx7xcChZiIXqMlm/htOzPWVIfqv4JsnqxgXc/i91GJuf IQEIZhJg6RYhUXEms8gJqCNunVmEw1IuGnpBdK50iROW5VioJOmfkp1btS7beXUKIRHe MrHS8wm2383gcgdmNrZ720iNjLFAQ7rPBnl5WP/8R1RAcMEs6YRmsKu2yiZTSsE9gntd Eyfu2fn+KrNEjgMJYh37XC5enVNprQqCILJYkl4FS9h/JOq7v6HtbkjpOysuXr7CVtrF GDUt5dsUVFv+vXY/tEyjS+sIoSA7QvUgxdQZdfeY83ptgKOSrVNPVElq/xgBOxL36/Ta MNqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PStWaomu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/15] target/arm/ptw: Pass ARMSecurityState to regime_translation_disabled() Date: Mon, 7 Aug 2023 15:15:04 +0100 Message-Id: <20230807141514.19075-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Plumb the ARMSecurityState through to regime_translation_disabled() rather than just a bool is_secure. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a873fbe0239..63dd8e3cbe1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -206,9 +206,10 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn) /* Return true if the specified stage of address translation is disabled */ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, - bool is_secure) + ARMSecuritySpace space) { uint64_t hcr_el2; + bool is_secure = arm_space_is_secure(space); if (arm_feature(env, ARM_FEATURE_M)) { switch (env->v7m.mpu_ctrl[is_secure] & @@ -2057,9 +2058,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t base; ARMMMUIdx mmu_idx = ptw->in_mmu_idx; bool is_user = regime_is_user(env, mmu_idx); - bool is_secure = arm_space_is_secure(ptw->in_space); - if (regime_translation_disabled(env, mmu_idx, is_secure)) { + if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) { /* MPU disabled. */ result->f.phys_addr = address; result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -2231,7 +2231,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, result->f.lg_page_size = TARGET_PAGE_BITS; result->f.prot = 0; - if (regime_translation_disabled(env, mmu_idx, secure) || + if (regime_translation_disabled(env, mmu_idx, ptw->in_space) || m_is_ppb_region(env, address)) { /* * MPU disabled or M profile PPB access: use default memory map. @@ -2475,7 +2475,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, * are done in arm_v7m_load_vector(), which always does a direct * read using address_space_ldl(), rather than going via this function. */ - if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx, arm_secure_to_space(secure))) { + /* MPU disabled */ hit = true; } else if (m_is_ppb_region(env, address)) { hit = true; @@ -3303,7 +3304,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, */ ptw->in_mmu_idx = mmu_idx = s1_mmu_idx; if (arm_feature(env, ARM_FEATURE_EL2) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2, is_secure)) { + !regime_translation_disabled(env, ARMMMUIdx_Stage2, ptw->in_space)) { return get_phys_addr_twostage(env, ptw, address, access_type, result, fi); } @@ -3362,7 +3363,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, /* Definitely a real MMU, not an MPU */ - if (regime_translation_disabled(env, mmu_idx, is_secure)) { + if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) { return get_phys_addr_disabled(env, ptw, address, access_type, result, fi); } From patchwork Mon Aug 7 14:15:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711127 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1565818rwb; Mon, 7 Aug 2023 07:17:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEBC/E02Ngz8r667U95M/sl3wo8j//6NIdH+d2d9/vwqCsG12Wijn2XPisoqsm70lmFCnTv X-Received: by 2002:a05:6214:4007:b0:63c:c3f0:82e6 with SMTP id kd7-20020a056214400700b0063cc3f082e6mr11498119qvb.60.1691417874084; Mon, 07 Aug 2023 07:17:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417874; cv=none; d=google.com; s=arc-20160816; b=PbSHcb/LlnjjErRxbOwbrS90v8U8BY61PmXwGwvj3Pn9OZhOI8SsHqkh6I/Z+8J2cm /Nf+vuSBoH9MO7WoA5iy2OpnLv6zR+j4JpydE9tF/qMg9nTWGQPEoKEYE++P8+nmtOhb bXz2UBKEOn7OFExIUAqK8boX2p0YgIoO0NJsEvBveHLzbeRWM6uBSzSVYqkcJXztFlQ0 IAWU+60l3Swf2ZEFxISykX1rcIeHd7YvmojS4pXuNODl7I+ZeaBw441gjveyPrIv4TOl AtZyav3jbEZ3hl/UCbZDf+7T0I5DVmvrzUoRwypo9xShxGxL2+JlUKIkfhu1ROan2RBm KqWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wGPGvej2mg6PydRuAT/KJYpLUQ8OQzMCYsuiZcL8/Tw=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=Tt2F4/J6/bZFN4wVFNhdDZ+OGtg6tB1s+g+yoq8ho21h3usDNR6qM94i9POSOURAKp +WwLmVQ4XbylPdQPFDDlBI4io4RbziYdbvbU8Qs+o/7cgdyzXJnZVydySfxvd+pZoxGy Ht+Ivtn9Qi3cZtBlb74W7daiki5XsBcZa5lbsCpz0C16t6+jlevYQfZhlTzRcpw8w4ms 2W+wAzxfwiTyX2Pu6AE6cyxYW0LeoWnVvVpV28rbF9YQxzCVqJ/Im+gSsrmSzT7/rBsu cLvvNxtpmicw1SC/DvFYMLpmm1bUI67km0v13UoDHS3Id1Wxt5uFxyEmpAbB1qbd65JZ R4pA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="G4PRJ3a/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:19 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 06/15] target/arm/ptw: Pass an ARMSecuritySpace to arm_hcr_el2_eff_secstate() Date: Mon, 7 Aug 2023 15:15:05 +0100 Message-Id: <20230807141514.19075-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org arm_hcr_el2_eff_secstate() takes a bool secure, which it uses to determine whether EL2 is enabled in the current security state. With the advent of FEAT_RME this is no longer sufficient, because EL2 can be enabled for Secure state but not for Root, and both of those will pass 'secure == true' in the callsites in ptw.c. As it happens in all of our callsites in ptw.c we either avoid making the call or else avoid using the returned value if we're doing a translation for Root, so this is not a behaviour change even if the experimental FEAT_RME is enabled. But it is less confusing in the ptw.c code if we avoid the use of a bool secure that duplicates some of the information in the ArmSecuritySpace argument. Make arm_hcr_el2_eff_secstate() take an ARMSecuritySpace argument instead. Because we always want to know the HCR_EL2 for the security state defined by the current effective value of SCR_EL3.{NSE,NS}, it makes no sense to pass ARMSS_Root here, and we assert that callers don't do that. To avoid the assert(), we thus push the call to arm_hcr_el2_eff_secstate() down into the cases in regime_translation_disabled() that need it, rather than calling the function and ignoring the result for the Root space translations. All other calls to this function in ptw.c are already in places where we have confirmed that the mmu_idx is a stage 2 translation or that the regime EL is not 3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- Changes v1->v2: instead of having arm_hcr_el2_eff_secstate() accept space == ARMSS_Root and return 0, have it assert that Root is not passed, and adjust regime_translation_disabled() accordingly. --- target/arm/cpu.h | 2 +- target/arm/helper.c | 8 +++++--- target/arm/ptw.c | 15 +++++++-------- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 88e5accda69..bcd65a63ca0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2555,7 +2555,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *env) * "for all purposes other than a direct read or write access of HCR_EL2." * Not included here is HCR_RW. */ -uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure); +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space); uint64_t arm_hcr_el2_eff(CPUARMState *env); uint64_t arm_hcrx_el2_eff(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index 50f61e42ca8..9862bc73b52 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5772,11 +5772,13 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, * Bits that are not included here: * RW (read from SCR_EL3.RW as needed) */ -uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure) +uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space) { uint64_t ret = env->cp15.hcr_el2; - if (!arm_is_el2_enabled_secstate(env, secure)) { + assert(space != ARMSS_Root); + + if (!arm_is_el2_enabled_secstate(env, arm_space_is_secure(space))) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". This is ARMv8.4-SecEL2 speak for @@ -5840,7 +5842,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) if (arm_feature(env, ARM_FEATURE_M)) { return 0; } - return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env)); + return arm_hcr_el2_eff_secstate(env, arm_security_space_below_el3(env)); } /* diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 63dd8e3cbe1..4c60de753dd 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -209,9 +209,9 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, ARMSecuritySpace space) { uint64_t hcr_el2; - bool is_secure = arm_space_is_secure(space); if (arm_feature(env, ARM_FEATURE_M)) { + bool is_secure = arm_space_is_secure(space); switch (env->v7m.mpu_ctrl[is_secure] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) { case R_V7M_MPU_CTRL_ENABLE_MASK: @@ -230,18 +230,19 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, } } - hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure); switch (mmu_idx) { case ARMMMUIdx_Stage2: case ARMMMUIdx_Stage2_S: /* HCR.DC means HCR.VM behaves as 1 */ + hcr_el2 = arm_hcr_el2_eff_secstate(env, space); return (hcr_el2 & (HCR_DC | HCR_VM)) == 0; case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */ + hcr_el2 = arm_hcr_el2_eff_secstate(env, space); if (hcr_el2 & HCR_TGE) { return true; } @@ -251,6 +252,7 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: /* HCR.DC means SCTLR_EL1.M behaves as 0 */ + hcr_el2 = arm_hcr_el2_eff_secstate(env, space); if (hcr_el2 & HCR_DC) { return true; } @@ -530,7 +532,6 @@ static bool fault_s1ns(ARMSecuritySpace space, ARMMMUIdx s2_mmu_idx) static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { - bool is_secure = ptw->in_secure; ARMMMUIdx mmu_idx = ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; uint8_t pte_attrs; @@ -587,7 +588,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, } if (regime_is_stage2(s2_mmu_idx)) { - uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); + uint64_t hcr = arm_hcr_el2_eff_secstate(env, ptw->in_space); if ((hcr & HCR_PTW) && S2_attrs_are_device(hcr, pte_attrs)) { /* @@ -3066,7 +3067,6 @@ static bool get_phys_addr_disabled(CPUARMState *env, ARMMMUFaultInfo *fi) { ARMMMUIdx mmu_idx = ptw->in_mmu_idx; - bool is_secure = arm_space_is_secure(ptw->in_space); uint8_t memattr = 0x00; /* Device nGnRnE */ uint8_t shareability = 0; /* non-shareable */ int r_el; @@ -3112,7 +3112,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ if (r_el == 1) { - uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure); + uint64_t hcr = arm_hcr_el2_eff_secstate(env, ptw->in_space); if (hcr & HCR_DC) { if (hcr & HCR_DCT) { memattr = 0xf0; /* Tagged, Normal, WB, RWA */ @@ -3149,7 +3149,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, { hwaddr ipa; int s1_prot, s1_lgpgsz; - bool is_secure = ptw->in_secure; ARMSecuritySpace in_space = ptw->in_space; bool ret, ipa_secure; ARMCacheAttrs cacheattrs1; @@ -3212,7 +3211,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, } /* Combine the S1 and S2 cache attributes. */ - hcr = arm_hcr_el2_eff_secstate(env, is_secure); + hcr = arm_hcr_el2_eff_secstate(env, in_space); if (hcr & HCR_DC) { /* * HCR.DC forces the first stage attributes to From patchwork Mon Aug 7 14:15:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711120 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1565424rwb; Mon, 7 Aug 2023 07:17:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFlh09kHKJ5e5dV3T7NiFyPc6K0r/WuhOJD06CJ97wQ37XuYfq6P/dtaqAjS51ESgC3Tc+U X-Received: by 2002:a05:6102:1c6:b0:443:898c:864d with SMTP id s6-20020a05610201c600b00443898c864dmr4198293vsq.14.1691417843371; Mon, 07 Aug 2023 07:17:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417843; cv=none; d=google.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:20 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 07/15] target/arm: Pass an ARMSecuritySpace to arm_is_el2_enabled_secstate() Date: Mon, 7 Aug 2023 15:15:06 +0100 Message-Id: <20230807141514.19075-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Pass an ARMSecuritySpace instead of a bool secure to arm_is_el2_enabled_secstate(). This doesn't change behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 13 ++++++++----- target/arm/helper.c | 2 +- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index bcd65a63ca0..02bc8f0e8e0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2504,17 +2504,19 @@ static inline bool arm_is_secure(CPUARMState *env) /* * Return true if the current security state has AArch64 EL2 or AArch32 Hyp. - * This corresponds to the pseudocode EL2Enabled() + * This corresponds to the pseudocode EL2Enabled(). */ -static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, + ARMSecuritySpace space) { + assert(space != ARMSS_Root); return arm_feature(env, ARM_FEATURE_EL2) - && (!secure || (env->cp15.scr_el3 & SCR_EEL2)); + && (space != ARMSS_Secure || (env->cp15.scr_el3 & SCR_EEL2)); } static inline bool arm_is_el2_enabled(CPUARMState *env) { - return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env)); + return arm_is_el2_enabled_secstate(env, arm_security_space_below_el3(env)); } #else @@ -2538,7 +2540,8 @@ static inline bool arm_is_secure(CPUARMState *env) return false; } -static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure) +static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, + ARMSecuritySpace space) { return false; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 9862bc73b52..8290ca0aaad 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5778,7 +5778,7 @@ uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, ARMSecuritySpace space) assert(space != ARMSS_Root); - if (!arm_is_el2_enabled_secstate(env, arm_space_is_secure(space))) { + if (!arm_is_el2_enabled_secstate(env, space)) { /* * "This register has no effect if EL2 is not enabled in the * current Security state". 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:20 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 08/15] target/arm/ptw: Only fold in NSTable bit effects in Secure state Date: Mon, 7 Aug 2023 15:15:07 +0100 Message-Id: <20230807141514.19075-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we do a translation in Secure state, the NSTable bits in table descriptors may downgrade us to NonSecure; we update ptw->in_secure and ptw->in_space accordingly. We guard that check correctly with a conditional that means it's only applied for Secure stage 1 translations. However, later on in get_phys_addr_lpae() we fold the effects of the NSTable bits into the final descriptor attributes bits, and there we do it unconditionally regardless of the CPU state. That means that in Realm state (where in_secure is false) we will set bit 5 in attrs, and later use it to decide to output to non-secure space. We don't in fact need to do this folding in at all any more (since commit 2f1ff4e7b9f30c): if an NSTable bit was set then we have already set ptw->in_space to ARMSS_NonSecure, and in that situation we don't look at attrs bit 5. The only thing we still need to deal with is the real NS bit in the final descriptor word, so we can just drop the code that ORed in the NSTable bit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 4c60de753dd..6e736bacd77 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1886,11 +1886,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, * Extract attributes from the (modified) descriptor, and apply * table descriptors. Stage 2 table descriptors do not include * any attribute fields. HPD disables all the table attributes - * except NSTable. + * except NSTable (which we have already handled). */ attrs = new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14)); if (!regime_is_stage2(mmu_idx)) { - attrs |= !ptw->in_secure << 5; /* NS */ if (!param.hpd) { attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ /* From patchwork Mon Aug 7 14:15:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711117 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1564986rwb; Mon, 7 Aug 2023 07:16:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGgjIA44/vqpSXaNIGPIh55nzFffqYODLCs6IfhpjJB00nXfq8DKEb8emy8PRhlAffkwzCR X-Received: by 2002:a05:622a:130c:b0:3f9:aa80:b48a with SMTP id v12-20020a05622a130c00b003f9aa80b48amr9680217qtk.8.1691417808081; Mon, 07 Aug 2023 07:16:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417808; cv=none; d=google.com; s=arc-20160816; b=jIxUuT4yryF/+z0AAFFQuyKRd0gpcgPmFGrwT5XdIX5iMYTGuE1lWKn5bLV2/9sWBH gBI8yaGfqJrjImX+22YaMy+0NK2W5Yzhxic9jXyiQudGw8JqlTyjwHgMNoN5fZmDUF+W ivcaL9pSvfCGPFKV2KnYu5LlkniW/cs3ZhsH0hZylGyQ4Yk19KqNXNcIvfg69o+tkLCL odWhpp77nOCFUNfQzEy2MZr97DNIXvt6+LO9IWxSBRC4uBSyxDSelJaz2UUMZxG8hGAL FcJGhH0uALpEICtphyMLSXO43WUoXxpDRZOFoTR0T4Lp+vjs9KqGIbLX+6NGqbGvU4VM Ngkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=uhsYVutNNAS0mc53Ap1xSb7YNraKnHLfqR3rpR5pcZc=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=yKuylTYMCteWXHZfAK4qhUXcwyVirLHiXVEBwIGES5/zulr6sBJdCWXEPtxNLharxq xxEJe3l11IQPVk7Wt45aceB7fbXGTGBbzzMFdvsSP8U6/A+LZhJn0mce1cxuooDH6cp8 PGYkuDlSxuCNR+q5T5O2fiLxR6awr22RzCLZy6rFPrFwFOZFUyy8kudm+gUNub6t+7X7 pv+eEf0OmsrI5NIf5yfE641qYG3BTRGVWAnBNJ+mgZ2/FFvaxVUbafQvnoTDdhsV0app no9jMj69jMJyc0FFGNdsFuYF8ZeKRqM53LpiA9aEmlqSbhacRKZJ/fAsG8DNMjDXxjpd iwNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xyksu1m+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 09/15] target/arm/ptw: Remove last uses of ptw->in_secure Date: Mon, 7 Aug 2023 15:15:08 +0100 Message-Id: <20230807141514.19075-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Replace the last uses of ptw->in_secure with appropriate checks on ptw->in_space. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 6e736bacd77..1ca25438c3c 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3249,7 +3249,6 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, ARMMMUFaultInfo *fi) { ARMMMUIdx mmu_idx = ptw->in_mmu_idx; - bool is_secure = ptw->in_secure; ARMMMUIdx s1_mmu_idx; /* @@ -3257,8 +3256,8 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, * cannot upgrade a NonSecure translation regime's attributes * to Secure or Realm. */ - result->f.attrs.secure = is_secure; result->f.attrs.space = ptw->in_space; + result->f.attrs.secure = arm_space_is_secure(ptw->in_space); switch (mmu_idx) { case ARMMMUIdx_Phys_S: @@ -3272,8 +3271,12 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1Translate *ptw, case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: - /* First stage lookup uses second stage for ptw. */ - ptw->in_ptw_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; + /* + * First stage lookup uses second stage for ptw; only + * Secure has both S and NS IPA and starts with Stage2_S. + */ + ptw->in_ptw_idx = (ptw->in_space == ARMSS_Secure) ? + ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; break; case ARMMMUIdx_Stage2: From patchwork Mon Aug 7 14:15:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711124 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1565668rwb; Mon, 7 Aug 2023 07:17:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEn8u7P586jII7nSeDuu/HDS/M8K+2kNrIISDATPsquE7fdZXGbypTeQlMqaYrJpqmw3/PC X-Received: by 2002:a05:622a:93:b0:400:9f2c:1211 with SMTP id o19-20020a05622a009300b004009f2c1211mr9776862qtw.29.1691417862275; Mon, 07 Aug 2023 07:17:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417862; cv=none; d=google.com; s=arc-20160816; b=PpdxJTxXbJpRIcIPPYtnkoYCdSznf66ITrsVmVlHxg1lt/3ztsgjVcEoJec7PukXSY F3+KY3MQN8+3E/9FkJfbbiItAI85OmjdJJmnQdS7rorGeD2hNeoJA7paZXpZ/7nSU7gv pZ25T3ewVxbvDKxSCEXiUc1DCKrkSGGRIPLlRJP4BTBd7VB7Tfd+FjD8FtJIHE9vjzTH aQ0J6YeJ6flNqdwbYXDSNllbkWxQjgtEhmJcyiQqCf1TD71Sskx6MJqb7OC8FPeMftrk N3i9r0mg63a0oUgo4SDzs8DJ8oWwvDstKPDfFa9WieLwobFvi1djyZhffHOTiWR0nb2p kLqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fPUvCziy6lhHDDMmfmybg6TLiyhiL/Fc4MTynATEnX0=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=lrcxEiYRrJv7SciIlUHSdbO3VUOsjx8JsfZeFhl/FluxP6wqQ0OcCCinwQZqII+yn7 IOGGqOSggrms9/ArO43DUVE2J1sX3a/kTL0NYQB78aal3IrsvqbYyhXnMTswp8i7C/yj MN9MdEycbpYBIiaQyzwiQk5O+NxU9VqsM8h/JQ7yfFCVapTNTn8CQbhlXU3yp3BvKI2A jZwLXoBxL63/SBVUK1kMamS8QDNEUWDVErhmY14ZXuXdaf0zcXsS95TQlpmPEy9X4pA4 ldNpAllks4hKNrjQuik9s4YOqdo0ofkQqFUz/Bv2furPTMUlW/23GKnwnxRjDGLMZ5J5 lWQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QgO+KSNt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 10/15] target/arm/ptw: Remove S1Translate::in_secure Date: Mon, 7 Aug 2023 15:15:09 +0100 Message-Id: <20230807141514.19075-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We no longer look at the in_secure field of the S1Translate struct anyway, so we can remove it and all the code which sets it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 1ca25438c3c..78bc679deef 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -51,13 +51,6 @@ typedef struct S1Translate { * value being Stage2 vs Stage2_S distinguishes those. */ ARMSecuritySpace in_space; - /* - * in_secure: whether the translation regime is a Secure one. - * This is always equal to arm_space_is_secure(in_space). - * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, - * this field is updated accordingly. - */ - bool in_secure; /* * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug * accesses will not update the guest page table access flags @@ -547,7 +540,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, S1Translate s2ptw = { .in_mmu_idx = s2_mmu_idx, .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), - .in_secure = arm_space_is_secure(s2_space), .in_space = s2_space, .in_debug = true, }; @@ -1784,7 +1776,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, QEMU_BUILD_BUG_ON(ARMMMUIdx_Phys_S + 1 != ARMMMUIdx_Phys_NS); QEMU_BUILD_BUG_ON(ARMMMUIdx_Stage2_S + 1 != ARMMMUIdx_Stage2); ptw->in_ptw_idx += 1; - ptw->in_secure = false; ptw->in_space = ARMSS_NonSecure; } @@ -3167,7 +3158,6 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, ptw->in_s1_is_el0 = ptw->in_mmu_idx == ARMMMUIdx_Stage1_E0; ptw->in_mmu_idx = ipa_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; - ptw->in_secure = ipa_secure; ptw->in_space = ipa_space; ptw->in_ptw_idx = ptw_idx_for_stage_2(env, ptw->in_mmu_idx); @@ -3403,7 +3393,6 @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address, { S1Translate ptw = { .in_mmu_idx = mmu_idx, - .in_secure = is_secure, .in_space = arm_secure_to_space(is_secure), }; return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); @@ -3475,7 +3464,6 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, } ptw.in_space = ss; - ptw.in_secure = arm_space_is_secure(ss); return get_phys_addr_gpc(env, &ptw, address, access_type, result, fi); } @@ -3489,7 +3477,6 @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, S1Translate ptw = { .in_mmu_idx = mmu_idx, .in_space = ss, - .in_secure = arm_space_is_secure(ss), .in_debug = true, }; GetPhysAddrResult res = {}; From patchwork Mon Aug 7 14:15:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711122 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1565646rwb; Mon, 7 Aug 2023 07:17:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHxEz9qXL3K12mysRaLc62cW8vlahiyoxn26CHMpDheQ7SkmJnE7mNqsQEoVAlm3+K5dkFk X-Received: by 2002:a1f:bf8c:0:b0:486:6cad:b6e7 with SMTP id p134-20020a1fbf8c000000b004866cadb6e7mr4084407vkf.10.1691417860625; Mon, 07 Aug 2023 07:17:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417860; cv=none; d=google.com; s=arc-20160816; b=Bmpxr8ake7mnkZJkxg9sSS10HRgQpCqpnOMrmNtD46XNKym6z5RmNkOShSW+gJebA1 7Umzq9GOsjZErjKOD6DIYSvXqXBAvraI0giXf+xXQiCD2Av88DgPLQJod9fgol3NU8n0 a5uYWhHPW/RYfFMnppUoXbH8JtGXbHJJhKkxZejieNMv5uV1RpjmXL/o7J2v65Ji93AY m/ZJm2tgAWXWGW4dU+gmKszS2AUASBb/Pz7027mH9hiccGwNv+9al9feO5ff+fe44GUj mFfqWM7bxYmt/GIhfuRI+v15sWK5Jjq69R9+jmxPkvKiHS4EMqkC34XIb7RaKj5cN6w4 KvNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=S38jOsOxbXZJPQo1Nn8IdqFJrWb3K/zbZSPVOOqu/8w=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=m/XWkdt9aHOG5zOWbz3oqjclP0ftpxE65EPNiE3pNlR7ki5H2BErgLbmB0WDLvWnt5 mFj4YuLhm29jDSbWmSf/YkH6PlbuzmIFtlmQdBfYBtVXp9LPXYsk+TcDPSmajiErsNt5 ZA+qdtXPhDIHfS39NftSkokgY7VENE0eUiJIB+XnP5sqVNjIvE8BhhLqxxBe7x5uwm7s 2qY3rLxRBdcGvG5hL5HJtmuBMfjlJJkqD6NCMGRFPWAIBMCcPP3BJYMizg2K43xvHRkT Gc2aBx91sX/ozUhVs/yKLAwgAkFq708tEmBYTxzTu3Ori7UpFGf2AYI0c6snJSaaKM99 UC7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qrFYfcE1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 11/15] target/arm/ptw: Drop S1Translate::out_secure Date: Mon, 7 Aug 2023 15:15:10 +0100 Message-Id: <20230807141514.19075-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We only use S1Translate::out_secure in two places, where we are setting up MemTxAttrs for a page table load. We can use arm_space_is_secure(ptw->out_space) instead, which guarantees that we're setting the MemTxAttrs secure and space fields consistently, and allows us to drop the out_secure field in S1Translate entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 78bc679deef..312ccabe92e 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -63,7 +63,6 @@ typedef struct S1Translate { * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}. */ bool in_s1_is_el0; - bool out_secure; bool out_rw; bool out_be; ARMSecuritySpace out_space; @@ -553,7 +552,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, pte_attrs = s2.cacheattrs.attrs; ptw->out_host = NULL; ptw->out_rw = false; - ptw->out_secure = s2.f.attrs.secure; ptw->out_space = s2.f.attrs.space; } else { #ifdef CONFIG_TCG @@ -572,7 +570,6 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, ptw->out_phys = full->phys_addr | (addr & ~TARGET_PAGE_MASK); ptw->out_rw = full->prot & PAGE_WRITE; pte_attrs = full->pte_attrs; - ptw->out_secure = full->attrs.secure; ptw->out_space = full->attrs.space; #else g_assert_not_reached(); @@ -630,8 +627,8 @@ static uint32_t arm_ldl_ptw(CPUARMState *env, S1Translate *ptw, } else { /* Page tables are in MMIO. */ MemTxAttrs attrs = { - .secure = ptw->out_secure, .space = ptw->out_space, + .secure = arm_space_is_secure(ptw->out_space), }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; @@ -676,8 +673,8 @@ static uint64_t arm_ldq_ptw(CPUARMState *env, S1Translate *ptw, } else { /* Page tables are in MMIO. */ MemTxAttrs attrs = { - .secure = ptw->out_secure, .space = ptw->out_space, + .secure = arm_space_is_secure(ptw->out_space), }; AddressSpace *as = arm_addressspace(cs, attrs); MemTxResult result = MEMTX_OK; From patchwork Mon Aug 7 14:15:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711125 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1565755rwb; Mon, 7 Aug 2023 07:17:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGCZQMv1aiTQUIBfrvzvOWoFPec8FJjnXxb5t9RY7R2yUu9OpP3G/gnn1gtuQYGiJgbfZ9Q X-Received: by 2002:a05:620a:f15:b0:76c:dc9c:3164 with SMTP id v21-20020a05620a0f1500b0076cdc9c3164mr7180914qkl.76.1691417868983; Mon, 07 Aug 2023 07:17:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417868; cv=none; d=google.com; s=arc-20160816; b=iwI762dsS/FqxtCMentb+KajS7PqxUx6j8ssalQGWatOl0Cfu+th8OMNT+ic4Tyby8 GaEPXny04Kf3Ol7kHSeHSmT7Pip+arj5mdv+qaswDNQOQ8zWloochkrVxB8cIiQutHyJ 7q2wXEeZFV63P+L4EVN0eStG6v2XAET2FGEEIV+XRLDAw8gRfOJGP91b7xlbrSwroUUS k5u3r9ytrbgjzXXf2oJi06RWd8umnMNpGUbU9gYrHq3KCdicbWi2FF6dNclTyWBza/bS Hkb6msLV2JdRxBsHfXU2xf5XeafUa0R473t9lzT9ZTUgvUzv+9BPRU7Eq5rJFwxP0Dko t1gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=/yyxHEqA/6T1J8G7sWRRyJB/3QTMgoPg9dM02AxAbq0=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=Etu3op2pV5SlFjaFjqZkx2HOHC9iDah2WTKMWHT3cG6iY9vXvZLggGGJQjEhjtSJ9B +/R6SDTg3VpIK7iyDYYvglfG8VksDCv9QKeQce3Ozzo6RAhlg0zfzDWEH86NtrJB+6oJ XRXHUr+q6hMva4uNK7ci0LKC4djBQm5L7CNCbvBg4XkKdRtf/jjyITLy/W1i9JDS9tWd 0YdCDIPd2zosLp1bBVaLxIB6xQZxNbT/3ToRcfvIfxi3pKor/qrwHmLwCSs68rT9/dRU cHV4OymUREMSIWodhr1hm3KE7Tp0AW0J0DDP/97zzOiUgWyGvV4svBmsfwsz5GgIlGzF BnCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dCZeRDrJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 12/15] target/arm/ptw: Set attributes correctly for MMU disabled data accesses Date: Mon, 7 Aug 2023 15:15:11 +0100 Message-Id: <20230807141514.19075-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When the MMU is disabled, data accesses should be Device nGnRnE, Outer Shareable, Untagged. We handle the other cases from AArch64.S1DisabledOutput() correctly but missed this one. Device nGnRnE is memattr == 0, so the only part we were missing was that shareability should be set to 2 for both insn fetches and data accesses. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 312ccabe92e..7f217a31895 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3108,11 +3108,13 @@ static bool get_phys_addr_disabled(CPUARMState *env, } } } - if (memattr == 0 && access_type == MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr = 0xee; /* Normal, WT, RA, NT */ - } else { - memattr = 0x44; /* Normal, NC, No */ + if (memattr == 0) { + if (access_type == MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr = 0xee; /* Normal, WT, RA, NT */ + } else { + memattr = 0x44; /* Normal, NC, No */ + } } shareability = 2; /* outer shareable */ } From patchwork Mon Aug 7 14:15:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711121 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1565491rwb; Mon, 7 Aug 2023 07:17:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGxeaqqZXl/UCZmsGemDHb9OUSe/SWPcQPBG12n2KluKTkTzzlbHbElJacbd5zDbO69J1GD X-Received: by 2002:a67:f550:0:b0:443:9248:3410 with SMTP id z16-20020a67f550000000b0044392483410mr4064412vsn.32.1691417849635; Mon, 07 Aug 2023 07:17:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417849; cv=none; d=google.com; s=arc-20160816; b=Spto+fbsfe2pWzLnJgtHsFNrmaYMwPV17Mf5xpl3lZDWtN3p9NLYUFwl9o5mUjP1v6 1w/LGvlI7Tvsxg3nNB2a4hP42VTqQb7SnXLuet4vFLnEugx4hQtyx8foeAXB0aKNQwDT n4mCU3cj86SLsEJqEQ7MhPQv8r6LyoTrx01mEWx1yGHT84K4N98e/LUYbHIz3TS3Rh7B BYVzwgY9eQXVedlOjlHUKd/OVGRy71XjliBQ2vPyIoZpKfq0DyLEaA61BbQUSv9HrSx7 OhouX7td0PGDi5fyp/2ZDdzm0no4Q15Bp7e9oAdsBvlfNUY91cud8K7Uc19/YTY43Dy2 eCpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=DFzTkjIJFWqjEqcRCrUZIPYv2Pvbteumi0MT6ZHxtV8=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=ou0TXUFwH9QGWdx+rzYnT4cWwL2ghUjHD7JuO1vT7I/j0ugtlNnCo/3F7i7dGInx4P rBkgWFigIdZD5Q56vDWzc+TnnvaDBBIUuavAMN3yTfPM59Guy8LjPtDkeaFwDqNT8CEu ORdMpbTT7lWK0vy15KJNx+40MmBDMbX7MfiVcqhP/9vDwGoVI7WMN6kKtGA53LfCYm0h Oz4x3fJR/GIaQ142hpY4brKAL2t2y4VZVAMfovOdD0CiWnZHpPMoLfKE909FrCT0g+25 T2kU/3ek8CXHfYHdBjEXK1CSdfd3dBykIA7FsCNV1LhB//bXs6bshToa4aTbKHGG9DCZ Eivw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tTeVrVun; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 13/15] target/arm/ptw: Check for block descriptors at invalid levels Date: Mon, 7 Aug 2023 15:15:12 +0100 Message-Id: <20230807141514.19075-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The architecture doesn't permit block descriptors at any arbitrary level of the page table walk; it depends on the granule size which levels are permitted. We implemented only a partial version of this check which assumes that block descriptors are valid at all levels except level 3, which meant that we wouldn't deliver the Translation fault for all cases of this sort of guest page table error. Implement the logic corresponding to the pseudocode AArch64.DecodeDescriptorType() and AArch64.BlockDescSupported(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7f217a31895..fbb0f8a0bf2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1551,6 +1551,25 @@ static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr, return INT_MIN; } +static bool lpae_block_desc_valid(ARMCPU *cpu, bool ds, + ARMGranuleSize gran, int level) +{ + /* + * See pseudocode AArch46.BlockDescSupported(): block descriptors + * are not valid at all levels, depending on the page size. + */ + switch (gran) { + case Gran4K: + return (level == 0 && ds) || level == 1 || level == 2; + case Gran16K: + return (level == 1 && ds) || level == 2; + case Gran64K: + return (level == 1 && arm_pamax(cpu) == 52) || level == 2; + default: + g_assert_not_reached(); + } +} + /** * get_phys_addr_lpae: perform one stage of page table walk, LPAE format * @@ -1786,8 +1805,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, new_descriptor = descriptor; restart_atomic_update: - if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) { - /* Invalid, or the Reserved level 3 encoding */ + if (!(descriptor & 1) || + (!(descriptor & 2) && + !lpae_block_desc_valid(cpu, param.ds, param.gran, level))) { + /* Invalid, or a block descriptor at an invalid level */ goto do_translation_fault; } From patchwork Mon Aug 7 14:15:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711126 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1565782rwb; Mon, 7 Aug 2023 07:17:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEcVf79hy5c8zm59tPguPvORx6mqJMgTIKzMbH5i9m/mRJMk/TIafXJo0rJKKxZrx6/gacc X-Received: by 2002:ac8:598d:0:b0:410:6b6:b9b3 with SMTP id e13-20020ac8598d000000b0041006b6b9b3mr7422492qte.55.1691417871406; Mon, 07 Aug 2023 07:17:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417871; cv=none; d=google.com; s=arc-20160816; b=aLVTo/pF9ACKloF52ga71qYVq0GV7alXZJX0Vxp2yMvq8lL45eX6bNRvDhPcrHBXc+ NYhJtblz5BIcQIC6g5x0/L/iYcBKedp18xctRfMBJkcrhZW3t1zIypQrGA16rO3EJjy0 +SkzSRm44LtWIx/1lIhixHQqePHBAHGlLRW7mHnu6iS05/cHLCECUEnDE6Tgl17Rztx5 aD277UeAtmOzJm6UxMDre4020AZ7/TaUcoAqGGI8kJqQ/aNndCfQcNP0JznJn24pJITl ncn2AqniKutcrANZT7vhXa5Ih368lJpHNcoeKbITYjAigs5RadDfM4CQ4u/fDzR5sWqv CAKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cr23TIsFZ3PjCpnV8UZBDI6iYURVIWjSxhQhgKrusGQ=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=q830MiE0uamrl3NpNUWOKxdK9qX6aMwQ9nTel/N/WSapmt8eO6QpmRxvV+4e+78NA5 UXHpZ1XsCh4U35w084pvz0F+CZlSNgwagIzXY1xDrH+EmPEqcfcgkJofrtMbbAMpSb6V apWTxD7lcpFZD6NZqke8NAEosdBpg76kRX1QQ6lKnSDKcGmcc+1fx4YrPcXlT0kzUhjo a9XWD9nczHWl8vnAkmiWB7Y0PnOJbsA2tzmCwA+H309z8uQVTdbAbTaaHhFt9LyVZGSS GyX7wVb9ltsgxqxnTK3u07fGUD1fvs75z54HRjFKRBrXKKQy6SOdUI5rjTbBfcOvOo+Z tBsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=giZh0fYh; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 14/15] target/arm/ptw: Report stage 2 fault level for stage 2 faults on stage 1 ptw Date: Mon, 7 Aug 2023 15:15:13 +0100 Message-Id: <20230807141514.19075-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When we report faults due to stage 2 faults during a stage 1 page table walk, the 'level' parameter should be the level of the walk in stage 2 that faulted, not the level of the walk in stage 1. Correct the reporting of these faults. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/ptw.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index fbb0f8a0bf2..07832eb8f76 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2048,9 +2048,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, do_translation_fault: fi->type = ARMFault_Translation; do_fault: - fi->level = level; - /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ - fi->stage2 = fi->s1ptw || regime_is_stage2(mmu_idx); + if (fi->s1ptw) { + /* Retain the existing stage 2 fi->level */ + assert(fi->stage2); + } else { + fi->level = level; + fi->stage2 = regime_is_stage2(mmu_idx); + } fi->s1ns = fault_s1ns(ptw->in_space, mmu_idx); return true; } From patchwork Mon Aug 7 14:15:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 711119 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1565352rwb; Mon, 7 Aug 2023 07:17:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEWet2Ny/EQINanouWDQs8Z4kug1VxHWgXlEB390IH4Req7yWhNxRqZedo6bw7WnfCrI19W X-Received: by 2002:ac8:4e50:0:b0:40f:f860:f025 with SMTP id e16-20020ac84e50000000b0040ff860f025mr9737055qtw.40.1691417836913; Mon, 07 Aug 2023 07:17:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691417836; cv=none; d=google.com; s=arc-20160816; b=yAkRFGg+5yUrc+bN/JQ2h3O6RN/K/oX/f8pu+FzdYqujsw42azX6r5AjDzh1vd9aHl cp67PwkD6MUps05Nb9/y7kYvWzKisk30FpKYTovQUmjnFJH2EZN+yoQe8/r875nVkGOc zuD/F6sYPtzpuDq1XbO6pCMnUx+PID+hOIHqNoPIGLgu96/7xhmt/EqYxGdebXKi61GE PMIdV+tvzSAUhJZ/worqmCPVAxGM4bv4m+Ue+FRJEg7cMANqk3hQLLCT40FuTbhxVgmX DC7Q9bU79aylGm0rCHpM5oPYLxPJrtXwVziD37NuHYrYOTVf8lSB2hTgllPMXgndIZXz P0kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=pZEGgSdgHuR4AUV+YoPa8xV6M+CUbZlyZQlCkoU7l74=; fh=jvpdohKmRoZMO537s6xMKXXtj7EZws1LOMQI/oP4vXs=; b=xZMPMCESvjbp9wE4BJci3/FMD+KRiUicaesEAEmvgo4eP+eNqs2qxIyW+7aaOa/Rdl cJqtpHk7fuoxpNRzeDl8YfDMIwkA7Lf7IfIAvCbjfrPZfA99uBnULQ+6z0ytcZua5pWq nwFW930cKuj0nV+dtdWOx9+30dh9tVrWtSGSYlnXv7jkBWfonZo9wPWNDvE8+pkazBLK pCwZbLAuRfaGaXbHfjW6a3Aelmv1AhnyeJWVqXF5DDRhIWUvmy2IY3rzk31MrmdeEb5J uSl/N30gKXNnmIEwfwyOxUuDc6f4KeeSFPwI46Gpzq0JPGx94IA/FX40kuyEnWB8xEt5 kBQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sfnzhwLW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id h20-20020a05600c261400b003fe2ebf479fsm10835617wma.36.2023.08.07.07.15.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 07:15:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 15/15] target/arm: Adjust PAR_EL1.SH for Device and Normal-NC memory types Date: Mon, 7 Aug 2023 15:15:14 +0100 Message-Id: <20230807141514.19075-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230807141514.19075-1-peter.maydell@linaro.org> References: <20230807141514.19075-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The PAR_EL1.SH field documents that for the cases of: * Device memory * Normal memory with both Inner and Outer Non-Cacheable the field should be 0b10 rather than whatever was in the translation table descriptor field. (In the pseudocode this is handled by PAREncodeShareability().) Perform this adjustment when assembling a PAR value. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8290ca0aaad..da5db6d3ff6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3342,6 +3342,19 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, } #ifdef CONFIG_TCG +static int par_el1_shareability(GetPhysAddrResult *res) +{ + /* + * The PAR_EL1.SH field must be 0b10 for Device or Normal-NC + * memory -- see pseudocode PAREncodeShareability(). + */ + if (((res->cacheattrs.attrs & 0xf0) == 0) || + res->cacheattrs.attrs == 0x44 || res->cacheattrs.attrs == 0x40) { + return 2; + } + return res->cacheattrs.shareability; +} + static uint64_t do_ats_write(CPUARMState *env, uint64_t value, MMUAccessType access_type, ARMMMUIdx mmu_idx, bool is_secure) @@ -3470,7 +3483,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, par64 |= (1 << 9); /* NS */ } par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */ - par64 |= res.cacheattrs.shareability << 7; /* SH */ + par64 |= par_el1_shareability(&res) << 7; /* SH */ } else { uint32_t fsr = arm_fi_to_lfsc(&fi);