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([2602:47:d490:6901:1eed:f77f:f320:8b14]) by smtp.gmail.com with ESMTPSA id t6-20020a170902e84600b001ae0152d280sm2188662plg.193.2023.08.04.14.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 14:33:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jniethe5@gmail.com, qemu-ppc@nongnu.org, bgray@linux.ibm.com Subject: [PATCH 1/7] tcg/ppc: Untabify tcg-target.c.inc Date: Fri, 4 Aug 2023 14:33:49 -0700 Message-Id: <20230804213355.294443-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804213355.294443-1-richard.henderson@linaro.org> References: <20230804213355.294443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 511e14b180..642d0fd128 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -221,7 +221,7 @@ static inline bool in_range_b(tcg_target_long target) } static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, - const tcg_insn_unit *target) + const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(in_range_b(disp)); @@ -241,7 +241,7 @@ static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) } static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, - const tcg_insn_unit *target) + const tcg_insn_unit *target) { ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); tcg_debug_assert(disp == (int16_t) disp); @@ -3587,7 +3587,7 @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, tcgv_vec_arg(t1), tcgv_vec_arg(t2)); vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v0), tcgv_vec_arg(t1)); - break; + break; case MO_32: tcg_debug_assert(!have_isa_2_07); From patchwork Fri Aug 4 21:33:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 710245 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp219982rwb; Fri, 4 Aug 2023 14:35:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHSzVUU+wJbeYSX35EX0J004bue91LwMTVJkbLzUhyXZ/6fzXz+/ozS6gZJUskGEdlhTMju X-Received: by 2002:ad4:51c9:0:b0:63a:19ad:224d with SMTP id p9-20020ad451c9000000b0063a19ad224dmr2424783qvq.61.1691184958386; Fri, 04 Aug 2023 14:35:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691184958; cv=none; d=google.com; s=arc-20160816; b=D+QktO7eeohYptBDEAeTf/orqjGhUqAg5uej9qoOCIyklo3tiWyzZe4aCE72e7J3Va RBIJoEvqjBxaMeJSZRDn3k6hSLcaYIH0+x6BKG94H+ZzzH1KMTjGUBb5lNije5anOWfu UUqCufQsnUEsFDhQ7rtTHJuYxNLmucB0HBHEAUKGXraUxo4QeN8yGmvTNPR5MKXjuHxs d11d7lvza7EJ91TtAXUdrcDCRAy23EQPngBUOV8W/mPY4Ay6Qn2u0e37vLfnj3tyqi+8 mT07DGNw84m64vxCDAgWVQztHLOihgI0Ee/hc4dSiKnGNC0gUuGVhJ4mWNnMibLm9lFe bH9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QXhvB8XyLuww2xCl1ZkNwGIY8SDIYkhxbiAR1SsdBhg=; fh=oDpcRIg3pzWA7lEsXr2+AuYCXCfAwFhPMEhHe0xWPuA=; b=xEGCPgXP6XgPb3k4tZWjEJJsnCkkDk7XjVPZ2DT4Le4cu92EFOdo/7x1O+4ORX1FUv T9FOvFzo7MQYUAMkJCoVbpeBa05VS6MLC3QE5NvxViTW2Qy8GJg23EEeXZu2QiTFvh7N wAQ6LRYpTzJL+koKcRm3KCA+Cncu10/xpHevQuieNAQc34iWWbyk++TjldA/EPPYuSF5 YV9FGHpTef5C7DLHabriHgViBncxFaEuM7OFHp0r9zsfcNE8izH4u5AUMQayYy/qZwR1 Y2Zs9pSlR8JkIZCSXT0+uw/fk1drbzWc8zPVz3aisR+a1aik8mz3b8vLQu7u05tWQxyt /+6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=foEKWYdG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:1eed:f77f:f320:8b14]) by smtp.gmail.com with ESMTPSA id t6-20020a170902e84600b001ae0152d280sm2188662plg.193.2023.08.04.14.33.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 14:33:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jniethe5@gmail.com, qemu-ppc@nongnu.org, bgray@linux.ibm.com Subject: [PATCH 2/7] tcg/ppc: Use PADDI in tcg_out_movi Date: Fri, 4 Aug 2023 14:33:50 -0700 Message-Id: <20230804213355.294443-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804213355.294443-1-richard.henderson@linaro.org> References: <20230804213355.294443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org PADDI can load 34-bit immediates and 34-bit pc-relative addresses. Signed-off-by: Richard Henderson Reviewed-by: Jordan Niethe --- tcg/ppc/tcg-target.c.inc | 47 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 642d0fd128..7fa2a2500b 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -707,6 +707,33 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, return true; } +/* Ensure that the prefixed instruction does not cross a 64-byte boundary. */ +static bool tcg_out_need_prefix_align(TCGContext *s) +{ + return ((uintptr_t)s->code_ptr & 0x3f) == 0x3c; +} + +static void tcg_out_prefix_align(TCGContext *s) +{ + if (tcg_out_need_prefix_align(s)) { + tcg_out32(s, NOP); + } +} + +/* Output Type 10 Prefix - Modified Load/Store Form (MLS:D) */ +static void tcg_out_mls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, + unsigned ra, tcg_target_long imm, bool r) +{ + tcg_insn_unit p, i; + + p = OPCD(1) | (2 << 24) | (r << 20) | ((imm >> 16) & 0x3ffff); + i = opc | TAI(rt, ra, imm); + + tcg_out_prefix_align(s); + tcg_out32(s, p); + tcg_out32(s, i); +} + static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, TCGReg base, tcg_target_long offset); @@ -992,6 +1019,26 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, return; } + /* + * Load values up to 34 bits, and pc-relative addresses, + * with one prefixed insn. + */ + if (have_isa_3_10) { + if (arg == sextract64(arg, 0, 34)) { + /* pli ret,value = paddi ret,0,value,0 */ + tcg_out_mls_d(s, ADDI, ret, 0, arg, 0); + return; + } + + tmp = tcg_out_need_prefix_align(s) * 4; + tmp = tcg_pcrel_diff(s, (void *)arg) - tmp; + if (tmp == sextract64(tmp, 0, 34)) { + /* pla ret,value = paddi ret,0,value,1 */ + tcg_out_mls_d(s, ADDI, ret, 0, tmp, 1); + return; + } + } + /* Load 32-bit immediates with two insns. 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([2602:47:d490:6901:1eed:f77f:f320:8b14]) by smtp.gmail.com with ESMTPSA id t6-20020a170902e84600b001ae0152d280sm2188662plg.193.2023.08.04.14.33.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 14:33:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jniethe5@gmail.com, qemu-ppc@nongnu.org, bgray@linux.ibm.com Subject: [PATCH 3/7] tcg/ppc: Use prefixed instructions in tcg_out_mem_long Date: Fri, 4 Aug 2023 14:33:51 -0700 Message-Id: <20230804213355.294443-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804213355.294443-1-richard.henderson@linaro.org> References: <20230804213355.294443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When the offset is out of range of the non-prefixed insn, but fits the 34-bit immediate of the prefixed insn, use that. Signed-off-by: Richard Henderson Reviewed-by: Jordan Niethe --- tcg/ppc/tcg-target.c.inc | 66 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 7fa2a2500b..d41c499b7d 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -323,6 +323,15 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) #define STDX XO31(149) #define STQ XO62( 2) +#define PLWA OPCD( 41) +#define PLD OPCD( 57) +#define PLXSD OPCD( 42) +#define PLXV OPCD(25 * 2 + 1) /* force tx=1 */ + +#define PSTD OPCD( 61) +#define PSTXSD OPCD( 46) +#define PSTXV OPCD(27 * 2 + 1) /* force tx=1 */ + #define ADDIC OPCD( 12) #define ADDI OPCD( 14) #define ADDIS OPCD( 15) @@ -720,6 +729,20 @@ static void tcg_out_prefix_align(TCGContext *s) } } +/* Output Type 00 Prefix - 8-Byte Load/Store Form (8LS:D) */ +static void tcg_out_8ls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, + unsigned ra, tcg_target_long imm, bool r) +{ + tcg_insn_unit p, i; + + p = OPCD(1) | (r << 20) | ((imm >> 16) & 0x3ffff); + i = opc | TAI(rt, ra, imm); + + tcg_out_prefix_align(s); + tcg_out32(s, p); + tcg_out32(s, i); +} + /* Output Type 10 Prefix - Modified Load/Store Form (MLS:D) */ static void tcg_out_mls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, unsigned ra, tcg_target_long imm, bool r) @@ -1364,6 +1387,49 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, break; } + /* For unaligned or large offsets, use the prefixed form. */ + if (have_isa_3_10 + && (offset != (int16_t)offset || (offset & align)) + && offset == sextract64(offset, 0, 34)) { + /* + * Note that the MLS:D insns retain their un-prefixed opcode, + * while the 8LS:D insns use a different opcode space. + */ + switch (opi) { + case LBZ: + case LHZ: + case LHA: + case LWZ: + case STB: + case STH: + case STW: + case ADDI: + tcg_out_mls_d(s, opi, rt, base, offset, 0); + return; + case LWA: + tcg_out_8ls_d(s, PLWA, rt, base, offset, 0); + return; + case LD: + tcg_out_8ls_d(s, PLD, rt, base, offset, 0); + return; + case STD: + tcg_out_8ls_d(s, PSTD, rt, base, offset, 0); + return; + case LXSD: + tcg_out_8ls_d(s, PLXSD, rt & 31, base, offset, 0); + return; + case STXSD: + tcg_out_8ls_d(s, PSTXSD, rt & 31, base, offset, 0); + return; + case LXV: + tcg_out_8ls_d(s, PLXV, rt & 31, base, offset, 0); + return; + case STXV: + tcg_out_8ls_d(s, PSTXV, rt & 31, base, offset, 0); + return; + } + } + /* For unaligned, or very large offsets, use the indexed form. */ if (offset & align || offset != (int32_t)offset || opi == 0) { if (rs == base) { From patchwork Fri Aug 4 21:33:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 710242 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp219901rwb; Fri, 4 Aug 2023 14:35:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFdPhWANv+P/lYEgwE/3b34A8R798BV62ZtGeJsNaRBIRA0mvmvwUr5CmzAC3x3z26OJihc X-Received: by 2002:a1f:3dc1:0:b0:486:4b9b:8f39 with SMTP id k184-20020a1f3dc1000000b004864b9b8f39mr1958922vka.11.1691184940592; Fri, 04 Aug 2023 14:35:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691184940; cv=none; d=google.com; s=arc-20160816; b=vaDp/W/8YHpxlfQ4JLHxHjKwsAOxoovq7PJFtSreJmrjH+dkQ+qnuoMBIfXFrE5DJ+ Rxhw8MHhLDQLJGljqyXSfeJFtWstTsqTOkJllrcy3hvT+s8SFxoYK4Hx8uYW9Npfp7CO P0259LsfOw4JNRN3D4C3OAqv9mvg38vwaF5LK2+H7e6SPy27czdlAvkWyuN/owvWapRC dUe2OIzO7TvYVy41ZMD6U2/BPlK+NHiKZhnuMYKqpyP5G2G94yKgBxX+AiRUQCKVDJ7V nLRj1swnt0aTQoo8nCy9sy3RVEzlILHeiq19+fqe+p7fLXGau2GtxYA0q83bFYonf3ME 8P9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XSfXUkEbJi6XSSeczzkehSgMMZNGjw0txB1UvXtXqsU=; fh=oDpcRIg3pzWA7lEsXr2+AuYCXCfAwFhPMEhHe0xWPuA=; b=qirRf166HaGNzn19dYp3Yl8s5lmk/4mltHeFF4jWqObBRZMc7j3JFEHAmcaxBg5Rc4 EvuTWwenV0hHcFu/c+8Aqh3ilU4ucbJtEn9vJnmCBvnBymEyNXIAq1F5sImPh2DacjWr UHaqf/9kEpk1yds6GVw3k3SdMHahvndTfKaIL8aUjNAi3UVAVqsSfxy8Ye6LWn2FQbWT pJ2uMJHk0vSsAEsru6fHDOZwT43BLQ2pfZKYgWr8Y5aU5VIApnT1Hrt1uqaLoEAo9stC QCVV6eFqdxb8cXx+idcG3MCDnqBYmaTQ648zcN5x0/BF3r6Q6ljHVRJgtj0bI1fGoK/e d9zA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e46yjR1Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:1eed:f77f:f320:8b14]) by smtp.gmail.com with ESMTPSA id t6-20020a170902e84600b001ae0152d280sm2188662plg.193.2023.08.04.14.33.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 14:33:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jniethe5@gmail.com, qemu-ppc@nongnu.org, bgray@linux.ibm.com Subject: [PATCH 4/7] tcg/ppc: Use PLD in tcg_out_movi for constant pool Date: Fri, 4 Aug 2023 14:33:52 -0700 Message-Id: <20230804213355.294443-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804213355.294443-1-richard.henderson@linaro.org> References: <20230804213355.294443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The prefixed instruction has a pc-relative form to use here. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d41c499b7d..a9e48a51c8 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -101,6 +101,10 @@ #define ALL_GENERAL_REGS 0xffffffffu #define ALL_VECTOR_REGS 0xffffffff00000000ull +#ifndef R_PPC64_PCREL34 +#define R_PPC64_PCREL34 132 +#endif + #define have_isel (cpuinfo & CPUINFO_ISEL) #ifndef CONFIG_SOFTMMU @@ -260,6 +264,19 @@ static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) return false; } +static bool reloc_pc34(tcg_insn_unit *src_rw, const tcg_insn_unit *target) +{ + const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); + ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); + + if (disp == sextract64(disp, 0, 34)) { + src_rw[0] = (src_rw[0] & ~0x3ffff) | ((disp >> 16) & 0x3ffff); + src_rw[1] = (src_rw[1] & ~0xffff) | (disp & 0xffff); + return true; + } + return false; +} + /* test if a constant matches the constraint */ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) { @@ -684,6 +701,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type, return reloc_pc14(code_ptr, target); case R_PPC_REL24: return reloc_pc24(code_ptr, target); + case R_PPC64_PCREL34: + return reloc_pc34(code_ptr, target); case R_PPC_ADDR16: /* * We are (slightly) abusing this relocation type. In particular, @@ -1107,6 +1126,11 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, } /* Use the constant pool, if possible. */ + if (have_isa_3_10) { + tcg_out_8ls_d(s, PLD, ret, 0, 0, 1); + new_pool_label(s, arg, R_PPC64_PCREL34, s->code_ptr - 2, 0); + return; + } if (!in_prologue && USE_REG_TB) { new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, tcg_tbrel_diff(s, NULL)); From patchwork Fri Aug 4 21:33:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 710241 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp219898rwb; Fri, 4 Aug 2023 14:35:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEu3yz3YYFCNLK3rqh+wbVleH3FxVya/t66yQzz2V9h9R0MbNHPbwlX6aQuRXDaq7GuZ4v7 X-Received: by 2002:a05:620a:44cd:b0:765:3e03:10db with SMTP id y13-20020a05620a44cd00b007653e0310dbmr3544167qkp.48.1691184940268; Fri, 04 Aug 2023 14:35:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691184940; cv=none; d=google.com; s=arc-20160816; b=Tp9jGUkVOoQrRoWYQvI0zVgCRcnnuZnVJNgB+6XZGNfulhsi6cWpIa5YSzsmKh7SNy BQj4okXp86T27TJDoFXzdQMI6ig4QgnXEl5a1w8xzkkjFPdK7rDRXBnI5pyfR3LiUbat bRtYKyZVSaYKOFIZXBNIpzKJtpEE+TmeR582U/PIOckg7t24cbDR6EGEYy2dkcR1hWYX sihfWiUlS1T0iEK2VPCcsUPWpOZZIMHVc4Ka6sKVYfNGLTSSSbgolStIBzd3PGQ+apts PvHfSiQZn9los4NMqKVO6L0TbNMkvXzSWcsxC5O5HbCE6ZqS7syAKWhbJsR7ZGfW/QcT FD7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7Fc9S/4//cSOxgnGncfnlKz99u+sNj+6+KTbB1MnhPw=; fh=oDpcRIg3pzWA7lEsXr2+AuYCXCfAwFhPMEhHe0xWPuA=; b=FqKJ7kdovIsGD1UgPmLQXAmDwmtyofPK3FH3JTT45H7AcD28U2TL4As4jOOHlA9Gry p/iTbVp7vGzQWIXcXFLzy3N1RWqIHS6v8oBf/8jKv3Flovn/kaxIj3dv3retYGivrTMw AV4fbGb0ONbd+WJw0Xa3HrOdskdSU/pRXua8w02tXCA1UHy/+GExWlPh6UjwRJCHlU24 Bu986EqwsByvo30wZNItevRJiXGGy9Ubtk4e775ijCSAmZa2NLibzfJygWvFc5jrII8l YVYqWo7V+snWnw4vHrLD0PiGU2qq80pqAN4wS/YBjZX6EO+NndKrxZmOQkLOoymnw8ET tmmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oUaIpjej; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:1eed:f77f:f320:8b14]) by smtp.gmail.com with ESMTPSA id t6-20020a170902e84600b001ae0152d280sm2188662plg.193.2023.08.04.14.34.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 14:34:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jniethe5@gmail.com, qemu-ppc@nongnu.org, bgray@linux.ibm.com Subject: [PATCH 5/7] tcg/ppc: Use prefixed instructions in tcg_out_dupi_vec Date: Fri, 4 Aug 2023 14:33:53 -0700 Message-Id: <20230804213355.294443-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804213355.294443-1-richard.henderson@linaro.org> References: <20230804213355.294443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The prefixed instructions have a pc-relative form to use here. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index a9e48a51c8..e8eced7cf3 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1191,6 +1191,18 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, /* * Otherwise we must load the value from the constant pool. */ + + if (have_isa_3_10) { + if (type == TCG_TYPE_V64) { + tcg_out_8ls_d(s, PLXSD, ret & 31, 0, 0, 1); + new_pool_label(s, val, R_PPC64_PCREL34, s->code_ptr - 2, 0); + } else { + tcg_out_8ls_d(s, PLXV, ret & 31, 0, 0, 1); + new_pool_l2(s, R_PPC64_PCREL34, s->code_ptr - 2, 0, val, val); + } + return; + } + if (USE_REG_TB) { rel = R_PPC_ADDR16; add = tcg_tbrel_diff(s, NULL); From patchwork Fri Aug 4 21:33:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 710239 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp219893rwb; Fri, 4 Aug 2023 14:35:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHu4saDwtFySlI5Bi5irbFdqKbYf46S4LP0XqKQpeNxxQvO5itNc0s2WIaWrYk0yj+ncz8D X-Received: by 2002:a67:f4ce:0:b0:447:6ba8:9a21 with SMTP id s14-20020a67f4ce000000b004476ba89a21mr2266325vsn.27.1691184939723; Fri, 04 Aug 2023 14:35:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691184939; cv=none; d=google.com; s=arc-20160816; b=k5udCDsYdyzMUqpgvsHeJi7CW861UVRRS1aRlzYyZMtNCW+eLfsdfKnpvcddY0erE1 K/u7JPwa3Kyd56foZhjGPYNAwXqLApyTfW2L6roN/u7AOmw53sqROJlIzOxQqus/zXnp qjw7FKHAeOH0BIiE5yWG+t9oVzU2g1T16RbUfu3pBnGB+5kV12O0XnP+piyO3kMSi6dP 167AD2zSAICWt0xs3hPHP9O/LvBjBL6UuSlQkFYKrBDDJ8jr7nUrAWf1cYcs1auuUuai 2f0zlNVIthwSsDMxXKqgpcH8YXVb8Lm9wgpWiDsgmSKOXPE6+1KeaMJsWr9L6U9vahpO kT4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=O5oE4+VawxP53rOCLWmxeNePvIcIJOdD/vpw31mMUWo=; fh=oDpcRIg3pzWA7lEsXr2+AuYCXCfAwFhPMEhHe0xWPuA=; b=umd2SV6wgMs+/XDMLLjsrWJvbxwt0qbv92dwy4zRlYilAlcKiRgex/UKSZ52vFzxQV jX+DRXwRQSHkPQOK1tTUycbKw6fBa4tSec7UgaAJoeUUisJpLO5C4H+5+aVjwqS8gkAq g6D0T34FQFa+j1tBiezM7hjasnVOUm9RhmksHFkjflciZz36gCs2coyNJwY/fgdNLRpT BzDbu1dUR8O5DZ99Nqn3Vn8A14ia7XloYvLiNPQ24xSKpOeyVfF4L7BpdfLjn0lZcXiA i7eY0R9FGMzWsFfdCIijbQwYSkfRQUVdm9lyuv/GpXzgTZ0PIfdPPJMRH8g1PAnr+LCE 4nxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UPoCeymM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([2602:47:d490:6901:1eed:f77f:f320:8b14]) by smtp.gmail.com with ESMTPSA id t6-20020a170902e84600b001ae0152d280sm2188662plg.193.2023.08.04.14.34.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 14:34:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jniethe5@gmail.com, qemu-ppc@nongnu.org, bgray@linux.ibm.com Subject: [PATCH 6/7] tcg/ppc: Disable USE_REG_TB for Power v3.1 Date: Fri, 4 Aug 2023 14:33:54 -0700 Message-Id: <20230804213355.294443-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804213355.294443-1-richard.henderson@linaro.org> References: <20230804213355.294443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org With Power v3.1, we have pc-relative addressing and so do not require a register holding the current TB. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e8eced7cf3..5b243b2353 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -83,7 +83,7 @@ #define TCG_VEC_TMP2 TCG_REG_V1 #define TCG_REG_TB TCG_REG_R31 -#define USE_REG_TB (TCG_TARGET_REG_BITS == 64) +#define USE_REG_TB (TCG_TARGET_REG_BITS == 64 && !have_isa_3_10) /* Shorthand for size of a pointer. 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([2602:47:d490:6901:1eed:f77f:f320:8b14]) by smtp.gmail.com with ESMTPSA id t6-20020a170902e84600b001ae0152d280sm2188662plg.193.2023.08.04.14.34.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Aug 2023 14:34:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: jniethe5@gmail.com, qemu-ppc@nongnu.org, bgray@linux.ibm.com Subject: [PATCH 7/7] tcg/ppc: Use prefixed instructions for tcg_out_goto_tb Date: Fri, 4 Aug 2023 14:33:55 -0700 Message-Id: <20230804213355.294443-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230804213355.294443-1-richard.henderson@linaro.org> References: <20230804213355.294443-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When a direct branch is out of range, we can load the destination for the indirect branch using PLA (for 16GB worth of buffer) and PLD from the TranslationBlock for everything larger. This means the patch affects exactly one instruction: B (plus filler), PLA or PLD. Which means we can update and execute the patch atomically. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 76 ++++++++++++++++++++++++++++++---------- 1 file changed, 58 insertions(+), 18 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 5b243b2353..47c71bb5f2 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2642,31 +2642,41 @@ static void tcg_out_goto_tb(TCGContext *s, int which) uintptr_t ptr = get_jmp_target_addr(s, which); if (USE_REG_TB) { + /* + * With REG_TB, we must always use indirect branching, + * so that the branch destination and TCG_REG_TB match. + */ ptrdiff_t offset = tcg_tbrel_diff(s, (void *)ptr); tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset); - - /* TODO: Use direct branches when possible. */ - set_jmp_insn_offset(s, which); tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS); /* For the unlinked case, need to reset TCG_REG_TB. */ set_jmp_reset_offset(s, which); tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, -tcg_current_code_size(s)); + return; + } + + if (have_isa_3_10) { + /* Align, so that we can patch 8 bytes atomically. */ + if ((uintptr_t)s->code_ptr & 7) { + tcg_out32(s, NOP); + } + set_jmp_insn_offset(s, which); + /* Direct branch will be patched by tb_target_set_jmp_target. */ + tcg_out_mls_d(s, ADDI, TCG_REG_TMP1, 0, 0, 1); } else { /* Direct branch will be patched by tb_target_set_jmp_target. */ - set_jmp_insn_offset(s, which); - tcg_out32(s, NOP); - + tcg_out32(s, B); /* When branch is out of range, fall through to indirect. */ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)ptr); - tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); - tcg_out32(s, BCCTR | BO_ALWAYS); - set_jmp_reset_offset(s, which); } + + tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); + tcg_out32(s, BCCTR | BO_ALWAYS); + set_jmp_reset_offset(s, which); } void tb_target_set_jmp_target(const TranslationBlock *tb, int n, @@ -2674,20 +2684,50 @@ void tb_target_set_jmp_target(const TranslationBlock *tb, int n, { uintptr_t addr = tb->jmp_target_addr[n]; intptr_t diff = addr - jmp_rx; - tcg_insn_unit insn; if (USE_REG_TB) { return; } - if (in_range_b(diff)) { - insn = B | (diff & 0x3fffffc); - } else { - insn = NOP; - } + if (have_isa_3_10) { + tcg_insn_unit insn1, insn2; + uint64_t pair; - qatomic_set((uint32_t *)jmp_rw, insn); - flush_idcache_range(jmp_rx, jmp_rw, 4); + if (in_range_b(diff)) { + insn1 = B | (diff & 0x3fffffc); + insn2 = NOP; + } else if (diff == sextract64(diff, 0, 34)) { + /* PLA tmp1, diff */ + insn1 = OPCD(1) | (2 << 24) | (1 << 20) | ((diff >> 16) & 0x3ffff); + insn2 = ADDI | TAI(TCG_REG_TMP1, 0, diff); + } else { + addr = (uintptr_t)&tb->jmp_target_addr[n]; + diff = addr - jmp_rx; + tcg_debug_assert(diff == sextract64(diff, 0, 34)); + /* PLD tmp1, diff */ + insn1 = OPCD(1) | (1 << 20) | ((diff >> 16) & 0x3ffff); + insn2 = PLD | TAI(TCG_REG_TMP1, 0, diff); + } + + if (HOST_BIG_ENDIAN) { + pair = ((uint64_t)insn1) << 32 | insn2; + } else { + pair = ((uint64_t)insn2) << 32 | insn1; + } + + qatomic_set((uint64_t *)jmp_rw, pair); + flush_idcache_range(jmp_rx, jmp_rw, 8); + } else { + tcg_insn_unit insn; + + if (in_range_b(diff)) { + insn = B | (diff & 0x3fffffc); + } else { + insn = NOP; + } + qatomic_set((uint32_t *)jmp_rw, insn); + flush_idcache_range(jmp_rx, jmp_rw, 4); + } } static void tcg_out_op(TCGContext *s, TCGOpcode opc,