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Mon, 31 Jul 2023 04:50:41 -0500 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 31 Jul 2023 04:50:37 -0500 From: Sai Krishna Potthuri To: Linus Walleij , Michal Simek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Tanmay Shah , Ben Levinsky , Marek Vasut , Roman Gushchin , Arnd Bergmann CC: , , , , , , Sai Krishna Potthuri Subject: [PATCH v3 2/4] firmware: xilinx: Add version check for TRISTATE configuration Date: Mon, 31 Jul 2023 15:20:24 +0530 Message-ID: <20230731095026.3766675-3-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230731095026.3766675-1-sai.krishna.potthuri@amd.com> References: <20230731095026.3766675-1-sai.krishna.potthuri@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT093:EE_|SA1PR12MB6894:EE_ X-MS-Office365-Filtering-Correlation-Id: 31b02021-a1e7-40a1-05f5-08db91ab9c8e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230028)(4636009)(39860400002)(346002)(376002)(136003)(396003)(451199021)(82310400008)(46966006)(40470700004)(36840700001)(5660300002)(7416002)(70586007)(70206006)(4326008)(2906002)(40480700001)(316002)(8936002)(54906003)(41300700001)(8676002)(478600001)(110136005)(6666004)(1076003)(36860700001)(40460700003)(26005)(47076005)(426003)(83380400001)(186003)(103116003)(36756003)(2616005)(921005)(356005)(336012)(81166007)(82740400003)(86362001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jul 2023 09:50:45.3639 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 31b02021-a1e7-40a1-05f5-08db91ab9c8e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT093.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6894 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Support for configuring TRISTATE parameter is added in ZYNQMP PMUFW(Xilinx ZynqMP Platform Management Firmware) Configuration Param Set version 2.0. If the requested configuration is TRISTATE and platform is ZYNQMP then check the version before requesting Xilinx firmware to set the configuration. Signed-off-by: Sai Krishna Potthuri Reviewed-by: Michal Simek --- drivers/firmware/xilinx/zynqmp.c | 9 +++++++++ include/linux/firmware/xlnx-zynqmp.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index e204e2866d74..e93b12ad0ddb 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -1148,6 +1148,15 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_get_config); int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, u32 value) { + int ret; + + if (pm_family_code == ZYNQMP_FAMILY_CODE && + param == PM_PINCTRL_CONFIG_TRI_STATE) { + ret = zynqmp_pm_feature(PM_PINCTRL_CONFIG_PARAM_SET); + if (ret < PM_PINCTRL_PARAM_SET_VERSION) + return -EOPNOTSUPP; + } + return zynqmp_pm_invoke_fn(PM_PINCTRL_CONFIG_PARAM_SET, pin, param, value, 0, NULL); } diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 075a8f7f1706..ac50eb98b17a 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -34,6 +34,8 @@ /* PM API versions */ #define PM_API_VERSION_2 2 +#define PM_PINCTRL_PARAM_SET_VERSION 2 + #define ZYNQMP_FAMILY_CODE 0x23 #define VERSAL_FAMILY_CODE 0x26 From patchwork Mon Jul 31 09:50:26 2023 Content-Type: text/plain; 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Mon, 31 Jul 2023 04:50:51 -0500 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Mon, 31 Jul 2023 04:50:46 -0500 From: Sai Krishna Potthuri To: Linus Walleij , Michal Simek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mathieu Poirier , Tanmay Shah , Ben Levinsky , Marek Vasut , Roman Gushchin , Arnd Bergmann CC: , , , , , , Sai Krishna Potthuri Subject: [PATCH v3 4/4] pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high impedance Date: Mon, 31 Jul 2023 15:20:26 +0530 Message-ID: <20230731095026.3766675-5-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230731095026.3766675-1-sai.krishna.potthuri@amd.com> References: <20230731095026.3766675-1-sai.krishna.potthuri@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT041:EE_|PH7PR12MB9067:EE_ X-MS-Office365-Filtering-Correlation-Id: aa069868-fed7-43da-a2cb-08db91aba0d7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230028)(4636009)(376002)(136003)(346002)(39860400002)(396003)(82310400008)(451199021)(36840700001)(46966006)(40470700004)(356005)(921005)(81166007)(82740400003)(40480700001)(86362001)(36756003)(103116003)(40460700003)(478600001)(6666004)(2616005)(336012)(186003)(1076003)(26005)(8676002)(8936002)(7416002)(5660300002)(70586007)(4326008)(70206006)(2906002)(54906003)(110136005)(41300700001)(316002)(36860700001)(426003)(83380400001)(47076005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Jul 2023 09:50:52.5572 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa069868-fed7-43da-a2cb-08db91aba0d7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT041.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9067 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add support to handle 'output-enable' and 'bias-high-impedance' configurations. Using these pinctrl properties observed hang issues with older PMUFW(Xilinx ZynqMP Platform Management Firmware), hence reverted the patch. Commit 9989bc33c4894e075167 ("Revert "pinctrl: pinctrl-zynqmp: Add support for output-enable and bias-high-impedance""). Support for configuring these properties added in PMUFW Configuration Set version 2.0. When there is a request for these configurations from pinctrl driver for ZynqMP platform, xilinx firmware driver checks for this version before configuring these properties to avoid the hang issue and proceeds further only when firmware version is >=2 otherwise it returns error. Signed-off-by: Sai Krishna Potthuri --- drivers/pinctrl/pinctrl-zynqmp.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 8d2cb0999f2f..f2be341f73e1 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -415,6 +415,10 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, break; case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_ENABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; case PIN_CONFIG_MODE_LOW_POWER: /* * These cases are mentioned in dts but configurable @@ -423,6 +427,11 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, */ ret = 0; break; + case PIN_CONFIG_OUTPUT_ENABLE: + param = PM_PINCTRL_CONFIG_TRI_STATE; + arg = PM_PINCTRL_TRI_STATE_DISABLE; + ret = zynqmp_pm_pinctrl_set_config(pin, param, arg); + break; default: dev_warn(pctldev->dev, "unsupported configuration parameter '%u'\n",