From patchwork Mon Jul 31 10:57:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB486C001DC for ; Mon, 31 Jul 2023 10:58:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229699AbjGaK6t (ORCPT ); Mon, 31 Jul 2023 06:58:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44254 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbjGaK6f (ORCPT ); Mon, 31 Jul 2023 06:58:35 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FD061735 for ; Mon, 31 Jul 2023 03:58:03 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-4f954d7309fso5403291e87.1 for ; Mon, 31 Jul 2023 03:58:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690801082; x=1691405882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wULRwpAxU3U7giaQfcAakpif5xyYnV0aX4xD6FbXu+4=; b=Yq4DmWPvbUoxP6gXv2c9bb23Ok/scjrMnK0wlUQw5HSsOVuEozvq/47KuuYP9ymBn2 ZCDW8tybhRytDhzpbdW7FU+ISs34WHtO6ZP2sVsOAZR16nsoWRton78ocZsQhMXJakVV 00AQcKuSRpY752xU4L58z0bxJ8LGTzqAYA2lux/g42gC+AHFN/ZRIHyOXCQGYcVbCdUZ TdH9q2+hhNwj31qYAbq8ZymXGgooeZYQIvDcHZBh8GjhPHEGP2S1B9ITQ8eE0xMDS+Ig N+AZltOx35sfldt3ropmmV2J6923YHA0Sc0rjnizAYPxEOYFJengZDT4ZMk5hyI4F3eE w4qA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690801082; x=1691405882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wULRwpAxU3U7giaQfcAakpif5xyYnV0aX4xD6FbXu+4=; b=AyinanGqh8AO5WYMQcm4dxuVcPz98okpkWr88cOxbbYJO8RiIGwO2Lo5+k6CzxaYTi CFbwYPfDOguECxVIfR08/aM6hJKPqC5tXkh59ajxxjIG+9I0PQenqh8dYgu1wAx+i+Ze RlnqnncrHwEOd3+WY5rREYpDFR8s+ZccYHOQz3ECAWXZvWh+M9F+38RIO52+/d4z42pl fq+QnCDq6ZKNo9ktNiNG0eV3nxOA4d5IfHieHFD98NCcmPj4wFkFuEykRhawLPIDSFQC +4mlw918OjCer70H+N4Y4U1sHIyLUUtt0YmR6PmRvgNURiB+d+6Hn286EYpinKNWDsww qSXA== X-Gm-Message-State: ABy/qLZSqu7ynJdNxC4h4nN0fxYMhtCGf25oNziMoBvN8uoG6sYYduO4 KXzm1n6h9qHleu6Avq4Lyo1gSw== X-Google-Smtp-Source: APBJJlENzXUf2/jahJ8muGuIEqlRMrLwYb2rc9i5rUDAA4jugvP2M1QvBj1/1nr3WM6/XDQopxz+nA== X-Received: by 2002:a05:6512:b97:b0:4fe:32cd:481f with SMTP id b23-20020a0565120b9700b004fe32cd481fmr1328540lfv.1.1690801081687; Mon, 31 Jul 2023 03:58:01 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c19-20020ac24153000000b004fb9fe34c27sm2025497lfi.92.2023.07.31.03.58.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 03:58:01 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 01/13] dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml Date: Mon, 31 Jul 2023 13:57:47 +0300 Message-Id: <20230731105759.3997549-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> References: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Migrate legacy bindings (described in qcom,ipq8074-qmp-pcie-phy.yaml) to qcom,sc8280xp-qmp-pcie-phy.yaml. This removes a need to declare the child PHY node or split resource regions. Signed-off-by: Dmitry Baryshkov --- .../phy/qcom,ipq8074-qmp-pcie-phy.yaml | 278 +++--------------- .../phy/qcom,msm8998-qmp-pcie-phy.yaml | 97 ++++++ .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 34 ++- 3 files changed, 163 insertions(+), 246 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-pcie-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml index 3d42ee3901a1..5073007267ad 100644 --- a/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml @@ -13,287 +13,79 @@ description: QMP PHY controller supports physical layer functionality for a number of controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. - Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see - qcom,sc8280xp-qmp-pcie-phy.yaml. - properties: compatible: enum: - qcom,ipq6018-qmp-pcie-phy - qcom,ipq8074-qmp-gen3-pcie-phy - qcom,ipq8074-qmp-pcie-phy - - qcom,msm8998-qmp-pcie-phy - - qcom,sc8180x-qmp-pcie-phy - - qcom,sdm845-qhp-pcie-phy - - qcom,sdm845-qmp-pcie-phy - - qcom,sdx55-qmp-pcie-phy - - qcom,sm8250-qmp-gen3x1-pcie-phy - - qcom,sm8250-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen4x2-pcie-phy reg: items: - description: serdes - "#address-cells": - enum: [ 1, 2 ] - - "#size-cells": - enum: [ 1, 2 ] - - ranges: true - clocks: - minItems: 2 - maxItems: 4 + maxItems: 3 clock-names: - minItems: 2 - maxItems: 4 + items: + - const: aux + - const: cfg_ahb + - const: pipe resets: - minItems: 1 maxItems: 2 reset-names: - minItems: 1 - maxItems: 2 - - vdda-phy-supply: true - - vdda-pll-supply: true - - vddp-ref-clk-supply: true - -patternProperties: - "^phy@[0-9a-f]+$": - type: object - description: single PHY-provider child node - properties: - reg: - minItems: 3 - maxItems: 6 - - clocks: - items: - - description: PIPE clock - - clock-names: - deprecated: true - items: - - const: pipe0 - - "#clock-cells": - const: 0 - - clock-output-names: - maxItems: 1 + items: + - const: phy + - const: common - "#phy-cells": - const: 0 + "#clock-cells": + const: 0 - required: - - reg - - clocks - - "#clock-cells" - - clock-output-names - - "#phy-cells" + clock-output-names: + maxItems: 1 - additionalProperties: false + "#phy-cells": + const: 0 required: - compatible - reg - - "#address-cells" - - "#size-cells" - - ranges - clocks - clock-names - resets - reset-names + - "#clock-cells" + - clock-output-names + - "#phy-cells" additionalProperties: false -allOf: - - if: - properties: - compatible: - contains: - enum: - - qcom,msm8998-qmp-pcie-phy - then: - properties: - clocks: - maxItems: 3 - clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - resets: - maxItems: 2 - reset-names: - items: - - const: phy - - const: common - required: - - vdda-phy-supply - - vdda-pll-supply - - - if: - properties: - compatible: - contains: - enum: - - qcom,ipq6018-qmp-pcie-phy - - qcom,ipq8074-qmp-gen3-pcie-phy - - qcom,ipq8074-qmp-pcie-phy - then: - properties: - clocks: - maxItems: 2 - clock-names: - items: - - const: aux - - const: cfg_ahb - resets: - maxItems: 2 - reset-names: - items: - - const: phy - - const: common - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc8180x-qmp-pcie-phy - - qcom,sdm845-qhp-pcie-phy - - qcom,sdm845-qmp-pcie-phy - - qcom,sdx55-qmp-pcie-phy - - qcom,sm8250-qmp-gen3x1-pcie-phy - - qcom,sm8250-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen4x2-pcie-phy - then: - properties: - clocks: - maxItems: 4 - clock-names: - items: - - const: aux - - const: cfg_ahb - - const: ref - - const: refgen - resets: - maxItems: 1 - reset-names: - items: - - const: phy - required: - - vdda-phy-supply - - vdda-pll-supply - - - if: - properties: - compatible: - contains: - enum: - - qcom,sc8180x-qmp-pcie-phy - - qcom,sm8250-qmp-gen3x2-pcie-phy - - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8450-qmp-gen4x2-pcie-phy - then: - patternProperties: - "^phy@[0-9a-f]+$": - properties: - reg: - items: - - description: TX lane 1 - - description: RX lane 1 - - description: PCS - - description: TX lane 2 - - description: RX lane 2 - - description: PCS_MISC - - - if: - properties: - compatible: - contains: - enum: - - qcom,sdm845-qmp-pcie-phy - - qcom,sdx55-qmp-pcie-phy - - qcom,sm8250-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - then: - patternProperties: - "^phy@[0-9a-f]+$": - properties: - reg: - items: - - description: TX - - description: RX - - description: PCS - - description: PCS_MISC - - - if: - properties: - compatible: - contains: - enum: - - qcom,ipq6018-qmp-pcie-phy - - qcom,ipq8074-qmp-pcie-phy - - qcom,msm8998-qmp-pcie-phy - - qcom,sdm845-qhp-pcie-phy - then: - patternProperties: - "^phy@[0-9a-f]+$": - properties: - reg: - items: - - description: TX - - description: RX - - description: PCS - examples: - | - #include - phy-wrapper@1c0e000 { - compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; - reg = <0x01c0e000 0x1c0>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x01c0e000 0x1000>; - - clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, - <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, - <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; - - resets = <&gcc GCC_PCIE_1_PHY_BCR>; - reset-names = "phy"; + #include + #include - vdda-phy-supply = <&vreg_l10c_0p88>; - vdda-pll-supply = <&vreg_l6b_1p2>; + phy@84000 { + compatible = "qcom,ipq6018-qmp-pcie-phy"; + reg = <0x0 0x00084000 0x0 0x1000>; - phy@200 { - reg = <0x200 0x170>, - <0x400 0x200>, - <0xa00 0x1f0>, - <0x600 0x170>, - <0x800 0x200>, - <0xe00 0xf4>; + clocks = <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe"; - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-output-names = "gcc_pcie0_pipe_clk_src"; + #clock-cells = <0>; - #clock-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; + #phy-cells = <0>; - #phy-cells = <0>; - }; + resets = <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names = "phy", + "common"; }; diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-pcie-phy.yaml new file mode 100644 index 000000000000..d05eef0e1ccd --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-pcie-phy.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (PCIe, MSM8998) + +maintainers: + - Vinod Koul + +description: + The QMP PHY controller supports physical layer functionality for a number of + controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB. + +properties: + compatible: + const: qcom,msm8998-qmp-pcie-phy + + reg: + items: + - description: serdes + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: pipe + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: common + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - clock-output-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + + phy@1c18000 { + compatible = "qcom,msm8998-qmp-pcie-phy"; + reg = <0x01c06000 0x1000>; + + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_CLKREF_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk_src"; + #clock-cells = <0>; + + #phy-cells = <0>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy", "common"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index ca55ed9d74ac..a2c894a33c1c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,11 +18,21 @@ properties: enum: - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy + - qcom,sc8180x-qmp-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy - qcom,sdx65-qmp-gen4x2-pcie-phy + - qcom,sm8150-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen4x2-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy @@ -40,7 +50,7 @@ properties: - const: aux - const: cfg_ahb - const: ref - - const: rchng + - enum: [rchng, refgen] - const: pipe - const: pipediv2 - const: phy_aux @@ -87,7 +97,6 @@ required: - reg - clocks - clock-names - - power-domains - resets - reset-names - vdda-phy-supply @@ -123,7 +132,17 @@ allOf: compatible: contains: enum: + - qcom,sc8180x-qmp-pcie-phy + - qcom,sdm845-qhp-pcie-phy + - qcom,sdm845-qmp-pcie-phy + - qcom,sdx55-qmp-pcie-phy + - qcom,sm8150-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x1-pcie-phy + - qcom,sm8250-qmp-gen3x2-pcie-phy + - qcom,sm8250-qmp-modem-pcie-phy - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy then: @@ -132,7 +151,16 @@ allOf: maxItems: 5 clock-names: maxItems: 5 - else: + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-qmp-gen3x1-pcie-phy + - qcom,sc8280xp-qmp-gen3x2-pcie-phy + - qcom,sc8280xp-qmp-gen3x4-pcie-phy + then: properties: clocks: minItems: 6 From patchwork Mon Jul 31 10:57:48 2023 Content-Type: text/plain; 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Rather than introducing additional code to handle legacy vs current bindings (and clock names), use devm_clk_bulk_get_optional(). Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 78 +++--------------------- 1 file changed, 7 insertions(+), 71 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index e15ea113b2db..f3717cb4a0e1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2194,9 +2194,6 @@ struct qmp_phy_cfg { const struct qmp_phy_init_tbl *serdes_4ln_tbl; int serdes_4ln_num; - /* clock ids to be requested */ - const char * const *clk_list; - int num_clks; /* resets to be requested */ const char * const *reset_list; int num_resets; @@ -2275,24 +2272,8 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) } /* list of clocks required by phy */ -static const char * const ipq8074_pciephy_clk_l[] = { - "aux", "cfg_ahb", -}; - -static const char * const msm8996_phy_clk_l[] = { - "aux", "cfg_ahb", "ref", -}; - -static const char * const sc8280xp_pciephy_clk_l[] = { - "aux", "cfg_ahb", "ref", "rchng", -}; - -static const char * const sdm845_pciephy_clk_l[] = { - "aux", "cfg_ahb", "ref", "refgen", -}; - -static const char * const sa8775p_pciephy_clk_l[] = { - "aux", "cfg_ahb", "ref", "rchng", "phy_aux", +static const char * const qmp_pciephy_clk_l[] = { + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", }; /* list of regulators */ @@ -2368,8 +2349,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .pcs = ipq8074_pcie_pcs_tbl, .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl), }, - .clk_list = ipq8074_pciephy_clk_l, - .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), .reset_list = ipq8074_pciephy_reset_l, .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), .vreg_list = NULL, @@ -2395,8 +2374,6 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl), }, - .clk_list = ipq8074_pciephy_clk_l, - .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), .reset_list = ipq8074_pciephy_reset_l, .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), .vreg_list = NULL, @@ -2424,8 +2401,6 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { .pcs_misc = ipq6018_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl), }, - .clk_list = ipq8074_pciephy_clk_l, - .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l), .reset_list = ipq8074_pciephy_reset_l, .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), .vreg_list = NULL, @@ -2451,8 +2426,6 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl), }, - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2474,8 +2447,6 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { .pcs = sdm845_qhp_pcie_pcs_tbl, .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl), }, - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2511,8 +2482,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl), }, - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2548,8 +2517,6 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl), }, - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2573,8 +2540,6 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { .pcs = msm8998_pcie_pcs_tbl, .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl), }, - .clk_list = msm8996_phy_clk_l, - .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), .reset_list = ipq8074_pciephy_reset_l, .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2602,8 +2567,6 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl), }, - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2637,8 +2600,6 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl), }, - .clk_list = sc8280xp_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2672,8 +2633,6 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl), }, - .clk_list = sc8280xp_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2710,8 +2669,6 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl, .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl), - .clk_list = sc8280xp_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2752,8 +2709,6 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl), }, - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2789,8 +2744,6 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl), }, - .clk_list = sc8280xp_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2826,8 +2779,6 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl), }, - .clk_list = sc8280xp_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2855,8 +2806,6 @@ static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl), }, - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2890,8 +2839,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl), }, - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2932,8 +2879,6 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl), }, - .clk_list = sdm845_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2961,8 +2906,6 @@ static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = { .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl, .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl), }, - .clk_list = sc8280xp_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -2992,8 +2935,6 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl, .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl), }, - .clk_list = sc8280xp_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = sm8550_qmp_phy_vreg_l, @@ -3029,8 +2970,6 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), }, - .clk_list = sa8775p_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sa8775p_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -3065,8 +3004,6 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl), }, - .clk_list = sa8775p_pciephy_clk_l, - .num_clks = ARRAY_SIZE(sa8775p_pciephy_clk_l), .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, @@ -3189,7 +3126,7 @@ static int qmp_pcie_init(struct phy *phy) goto err_assert_reset; } - ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); if (ret) goto err_assert_reset; @@ -3210,7 +3147,7 @@ static int qmp_pcie_exit(struct phy *phy) reset_control_bulk_assert(cfg->num_resets, qmp->resets); - clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); + clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); regulator_bulk_disable(cfg->num_vregs, qmp->vregs); @@ -3393,9 +3330,8 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) static int qmp_pcie_clk_init(struct qmp_pcie *qmp) { - const struct qmp_phy_cfg *cfg = qmp->cfg; struct device *dev = qmp->dev; - int num = cfg->num_clks; + int num = ARRAY_SIZE(qmp_pciephy_clk_l); int i; qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); @@ -3403,9 +3339,9 @@ static int qmp_pcie_clk_init(struct qmp_pcie *qmp) return -ENOMEM; for (i = 0; i < num; i++) - qmp->clks[i].id = cfg->clk_list[i]; + qmp->clks[i].id = qmp_pciephy_clk_l[i]; - return devm_clk_bulk_get(dev, num, qmp->clks); + return devm_clk_bulk_get_optional(dev, num, qmp->clks); } static void phy_clk_release_provider(void *res) From patchwork Mon Jul 31 10:57:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708868 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46411C001DF for ; Mon, 31 Jul 2023 10:58:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229812AbjGaK6v (ORCPT ); Mon, 31 Jul 2023 06:58:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229902AbjGaK6f (ORCPT ); Mon, 31 Jul 2023 06:58:35 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BDB71997 for ; Mon, 31 Jul 2023 03:58:05 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4fe0c566788so6988969e87.0 for ; Mon, 31 Jul 2023 03:58:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690801083; x=1691405883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rRDB6y7BOiVI1Vr/oVyT96U0NLtYbPnf2p0lWekO/No=; b=WIP4m6bb5gPcLIV0aCyq10N3LTVSdgiJ7o/MjomfbI/RxdiIxVRqJ2SsQ5LfAOD7vx h+6mbWi4X6jh8VwqycEy+Ajl4Re/WQ0SwRpzL3oX6+ZuB9NuqbqzLEt37+AW3pj8ItfX tILuVzewAXEsosRuyY5LKdVKi9PRihf9sr2CBj1hKWwxVVeRNoxxzzcFjattI0bQEgdC hy3NALm3hAj0UFKktgjcVEH5UcjhJ35p4Gmuz2lLnbIkDNlSdRKf1UelQ862Ua3yLEdd FLLdT1jH4uz26qN2TF29GrmBYMhzZPIBEsv0or50cd4Rq3LUic2o/URN/IMkoHCutAve vU+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690801083; x=1691405883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rRDB6y7BOiVI1Vr/oVyT96U0NLtYbPnf2p0lWekO/No=; b=SqT9I0f/3Wua6CclExWq9PGGPQ9P8HxWH2tApR2FdYKvBOYkXXiSmKkk3g4hR+XVWQ dIG7ED6xgnpz/R76YAxz0IamK2vr7XG0zh4Ode/259sJ4EywwGJCc04P3YGGIzl/wLeW n8ZoQ4mF5iux2hKdxnsZryYUdCTyVMyTj1qDevbVN02Cu6wEGMpto1UWA3zTn7DppiIW 7hrL16+FbDqSsHKjvLaEQgj2ZFzlIuoMIu51Hlxs3enfKhps/2m3ozN/aVKyqT9nT8Tu VL5ujYpBQqrxJfb29fzb/VO5x3uLO1LhpRS1HfXU+ZgVG+i+4NbsqBzNthDidghwdu1A uA7w== X-Gm-Message-State: ABy/qLZ89zTjJq3pPAASvwOngIy/IAUrGEDOhYIu50s2nCp0Jt9YLdZA qGr2eVKu6n4jdF7ty2EgohYpIQ== X-Google-Smtp-Source: APBJJlHbSIL4cwbiyzPPcCK0HAhip6BS1jeEFTN/e9eMy7sLisNPLEbn3snuYLVwtogM9VUf2Nolfg== X-Received: by 2002:ac2:5b1d:0:b0:4fd:d1df:9bda with SMTP id v29-20020ac25b1d000000b004fdd1df9bdamr5309658lfn.42.1690801083340; Mon, 31 Jul 2023 03:58:03 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c19-20020ac24153000000b004fb9fe34c27sm2025497lfi.92.2023.07.31.03.58.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 03:58:02 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 03/13] phy: qcom-qmp-pcie: populate offsets configuration Date: Mon, 31 Jul 2023 13:57:49 +0300 Message-Id: <20230731105759.3997549-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> References: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Populate offsets configuration for the rest of UFS PHYs to make it possible to switch them to the new (single-node) bindings style. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index f3717cb4a0e1..f304a2c4a5c2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2294,6 +2294,56 @@ static const char * const sdm845_pciephy_reset_l[] = { "phy", }; +static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = { + .serdes = 0, + .pcs = 0x1800, + .tx = 0x0800, + /* no .rx for QHP */ +}; + +static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = { + .serdes = 0, + .pcs = 0x0800, + .tx = 0x0200, + .rx = 0x0400, +}; + +static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = { + .serdes = 0, + .pcs = 0x0800, + .pcs_misc = 0x0600, + .tx = 0x0200, + .rx = 0x0400, +}; + +static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = { + .serdes = 0, + .pcs = 0x0800, + .pcs_misc = 0x0c00, + .tx = 0x0200, + .rx = 0x0400, +}; + +static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = { + .serdes = 0, + .pcs = 0x0a00, + .pcs_misc = 0x0e00, + .tx = 0x0200, + .rx = 0x0400, + .tx2 = 0x0600, + .rx2 = 0x0800, +}; + +static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = { + .serdes = 0x1000, + .pcs = 0x1200, + .pcs_misc = 0x1600, + .tx = 0x0000, + .rx = 0x0200, + .tx2 = 0x0800, + .rx2 = 0x0a00, +}; + static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { .serdes = 0, .pcs = 0x0200, @@ -2304,6 +2354,16 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = { .rx2 = 0x1800, }; +static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = { + .serdes = 0x1000, + .pcs = 0x1200, + .pcs_misc = 0x1400, + .tx = 0x0000, + .rx = 0x0200, + .tx2 = 0x0800, + .rx2 = 0x0a00, +}; + static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = { .serdes = 0x1000, .pcs = 0x1200, @@ -2339,6 +2399,8 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = { static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .lanes = 1, + .offsets = &qmp_pcie_offsets_v2, + .tbls = { .serdes = ipq8074_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl), @@ -2362,6 +2424,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { .lanes = 1, + .offsets = &qmp_pcie_offsets_v4x1, + .tbls = { .serdes = ipq8074_pcie_gen3_serdes_tbl, .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl), @@ -2389,6 +2453,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { .lanes = 1, + .offsets = &qmp_pcie_offsets_v4x1, + .tbls = { .serdes = ipq6018_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl), @@ -2414,6 +2480,8 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { .lanes = 1, + .offsets = &qmp_pcie_offsets_v3, + .tbls = { .serdes = sdm845_qmp_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl), @@ -2439,6 +2507,8 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { .lanes = 1, + .offsets = &qmp_pcie_offsets_qhp, + .tbls = { .serdes = sdm845_qhp_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl), @@ -2460,6 +2530,8 @@ static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { .lanes = 1, + .offsets = &qmp_pcie_offsets_v4x1, + .tbls = { .serdes = sm8250_qmp_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), @@ -2495,6 +2567,8 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { .lanes = 2, + .offsets = &qmp_pcie_offsets_v4x2, + .tbls = { .serdes = sm8250_qmp_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl), @@ -2530,6 +2604,8 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { static const struct qmp_phy_cfg msm8998_pciephy_cfg = { .lanes = 1, + .offsets = &qmp_pcie_offsets_v3, + .tbls = { .serdes = msm8998_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl), @@ -2555,6 +2631,8 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { .lanes = 2, + .offsets = &qmp_pcie_offsets_v4x2, + .tbls = { .serdes = sc8180x_qmp_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl), @@ -2682,6 +2760,8 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .lanes = 2, + .offsets = &qmp_pcie_offsets_v4_20, + .tbls = { .serdes = sdx55_qmp_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl), @@ -2819,6 +2899,8 @@ static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = { static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { .lanes = 1, + .offsets = &qmp_pcie_offsets_v5, + .tbls = { .serdes = sm8450_qmp_gen3_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl), @@ -2852,6 +2934,8 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { .lanes = 2, + .offsets = &qmp_pcie_offsets_v5_20, + .tbls = { .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl, .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl), From patchwork Mon Jul 31 10:57:50 2023 Content-Type: text/plain; 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Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 32 ++++++++++----------------- 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 47b8b1d6730a..3c8a2f4e26a3 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -278,33 +278,25 @@ qusb_phy_0: qusb@79000 { pcie_phy: phy@84000 { compatible = "qcom,ipq6018-qmp-pcie-phy"; - reg = <0x0 0x00084000 0x0 0x1bc>; /* Serdes PLL */ + reg = <0x0 0x00084000 0x0 0x1000>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges; clocks = <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>; - clock-names = "aux", "cfg_ahb"; + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe"; + + clock-output-names = "gcc_pcie0_pipe_clk_src"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE0_PHY_BCR>, <&gcc GCC_PCIE0PHY_PHY_BCR>; reset-names = "phy", "common"; - - pcie_phy0: phy@84200 { - reg = <0x0 0x00084200 0x0 0x16c>, /* Serdes Tx */ - <0x0 0x00084400 0x0 0x200>, /* Serdes Rx */ - <0x0 0x00084800 0x0 0x1f0>, /* PCS: Lane0, COM, PCIE */ - <0x0 0x00084c00 0x0 0xf4>; /* pcs_misc */ - #phy-cells = <0>; - - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "gcc_pcie0_pipe_clk_src"; - #clock-cells = <0>; - }; }; mdio: mdio@90000 { @@ -756,7 +748,7 @@ pcie0: pci@20000000 { #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_phy0>; + phys = <&pcie_phy>; phy-names = "pciephy"; ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, From patchwork Mon Jul 31 10:57:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708867 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DBF4C04FDF for ; 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Mon, 31 Jul 2023 03:58:04 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c19-20020ac24153000000b004fb9fe34c27sm2025497lfi.92.2023.07.31.03.58.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 03:58:04 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 05/13] arm64: dts: qcom: ipq8074: switch PCIe QMP PHY to new style of bindings Date: Mon, 31 Jul 2023 13:57:51 +0300 Message-Id: <20230731105759.3997549-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> References: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 63 +++++++++++---------------- 1 file changed, 26 insertions(+), 37 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 00ed71936b47..e4447a9d7929 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -211,59 +211,48 @@ qusb_phy_0: phy@79000 { pcie_qmp0: phy@84000 { compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; - reg = <0x00084000 0x1bc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + reg = <0x00084000 0x1000>; clocks = <&gcc GCC_PCIE0_AUX_CLK>, - <&gcc GCC_PCIE0_AHB_CLK>; - clock-names = "aux", "cfg_ahb"; + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe"; + + clock-output-names = "pcie20_phy0_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; + resets = <&gcc GCC_PCIE0_PHY_BCR>, <&gcc GCC_PCIE0PHY_PHY_BCR>; reset-names = "phy", "common"; status = "disabled"; - - pcie_phy0: phy@84200 { - reg = <0x84200 0x16c>, - <0x84400 0x200>, - <0x84800 0x1f0>, - <0x84c00 0xf4>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_PCIE0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "pcie20_phy0_pipe_clk"; - }; }; pcie_qmp1: phy@8e000 { compatible = "qcom,ipq8074-qmp-pcie-phy"; - reg = <0x0008e000 0x1c4>; - #address-cells = <1>; - #size-cells = <1>; - ranges; + reg = <0x0008e000 0x1000>; clocks = <&gcc GCC_PCIE1_AUX_CLK>, - <&gcc GCC_PCIE1_AHB_CLK>; - clock-names = "aux", "cfg_ahb"; + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "pipe"; + + clock-output-names = "pcie20_phy1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; + resets = <&gcc GCC_PCIE1_PHY_BCR>, <&gcc GCC_PCIE1PHY_PHY_BCR>; reset-names = "phy", "common"; status = "disabled"; - - pcie_phy1: phy@8e200 { - reg = <0x8e200 0x130>, - <0x8e400 0x200>, - <0x8e800 0x1f8>; - #phy-cells = <0>; - #clock-cells = <0>; - clocks = <&gcc GCC_PCIE1_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "pcie20_phy1_pipe_clk"; - }; }; mdio: mdio@90000 { @@ -807,7 +796,7 @@ pcie1: pci@10000000 { #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_phy1>; + phys = <&pcie_qmp1>; phy-names = "pciephy"; ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ @@ -869,7 +858,7 @@ pcie0: pci@20000000 { #address-cells = <3>; #size-cells = <2>; - phys = <&pcie_phy0>; + phys = <&pcie_qmp0>; phy-names = "pciephy"; ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ From patchwork Mon Jul 31 10:57:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708866 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF69FC001DF for ; Mon, 31 Jul 2023 10:58:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230483AbjGaK6z (ORCPT ); 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Mon, 31 Jul 2023 03:58:05 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 06/13] arm64: dts: qcom: msm8998: switch PCIe QMP PHY to new style of bindings Date: Mon, 31 Jul 2023 13:57:52 +0300 Message-Id: <20230731105759.3997549-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> References: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 30 ++++++++++++--------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index d0af22fa63f2..94921e75f8c2 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -926,7 +926,7 @@ pcie0: pci@1c00000 { #address-cells = <3>; #size-cells = <2>; num-lanes = <1>; - phys = <&pciephy>; + phys = <&pcie_phy>; phy-names = "pciephy"; status = "disabled"; @@ -956,32 +956,28 @@ pcie0: pci@1c00000 { pcie_phy: phy@1c06000 { compatible = "qcom,msm8998-qmp-pcie-phy"; - reg = <0x01c06000 0x18c>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x01c06000 0x1000>; status = "disabled"; - ranges; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE_CLKREF_CLK>; - clock-names = "aux", "cfg_ahb", "ref"; + <&gcc GCC_PCIE_CLKREF_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk_src"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; reset-names = "phy", "common"; vdda-phy-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l2a_1p2>; - - pciephy: phy@1c06800 { - reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>; - #phy-cells = <0>; - - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "pcie_0_pipe_clk_src"; - #clock-cells = <0>; - }; }; ufshc: ufshc@1da4000 { From patchwork Mon Jul 31 10:57:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B9FAC001E0 for ; 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Mon, 31 Jul 2023 03:58:06 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c19-20020ac24153000000b004fb9fe34c27sm2025497lfi.92.2023.07.31.03.58.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 03:58:05 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 07/13] arm64: dts: qcom: sc7280: switch PCIe QMP PHY to new style of bindings Date: Mon, 31 Jul 2023 13:57:53 +0300 Message-Id: <20230731105759.3997549-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> References: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 36 ++++++++++------------------ 1 file changed, 12 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 4353f7265877..670092731c6c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -869,7 +869,7 @@ gcc: clock-controller@100000 { reg = <0 0x00100000 0 0x1f0000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <0>, <&pcie1_lane>, + <0>, <&pcie1_phy>, <0>, <0>, <0>, <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", @@ -2121,7 +2121,7 @@ pcie1: pci@1c08000 { clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane>, + <&pcie1_phy>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2155,7 +2155,7 @@ pcie1: pci@1c08000 { power-domains = <&gcc GCC_PCIE_1_GDSC>; - phys = <&pcie1_lane>; + phys = <&pcie1_phy>; phy-names = "pciephy"; pinctrl-names = "default"; @@ -2171,15 +2171,18 @@ pcie1: pci@1c08000 { pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; - reg = <0 0x01c0e000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c0e000 0 0x1000>; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_CLKREF_EN>, - <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen", "pipe"; + + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; @@ -2188,21 +2191,6 @@ pcie1_phy: phy@1c0e000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie1_lane: phy@1c0e200 { - reg = <0 0x01c0e200 0 0x170>, - <0 0x01c0e400 0 0x200>, - <0 0x01c0ea00 0 0x1f0>, - <0 0x01c0e600 0 0x170>, - <0 0x01c0e800 0 0x200>, - <0 0x01c0ee00 0 0xf4>; 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 140 ++++++++++---------------- 1 file changed, 51 insertions(+), 89 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 486f7ffef43b..fae149e33b98 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1749,7 +1749,7 @@ pcie0: pci@1c00000 { <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie0_lane>; + phys = <&pcie0_phy>; phy-names = "pciephy"; status = "disabled"; @@ -1757,15 +1757,20 @@ pcie0: pci@1c00000 { pcie0_phy: phy-wrapper@1c06000 { compatible = "qcom,sc8180x-qmp-pcie-phy"; - reg = <0 0x1c06000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x1c06000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + #clock-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; @@ -1774,21 +1779,6 @@ pcie0_phy: phy-wrapper@1c06000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie0_lane: phy@1c06200 { - reg = <0 0x1c06200 0 0x170>, /* tx0 */ - <0 0x1c06400 0 0x200>, /* rx0 */ - <0 0x1c06a00 0 0x1f0>, /* pcs */ - <0 0x1c06600 0 0x170>, /* tx1 */ - <0 0x1c06800 0 0x200>, /* rx1 */ - <0 0x1c06e00 0 0xf4>; /* pcs_com */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - #phy-cells = <0>; - }; }; pcie3: pci@1c08000 { @@ -1856,7 +1846,7 @@ pcie3: pci@1c08000 { <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie3_lane>; + phys = <&pcie3_phy>; phy-names = "pciephy"; status = "disabled"; @@ -1864,15 +1854,21 @@ pcie3: pci@1c08000 { pcie3_phy: phy-wrapper@1c0c000 { compatible = "qcom,sc8180x-qmp-pcie-phy"; - reg = <0 0x1c0c000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x1c0c000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_3_CFG_AHB_CLK>, <&gcc GCC_PCIE_3_CLKREF_CLK>, - <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_3_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + #clock-cells = <0>; + clock-output-names = "pcie_3_pipe_clk"; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_3_PHY_BCR>; reset-names = "phy"; @@ -1881,21 +1877,6 @@ pcie3_phy: phy-wrapper@1c0c000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie3_lane: phy@1c0c200 { - reg = <0 0x1c0c200 0 0x170>, /* tx0 */ - <0 0x1c0c400 0 0x200>, /* rx0 */ - <0 0x1c0ca00 0 0x1f0>, /* pcs */ - <0 0x1c0c600 0 0x170>, /* tx1 */ - <0 0x1c0c800 0 0x200>, /* rx1 */ - <0 0x1c0ce00 0 0xf4>; /* pcs_com */ - clocks = <&gcc GCC_PCIE_3_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - clock-output-names = "pcie_3_pipe_clk"; - #phy-cells = <0>; - }; }; pcie1: pci@1c10000 { @@ -1963,7 +1944,7 @@ pcie1: pci@1c10000 { <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie1_lane>; + phys = <&pcie1_phy>; phy-names = "pciephy"; status = "disabled"; @@ -1971,15 +1952,21 @@ pcie1: pci@1c10000 { pcie1_phy: phy-wrapper@1c16000 { compatible = "qcom,sc8180x-qmp-pcie-phy"; - reg = <0 0x1c16000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x1c16000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_CLKREF_CLK>, - <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + #clock-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; @@ -1988,21 +1975,6 @@ pcie1_phy: phy-wrapper@1c16000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie1_lane: phy@1c0e200 { - reg = <0 0x1c16200 0 0x170>, /* tx0 */ - <0 0x1c16400 0 0x200>, /* rx0 */ - <0 0x1c16a00 0 0x1f0>, /* pcs */ - <0 0x1c16600 0 0x170>, /* tx1 */ - <0 0x1c16800 0 0x200>, /* rx1 */ - <0 0x1c16e00 0 0xf4>; /* pcs_com */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - #clock-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - - #phy-cells = <0>; - }; }; pcie2: pci@1c18000 { @@ -2070,7 +2042,7 @@ pcie2: pci@1c18000 { <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie2_lane>; + phys = <&pcie2_phy>; phy-names = "pciephy"; status = "disabled"; @@ -2078,15 +2050,21 @@ pcie2: pci@1c18000 { pcie2_phy: phy-wrapper@1c1c000 { compatible = "qcom,sc8180x-qmp-pcie-phy"; - reg = <0 0x1c1c000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x1c1c000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_2_CFG_AHB_CLK>, <&gcc GCC_PCIE_2_CLKREF_CLK>, - <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + #clock-cells = <0>; + clock-output-names = "pcie_3_pipe_clk"; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_2_PHY_BCR>; reset-names = "phy"; @@ -2095,22 +2073,6 @@ pcie2_phy: phy-wrapper@1c1c000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie2_lane: phy@1c0e200 { - reg = <0 0x1c1c200 0 0x170>, /* tx0 */ - <0 0x1c1c400 0 0x200>, /* rx0 */ - <0 0x1c1ca00 0 0x1f0>, /* pcs */ - <0 0x1c1c600 0 0x170>, /* tx1 */ - <0 0x1c1c800 0 0x200>, /* rx1 */ - <0 0x1c1ce00 0 0xf4>; /* pcs_com */ - clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - clock-output-names = "pcie_2_pipe_clk"; - - #phy-cells = <0>; - }; }; ufs_mem_hc: ufshc@1d84000 { From patchwork Mon Jul 31 10:57:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D94DC04FE0 for ; Mon, 31 Jul 2023 10:58:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230354AbjGaK65 (ORCPT ); Mon, 31 Jul 2023 06:58:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230328AbjGaK6h (ORCPT ); Mon, 31 Jul 2023 06:58:37 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB527123 for ; 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Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 71 ++++++++++++---------------- 1 file changed, 30 insertions(+), 41 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 3d4050548f3a..ef7b6994fdab 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -1198,8 +1198,8 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, - <&pcie0_lane>, - <&pcie1_lane>; + <&pcie0_phy>, + <&pcie1_phy>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", @@ -2371,7 +2371,7 @@ pcie0: pci@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie0_phy>; phy-names = "pciephy"; status = "disabled"; @@ -2379,15 +2379,22 @@ pcie0: pci@1c00000 { pcie0_phy: phy@1c06000 { compatible = "qcom,sdm845-qmp-pcie-phy"; - reg = <0 0x01c06000 0 0x18c>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c06000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; @@ -2396,19 +2403,6 @@ pcie0_phy: phy@1c06000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie0_lane: phy@1c06200 { - reg = <0 0x01c06200 0 0x128>, - <0 0x01c06400 0 0x1fc>, - <0 0x01c06800 0 0x218>, - <0 0x01c06600 0 0x70>; - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; }; pcie1: pci@1c08000 { @@ -2481,7 +2475,7 @@ pcie1: pci@1c08000 { power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_lane>; + phys = <&pcie1_phy>; phy-names = "pciephy"; status = "disabled"; @@ -2489,15 +2483,22 @@ pcie1: pci@1c08000 { pcie1_phy: phy@1c0a000 { compatible = "qcom,sdm845-qhp-pcie-phy"; - reg = <0 0x01c0a000 0 0x800>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c0a000 0 0x2000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_CLKREF_CLK>, - <&gcc GCC_PCIE_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; @@ -2506,18 +2507,6 @@ pcie1_phy: phy@1c0a000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie1_lane: phy@1c06200 { - reg = <0 0x01c0a800 0 0x800>, - <0 0x01c0a800 0 0x800>, - <0 0x01c0b800 0 0x400>; - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; }; mem_noc: interconnect@1380000 { From patchwork Mon Jul 31 10:57:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53B7AC001DC for ; Mon, 31 Jul 2023 10:59:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230352AbjGaK66 (ORCPT ); Mon, 31 Jul 2023 06:58:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230357AbjGaK6i (ORCPT ); Mon, 31 Jul 2023 06:58:38 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68CBD18C for ; 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As a part of this conversion also add the missing "ref" clock to the PCIe PHY devices. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 70 ++++++++++++---------------- 1 file changed, 30 insertions(+), 40 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 4381527da3fb..2baac91aecfb 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1874,7 +1874,7 @@ pcie0: pci@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie0_phy>; phy-names = "pciephy"; perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; @@ -1888,14 +1888,22 @@ pcie0: pci@1c00000 { pcie0_phy: phy@1c06000 { compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; - reg = <0 0x01c06000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c06000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, - <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "refgen"; + <&gcc GCC_PCIE_0_CLKREF_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; @@ -1904,18 +1912,6 @@ pcie0_phy: phy@1c06000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie0_lane: phy@1c06200 { - reg = <0 0x01c06200 0 0x170>, /* tx */ - <0 0x01c06400 0 0x200>, /* rx */ - <0 0x01c06800 0 0x1f0>, /* pcs */ - <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; }; pcie1: pci@1c08000 { @@ -1972,7 +1968,7 @@ pcie1: pci@1c08000 { power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_lane>; + phys = <&pcie1_phy>; phy-names = "pciephy"; perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; @@ -1986,14 +1982,22 @@ pcie1: pci@1c08000 { pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; - reg = <0 0x01c0e000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c0e000 0 0x1000>; clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, - <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "refgen"; + <&gcc GCC_PCIE_1_CLKREF_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; @@ -2002,20 +2006,6 @@ pcie1_phy: phy@1c0e000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie1_lane: phy@1c0e200 { - reg = <0 0x01c0e200 0 0x170>, /* tx0 */ - <0 0x01c0e400 0 0x200>, /* rx0 */ - <0 0x01c0ea00 0 0x1f0>, /* pcs */ - <0 0x01c0e600 0 0x170>, /* tx1 */ - <0 0x01c0e800 0 0x200>, /* rx1 */ - <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; }; ufs_mem_hc: ufshc@1d84000 { From patchwork Mon Jul 31 10:57:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708476 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C38C6C41513 for ; Mon, 31 Jul 2023 10:59:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230449AbjGaK7A (ORCPT ); Mon, 31 Jul 2023 06:59:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230373AbjGaK6i (ORCPT ); Mon, 31 Jul 2023 06:58:38 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29692129 for ; Mon, 31 Jul 2023 03:58:11 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4fe21e7f3d1so4164906e87.3 for ; Mon, 31 Jul 2023 03:58:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690801089; x=1691405889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nIGzOBMVuyuP3wGtKFIirwjJutlmFvuN8dVY84iac/E=; b=CxgWY0olF44IuFTdITsB4OPNEoynHiVFdktoDJwrWIzSFG7mRIdFXVyTpgWqmSMkfA +HFr0QModpY4WQ4WbSmUo+oSBKcV/gLxOMcK0lu/e8ehbG/RDEHbUTWF6utZE9TOFu3M dl3ltu+N6FfqMoxUt+brkUlR5H+AfkLjJBYaxSYsZhXllc50BS/WGZe1zKEp5piFNRY2 c43Hh3sc6H0CQM56MUdfh4D9dQV3hd+TbBiiKeuEx8/TIMjVRjoVdgsow8FZ1MGbRmGd 7NkgGxYomJeuJvcb30ewmmG7zEnCYEl8cBiYKz3mJC5l4JnUsmgLvRcQry7hnq8c12OB W6sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690801089; x=1691405889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nIGzOBMVuyuP3wGtKFIirwjJutlmFvuN8dVY84iac/E=; b=c+HWx522tUe6oGAvMCFEb54w/CUk8E9PvgSqixkEfwNaPGt3zh4kdpGXe9pCezDOA7 W+/D+QwziiEcvWNpaSY8q8xHfBX+WAZDqe0RgpOvcjM5gJIELcjg48xaBIClbClb8bKi e2PeiWXPxXS/c0UYo+maW0f5M+bDyMIpfvnZ/9p9x91nevHzFeYFIdT0NjjsC+hXid7l UAWt163knLc3rD+8m5ykWYZPESSbDwLjjmKkMymjJBRNn7TpTKOSEib0z5MacD4cVcNx vjTvdwADoY8jjJu8A0w9arH3Uk8aeCz5wwVa17aZWhQfU1gWDtrd3/I8tvf8RUMWd+oL 55fA== X-Gm-Message-State: ABy/qLYxeRR9sMrJve342cuB+FjO5G00m7jjQMNG2f2La7Ev7r4CaMmr JP2WxP/iM9C4fOZcoOLqrpWlgA== X-Google-Smtp-Source: APBJJlEs3RDf4d6TDjtGUuxhN6X/a8r+yeBp7lb1zFdhWiTeFZGA+CcuXT8Mdir491Ok7MHwemFU8w== X-Received: by 2002:a19:9116:0:b0:4f8:6625:f2ca with SMTP id t22-20020a199116000000b004f86625f2camr4832688lfd.61.1690801089532; Mon, 31 Jul 2023 03:58:09 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c19-20020ac24153000000b004fb9fe34c27sm2025497lfi.92.2023.07.31.03.58.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 03:58:08 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 11/13] arm64: dts: qcom: sm8250: switch PCIe QMP PHY to new style of bindings Date: Mon, 31 Jul 2023 13:57:57 +0300 Message-Id: <20230731105759.3997549-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> References: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 112 +++++++++++---------------- 1 file changed, 45 insertions(+), 67 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 1365052e0a13..abe39b0470da 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -1899,7 +1899,7 @@ pcie0: pci@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie0_phy>; phy-names = "pciephy"; perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; @@ -1914,15 +1914,23 @@ pcie0: pci@1c00000 { pcie0_phy: phy@1c06000 { compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; - reg = <0 0x01c06000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c06000 0 0x1000>; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_WIFI_CLKREF_EN>, - <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; @@ -1931,20 +1939,6 @@ pcie0_phy: phy@1c06000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie0_lane: phy@1c06200 { - reg = <0 0x01c06200 0 0x170>, /* tx */ - <0 0x01c06400 0 0x200>, /* rx */ - <0 0x01c06800 0 0x1f0>, /* pcs */ - <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - - #clock-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; }; pcie1: pci@1c08000 { @@ -2006,7 +2000,7 @@ pcie1: pci@1c08000 { power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_lane>; + phys = <&pcie1_phy>; phy-names = "pciephy"; perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; @@ -2021,15 +2015,23 @@ pcie1: pci@1c08000 { pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; - reg = <0 0x01c0e000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c0e000 0 0x1000>; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, - <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; @@ -2038,22 +2040,6 @@ pcie1_phy: phy@1c0e000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie1_lane: phy@1c0e200 { - reg = <0 0x01c0e200 0 0x170>, /* tx0 */ - <0 0x01c0e400 0 0x200>, /* rx0 */ - <0 0x01c0ea00 0 0x1f0>, /* pcs */ - <0 0x01c0e600 0 0x170>, /* tx1 */ - <0 0x01c0e800 0 0x200>, /* rx1 */ - <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - - #clock-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; }; pcie2: pci@1c10000 { @@ -2115,7 +2101,7 @@ pcie2: pci@1c10000 { power-domains = <&gcc PCIE_2_GDSC>; - phys = <&pcie2_lane>; + phys = <&pcie2_phy>; phy-names = "pciephy"; perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; @@ -2130,15 +2116,23 @@ pcie2: pci@1c10000 { pcie2_phy: phy@1c16000 { compatible = "qcom,sm8250-qmp-modem-pcie-phy"; - reg = <0 0x01c16000 0 0x1c0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c16000 0 0x1000>; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_2_CFG_AHB_CLK>, <&gcc GCC_PCIE_MDM_CLKREF_EN>, - <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE_2_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "refgen", + "pipe"; + + clock-output-names = "pcie_2_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_2_PHY_BCR>; reset-names = "phy"; @@ -2147,22 +2141,6 @@ pcie2_phy: phy@1c16000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie2_lane: phy@1c16200 { - reg = <0 0x01c16200 0 0x170>, /* tx0 */ - <0 0x01c16400 0 0x200>, /* rx0 */ - <0 0x01c16a00 0 0x1f0>, /* pcs */ - <0 0x01c16600 0 0x170>, /* tx1 */ - <0 0x01c16800 0 0x200>, /* rx1 */ - <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ - clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - - #clock-cells = <0>; - clock-output-names = "pcie_2_pipe_clk"; - }; }; ufs_mem_hc: ufshc@1d84000 { From patchwork Mon Jul 31 10:57:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708864 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A488FC001DF for ; Mon, 31 Jul 2023 10:59:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230306AbjGaK67 (ORCPT ); Mon, 31 Jul 2023 06:58:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230449AbjGaK6i (ORCPT ); Mon, 31 Jul 2023 06:58:38 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CD9D199 for ; Mon, 31 Jul 2023 03:58:12 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4fe1c285690so5804424e87.3 for ; Mon, 31 Jul 2023 03:58:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690801090; x=1691405890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1TgQueK3/uQvVobd2EvrYhwR6ZFnqzSrsZ0Yi98Vg28=; b=Z+wBjWb9Ttgc8Dl53xaGn99ROFYCnXDAW8dq5cVsWdyGi8zs+YTkwFZEs7mi4wKPIH pWBjVuRs0wWec0zTOvqqh9Y1BKvfVSdMviR31aMLNuNwmmowP+HTR25Pt/99nE/6iY/t gX8OTshRqwefZfyFlQ/7Ajvc+NmsuJg1ygN3J+O8RCWBU80C5KC/F9JpSjE99vtu09pv E+gMdUpbmDbEO02MV86SK0qpH3bIZM0Eq4MuEiELvOeF8xG2nS6aABdi5n149VJnNcOE RQyCd4hqh9mnJxaQD045cYqKAoXwQ1ze+Y+oNlOYPepgHC1n8UaGBJ7Ya0pvm+FH47xU whKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690801090; x=1691405890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1TgQueK3/uQvVobd2EvrYhwR6ZFnqzSrsZ0Yi98Vg28=; b=iAcHSDNChwNqBBR/jW0CKp7CmCq/eaCiey6ZNA0y7XEf2P7r5Jyx+K3tHL48q9UCtk 8g+OmcdTV18ueCdOQJMVL3x+ZdE3rXt4vJESV9Kqx9kvIOWxWU3HTDqu7q8z4RK7QVDb QPvdN5XMDKDdDWDmPRKEuYp7rC++p//PYXXuJbob6D92ANP3S3QlX+xaYcOVmkGfxb4T QqVBmkci0OCSVnTUpU0zAYQ23uoY+iR2JpGTTTd551P1UzXUAgmFUjF8aWgZe+BBhzs7 LEqKYDmNYM+x9PwOVAYW5b05/07LTJSyoKJhHPBS2P0MSRJyg3qV0lDC9bEndX+Tonwq /+Dw== X-Gm-Message-State: ABy/qLah8/+g3R8wj/32pjpzpVzG4BURTZrlT0r+XUPGHJNcq7fuwFBv BvgFu0o6ZrYeVgCj0AU3n/N3dA== X-Google-Smtp-Source: APBJJlGyanc6hK7anoIxm79l+wel/dbIrN5rOBPgB2deup9ZWfNMmJz/fXJsTY5fROZmEYxGt+EtLA== X-Received: by 2002:a05:6512:3583:b0:4f9:b649:23d2 with SMTP id m3-20020a056512358300b004f9b64923d2mr5058611lfr.42.1690801090373; Mon, 31 Jul 2023 03:58:10 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c19-20020ac24153000000b004fb9fe34c27sm2025497lfi.92.2023.07.31.03.58.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 03:58:09 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 12/13] arm64: dts: qcom: sm8450: switch PCIe QMP PHY to new style of bindings Date: Mon, 31 Jul 2023 13:57:58 +0300 Message-Id: <20230731105759.3997549-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> References: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). As a part of this conversion also change the "refgen" name to more correct "rchng". Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 82 ++++++++++++---------------- 1 file changed, 35 insertions(+), 47 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 8c58b7747ff9..02153f6cb274 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -750,8 +750,8 @@ gcc: clock-controller@100000 { #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <&pcie0_lane>, - <&pcie1_lane>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, @@ -1775,7 +1775,7 @@ pcie0: pci@1c00000 { clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, - <&pcie0_lane>, + <&pcie0_phy>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -1806,7 +1806,7 @@ pcie0: pci@1c00000 { power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_lane>; + phys = <&pcie0_phy>; phy-names = "pciephy"; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; @@ -1820,15 +1820,23 @@ pcie0: pci@1c00000 { pcie0_phy: phy@1c06000 { compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; - reg = <0 0x01c06000 0 0x200>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c06000 0 0x2000>; + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_EN>, - <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + clock-output-names = "pcie_0_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_0_PHY_BCR>; reset-names = "phy"; @@ -1837,19 +1845,6 @@ pcie0_phy: phy@1c06000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie0_lane: phy@1c06200 { - reg = <0 0x01c06e00 0 0x200>, /* tx */ - <0 0x01c07000 0 0x200>, /* rx */ - <0 0x01c06200 0 0x200>, /* pcs */ - <0 0x01c06600 0 0x200>; /* pcs_pcie */ - clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_0_pipe_clk"; - }; }; pcie1: pci@1c08000 { @@ -1889,7 +1884,7 @@ pcie1: pci@1c08000 { clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, - <&pcie1_lane>, + <&pcie1_phy>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -1918,7 +1913,7 @@ pcie1: pci@1c08000 { power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_lane>; + phys = <&pcie1_phy>; phy-names = "pciephy"; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; @@ -1930,17 +1925,25 @@ pcie1: pci@1c08000 { status = "disabled"; }; - pcie1_phy: phy@1c0f000 { + pcie1_phy: phy@1c0e000 { compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; - reg = <0 0x01c0f000 0 0x200>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + reg = <0 0x01c0e000 0 0x2000>; + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, <&gcc GCC_PCIE_1_CLKREF_EN>, - <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "refgen"; + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + clock-output-names = "pcie_1_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_1_PHY_BCR>; reset-names = "phy"; @@ -1949,21 +1952,6 @@ pcie1_phy: phy@1c0f000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie1_lane: phy@1c0e000 { - reg = <0 0x01c0e000 0 0x200>, /* tx */ - <0 0x01c0e200 0 0x300>, /* rx */ - <0 0x01c0f200 0 0x200>, /* pcs */ - <0 0x01c0e800 0 0x200>, /* tx */ - <0 0x01c0ea00 0 0x300>, /* rx */ - <0 0x01c0f400 0 0xc00>; /* pcs_pcie */ - clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; - clock-names = "pipe0"; - - #clock-cells = <0>; - #phy-cells = <0>; - clock-output-names = "pcie_1_pipe_clk"; - }; }; config_noc: interconnect@1500000 { From patchwork Mon Jul 31 10:57:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 708863 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7839EC001DF for ; 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Mon, 31 Jul 2023 03:58:11 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c19-20020ac24153000000b004fb9fe34c27sm2025497lfi.92.2023.07.31.03.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 03:58:10 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Philipp Zabel , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v2 13/13] ARM: dts: qcom-sdx55: switch PCIe QMP PHY to new style of bindings Date: Mon, 31 Jul 2023 13:57:59 +0300 Message-Id: <20230731105759.3997549-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> References: <20230731105759.3997549-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change the PCIe QMP PHY to use newer style of QMP PHY bindings (single resource region, no per-PHY subnodes). Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 31 ++++++++++---------------- 1 file changed, 12 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 55ce87b75253..4b0039ccd0da 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -379,7 +379,7 @@ pcie_rc: pcie@1c00000 { power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie_lane>; + phys = <&pcie_phy>; phy-names = "pciephy"; status = "disabled"; @@ -428,7 +428,7 @@ pcie_ep: pcie-ep@1c00000 { resets = <&gcc GCC_PCIE_BCR>; reset-names = "core"; power-domains = <&gcc PCIE_GDSC>; - phys = <&pcie_lane>; + phys = <&pcie_phy>; phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; @@ -438,18 +438,25 @@ pcie_ep: pcie-ep@1c00000 { pcie_phy: phy@1c07000 { compatible = "qcom,sdx55-qmp-pcie-phy"; - reg = <0x01c07000 0x1c4>; + reg = <0x01c07000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges; clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, <&gcc GCC_PCIE_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK>; clock-names = "aux", "cfg_ahb", "ref", - "refgen"; + "refgen", + "pipe"; + + clock-output-names = "pcie_pipe_clk"; + #clock-cells = <0>; + + #phy-cells = <0>; resets = <&gcc GCC_PCIE_PHY_BCR>; reset-names = "phy"; @@ -458,20 +465,6 @@ pcie_phy: phy@1c07000 { assigned-clock-rates = <100000000>; status = "disabled"; - - pcie_lane: lanes@1c06000 { - reg = <0x01c06000 0x104>, /* tx0 */ - <0x01c06200 0x328>, /* rx0 */ - <0x01c07200 0x1e8>, /* pcs */ - <0x01c06800 0x104>, /* tx1 */ - <0x01c06a00 0x328>, /* rx1 */ - <0x01c07600 0x800>; /* pcs_misc */ - clocks = <&gcc GCC_PCIE_PIPE_CLK>; - clock-names = "pipe0"; - - #phy-cells = <0>; - clock-output-names = "pcie_pipe_clk"; - }; }; ipa: ipa@1e40000 {