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([178.197.222.183]) by smtp.gmail.com with ESMTPSA id s4-20020a170906c30400b009926928d486sm6374444ejz.35.2023.07.31.09.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 31 Jul 2023 09:55:27 -0700 (PDT) From: Krzysztof Kozlowski To: Srinivas Kandagatla , Banajit Goswami , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH] ASoC: codecs: rx-macro: Enable RX path clock to match POST_PMD Date: Mon, 31 Jul 2023 18:55:22 +0200 Message-Id: <20230731165522.328301-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Message-ID-Hash: V4H4AMKDYYG6KWZT4TUHJXU5QXOPL4A6 X-Message-ID-Hash: V4H4AMKDYYG6KWZT4TUHJXU5QXOPL4A6 X-MailFrom: krzysztof.kozlowski@linaro.org X-Mailman-Rule-Misses: dmarc-mitigation; no-senders; approved; emergency; loop; banned-address; member-moderation; header-match-alsa-devel.alsa-project.org-0; header-match-alsa-devel.alsa-project.org-1; nonmember-moderation; administrivia; implicit-dest; max-recipients; max-size; news-moderation; no-subject; digests; suspicious-header X-Mailman-Version: 3.3.8 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" Archived-At: List-Archive: List-Help: List-Owner: List-Post: List-Subscribe: List-Unsubscribe: The driver disables RX path clock in SND_SOC_DAPM_POST_PMD of rx_macro_enable_interp_clk() and rx_macro_enable_mix_path(). Make the code symmetrical by enabling the clock in SND_SOC_DAPM_PRE_PMU. This also matches downstream Qualcomm driver for Qualcomm SM8550 SoC. Signed-off-by: Krzysztof Kozlowski --- sound/soc/codecs/lpass-rx-macro.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-macro.c index 685ca95ef4a9..a758ef4f575a 100644 --- a/sound/soc/codecs/lpass-rx-macro.c +++ b/sound/soc/codecs/lpass-rx-macro.c @@ -2529,6 +2529,9 @@ static int rx_macro_enable_interp_clk(struct snd_soc_component *component, CDC_RX_PATH_PGA_MUTE_MASK, 0x1); snd_soc_component_write_field(component, dsm_reg, CDC_RX_RXn_DSM_CLK_EN_MASK, 0x1); + snd_soc_component_update_bits(component, main_reg, + CDC_RX_PATH_CLK_EN_MASK, + CDC_RX_PATH_CLK_ENABLE); snd_soc_component_update_bits(component, rx_cfg2_reg, CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x03); rx_macro_load_compander_coeff(component, rx, interp_idx, event); @@ -2595,6 +2598,9 @@ static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w, switch (event) { case SND_SOC_DAPM_PRE_PMU: rx_macro_enable_interp_clk(component, event, w->shift); + snd_soc_component_update_bits(component, mix_reg, + CDC_RX_RXn_MIX_CLK_EN_MASK, + CDC_RX_RXn_MIX_CLK_EN_MASK); break; case SND_SOC_DAPM_POST_PMU: snd_soc_component_write(component, gain_reg,