From patchwork Thu Jul 27 14:45:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 707089 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45B39C001E0 for ; Thu, 27 Jul 2023 14:46:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233869AbjG0OqG (ORCPT ); Thu, 27 Jul 2023 10:46:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233949AbjG0OqF (ORCPT ); Thu, 27 Jul 2023 10:46:05 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7ADA30EB for ; Thu, 27 Jul 2023 07:45:47 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-4fe0d5f719dso1805916e87.2 for ; Thu, 27 Jul 2023 07:45:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690469146; x=1691073946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ozXv1DbyX/9IhURbF1Fhd2b0LEweNNt8AgMpeAaCDSs=; b=f9wp7aF+JtlvjPCrxW+wyk6MQOJhgz9FgjxG/z6ZPtxWdM81p5lw/WJ9D7L7f6OWP0 DxPSFOxjJGzy/0oy3rFjThgKNk2yok0MadMiMQT866V7H3M49e8S4D3DRdQgxBy/o7Aw 23mm1HMpVVKB7MNkivPFO/6UaB5/QhRsuQlPNTgKRj0NG5xCTFNl4wfH0bE4z82pdg/Q Gt5TgpJu5zr9U8QVEEXpynYF10tTsw/EfM0FahQFz8L0pcv6lxzHAnE6Rwj2NIfpaj3J +/opyClhe25uissfWfgvrjavAjzh7HT6KxH65ujzcCgpu3sZ0EqxqbYCvnFjjD+XFefg cM6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690469146; x=1691073946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ozXv1DbyX/9IhURbF1Fhd2b0LEweNNt8AgMpeAaCDSs=; b=YnwuAN7QsCTpIHRkOIYMYQRm2bTGPBuVs2InZQGxtWdJ1128ZBab4i2N9v9I3TtC8S Tr3hjUTC162kCMonxXcRyESnICVf4D+3ZyaBg4pTeb5ozEZEuqTqDEvI29gZsGi6H7y/ bJNDHFDYLZvjeQHgktwC3xXe2cAPbs+epIUnZL55DW4DK5oaEZCVpod5peKowFZMrqiO hMZR7LJkeEQLw2TyXIBYZtjWvyWscicmaqPLy3DTyrj0C7un5ZEca1WJivder8dFkLf/ pwLxMMQ5kHLfuhF+j0cCCMY6qgSFLIWjbU0d9lOUuZnZUFG/Up1E8GlinxHwGq3R91rO 0xLw== X-Gm-Message-State: ABy/qLbipglhSlcvl0Yoz6a+7lqxOyxB1RwOturI/3qrcMsTbRpj2AMS AJ461V0+sBboey3zJzQkqO2kLg== X-Google-Smtp-Source: APBJJlFhMrD49VU49jXEomb0dk47f28sgcEyHBNeyokLEu/IKGXr7EkYXVKw7fd6oWwSDZ4pdHuCYA== X-Received: by 2002:ac2:4343:0:b0:4f9:586b:dba1 with SMTP id o3-20020ac24343000000b004f9586bdba1mr1947280lfl.4.1690469145967; Thu, 27 Jul 2023 07:45:45 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d28-20020ac2545c000000b004fb86662871sm334110lfn.233.2023.07.27.07.45.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 07:45:45 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Neil Armstrong Subject: [PATCH v4 1/5] drm/msm/dpu: inline __intr_offset Date: Thu, 27 Jul 2023 17:45:39 +0300 Message-Id: <20230727144543.1483630-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727144543.1483630-1-dmitry.baryshkov@linaro.org> References: <20230727144543.1483630-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Inline __intr_offset(), there is no point in having a separate oneline function for setting base block address. Reviewed-by: Neil Armstrong Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 5e2d68ebb113..0776b0f6df4f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -435,12 +435,6 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx) return intr_status; } -static void __intr_offset(const struct dpu_mdss_cfg *m, - void __iomem *addr, struct dpu_hw_blk_reg_map *hw) -{ - hw->blk_addr = addr + m->mdp[0].base; -} - struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, const struct dpu_mdss_cfg *m) { @@ -454,7 +448,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, if (!intr) return ERR_PTR(-ENOMEM); - __intr_offset(m, addr, &intr->hw); + intr->hw.blk_addr = addr + m->mdp[0].base; intr->total_irqs = nirq; From patchwork Thu Jul 27 14:45:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 707088 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC5AAC001DC for ; Thu, 27 Jul 2023 14:46:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234011AbjG0OqS (ORCPT ); Thu, 27 Jul 2023 10:46:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234020AbjG0OqF (ORCPT ); Thu, 27 Jul 2023 10:46:05 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB36F30F5 for ; Thu, 27 Jul 2023 07:45:48 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4f95bf5c493so1861636e87.3 for ; Thu, 27 Jul 2023 07:45:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1690469147; x=1691073947; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ySkrUDanMc9ZbI2s5Lw++O0slJDHRsqtls5Tv4CEjbo=; b=rOzA7S76EDTb2qD731viBkqHuLSRuSprdbhRGaIWQDC9+CCyOYTwsYIuiV1kErKAqK pP52ocynh4QkFszSvRDc0Ziks7zNb0UlkAtBuxTCHXlrqg2hdnQARPw9rkYcuA/+cZUV aJHc/4Bxj60OS0uDDevmxrX/Wqzh2C7yuEvrHB0VB+TCd6eLVxwFkPk/5fqU/YqoSLyB +lP9VAKWpwfPp0spwCRkQIkFTl3S+rl0OzsHT1du+ML2VsGISSHmsnU5WqQohjpbpXLR +pL5bozcZYbAVLXI5xMuBSadFsJyyhV07Q+jnR0W09k51F1TPyxjzj6ev9URkomIJSxX XSyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690469147; x=1691073947; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ySkrUDanMc9ZbI2s5Lw++O0slJDHRsqtls5Tv4CEjbo=; b=CnDwkSrl8aRaq/rTn/agVsBYSDKY48E/PYZ4hEmVf/gQ3+utafIa2hqzDFDzvjmO7Y +y0SgjzNTQqp5hYal5fxH4AMGi+RPL9LxonmiD4lmcYeOFsbN1Q1kgCJGz+k8aYAOWVj m1cJpvY6quTxO4RFJl9WvfPqpIlSuvIJD0prkOwCMLp1SF4LwZhjn7hjkSjxmHx0OUGH l38fJaSRGpCXHJbdxjvBOvLXe5jr3amdHzxF45J7yPyztGlRakUvzdck2kk0CYyDT2Yg xcM8eVoobqMGWxo6it4RPj1UEQ3H/G/ZXwPcamNj1gGQ4ssKTTM5P/xesQMAPWFEy9IR GYKA== X-Gm-Message-State: ABy/qLaG9d+rUlhx55Kc60rfRx1vzFSdpcq2+nArNn+PvhdEa62BYzjA k+RAVzysEL5B8CyszCSUNuvqqw== X-Google-Smtp-Source: APBJJlGd8gH4gBBz5NHcNIkymr7usd3IzWwDdNx5XcfUIww8mQX2s9ImQTa3YtyedY3G3LnAUHybPg== X-Received: by 2002:ac2:5f81:0:b0:4fe:d9e:a47 with SMTP id r1-20020ac25f81000000b004fe0d9e0a47mr1789383lfe.69.1690469146920; Thu, 27 Jul 2023 07:45:46 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d28-20020ac2545c000000b004fb86662871sm334110lfn.233.2023.07.27.07.45.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Jul 2023 07:45:46 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Neil Armstrong Subject: [PATCH v4 2/5] drm/msm/dpu: split interrupt address arrays Date: Thu, 27 Jul 2023 17:45:40 +0300 Message-Id: <20230727144543.1483630-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230727144543.1483630-1-dmitry.baryshkov@linaro.org> References: <20230727144543.1483630-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no point in having a single enum (and a single array) for both DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single enum and two IRQ address arrays. Reviewed-by: Neil Armstrong Reviewed-by: Marijn Suijten Fixes: c7314613226a0 ("drm/msm: Add missing struct identifier") Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------ .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++--- 2 files changed, 72 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c index 0776b0f6df4f..0cecdc847b49 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c @@ -51,11 +51,9 @@ struct dpu_intr_reg { }; /* - * struct dpu_intr_reg - List of DPU interrupt registers - * - * When making changes be sure to sync with dpu_hw_intr_reg + * dpu_intr_set_legacy - List of DPU interrupt registers for DPU <= 6.x */ -static const struct dpu_intr_reg dpu_intr_set[] = { +static const struct dpu_intr_reg dpu_intr_set_legacy[] = { [MDP_SSPP_TOP0_INTR] = { INTR_CLEAR, INTR_EN, @@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = { MDP_AD4_INTR_EN_OFF(1), MDP_AD4_INTR_STATUS_OFF(1), }, - [MDP_INTF0_7xxx_INTR] = { +}; + +/* + * dpu_intr_set_7xxx - List of DPU interrupt registers for DPU >= 7.0 + */ +static const struct dpu_intr_reg dpu_intr_set_7xxx[] = { + [MDP_SSPP_TOP0_INTR] = { + INTR_CLEAR, + INTR_EN, + INTR_STATUS + }, + [MDP_SSPP_TOP0_INTR2] = { + INTR2_CLEAR, + INTR2_EN, + INTR2_STATUS + }, + [MDP_SSPP_TOP0_HIST_INTR] = { + HIST_INTR_CLEAR, + HIST_INTR_EN, + HIST_INTR_STATUS + }, + [MDP_INTF0_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(0), MDP_INTF_REV_7xxx_INTR_EN(0), MDP_INTF_REV_7xxx_INTR_STATUS(0) }, - [MDP_INTF1_7xxx_INTR] = { + [MDP_INTF1_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(1), MDP_INTF_REV_7xxx_INTR_EN(1), MDP_INTF_REV_7xxx_INTR_STATUS(1) }, - [MDP_INTF1_7xxx_TEAR_INTR] = { + [MDP_INTF1_TEAR_INTR] = { MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1), MDP_INTF_REV_7xxx_INTR_TEAR_EN(1), MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1) }, - [MDP_INTF2_7xxx_INTR] = { + [MDP_INTF2_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(2), MDP_INTF_REV_7xxx_INTR_EN(2), MDP_INTF_REV_7xxx_INTR_STATUS(2) }, - [MDP_INTF2_7xxx_TEAR_INTR] = { + [MDP_INTF2_TEAR_INTR] = { MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2), MDP_INTF_REV_7xxx_INTR_TEAR_EN(2), MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2) }, - [MDP_INTF3_7xxx_INTR] = { + [MDP_INTF3_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(3), MDP_INTF_REV_7xxx_INTR_EN(3), MDP_INTF_REV_7xxx_INTR_STATUS(3) }, - [MDP_INTF4_7xxx_INTR] = { + [MDP_INTF4_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(4), MDP_INTF_REV_7xxx_INTR_EN(4), MDP_INTF_REV_7xxx_INTR_STATUS(4) }, - [MDP_INTF5_7xxx_INTR] = { + [MDP_INTF5_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(5), MDP_INTF_REV_7xxx_INTR_EN(5), MDP_INTF_REV_7xxx_INTR_STATUS(5) }, - [MDP_INTF6_7xxx_INTR] = { + [MDP_INTF6_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(6), MDP_INTF_REV_7xxx_INTR_EN(6), MDP_INTF_REV_7xxx_INTR_STATUS(6) }, - [MDP_INTF7_7xxx_INTR] = { + [MDP_INTF7_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(7), MDP_INTF_REV_7xxx_INTR_EN(7), MDP_INTF_REV_7xxx_INTR_STATUS(7) }, - [MDP_INTF8_7xxx_INTR] = { + [MDP_INTF8_INTR] = { MDP_INTF_REV_7xxx_INTR_CLEAR(8), MDP_INTF_REV_7xxx_INTR_EN(8), MDP_INTF_REV_7xxx_INTR_STATUS(8) @@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms) return IRQ_NONE; spin_lock_irqsave(&intr->irq_lock, irq_flags); - for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) { + for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) { if (!test_bit(reg_idx, &intr->irq_mask)) continue; /* Read interrupt status */ - irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off); + irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off); /* Read enable mask */ - enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off); + enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off); /* and clear the interrupt */ if (irq_status) - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, + DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off, irq_status); /* Finally update IRQ status based on enable mask */ @@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx) assert_spin_locked(&intr->irq_lock); reg_idx = DPU_IRQ_REG(irq_idx); - reg = &dpu_intr_set[reg_idx]; + reg = &intr->intr_set[reg_idx]; + + /* Is this interrupt register supported on the platform */ + if (WARN_ON(!reg->en_off)) + return -EINVAL; cache_irq_mask = intr->cache_irq_mask[reg_idx]; if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) { @@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx) assert_spin_locked(&intr->irq_lock); reg_idx = DPU_IRQ_REG(irq_idx); - reg = &dpu_intr_set[reg_idx]; + reg = &intr->intr_set[reg_idx]; cache_irq_mask = intr->cache_irq_mask[reg_idx]; if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) { @@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms) if (!intr) return; - for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { + for (i = 0; i < MDP_INTR_MAX; i++) { if (test_bit(i, &intr->irq_mask)) DPU_REG_WRITE(&intr->hw, - dpu_intr_set[i].clr_off, 0xffffffff); + intr->intr_set[i].clr_off, 0xffffffff); } /* ensure register writes go through */ @@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms) if (!intr) return; - for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) { + for (i = 0; i < MDP_INTR_MAX; i++) { if (test_bit(i, &intr->irq_mask)) DPU_REG_WRITE(&intr->hw, - dpu_intr_set[i].en_off, 0x00000000); + intr->intr_set[i].en_off, 0x00000000); } /* ensure register writes go through */ @@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx) reg_idx = DPU_IRQ_REG(irq_idx); intr_status = DPU_REG_READ(&intr->hw, - dpu_intr_set[reg_idx].status_off) & + intr->intr_set[reg_idx].status_off) & DPU_IRQ_MASK(irq_idx); if (intr_status) - DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off, + DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off, intr_status); /* ensure register writes go through */ @@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr, if (!intr) return ERR_PTR(-ENOMEM); + if (m->mdss_ver->core_major_ver >= 7) + intr->intr_set = dpu_intr_set_7xxx; + else + intr->intr_set = dpu_intr_set_legacy; + intr->hw.blk_addr = addr + m->mdp[0].base; intr->total_irqs = nirq; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 1f2dabc54c22..f329d6d7f646 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -23,24 +23,29 @@ enum dpu_hw_intr_reg { MDP_INTF3_INTR, MDP_INTF4_INTR, MDP_INTF5_INTR, + MDP_INTF6_INTR, + MDP_INTF7_INTR, + MDP_INTF8_INTR, MDP_INTF1_TEAR_INTR, MDP_INTF2_TEAR_INTR, MDP_AD4_0_INTR, MDP_AD4_1_INTR, - MDP_INTF0_7xxx_INTR, - MDP_INTF1_7xxx_INTR, - MDP_INTF1_7xxx_TEAR_INTR, - MDP_INTF2_7xxx_INTR, - MDP_INTF2_7xxx_TEAR_INTR, - MDP_INTF3_7xxx_INTR, - MDP_INTF4_7xxx_INTR, - MDP_INTF5_7xxx_INTR, - MDP_INTF6_7xxx_INTR, - MDP_INTF7_7xxx_INTR, - MDP_INTF8_7xxx_INTR, MDP_INTR_MAX, }; +/* compatibility */ +#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR +#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR +#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR +#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR +#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR +#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR +#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR +#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR +#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR +#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR +#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR + #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset) /** @@ -60,6 +65,7 @@ struct dpu_hw_intr { u32 total_irqs; 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Now it is time to drop them and use unified symbol names. Reviewed-by: Neil Armstrong Reviewed-by: Marijn Suijten Signed-off-by: Dmitry Baryshkov --- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 4 ++-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +- .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 4 ++-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 4 ++-- .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 13 ------------- 6 files changed, 9 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h index 90efde5e9da5..941b585bd56f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h @@ -329,7 +329,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x2c4, @@ -339,7 +339,7 @@ static const struct dpu_intf_cfg sm8350_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h index 0a5dcec343fc..b18bb7ce2f94 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h @@ -210,7 +210,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_5", .id = INTF_5, .base = 0x39000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 7b1395f9e710..b08096f0d50b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -344,7 +344,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x300, @@ -354,7 +354,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h index 4999f3d8f2e2..9e0ad71c12a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h @@ -352,7 +352,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x300, @@ -362,7 +362,7 @@ static const struct dpu_intf_cfg sm8450_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h index 401c6c2da367..2a19e4c0af1a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h @@ -366,7 +366,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), }, { .name = "intf_2", .id = INTF_2, .base = 0x36000, .len = 0x300, @@ -376,7 +376,7 @@ static const struct dpu_intf_cfg sm8550_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), }, { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h index 6e0d0188edc6..dab761e54863 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h @@ -36,19 +36,6 @@ enum dpu_hw_intr_reg { #define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0)) -/* compatibility */ -#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR -#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR -#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR -#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR -#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR -#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR -#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR -#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR -#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR -#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR -#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR - #define DPU_IRQ_IDX(reg_idx, offset) (reg_idx * 32 + offset) /**